#include <stdint.h>
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/iobuf.h>
#include <ipxe/malloc.h>
#include <ipxe/pci.h>
#include "skge.h"

Enumerations
enum	led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST, MO_LED_NORM = 0, MO_LED_BLINK = 1, MO_LED_OFF = 2, MO_LED_ON = 3 }

Functions
	FILE_LICENCE (GPL2_ONLY)

static int	skge_up (struct net_device *dev)

static void	skge_down (struct net_device *dev)

static void	skge_tx_clean (struct net_device *dev)

static int	xm_phy_write (struct skge_hw *hw, int port, u16 reg, u16 val)

static int	gm_phy_write (struct skge_hw *hw, int port, u16 reg, u16 val)

static void	yukon_init (struct skge_hw *hw, int port)

static void	genesis_mac_init (struct skge_hw *hw, int port)

static void	genesis_link_up (struct skge_port *skge)

static void	skge_phyirq (struct skge_hw *hw)

static void	skge_poll (struct net_device *dev)

static int	skge_xmit_frame (struct net_device dev, struct io_buffer iob)

static void	skge_net_irq (struct net_device *dev, int enable)

static void	skge_rx_refill (struct net_device *dev)

static u32	skge_supported_modes (const struct skge_hw *hw)

static u32	hwkhz (const struct skge_hw *hw)

static u32	skge_usecs2clk (const struct skge_hw *hw, u32 usec)

static void	skge_led (struct skge_port *skge, enum led_mode mode)

static int	skge_ring_alloc (struct skge_ring ring, void vaddr, u32 base, size_t num)

static void	skge_rx_setup (struct skge_port skge __unused, struct skge_element e, struct io_buffer *iob, unsigned int bufsize)

static void	skge_rx_reuse (struct skge_element *e, unsigned int size)

static void	skge_rx_clean (struct skge_port *skge)

static void	skge_link_up (struct skge_port *skge)

static void	skge_link_down (struct skge_port *skge)

static void	xm_link_down (struct skge_hw *hw, int port)

static int	__xm_phy_read (struct skge_hw hw, int port, u16 reg, u16 val)

static u16	xm_phy_read (struct skge_hw *hw, int port, u16 reg)

static void	genesis_init (struct skge_hw *hw)

static void	genesis_reset (struct skge_hw *hw, int port)

static void	bcom_check_link (struct skge_hw *hw, int port)

static void	bcom_phy_init (struct skge_port *skge)

static void	xm_phy_init (struct skge_port *skge)

static int	xm_check_link (struct net_device *dev)

static void	xm_link_timer (struct skge_port *skge)

static void	genesis_stop (struct skge_port *skge)

static void	bcom_phy_intr (struct skge_port *skge)

static int	__gm_phy_read (struct skge_hw hw, int port, u16 reg, u16 val)

static u16	gm_phy_read (struct skge_hw *hw, int port, u16 reg)

static void	yukon_reset (struct skge_hw *hw, int port)

static int	is_yukon_lite_a0 (struct skge_hw *hw)

static void	yukon_mac_init (struct skge_hw *hw, int port)

static void	yukon_suspend (struct skge_hw *hw, int port)

static void	yukon_stop (struct skge_port *skge)

static u16	yukon_speed (const struct skge_hw *hw __unused, u16 aux)

static void	yukon_link_up (struct skge_port *skge)

static void	yukon_link_down (struct skge_port *skge)

static void	yukon_phy_intr (struct skge_port *skge)

static void	skge_ramset (struct skge_hw *hw, u16 q, u32 start, size_t len)

static void	skge_qset (struct skge_port skge, u16 q, const struct skge_element e)

void	skge_free (struct net_device *dev)

static void	skge_rx_stop (struct skge_hw *hw, int port)

static int	skge_tx_avail (const struct skge_ring *ring)

static u16	phy_length (const struct skge_hw *hw, u32 status)

static int	bad_phy_status (const struct skge_hw *hw, u32 status)

static void	skge_tx_done (struct net_device *dev)

static void	skge_rx_done (struct net_device *dev)

static const char *	skge_board_name (const struct skge_hw *hw)

static int	skge_reset (struct skge_hw *hw)

static struct net_device *	skge_devinit (struct skge_hw *hw, int port, int highmem __unused)

static void	skge_show_addr (struct net_device *dev)

static int	skge_probe (struct pci_device *pdev)

static void	skge_remove (struct pci_device *pdev)

Variables
static struct pci_device_id	skge_id_table []

static struct net_device_operations	skge_operations

static const int	txqaddr [] = { Q_XA1, Q_XA2 }

static const int	rxqaddr [] = { Q_R1, Q_R2 }

static const u32	portmask [] = { IS_PORT_1, IS_PORT_2 }

static const u16	phy_pause_map []

static const u16	fiber_pause_map []

struct {
u8 id

const char * name

}	skge_chips []

struct pci_driver skge_driver	__pci_driver

Enumeration Type Documentation

◆ led_mode

enum led_mode

Enumerator
LED_MODE_OFF
LED_MODE_ON
LED_MODE_TST
MO_LED_NORM
MO_LED_BLINK
MO_LED_OFF
MO_LED_ON

Definition at line 132 of file skge.c.

132 { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };

LED_MODE_OFF

Definition: skge.c:132

LED_MODE_ON

Definition: skge.c:132

LED_MODE_TST

Definition: skge.c:132

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_ONLY )

◆ skge_up()

static int skge_up ( struct net_device * dev )

static

Definition at line 1707 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u32 chunk, ram_addr;
         int err;
 
         DBG2(PFX "%s: enabling interface\n", dev->name);
 
         skge->mem = malloc_phys(RING_SIZE, SKGE_RING_ALIGN);
         skge->dma = virt_to_bus(skge->mem);
         if (!skge->mem)
                 return -ENOMEM;
         memset(skge->mem, 0, RING_SIZE);
 
         assert(!(skge->dma & 7));
 
         /* FIXME: find out whether 64 bit iPXE will be loaded > 4GB */
         if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) {
                 DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n");
                 err = -EINVAL;
                 goto err;
         }
 
         err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC);
         if (err)
                 goto err;
 
         /* this call relies on e->iob and d->control to be 0
          * This is assured by calling memset() on skge->mem and using zalloc()
          * for the skge_element structures.
          */
         skge_rx_refill(dev);
 
         err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE,
                               skge->dma + RX_RING_SIZE, NUM_TX_DESC);
         if (err)
                 goto err;
 
         /* Initialize MAC */
         if (hw->chip_id == CHIP_ID_GENESIS)
                 genesis_mac_init(hw, port);
         else
                 yukon_mac_init(hw, port);
 
         /* Configure RAMbuffers - equally between ports and tx/rx */
         chunk = (hw->ram_size  - hw->ram_offset) / (hw->ports * 2);
         ram_addr = hw->ram_offset + 2 * chunk * port;
 
         skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
         skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
 
         assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean));
         skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
         skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
 
         /* Start receiver BMU */
         wmb();
         skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
         skge_led(skge, LED_MODE_ON);
 
         hw->intr_mask |= portmask[port];
         skge_write32(hw, B0_IMSK, hw->intr_mask);
 
         return 0;
 
  err:
         skge_rx_clean(skge);
         skge_free(dev);
 
         return err;
 }

References assert(), B0_IMSK, CHIP_ID_GENESIS, CSR_IRQ_CL_F, CSR_START, DBG, DBG2, skge_hw::dev, skge_port::dma, EINVAL, ENOMEM, genesis_mac_init(), skge_port::hw, LED_MODE_ON, malloc_phys(), skge_port::mem, memset(), net_device::name, NUM_RX_DESC, NUM_TX_DESC, PFX, port, skge_port::port, portmask, net_device::priv, Q_ADDR, Q_CSR, RING_SIZE, skge_port::rx_ring, RX_RING_SIZE, rxqaddr, skge_free(), skge_led(), skge_qset(), skge_ramset(), SKGE_RING_ALIGN, skge_ring_alloc(), skge_rx_clean(), skge_rx_refill(), skge_write32(), skge_write8(), skge_ring::to_clean, skge_ring::to_use, skge_port::tx_ring, txqaddr, virt_to_bus(), wmb(), and yukon_mac_init().

◆ skge_down()

static void skge_down ( struct net_device * dev )

static

Definition at line 1790 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
 
         if (skge->mem == NULL)
                 return;
 
         DBG2(PFX "%s: disabling interface\n", dev->name);
 
         if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
                 skge->use_xm_link_timer = 0;
 
         netdev_link_down(dev);
 
         hw->intr_mask &= ~portmask[port];
         skge_write32(hw, B0_IMSK, hw->intr_mask);
 
         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
         if (hw->chip_id == CHIP_ID_GENESIS)
                 genesis_stop(skge);
         else
                 yukon_stop(skge);
 
         /* Stop transmitter */
         skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
         skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
                      RB_RST_SET|RB_DIS_OP_MD);
 
 
         /* Disable Force Sync bit and Enable Alloc bit */
         skge_write8(hw, SK_REG(port, TXA_CTRL),
                     TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
 
         /* Stop Interval Timer and Limit Counter of Tx Arbiter */
         skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
         skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
 
         /* Reset PCI FIFO */
         skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
         skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
 
         /* Reset the RAM Buffer async Tx queue */
         skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
 
         skge_rx_stop(hw, port);
 
         if (hw->chip_id == CHIP_ID_GENESIS) {
                 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
                 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
         } else {
                 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
                 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
         }
 
         skge_led(skge, LED_MODE_OFF);
 
         skge_tx_clean(dev);
 
         skge_rx_clean(skge);
 
         skge_free(dev);
         return;
 }

References B0_IMSK, CHIP_ID_GENESIS, CSR_SET_RESET, CSR_STOP, DBG2, skge_hw::dev, genesis_stop(), GMF_RST_SET, skge_port::hw, LED_MODE_OFF, LED_OFF, LNK_LED_REG, skge_port::mem, MFF_RST_SET, net_device::name, netdev_link_down(), NULL, PFX, port, skge_port::port, portmask, net_device::priv, Q_ADDR, Q_CSR, Q_XA1, Q_XA2, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, RB_RST_SET, RX_GMF_CTRL_T, RX_MFF_CTRL2, SK_PHY_XMAC, SK_REG, skge_free(), skge_led(), skge_rx_clean(), skge_rx_stop(), skge_tx_clean(), skge_write32(), skge_write8(), TX_GMF_CTRL_T, TX_MFF_CTRL2, TXA_CTRL, TXA_DIS_ALLOC, TXA_DIS_FSYNC, TXA_ITI_INI, TXA_LIM_INI, TXA_STOP_RC, txqaddr, skge_port::use_xm_link_timer, and yukon_stop().

◆ skge_tx_clean()

static void skge_tx_clean ( struct net_device * dev )

static

Definition at line 1909 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_element *e;
 
         for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
                 struct skge_tx_desc *td = e->desc;
                 td->control = 0;
         }
 
         skge->tx_ring.to_clean = e;
 }

References skge_tx_desc::control, skge_element::desc, skge_element::next, net_device::priv, skge_ring::to_clean, skge_ring::to_use, and skge_port::tx_ring.

Referenced by skge_down().

◆ xm_phy_write()

static int xm_phy_write	(	struct skge_hw *	hw,
		int	port,
		u16	reg,
		u16	val
	)

static

Definition at line 458 of file skge.c.

 {
         int i;
 
         xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
         for (i = 0; i < PHY_RETRIES; i++) {
                 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
                         goto ready;
                 udelay(1);
         }
         return -EIO;
 
  ready:
         xm_write16(hw, port, XM_PHY_DATA, val);
         for (i = 0; i < PHY_RETRIES; i++) {
                 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
                         return 0;
                 udelay(1);
         }
         return -ETIMEDOUT;
 }

References EIO, ETIMEDOUT, PHY_RETRIES, port, reg, udelay(), val, XM_MMU_CMD, XM_MMU_PHY_BUSY, XM_PHY_ADDR, XM_PHY_DATA, xm_read16(), and xm_write16().

Referenced by bcom_phy_init(), bcom_phy_intr(), genesis_link_up(), skge_led(), and xm_phy_init().

◆ gm_phy_write()

static int gm_phy_write	(	struct skge_hw *	hw,
		int	port,
		u16	reg,
		u16	val
	)

static

Definition at line 1159 of file skge.c.

 {
         int i;
 
         gma_write16(hw, port, GM_SMI_DATA, val);
         gma_write16(hw, port, GM_SMI_CTRL,
                          GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
         for (i = 0; i < PHY_RETRIES; i++) {
                 udelay(1);
 
                 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
                         return 0;
         }
 
         DBG(PFX "%s: phy write timeout port %x reg %x val %x\n",
             hw->dev[port]->name,
             port, reg, val);
         return -EIO;
 }

References DBG, EIO, GM_SMI_CT_BUSY, GM_SMI_CT_PHY_AD, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), PFX, PHY_RETRIES, port, reg, udelay(), and val.

Referenced by skge_led(), yukon_init(), yukon_link_down(), yukon_link_up(), yukon_reset(), and yukon_suspend().

◆ yukon_init()

static void yukon_init	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 1210 of file skge.c.

 {
         struct skge_port *skge = hw->dev[port]->priv;
         u16 ctrl, ct1000, adv;
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 
                 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
                           PHY_M_EC_MAC_S_MSK);
                 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
 
                 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
 
                 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
         }
 
         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
         if (skge->autoneg == AUTONEG_DISABLE)
                 ctrl &= ~PHY_CT_ANE;
 
         ctrl |= PHY_CT_RESET;
         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
         ctrl = 0;
         ct1000 = 0;
         adv = PHY_AN_CSMA;
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 if (hw->copper) {
                         if (skge->advertising & ADVERTISED_1000baseT_Full)
                                 ct1000 |= PHY_M_1000C_AFD;
                         if (skge->advertising & ADVERTISED_1000baseT_Half)
                                 ct1000 |= PHY_M_1000C_AHD;
                         if (skge->advertising & ADVERTISED_100baseT_Full)
                                 adv |= PHY_M_AN_100_FD;
                         if (skge->advertising & ADVERTISED_100baseT_Half)
                                 adv |= PHY_M_AN_100_HD;
                         if (skge->advertising & ADVERTISED_10baseT_Full)
                                 adv |= PHY_M_AN_10_FD;
                         if (skge->advertising & ADVERTISED_10baseT_Half)
                                 adv |= PHY_M_AN_10_HD;
 
                         /* Set Flow-control capabilities */
                         adv |= phy_pause_map[skge->flow_control];
                 } else {
                         if (skge->advertising & ADVERTISED_1000baseT_Full)
                                 adv |= PHY_M_AN_1000X_AFD;
                         if (skge->advertising & ADVERTISED_1000baseT_Half)
                                 adv |= PHY_M_AN_1000X_AHD;
 
                         adv |= fiber_pause_map[skge->flow_control];
                 }
 
                 /* Restart Auto-negotiation */
                 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
         } else {
                 /* forced speed/duplex settings */
                 ct1000 = PHY_M_1000C_MSE;
 
                 if (skge->duplex == DUPLEX_FULL)
                         ctrl |= PHY_CT_DUP_MD;
 
                 switch (skge->speed) {
                 case SPEED_1000:
                         ctrl |= PHY_CT_SP1000;
                         break;
                 case SPEED_100:
                         ctrl |= PHY_CT_SP100;
                         break;
                 }
 
                 ctrl |= PHY_CT_RESET;
         }
 
         gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
 
         gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
         /* Enable phy interrupt on autonegotiation complete (or link up) */
         if (skge->autoneg == AUTONEG_ENABLE)
                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
         else
                 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
 }

References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, skge_port::advertising, skge_port::autoneg, AUTONEG_DISABLE, AUTONEG_ENABLE, ctrl, skge_port::duplex, DUPLEX_FULL, fiber_pause_map, skge_port::flow_control, gm_phy_read(), gm_phy_write(), MAC_TX_CLK_25_MHZ, PHY_AN_CSMA, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_CT_RESET, PHY_CT_SP100, PHY_CT_SP1000, PHY_M_1000C_AFD, PHY_M_1000C_AHD, PHY_M_1000C_MSE, PHY_M_AN_1000X_AFD, PHY_M_AN_1000X_AHD, PHY_M_AN_100_FD, PHY_M_AN_100_HD, PHY_M_AN_10_FD, PHY_M_AN_10_HD, PHY_M_EC_M_DSC, PHY_M_EC_M_DSC_MSK, PHY_M_EC_MAC_S, PHY_M_EC_MAC_S_MSK, PHY_M_EC_S_DSC, PHY_M_EC_S_DSC_MSK, PHY_M_IS_AN_MSK, PHY_M_IS_DEF_MSK, PHY_MARV_1000T_CTRL, PHY_MARV_AUNE_ADV, PHY_MARV_CTRL, PHY_MARV_EXT_CTRL, PHY_MARV_INT_MASK, phy_pause_map, port, skge_port::speed, SPEED_100, and SPEED_1000.

Referenced by yukon_link_down(), and yukon_mac_init().

◆ genesis_mac_init()

static void genesis_mac_init	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 852 of file skge.c.

 {
         struct net_device *dev = hw->dev[port];
         struct skge_port *skge = dev->priv;
         int i;
         u32 r;
         const u8 zero[6]  = { 0 };
 
         for (i = 0; i < 10; i++) {
                 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
                              MFF_SET_MAC_RST);
                 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
                         goto reset_ok;
                 udelay(1);
         }
 
         DBG(PFX "%s: genesis reset failed\n", dev->name);
 
  reset_ok:
         /* Unreset the XMAC. */
         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
 
         /*
          * Perform additional initialization for external PHYs,
          * namely for the 1000baseTX cards that use the XMAC's
          * GMII mode.
          */
         if (hw->phy_type != SK_PHY_XMAC) {
                 /* Take external Phy out of reset */
                 r = skge_read32(hw, B2_GP_IO);
                 if (port == 0)
                         r |= GP_DIR_0|GP_IO_0;
                 else
                         r |= GP_DIR_2|GP_IO_2;
 
                 skge_write32(hw, B2_GP_IO, r);
 
                 /* Enable GMII interface */
                 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
         }
 
 
         switch(hw->phy_type) {
         case SK_PHY_XMAC:
                 xm_phy_init(skge);
                 break;
         case SK_PHY_BCOM:
                 bcom_phy_init(skge);
                 bcom_check_link(hw, port);
         }
 
         /* Set Station Address */
         xm_outaddr(hw, port, XM_SA, dev->ll_addr);
 
         /* We don't use match addresses so clear */
         for (i = 1; i < 16; i++)
                 xm_outaddr(hw, port, XM_EXM(i), zero);
 
         /* Clear MIB counters */
         xm_write16(hw, port, XM_STAT_CMD,
                         XM_SC_CLR_RXC | XM_SC_CLR_TXC);
         /* Clear two times according to Errata #3 */
         xm_write16(hw, port, XM_STAT_CMD,
                         XM_SC_CLR_RXC | XM_SC_CLR_TXC);
 
         /* configure Rx High Water Mark (XM_RX_HI_WM) */
         xm_write16(hw, port, XM_RX_HI_WM, 1450);
 
         /* We don't need the FCS appended to the packet. */
         r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
 
         if (skge->duplex == DUPLEX_HALF) {
                 /*
                  * If in manual half duplex mode the other side might be in
                  * full duplex mode, so ignore if a carrier extension is not seen
                  * on frames received
                  */
                 r |= XM_RX_DIS_CEXT;
         }
         xm_write16(hw, port, XM_RX_CMD, r);
 
         /* We want short frames padded to 60 bytes. */
         xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
 
         xm_write16(hw, port, XM_TX_THR, 512);
 
         /*
          * Enable the reception of all error frames. This is is
          * a necessary evil due to the design of the XMAC. The
          * XMAC's receive FIFO is only 8K in size, however jumbo
          * frames can be up to 9000 bytes in length. When bad
          * frame filtering is enabled, the XMAC's RX FIFO operates
          * in 'store and forward' mode. For this to work, the
          * entire frame has to fit into the FIFO, but that means
          * that jumbo frames larger than 8192 bytes will be
          * truncated. Disabling all bad frame filtering causes
          * the RX FIFO to operate in streaming mode, in which
          * case the XMAC will start transferring frames out of the
          * RX FIFO as soon as the FIFO threshold is reached.
          */
         xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
 
 
         /*
          * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
          *      - Enable all bits excepting 'Octets Rx OK Low CntOv'
          *        and 'Octets Rx OK Hi Cnt Ov'.
          */
         xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
 
         /*
          * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
          *      - Enable all bits excepting 'Octets Tx OK Low CntOv'
          *        and 'Octets Tx OK Hi Cnt Ov'.
          */
         xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
 
         /* Configure MAC arbiter */
         skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
 
         /* configure timeout values */
         skge_write8(hw, B3_MA_TOINI_RX1, 72);
         skge_write8(hw, B3_MA_TOINI_RX2, 72);
         skge_write8(hw, B3_MA_TOINI_TX1, 72);
         skge_write8(hw, B3_MA_TOINI_TX2, 72);
 
         skge_write8(hw, B3_MA_RCINI_RX1, 0);
         skge_write8(hw, B3_MA_RCINI_RX2, 0);
         skge_write8(hw, B3_MA_RCINI_TX1, 0);
         skge_write8(hw, B3_MA_RCINI_TX2, 0);
 
         /* Configure Rx MAC FIFO */
         skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
         skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
         skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
 
         /* Configure Tx MAC FIFO */
         skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
         skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
 
         /* enable timeout timers */
         skge_write16(hw, B3_PA_CTRL,
                      (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
 }

References B2_GP_IO, B3_MA_RCINI_RX1, B3_MA_RCINI_RX2, B3_MA_RCINI_TX1, B3_MA_RCINI_TX2, B3_MA_TO_CTRL, B3_MA_TOINI_RX1, B3_MA_TOINI_RX2, B3_MA_TOINI_TX1, B3_MA_TOINI_TX2, B3_PA_CTRL, bcom_check_link(), bcom_phy_init(), DBG, net_device::dev, skge_port::duplex, DUPLEX_HALF, GP_DIR_0, GP_DIR_2, GP_IO_0, GP_IO_2, net_device::ll_addr, MA_RST_CLR, MFF_CLR_MAC_RST, MFF_ENA_OP_MD, MFF_ENA_TIM_PAT, MFF_RST_CLR, MFF_SET_MAC_RST, MFF_TX_CTRL_DEF, net_device::name, PA_ENA_TO_TX1, PA_ENA_TO_TX2, PFX, port, net_device::priv, r, RX_MFF_CTRL1, RX_MFF_CTRL2, SK_PHY_BCOM, SK_PHY_XMAC, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), skge_write8(), TX_MFF_CTRL1, TX_MFF_CTRL2, udelay(), XM_DEF_MODE, XM_EXM, XM_HW_CFG, XM_HW_GMII_MD, XM_MODE, xm_outaddr(), xm_phy_init(), XM_RX_CMD, XM_RX_DIS_CEXT, XM_RX_EV_MSK, XM_RX_HI_WM, XM_RX_LENERR_OK, XM_RX_STRIP_FCS, XM_SA, XM_SC_CLR_RXC, XM_SC_CLR_TXC, XM_STAT_CMD, XM_TX_AUTO_PAD, XM_TX_CMD, XM_TX_EV_MSK, XM_TX_THR, xm_write16(), xm_write32(), XMR_DEF_MSK, and XMT_DEF_MSK.

Referenced by skge_up().

◆ genesis_link_up()

static void genesis_link_up ( struct skge_port * skge )

static

Definition at line 1045 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 cmd, msk;
         u32 mode;
 
         cmd = xm_read16(hw, port, XM_MMU_CMD);
 
         /*
          * enabling pause frame reception is required for 1000BT
          * because the XMAC is not reset if the link is going down
          */
         if (skge->flow_status == FLOW_STAT_NONE ||
             skge->flow_status == FLOW_STAT_LOC_SEND)
                 /* Disable Pause Frame Reception */
                 cmd |= XM_MMU_IGN_PF;
         else
                 /* Enable Pause Frame Reception */
                 cmd &= ~XM_MMU_IGN_PF;
 
         xm_write16(hw, port, XM_MMU_CMD, cmd);
 
         mode = xm_read32(hw, port, XM_MODE);
         if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
             skge->flow_status == FLOW_STAT_LOC_SEND) {
                 /*
                  * Configure Pause Frame Generation
                  * Use internal and external Pause Frame Generation.
                  * Sending pause frames is edge triggered.
                  * Send a Pause frame with the maximum pause time if
                  * internal oder external FIFO full condition occurs.
                  * Send a zero pause time frame to re-start transmission.
                  */
                 /* XM_PAUSE_DA = '010000C28001' (default) */
                 /* XM_MAC_PTIME = 0xffff (maximum) */
                 /* remember this value is defined in big endian (!) */
                 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
 
                 mode |= XM_PAUSE_MODE;
                 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
         } else {
                 /*
                  * disable pause frame generation is required for 1000BT
                  * because the XMAC is not reset if the link is going down
                  */
                 /* Disable Pause Mode in Mode Register */
                 mode &= ~XM_PAUSE_MODE;
 
                 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
         }
 
         xm_write32(hw, port, XM_MODE, mode);
 
         /* Turn on detection of Tx underrun */
         msk = xm_read16(hw, port, XM_IMSK);
         msk &= ~XM_IS_TXF_UR;
         xm_write16(hw, port, XM_IMSK, msk);
 
         xm_read16(hw, port, XM_ISRC);
 
         /* get MMU Command Reg. */
         cmd = xm_read16(hw, port, XM_MMU_CMD);
         if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
                 cmd |= XM_MMU_GMII_FD;
 
         /*
          * Workaround BCOM Errata (#10523) for all BCom Phys
          * Enable Power Management after link up
          */
         if (hw->phy_type == SK_PHY_BCOM) {
                 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
                              xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
                              & ~PHY_B_AC_DIS_PM);
                 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
         }
 
         /* enable Rx/Tx */
         xm_write16(hw, port, XM_MMU_CMD,
                         cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
         skge_link_up(skge);
 }

References cmd, skge_port::duplex, DUPLEX_FULL, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_SYMMETRIC, skge_port::flow_status, skge_port::hw, MFF_DIS_PAUSE, MFF_ENA_PAUSE, PHY_B_AC_DIS_PM, PHY_B_DEF_MSK, PHY_BCOM_AUX_CTRL, PHY_BCOM_INT_MASK, port, skge_port::port, RX_MFF_CTRL1, SK_PHY_BCOM, SK_PHY_XMAC, SK_REG, skge_link_up(), skge_write16(), XM_IMSK, XM_IS_TXF_UR, XM_ISRC, XM_MAC_PTIME, XM_MMU_CMD, XM_MMU_ENA_RX, XM_MMU_ENA_TX, XM_MMU_GMII_FD, XM_MMU_IGN_PF, XM_MODE, XM_PAUSE_MODE, xm_phy_read(), xm_phy_write(), xm_read16(), xm_read32(), xm_write16(), and xm_write32().

Referenced by bcom_check_link(), and xm_check_link().

◆ skge_phyirq()

static void skge_phyirq ( struct skge_hw * hw )

static

Definition at line 2082 of file skge.c.

 {
         int port;
 
         for (port = 0; port < hw->ports; port++) {
                 struct net_device *dev = hw->dev[port];
                 struct skge_port *skge = dev->priv;
 
                 if (hw->chip_id != CHIP_ID_GENESIS)
                         yukon_phy_intr(skge);
                 else if (hw->phy_type == SK_PHY_BCOM)
                         bcom_phy_intr(skge);
         }
 
         hw->intr_mask |= IS_EXT_REG;
         skge_write32(hw, B0_IMSK, hw->intr_mask);
         skge_read32(hw, B0_IMSK);
 }

References B0_IMSK, bcom_phy_intr(), CHIP_ID_GENESIS, net_device::dev, IS_EXT_REG, port, net_device::priv, SK_PHY_BCOM, skge_read32(), skge_write32(), and yukon_phy_intr().

Referenced by skge_poll().

◆ skge_poll()

static void skge_poll ( struct net_device * dev )

static

Definition at line 2051 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
         u32 status;
 
         /* reading this register ACKs interrupts */
         status = skge_read32(hw, B0_SP_ISRC);
 
         /* Link event? */
         if (status & IS_EXT_REG) {
                 skge_phyirq(hw);
                 if (skge->use_xm_link_timer)
                         xm_link_timer(skge);
         }
 
         skge_tx_done(dev);
 
         skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
 
         skge_rx_done(dev);
 
         /* restart receiver */
         wmb();
         skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
 
         skge_read32(hw, B0_IMSK);
 
         return;
 }

References B0_IMSK, B0_SP_ISRC, CSR_IRQ_CL_F, CSR_START, skge_hw::dev, skge_port::hw, IS_EXT_REG, skge_port::port, net_device::priv, Q_ADDR, Q_CSR, rxqaddr, skge_phyirq(), skge_read32(), skge_rx_done(), skge_tx_done(), skge_write8(), status, skge_port::use_xm_link_timer, wmb(), and xm_link_timer().

◆ skge_xmit_frame()

static int skge_xmit_frame	(	struct net_device *	dev,
		struct io_buffer *	iob
	)

static

Definition at line 1863 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
         struct skge_element *e;
         struct skge_tx_desc *td;
         u32 control, len;
         u64 map;
 
         if (skge_tx_avail(&skge->tx_ring) < 1)
                 return -EBUSY;
 
         e = skge->tx_ring.to_use;
         td = e->desc;
         assert(!(td->control & BMU_OWN));
         e->iob = iob;
         len = iob_len(iob);
         map = virt_to_bus(iob->data);
 
         td->dma_lo = map;
         td->dma_hi = map >> 32;
 
         control = BMU_CHECK;
 
         control |= BMU_EOF| BMU_IRQ_EOF;
         /* Make sure all the descriptors written */
         wmb();
         td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
         wmb();
 
         skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
 
         DBGIO(PFX "%s: tx queued, slot %td, len %d\n",
              dev->name, e - skge->tx_ring.start, (unsigned int)len);
 
         skge->tx_ring.to_use = e->next;
         wmb();
 
         if (skge_tx_avail(&skge->tx_ring) <= 1) {
                 DBG(PFX "%s: transmit queue full\n", dev->name);
         }
 
         return 0;
 }

References assert(), BMU_CHECK, BMU_EOF, BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_SW, control, skge_tx_desc::control, CSR_START, io_buffer::data, DBG, DBGIO, skge_element::desc, skge_tx_desc::dma_hi, skge_tx_desc::dma_lo, EBUSY, skge_port::hw, skge_element::iob, iob_len(), len, map, net_device::name, skge_element::next, PFX, skge_port::port, net_device::priv, Q_ADDR, Q_CSR, skge_tx_avail(), skge_write8(), skge_ring::start, skge_ring::to_use, skge_port::tx_ring, txqaddr, virt_to_bus(), and wmb().

◆ skge_net_irq()

static void skge_net_irq	(	struct net_device *	dev,
		int	enable
	)

static

Definition at line 2448 of file skge.c.

                                                                 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
 
         if (enable)
                 hw->intr_mask |= portmask[skge->port];
         else
                 hw->intr_mask &= ~portmask[skge->port];
         skge_write32(hw, B0_IMSK, hw->intr_mask);
 }

References B0_IMSK, skge_port::hw, skge_port::port, portmask, net_device::priv, and skge_write32().

◆ skge_rx_refill()

static void skge_rx_refill ( struct net_device * dev )

static

Definition at line 1962 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_ring *ring = &skge->rx_ring;
         struct skge_element *e;
         struct io_buffer *iob;
         struct skge_rx_desc *rd;
         u32 control;
         int i;
 
         for (i = 0; i < NUM_RX_DESC; i++) {
                 e = ring->to_clean;
                 rd = e->desc;
                 iob = e->iob;
                 control = rd->control;
 
                 /* nothing to do here */
                 if (iob || (control & BMU_OWN))
                         continue;
 
                 DBG2("refilling rx desc %zd: ", (ring->to_clean - ring->start));
 
                 iob = alloc_iob(RX_BUF_SIZE);
                 if (iob) {
                         skge_rx_setup(skge, e, iob, RX_BUF_SIZE);
                 } else {
                         DBG("descr %zd: alloc_iob() failed\n",
                              (ring->to_clean - ring->start));
                         /* We pass the descriptor to the NIC even if the
                          * allocation failed. The card will stop as soon as it
                          * encounters a descriptor with the OWN bit set to 0,
                          * thus never getting to the next descriptor that might
                          * contain a valid io_buffer. This would effectively
                          * stall the receive.
                          */
                         skge_rx_setup(skge, e, NULL, 0);
                 }
 
                 ring->to_clean = e->next;
         }
 }

References alloc_iob(), BMU_OWN, control, skge_rx_desc::control, DBG, DBG2, skge_element::desc, skge_element::iob, skge_element::next, NULL, NUM_RX_DESC, net_device::priv, RX_BUF_SIZE, skge_port::rx_ring, skge_rx_setup(), skge_ring::start, and skge_ring::to_clean.

Referenced by skge_rx_done(), and skge_up().

◆ skge_supported_modes()

static u32 skge_supported_modes ( const struct skge_hw * hw )

static

Definition at line 92 of file skge.c.

 {
         u32 supported;
 
         if (hw->copper) {
                 supported = SUPPORTED_10baseT_Half
                         | SUPPORTED_10baseT_Full
                         | SUPPORTED_100baseT_Half
                         | SUPPORTED_100baseT_Full
                         | SUPPORTED_1000baseT_Half
                         | SUPPORTED_1000baseT_Full
                         | SUPPORTED_Autoneg| SUPPORTED_TP;
 
                 if (hw->chip_id == CHIP_ID_GENESIS)
                         supported &= ~(SUPPORTED_10baseT_Half
                                              | SUPPORTED_10baseT_Full
                                              | SUPPORTED_100baseT_Half
                                              | SUPPORTED_100baseT_Full);
 
                 else if (hw->chip_id == CHIP_ID_YUKON)
                         supported &= ~SUPPORTED_1000baseT_Half;
         } else
                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
                         | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
 
         return supported;
 }

References CHIP_ID_GENESIS, CHIP_ID_YUKON, supported, SUPPORTED_1000baseT_Full, SUPPORTED_1000baseT_Half, SUPPORTED_100baseT_Full, SUPPORTED_100baseT_Half, SUPPORTED_10baseT_Full, SUPPORTED_10baseT_Half, SUPPORTED_Autoneg, SUPPORTED_FIBRE, and SUPPORTED_TP.

Referenced by skge_devinit().

◆ hwkhz()

static u32 hwkhz ( const struct skge_hw * hw )

inlinestatic

Definition at line 121 of file skge.c.

 {
         return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
 }

References CHIP_ID_GENESIS.

Referenced by skge_usecs2clk().

◆ skge_usecs2clk()

static u32 skge_usecs2clk	(	const struct skge_hw *	hw,
		u32	usec
	)

inlinestatic

Definition at line 127 of file skge.c.

 {
         return hwkhz(hw) * usec / 1000;
 }

References hwkhz().

Referenced by skge_reset().

◆ skge_led()

static void skge_led	(	struct skge_port *	skge,
		enum led_mode	mode
	)

static

Definition at line 133 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
 
         if (hw->chip_id == CHIP_ID_GENESIS) {
                 switch (mode) {
                 case LED_MODE_OFF:
                         if (hw->phy_type == SK_PHY_BCOM)
                                 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
                         else {
                                 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
                                 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
                         }
                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
                         skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
                         break;
 
                 case LED_MODE_ON:
                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
                         skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
 
                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
                         skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
 
                         break;
 
                 case LED_MODE_TST:
                         skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
                         skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
                         skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
 
                         if (hw->phy_type == SK_PHY_BCOM)
                                 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
                         else {
                                 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
                                 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
                                 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
                         }
 
                 }
         } else {
                 switch (mode) {
                 case LED_MODE_OFF:
                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                      PHY_M_LED_MO_DUP(MO_LED_OFF)  |
                                      PHY_M_LED_MO_10(MO_LED_OFF)   |
                                      PHY_M_LED_MO_100(MO_LED_OFF)  |
                                      PHY_M_LED_MO_1000(MO_LED_OFF) |
                                      PHY_M_LED_MO_RX(MO_LED_OFF));
                         break;
                 case LED_MODE_ON:
                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
                                      PHY_M_LED_PULS_DUR(PULS_170MS) |
                                      PHY_M_LED_BLINK_RT(BLINK_84MS) |
                                      PHY_M_LEDC_TX_CTRL |
                                      PHY_M_LEDC_DP_CTRL);
 
                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                      PHY_M_LED_MO_RX(MO_LED_OFF) |
                                      (skge->speed == SPEED_100 ?
                                       PHY_M_LED_MO_100(MO_LED_ON) : 0));
                         break;
                 case LED_MODE_TST:
                         gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
                         gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                      PHY_M_LED_MO_DUP(MO_LED_ON)  |
                                      PHY_M_LED_MO_10(MO_LED_ON)   |
                                      PHY_M_LED_MO_100(MO_LED_ON)  |
                                      PHY_M_LED_MO_1000(MO_LED_ON) |
                                      PHY_M_LED_MO_RX(MO_LED_ON));
                 }
         }
 }

References BLINK_84MS, CHIP_ID_GENESIS, gm_phy_write(), skge_port::hw, LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST, LED_START, LED_T_OFF, LED_T_ON, LINKLED_LINKSYNC_ON, LINKLED_OFF, LINKLED_ON, LNK_LED_REG, MO_LED_OFF, MO_LED_ON, PHY_B_PEC_LED_OFF, PHY_B_PEC_LED_ON, PHY_BCOM_P_EXT_CTRL, PHY_M_LED_BLINK_RT, PHY_M_LED_MO_10, PHY_M_LED_MO_100, PHY_M_LED_MO_1000, PHY_M_LED_MO_DUP, PHY_M_LED_MO_RX, PHY_M_LED_PULS_DUR, PHY_M_LEDC_DP_CTRL, PHY_M_LEDC_TX_CTRL, PHY_MARV_LED_CTRL, PHY_MARV_LED_OVER, port, skge_port::port, PULS_170MS, RX_LED_CTRL, RX_LED_TST, RX_LED_VAL, SK_PHY_BCOM, SK_REG, skge_write32(), skge_write8(), skge_port::speed, SPEED_100, TX_LED_CTRL, TX_LED_TST, TX_LED_VAL, and xm_phy_write().

Referenced by skge_down(), and skge_up().

◆ skge_ring_alloc()

static int skge_ring_alloc	(	struct skge_ring *	ring,
		void *	vaddr,
		u32	base,
		size_t	num
	)

static

Definition at line 311 of file skge.c.

 {
         struct skge_tx_desc *d;
         struct skge_element *e;
         unsigned int i;
 
         ring->start = zalloc(num*sizeof(*e));
         if (!ring->start)
                 return -ENOMEM;
 
         for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) {
                 e->desc = d;
                 if (i == num - 1) {
                         e->next = ring->start;
                         d->next_offset = base;
                 } else {
                         e->next = e + 1;
                         d->next_offset = base + (i+1) * sizeof(*d);
                 }
         }
         ring->to_use = ring->to_clean = ring->start;
 
         return 0;
 }

References base, skge_element::desc, ENOMEM, skge_element::next, skge_tx_desc::next_offset, num, skge_ring::start, skge_ring::to_clean, skge_ring::to_use, and zalloc().

Referenced by skge_up().

◆ skge_rx_setup()

static void skge_rx_setup	(	struct skge_port *skge	__unused,
		struct skge_element *	e,
		struct io_buffer *	iob,
		unsigned int	bufsize
	)

static

Definition at line 338 of file skge.c.

 {
         struct skge_rx_desc *rd = e->desc;
         u64 map;
 
         map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0;
 
         rd->dma_lo = map;
         rd->dma_hi = map >> 32;
         e->iob = iob;
         rd->csum1_start = ETH_HLEN;
         rd->csum2_start = ETH_HLEN;
         rd->csum1 = 0;
         rd->csum2 = 0;
 
         wmb();
 
         rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
 }

References BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_TCP_CHECK, bufsize, skge_rx_desc::control, skge_rx_desc::csum1, skge_rx_desc::csum1_start, skge_rx_desc::csum2, skge_rx_desc::csum2_start, io_buffer::data, skge_element::desc, skge_rx_desc::dma_hi, skge_rx_desc::dma_lo, ETH_HLEN, skge_element::iob, map, NULL, virt_to_bus(), and wmb().

Referenced by skge_rx_refill().

◆ skge_rx_reuse()

static void skge_rx_reuse	(	struct skge_element *	e,
		unsigned int	size
	)

inlinestatic

Definition at line 364 of file skge.c.

 {
         struct skge_rx_desc *rd = e->desc;
 
         rd->csum2 = 0;
         rd->csum2_start = ETH_HLEN;
 
         wmb();
 
         rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
 }

References BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_TCP_CHECK, skge_rx_desc::control, skge_rx_desc::csum2, skge_rx_desc::csum2_start, skge_element::desc, ETH_HLEN, size, and wmb().

◆ skge_rx_clean()

static void skge_rx_clean ( struct skge_port * skge )

static

Definition at line 378 of file skge.c.

 {
         struct skge_ring *ring = &skge->rx_ring;
         struct skge_element *e;
 
         e = ring->start;
         do {
                 struct skge_rx_desc *rd = e->desc;
                 rd->control = 0;
                 if (e->iob) {
                         free_iob(e->iob);
                         e->iob = NULL;
                 }
         } while ((e = e->next) != ring->start);
 }

References skge_rx_desc::control, skge_element::desc, free_iob(), skge_element::iob, skge_element::next, NULL, skge_port::rx_ring, and skge_ring::start.

Referenced by skge_down(), and skge_up().

◆ skge_link_up()

static void skge_link_up ( struct skge_port * skge )

static

Definition at line 394 of file skge.c.

 {
         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
                     LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
 
         netdev_link_up(skge->netdev);
 
         DBG2(PFX "%s: Link is up at %d Mbps, %s duplex\n",
              skge->netdev->name, skge->speed,
              skge->duplex == DUPLEX_FULL ? "full" : "half");
 }

References DBG2, skge_port::duplex, DUPLEX_FULL, skge_port::hw, LED_BLK_OFF, LED_ON, LED_SYNC_OFF, LNK_LED_REG, net_device::name, skge_port::netdev, netdev_link_up(), PFX, skge_port::port, SK_REG, skge_write8(), and skge_port::speed.

Referenced by genesis_link_up(), and yukon_link_up().

◆ skge_link_down()

static void skge_link_down ( struct skge_port * skge )

static

Definition at line 406 of file skge.c.

 {
         skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
         netdev_link_down(skge->netdev);
 
         DBG2(PFX "%s: Link is down.\n", skge->netdev->name);
 }

References DBG2, skge_port::hw, LED_OFF, LNK_LED_REG, net_device::name, skge_port::netdev, netdev_link_down(), PFX, skge_port::port, SK_REG, and skge_write8().

Referenced by xm_link_down(), and yukon_link_down().

◆ xm_link_down()

static void xm_link_down	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 415 of file skge.c.

 {
         struct net_device *dev = hw->dev[port];
         struct skge_port *skge = dev->priv;
 
         xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
 
         if (netdev_link_ok(dev))
                 skge_link_down(skge);
 }

References net_device::dev, netdev_link_ok(), port, net_device::priv, skge_link_down(), XM_IMSK, XM_IMSK_DISABLE, and xm_write16().

Referenced by bcom_check_link(), and xm_check_link().

◆ __xm_phy_read()

static int __xm_phy_read	(	struct skge_hw *	hw,
		int	port,
		u16	reg,
		u16 *	val
	)

static

Definition at line 426 of file skge.c.

 {
         int i;
 
         xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
         *val = xm_read16(hw, port, XM_PHY_DATA);
 
         if (hw->phy_type == SK_PHY_XMAC)
                 goto ready;
 
         for (i = 0; i < PHY_RETRIES; i++) {
                 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
                         goto ready;
                 udelay(1);
         }
 
         return -ETIMEDOUT;
  ready:
         *val = xm_read16(hw, port, XM_PHY_DATA);
 
         return 0;
 }

References ETIMEDOUT, PHY_RETRIES, port, reg, SK_PHY_XMAC, udelay(), val, XM_MMU_CMD, XM_MMU_PHY_RDY, XM_PHY_ADDR, XM_PHY_DATA, xm_read16(), and xm_write16().

Referenced by xm_phy_read().

◆ xm_phy_read()

static u16 xm_phy_read	(	struct skge_hw *	hw,
		int	port,
		u16	reg
	)

static

Definition at line 449 of file skge.c.

 {
         u16 v = 0;
         if (__xm_phy_read(hw, port, reg, &v))
                 DBG(PFX "%s: phy read timed out\n",
                        hw->dev[port]->name);
         return v;
 }

References __xm_phy_read(), DBG, PFX, port, and reg.

Referenced by bcom_check_link(), bcom_phy_init(), bcom_phy_intr(), genesis_link_up(), and xm_check_link().

◆ genesis_init()

static void genesis_init ( struct skge_hw * hw )

static

Definition at line 480 of file skge.c.

 {
         /* set blink source counter */
         skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
         skge_write8(hw, B2_BSC_CTRL, BSC_START);
 
         /* configure mac arbiter */
         skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
 
         /* configure mac arbiter timeout values */
         skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
         skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
         skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
         skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
 
         skge_write8(hw, B3_MA_RCINI_RX1, 0);
         skge_write8(hw, B3_MA_RCINI_RX2, 0);
         skge_write8(hw, B3_MA_RCINI_TX1, 0);
         skge_write8(hw, B3_MA_RCINI_TX2, 0);
 
         /* configure packet arbiter timeout */
         skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
         skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
         skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
         skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
         skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
 }

References B2_BSC_CTRL, B2_BSC_INI, B3_MA_RCINI_RX1, B3_MA_RCINI_RX2, B3_MA_RCINI_TX1, B3_MA_RCINI_TX2, B3_MA_TO_CTRL, B3_MA_TOINI_RX1, B3_MA_TOINI_RX2, B3_MA_TOINI_TX1, B3_MA_TOINI_TX2, B3_PA_CTRL, B3_PA_TOINI_RX1, B3_PA_TOINI_RX2, B3_PA_TOINI_TX1, B3_PA_TOINI_TX2, BSC_START, MA_RST_CLR, PA_RST_CLR, SK_BLK_DUR, SK_FACT_53, SK_MAC_TO_53, SK_PKT_TO_MAX, skge_write16(), skge_write32(), and skge_write8().

Referenced by skge_reset().

◆ genesis_reset()

static void genesis_reset	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 508 of file skge.c.

 {
         const u8 zero[8]  = { 0 };
         u32 reg;
 
         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
 
         /* reset the statistics module */
         xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
         xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
         xm_write32(hw, port, XM_MODE, 0);               /* clear Mode Reg */
         xm_write16(hw, port, XM_TX_CMD, 0);     /* reset TX CMD Reg */
         xm_write16(hw, port, XM_RX_CMD, 0);     /* reset RX CMD Reg */
 
         /* disable Broadcom PHY IRQ */
         if (hw->phy_type == SK_PHY_BCOM)
                 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
 
         xm_outhash(hw, port, XM_HSM, zero);
 
         /* Flush TX and RX fifo */
         reg = xm_read32(hw, port, XM_MODE);
         xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
         xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
 }

References GMAC_IRQ_MSK, PHY_BCOM_INT_MASK, port, reg, SK_PHY_BCOM, SK_REG, skge_write8(), XM_GP_PORT, XM_GP_RES_STAT, XM_HSM, XM_IMSK, XM_IMSK_DISABLE, XM_MD_FRF, XM_MD_FTF, XM_MODE, xm_outhash(), xm_read32(), XM_RX_CMD, XM_TX_CMD, xm_write16(), and xm_write32().

Referenced by genesis_stop(), and skge_reset().

◆ bcom_check_link()

static void bcom_check_link	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 553 of file skge.c.

 {
         struct net_device *dev = hw->dev[port];
         struct skge_port *skge = dev->priv;
         u16 status;
 
         /* read twice because of latch */
         xm_phy_read(hw, port, PHY_BCOM_STAT);
         status = xm_phy_read(hw, port, PHY_BCOM_STAT);
 
         if ((status & PHY_ST_LSYNC) == 0) {
                 xm_link_down(hw, port);
                 return;
         }
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 u16 lpa, aux;
 
                 if (!(status & PHY_ST_AN_OVER))
                         return;
 
                 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
                 if (lpa & PHY_B_AN_RF) {
                         DBG(PFX "%s: remote fault\n",
                                dev->name);
                         return;
                 }
 
                 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
 
                 /* Check Duplex mismatch */
                 switch (aux & PHY_B_AS_AN_RES_MSK) {
                 case PHY_B_RES_1000FD:
                         skge->duplex = DUPLEX_FULL;
                         break;
                 case PHY_B_RES_1000HD:
                         skge->duplex = DUPLEX_HALF;
                         break;
                 default:
                         DBG(PFX "%s: duplex mismatch\n",
                                dev->name);
                         return;
                 }
 
                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
                 switch (aux & PHY_B_AS_PAUSE_MSK) {
                 case PHY_B_AS_PAUSE_MSK:
                         skge->flow_status = FLOW_STAT_SYMMETRIC;
                         break;
                 case PHY_B_AS_PRR:
                         skge->flow_status = FLOW_STAT_REM_SEND;
                         break;
                 case PHY_B_AS_PRT:
                         skge->flow_status = FLOW_STAT_LOC_SEND;
                         break;
                 default:
                         skge->flow_status = FLOW_STAT_NONE;
                 }
                 skge->speed = SPEED_1000;
         }
 
         if (!netdev_link_ok(dev))
                 genesis_link_up(skge);
 }

References skge_port::autoneg, AUTONEG_ENABLE, DBG, net_device::dev, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, genesis_link_up(), net_device::name, netdev_link_ok(), PFX, PHY_B_AN_RF, PHY_B_AS_AN_RES_MSK, PHY_B_AS_PAUSE_MSK, PHY_B_AS_PRR, PHY_B_AS_PRT, PHY_B_RES_1000FD, PHY_B_RES_1000HD, PHY_BCOM_AUX_STAT, PHY_BCOM_STAT, PHY_ST_AN_OVER, PHY_ST_LSYNC, PHY_XMAC_AUNE_LP, port, net_device::priv, skge_port::speed, SPEED_1000, status, xm_link_down(), and xm_phy_read().

Referenced by bcom_phy_intr(), and genesis_mac_init().

◆ bcom_phy_init()

static void bcom_phy_init ( struct skge_port * skge )

static

Definition at line 621 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         unsigned int i;
         u16 id1, r, ext, ctl;
 
         /* magic workaround patterns for Broadcom */
         static const struct {
                 u16 reg;
                 u16 val;
         } A1hack[] = {
                 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
                 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
                 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
                 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
         }, C0hack[] = {
                 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
                 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
         };
 
         /* read Id from external PHY (all have the same address) */
         id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
 
         /* Optimize MDIO transfer by suppressing preamble. */
         r = xm_read16(hw, port, XM_MMU_CMD);
         r |=  XM_MMU_NO_PRE;
         xm_write16(hw, port, XM_MMU_CMD,r);
 
         switch (id1) {
         case PHY_BCOM_ID1_C0:
                 /*
                  * Workaround BCOM Errata for the C0 type.
                  * Write magic patterns to reserved registers.
                  */
                 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
                         xm_phy_write(hw, port,
                                      C0hack[i].reg, C0hack[i].val);
 
                 break;
         case PHY_BCOM_ID1_A1:
                 /*
                  * Workaround BCOM Errata for the A1 type.
                  * Write magic patterns to reserved registers.
                  */
                 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
                         xm_phy_write(hw, port,
                                      A1hack[i].reg, A1hack[i].val);
                 break;
         }
 
         /*
          * Workaround BCOM Errata (#10523) for all BCom PHYs.
          * Disable Power Management after reset.
          */
         r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
         r |= PHY_B_AC_DIS_PM;
         xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
 
         /* Dummy read */
         xm_read16(hw, port, XM_ISRC);
 
         ext = PHY_B_PEC_EN_LTR; /* enable tx led */
         ctl = PHY_CT_SP1000;    /* always 1000mbit */
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 /*
                  * Workaround BCOM Errata #1 for the C5 type.
                  * 1000Base-T Link Acquisition Failure in Slave Mode
                  * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
                  */
                 u16 adv = PHY_B_1000C_RD;
                 if (skge->advertising & ADVERTISED_1000baseT_Half)
                         adv |= PHY_B_1000C_AHD;
                 if (skge->advertising & ADVERTISED_1000baseT_Full)
                         adv |= PHY_B_1000C_AFD;
                 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
 
                 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
         } else {
                 if (skge->duplex == DUPLEX_FULL)
                         ctl |= PHY_CT_DUP_MD;
                 /* Force to slave */
                 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
         }
 
         /* Set autonegotiation pause parameters */
         xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
                      phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
 
         xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
         xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
 
         /* Use link status change interrupt */
         xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
 }

References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, skge_port::advertising, ARRAY_SIZE, skge_port::autoneg, AUTONEG_ENABLE, skge_port::duplex, DUPLEX_FULL, ext, skge_port::flow_control, skge_port::hw, PHY_AN_CSMA, PHY_B_1000C_AFD, PHY_B_1000C_AHD, PHY_B_1000C_MSE, PHY_B_1000C_RD, PHY_B_AC_DIS_PM, PHY_B_DEF_MSK, PHY_B_PEC_EN_LTR, PHY_BCOM_1000T_CTRL, PHY_BCOM_AUNE_ADV, PHY_BCOM_AUX_CTRL, PHY_BCOM_CTRL, PHY_BCOM_ID1_A1, PHY_BCOM_ID1_C0, PHY_BCOM_INT_MASK, PHY_BCOM_P_EXT_CTRL, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_CT_SP1000, phy_pause_map, PHY_XMAC_ID1, port, skge_port::port, r, reg, val, XM_ISRC, XM_MMU_CMD, XM_MMU_NO_PRE, xm_phy_read(), xm_phy_write(), xm_read16(), and xm_write16().

Referenced by genesis_mac_init().

◆ xm_phy_init()

static void xm_phy_init ( struct skge_port * skge )

static

Definition at line 718 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 ctrl = 0;
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 if (skge->advertising & ADVERTISED_1000baseT_Half)
                         ctrl |= PHY_X_AN_HD;
                 if (skge->advertising & ADVERTISED_1000baseT_Full)
                         ctrl |= PHY_X_AN_FD;
 
                 ctrl |= fiber_pause_map[skge->flow_control];
 
                 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
 
                 /* Restart Auto-negotiation */
                 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
         } else {
                 /* Set DuplexMode in Config register */
                 if (skge->duplex == DUPLEX_FULL)
                         ctrl |= PHY_CT_DUP_MD;
                 /*
                  * Do NOT enable Auto-negotiation here. This would hold
                  * the link down because no IDLEs are transmitted
                  */
         }
 
         xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
 
         /* Poll PHY for status changes */
         skge->use_xm_link_timer = 1;
 }

References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, skge_port::advertising, skge_port::autoneg, AUTONEG_ENABLE, ctrl, skge_port::duplex, DUPLEX_FULL, fiber_pause_map, skge_port::flow_control, skge_port::hw, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_X_AN_FD, PHY_X_AN_HD, PHY_XMAC_AUNE_ADV, PHY_XMAC_CTRL, port, skge_port::port, skge_port::use_xm_link_timer, and xm_phy_write().

Referenced by genesis_mac_init().

◆ xm_check_link()

static int xm_check_link ( struct net_device * dev )

static

Definition at line 752 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 status;
 
         /* read twice because of latch */
         xm_phy_read(hw, port, PHY_XMAC_STAT);
         status = xm_phy_read(hw, port, PHY_XMAC_STAT);
 
         if ((status & PHY_ST_LSYNC) == 0) {
                 xm_link_down(hw, port);
                 return 0;
         }
 
         if (skge->autoneg == AUTONEG_ENABLE) {
                 u16 lpa, res;
 
                 if (!(status & PHY_ST_AN_OVER))
                         return 0;
 
                 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
                 if (lpa & PHY_B_AN_RF) {
                         DBG(PFX "%s: remote fault\n",
                                dev->name);
                         return 0;
                 }
 
                 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
 
                 /* Check Duplex mismatch */
                 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
                 case PHY_X_RS_FD:
                         skge->duplex = DUPLEX_FULL;
                         break;
                 case PHY_X_RS_HD:
                         skge->duplex = DUPLEX_HALF;
                         break;
                 default:
                         DBG(PFX "%s: duplex mismatch\n",
                                dev->name);
                         return 0;
                 }
 
                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
                 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
                      skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
                     (lpa & PHY_X_P_SYM_MD))
                         skge->flow_status = FLOW_STAT_SYMMETRIC;
                 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
                          (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
                         /* Enable PAUSE receive, disable PAUSE transmit */
                         skge->flow_status  = FLOW_STAT_REM_SEND;
                 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
                          (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
                         /* Disable PAUSE receive, enable PAUSE transmit */
                         skge->flow_status = FLOW_STAT_LOC_SEND;
                 else
                         skge->flow_status = FLOW_STAT_NONE;
 
                 skge->speed = SPEED_1000;
         }
 
         if (!netdev_link_ok(dev))
                 genesis_link_up(skge);
         return 1;
 }

References skge_port::autoneg, AUTONEG_ENABLE, DBG, skge_hw::dev, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, skge_port::flow_control, FLOW_MODE_LOC_SEND, FLOW_MODE_SYM_OR_REM, FLOW_MODE_SYMMETRIC, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, genesis_link_up(), skge_port::hw, net_device::name, netdev_link_ok(), PFX, PHY_B_AN_RF, PHY_ST_AN_OVER, PHY_ST_LSYNC, PHY_X_P_ASYM_MD, PHY_X_P_BOTH_MD, PHY_X_P_SYM_MD, PHY_X_RS_FD, PHY_X_RS_HD, PHY_X_RS_PAUSE, PHY_XMAC_AUNE_LP, PHY_XMAC_RES_ABI, PHY_XMAC_STAT, port, skge_port::port, net_device::priv, skge_port::speed, SPEED_1000, status, xm_link_down(), and xm_phy_read().

Referenced by xm_link_timer().

◆ xm_link_timer()

static void xm_link_timer ( struct skge_port * skge )

static

Definition at line 827 of file skge.c.

 {
         struct net_device *dev = skge->netdev;
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         int i;
 
         /*
          * Verify that the link by checking GPIO register three times.
          * This pin has the signal from the link_sync pin connected to it.
          */
         for (i = 0; i < 3; i++) {
                 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
                         return;
         }
 
         /* Re-enable interrupt to detect link down */
         if (xm_check_link(dev)) {
                 u16 msk = xm_read16(hw, port, XM_IMSK);
                 msk &= ~XM_IS_INP_ASS;
                 xm_write16(hw, port, XM_IMSK, msk);
                 xm_read16(hw, port, XM_ISRC);
         }
 }

References net_device::dev, skge_hw::dev, skge_port::hw, skge_port::netdev, port, skge_port::port, xm_check_link(), XM_GP_INP_ASS, XM_GP_PORT, XM_IMSK, XM_IS_INP_ASS, XM_ISRC, xm_read16(), and xm_write16().

Referenced by skge_poll().

◆ genesis_stop()

static void genesis_stop ( struct skge_port * skge )

static

Definition at line 998 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         unsigned retries = 1000;
         u16 cmd;
 
         /* Disable Tx and Rx */
         cmd = xm_read16(hw, port, XM_MMU_CMD);
         cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
         xm_write16(hw, port, XM_MMU_CMD, cmd);
 
         genesis_reset(hw, port);
 
         /* Clear Tx packet arbiter timeout IRQ */
         skge_write16(hw, B3_PA_CTRL,
                      port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
 
         /* Reset the MAC */
         skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
         do {
                 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
                 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
                         break;
         } while (--retries > 0);
 
         /* For external PHYs there must be special handling */
         if (hw->phy_type != SK_PHY_XMAC) {
                 u32 reg = skge_read32(hw, B2_GP_IO);
                 if (port == 0) {
                         reg |= GP_DIR_0;
                         reg &= ~GP_IO_0;
                 } else {
                         reg |= GP_DIR_2;
                         reg &= ~GP_IO_2;
                 }
                 skge_write32(hw, B2_GP_IO, reg);
                 skge_read32(hw, B2_GP_IO);
         }
 
         xm_write16(hw, port, XM_MMU_CMD,
                         xm_read16(hw, port, XM_MMU_CMD)
                         & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
 
         xm_read16(hw, port, XM_MMU_CMD);
 }

References B2_GP_IO, B3_PA_CTRL, cmd, genesis_reset(), GP_DIR_0, GP_DIR_2, GP_IO_0, GP_IO_2, skge_port::hw, MFF_CLR_MAC_RST, MFF_SET_MAC_RST, PA_CLR_TO_TX1, PA_CLR_TO_TX2, port, skge_port::port, reg, SK_PHY_XMAC, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), TX_MFF_CTRL1, XM_MMU_CMD, XM_MMU_ENA_RX, XM_MMU_ENA_TX, xm_read16(), and xm_write16().

Referenced by skge_down().

◆ bcom_phy_intr()

static void bcom_phy_intr ( struct skge_port * skge )

inlinestatic

Definition at line 1129 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 isrc;
 
         isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
         DBGIO(PFX "%s: phy interrupt status 0x%x\n",
              skge->netdev->name, isrc);
 
         if (isrc & PHY_B_IS_PSE)
                 DBG(PFX "%s: uncorrectable pair swap error\n",
                     hw->dev[port]->name);
 
         /* Workaround BCom Errata:
          *      enable and disable loopback mode if "NO HCD" occurs.
          */
         if (isrc & PHY_B_IS_NO_HDCL) {
                 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
                 xm_phy_write(hw, port, PHY_BCOM_CTRL,
                                   ctrl | PHY_CT_LOOP);
                 xm_phy_write(hw, port, PHY_BCOM_CTRL,
                                   ctrl & ~PHY_CT_LOOP);
         }
 
         if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
                 bcom_check_link(hw, port);
 
 }

References bcom_check_link(), ctrl, DBG, DBGIO, skge_port::hw, net_device::name, skge_port::netdev, PFX, PHY_B_IS_AN_PR, PHY_B_IS_LST_CHANGE, PHY_B_IS_NO_HDCL, PHY_B_IS_PSE, PHY_BCOM_CTRL, PHY_BCOM_INT_STAT, PHY_CT_LOOP, port, skge_port::port, xm_phy_read(), and xm_phy_write().

Referenced by skge_phyirq().

◆ __gm_phy_read()

static int __gm_phy_read	(	struct skge_hw *	hw,
		int	port,
		u16	reg,
		u16 *	val
	)

static

Definition at line 1179 of file skge.c.

 {
         int i;
 
         gma_write16(hw, port, GM_SMI_CTRL,
                          GM_SMI_CT_PHY_AD(hw->phy_addr)
                          | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
 
         for (i = 0; i < PHY_RETRIES; i++) {
                 udelay(1);
                 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
                         goto ready;
         }
 
         return -ETIMEDOUT;
  ready:
         *val = gma_read16(hw, port, GM_SMI_DATA);
         return 0;
 }

References ETIMEDOUT, GM_SMI_CT_OP_RD, GM_SMI_CT_PHY_AD, GM_SMI_CT_RD_VAL, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), PHY_RETRIES, port, reg, udelay(), and val.

Referenced by gm_phy_read().

◆ gm_phy_read()

static u16 gm_phy_read	(	struct skge_hw *	hw,
		int	port,
		u16	reg
	)

static

Definition at line 1199 of file skge.c.

 {
         u16 v = 0;
         if (__gm_phy_read(hw, port, reg, &v))
                 DBG(PFX "%s: phy read timeout port %x reg %x val %x\n",
                hw->dev[port]->name,
                port, reg, v);
         return v;
 }

References __gm_phy_read(), DBG, PFX, port, and reg.

Referenced by yukon_init(), yukon_link_down(), yukon_phy_intr(), and yukon_suspend().

◆ yukon_reset()

static void yukon_reset	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 1297 of file skge.c.

 {
         gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
         gma_write16(hw, port, GM_MC_ADDR_H1, 0);        /* clear MC hash */
         gma_write16(hw, port, GM_MC_ADDR_H2, 0);
         gma_write16(hw, port, GM_MC_ADDR_H3, 0);
         gma_write16(hw, port, GM_MC_ADDR_H4, 0);
 
         gma_write16(hw, port, GM_RX_CTRL,
                          gma_read16(hw, port, GM_RX_CTRL)
                          | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
 }

References GM_MC_ADDR_H1, GM_MC_ADDR_H2, GM_MC_ADDR_H3, GM_MC_ADDR_H4, gm_phy_write(), GM_RX_CTRL, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, gma_read16(), gma_write16(), PHY_MARV_INT_MASK, and port.

Referenced by skge_reset(), and yukon_stop().

◆ is_yukon_lite_a0()

static int is_yukon_lite_a0 ( struct skge_hw * hw )

static

Definition at line 1311 of file skge.c.

 {
         u32 reg;
         int ret;
 
         if (hw->chip_id != CHIP_ID_YUKON)
                 return 0;
 
         reg = skge_read32(hw, B2_FAR);
         skge_write8(hw, B2_FAR + 3, 0xff);
         ret = (skge_read8(hw, B2_FAR + 3) != 0);
         skge_write32(hw, B2_FAR, reg);
         return ret;
 }

References B2_FAR, CHIP_ID_YUKON, reg, skge_read32(), skge_read8(), skge_write32(), and skge_write8().

Referenced by yukon_mac_init().

◆ yukon_mac_init()

static void yukon_mac_init	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 1326 of file skge.c.

 {
         struct skge_port *skge = hw->dev[port]->priv;
         int i;
         u32 reg;
         const u8 *addr = hw->dev[port]->ll_addr;
 
         /* WA code for COMA mode -- set PHY reset */
         if (hw->chip_id == CHIP_ID_YUKON_LITE &&
             hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
                 reg = skge_read32(hw, B2_GP_IO);
                 reg |= GP_DIR_9 | GP_IO_9;
                 skge_write32(hw, B2_GP_IO, reg);
         }
 
         /* hard reset */
         skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
         skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 
         /* WA code for COMA mode -- clear PHY reset */
         if (hw->chip_id == CHIP_ID_YUKON_LITE &&
             hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
                 reg = skge_read32(hw, B2_GP_IO);
                 reg |= GP_DIR_9;
                 reg &= ~GP_IO_9;
                 skge_write32(hw, B2_GP_IO, reg);
         }
 
         /* Set hardware config mode */
         reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
                 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
         reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
 
         /* Clear GMC reset */
         skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
         skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
         skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
 
         if (skge->autoneg == AUTONEG_DISABLE) {
                 reg = GM_GPCR_AU_ALL_DIS;
                 gma_write16(hw, port, GM_GP_CTRL,
                                  gma_read16(hw, port, GM_GP_CTRL) | reg);
 
                 switch (skge->speed) {
                 case SPEED_1000:
                         reg &= ~GM_GPCR_SPEED_100;
                         reg |= GM_GPCR_SPEED_1000;
                         break;
                 case SPEED_100:
                         reg &= ~GM_GPCR_SPEED_1000;
                         reg |= GM_GPCR_SPEED_100;
                         break;
                 case SPEED_10:
                         reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
                         break;
                 }
 
                 if (skge->duplex == DUPLEX_FULL)
                         reg |= GM_GPCR_DUP_FULL;
         } else
                 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
 
         switch (skge->flow_control) {
         case FLOW_MODE_NONE:
                 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
                 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
                 break;
         case FLOW_MODE_LOC_SEND:
                 /* disable Rx flow-control */
                 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
                 break;
         case FLOW_MODE_SYMMETRIC:
         case FLOW_MODE_SYM_OR_REM:
                 /* enable Tx & Rx flow-control */
                 break;
         }
 
         gma_write16(hw, port, GM_GP_CTRL, reg);
         skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
 
         yukon_init(hw, port);
 
         /* MIB clear */
         reg = gma_read16(hw, port, GM_PHY_ADDR);
         gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
 
         for (i = 0; i < GM_MIB_CNT_SIZE; i++)
                 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
         gma_write16(hw, port, GM_PHY_ADDR, reg);
 
         /* transmit control */
         gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
 
         /* receive control reg: unicast + multicast + no FCS  */
         gma_write16(hw, port, GM_RX_CTRL,
                          GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
 
         /* transmit flow control */
         gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
 
         /* transmit parameter */
         gma_write16(hw, port, GM_TX_PARAM,
                          TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
                          TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
                          TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
 
         /* configure the Serial Mode Register */
         reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
                 | GM_SMOD_VLAN_ENA
                 | IPG_DATA_VAL(IPG_DATA_DEF);
 
         gma_write16(hw, port, GM_SERIAL_MODE, reg);
 
         /* physical address: used for pause frames */
         gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
         /* virtual address for data */
         gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
 
         /* enable interrupt mask for counter overflows */
         gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
         gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
         gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
 
         /* Initialize Mac Fifo */
 
         /* Configure Rx MAC FIFO */
         skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
         reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
 
         /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
         if (is_yukon_lite_a0(hw))
                 reg &= ~GMF_RX_F_FL_ON;
 
         skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
         skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
         /*
          * because Pause Packet Truncation in GMAC is not working
          * we have to increase the Flush Threshold to 64 bytes
          * in order to flush pause packets in Rx FIFO on Yukon-1
          */
         skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
 
         /* Configure Tx MAC FIFO */
         skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
         skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
 }

References addr, skge_port::autoneg, AUTONEG_DISABLE, B2_GP_IO, CHIP_ID_YUKON_LITE, CHIP_REV_YU_LITE_A3, DATA_BLIND_DEF, DATA_BLIND_VAL, skge_port::duplex, DUPLEX_FULL, skge_port::flow_control, FLOW_MODE_LOC_SEND, FLOW_MODE_NONE, FLOW_MODE_SYM_OR_REM, FLOW_MODE_SYMMETRIC, GM_GP_CTRL, GM_GPCR_AU_ALL_DIS, GM_GPCR_AU_FCT_DIS, GM_GPCR_DUP_FULL, GM_GPCR_FC_RX_DIS, GM_GPCR_FC_TX_DIS, GM_GPCR_SPEED_100, GM_GPCR_SPEED_1000, GM_MIB_CNT_BASE, GM_MIB_CNT_SIZE, GM_PAR_MIB_CLR, GM_PHY_ADDR, GM_RX_CTRL, GM_RX_IRQ_MSK, GM_RXCR_CRC_DIS, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, GM_SERIAL_MODE, GM_SMOD_VLAN_ENA, GM_SRC_ADDR_1L, GM_SRC_ADDR_2L, GM_TR_IRQ_MSK, GM_TX_CTRL, GM_TX_FLOW_CTRL, GM_TX_IRQ_MSK, GM_TX_PARAM, gma_read16(), gma_set_addr(), gma_write16(), GMAC_CTRL, GMAC_IRQ_SRC, GMC_PAUSE_OFF, GMC_PAUSE_ON, GMC_RST_CLR, GMC_RST_SET, GMF_OPER_ON, GMF_RST_CLR, GMF_RX_F_FL_ON, GP_DIR_9, GP_IO_9, GPC_ANEG_ADV_ALL_M, GPC_DIS_FC, GPC_DIS_SLEEP, GPC_ENA_PAUSE, GPC_ENA_XC, GPC_HWCFG_GMII_COP, GPC_HWCFG_GMII_FIB, GPC_INT_POL_HI, GPC_RST_CLR, GPC_RST_SET, GPHY_CTRL, IPG_DATA_DEF, IPG_DATA_VAL, is_yukon_lite_a0(), port, reg, RX_FF_FL_DEF_MSK, RX_GMF_CTRL_T, RX_GMF_FL_MSK, RX_GMF_FL_THR, RX_GMF_FL_THR_DEF, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), skge_write8(), skge_port::speed, SPEED_10, SPEED_100, SPEED_1000, TX_COL_DEF, TX_COL_THR, TX_GMF_CTRL_T, TX_IPG_JAM_DATA, TX_IPG_JAM_DEF, TX_JAM_IPG_DEF, TX_JAM_IPG_VAL, TX_JAM_LEN_DEF, TX_JAM_LEN_VAL, and yukon_init().

Referenced by skge_up().

◆ yukon_suspend()

static void yukon_suspend	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 1474 of file skge.c.

 {
         u16 ctrl;
 
         ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
         ctrl |= PHY_M_PC_POL_R_DIS;
         gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 
         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
         ctrl |= PHY_CT_RESET;
         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 
         /* switch IEEE compatible power down mode on */
         ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
         ctrl |= PHY_CT_PDOWN;
         gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 }

References ctrl, gm_phy_read(), gm_phy_write(), PHY_CT_PDOWN, PHY_CT_RESET, PHY_M_PC_POL_R_DIS, PHY_MARV_CTRL, PHY_MARV_PHY_CTRL, and port.

Referenced by yukon_stop().

◆ yukon_stop()

static void yukon_stop ( struct skge_port * skge )

static

Definition at line 1492 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
 
         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
         yukon_reset(hw, port);
 
         gma_write16(hw, port, GM_GP_CTRL,
                          gma_read16(hw, port, GM_GP_CTRL)
                          & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
         gma_read16(hw, port, GM_GP_CTRL);
 
         yukon_suspend(hw, port);
 
         /* set GPHY Control reset */
         skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
 }

References GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gma_read16(), gma_write16(), GMAC_CTRL, GMAC_IRQ_MSK, GMC_RST_SET, GPC_RST_SET, GPHY_CTRL, skge_port::hw, port, skge_port::port, SK_REG, skge_write8(), yukon_reset(), and yukon_suspend().

Referenced by skge_down().

◆ yukon_speed()

static u16 yukon_speed	(	const struct skge_hw *hw	__unused,
		u16	aux
	)

static

Definition at line 1512 of file skge.c.

 {
         switch (aux & PHY_M_PS_SPEED_MSK) {
         case PHY_M_PS_SPEED_1000:
                 return SPEED_1000;
         case PHY_M_PS_SPEED_100:
                 return SPEED_100;
         default:
                 return SPEED_10;
         }
 }

References PHY_M_PS_SPEED_100, PHY_M_PS_SPEED_1000, PHY_M_PS_SPEED_MSK, SPEED_10, SPEED_100, and SPEED_1000.

Referenced by yukon_phy_intr().

◆ yukon_link_up()

static void yukon_link_up ( struct skge_port * skge )

static

Definition at line 1524 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 reg;
 
         /* Enable Transmit FIFO Underrun */
         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
 
         reg = gma_read16(hw, port, GM_GP_CTRL);
         if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
                 reg |= GM_GPCR_DUP_FULL;
 
         /* enable Rx/Tx */
         reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
         gma_write16(hw, port, GM_GP_CTRL, reg);
 
         gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
         skge_link_up(skge);
 }

References skge_port::autoneg, AUTONEG_ENABLE, skge_port::duplex, DUPLEX_FULL, GM_GP_CTRL, GM_GPCR_DUP_FULL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_write(), gma_read16(), gma_write16(), GMAC_DEF_MSK, GMAC_IRQ_MSK, skge_port::hw, PHY_M_IS_DEF_MSK, PHY_MARV_INT_MASK, port, skge_port::port, reg, SK_REG, skge_link_up(), and skge_write8().

Referenced by yukon_phy_intr().

◆ yukon_link_down()

static void yukon_link_down ( struct skge_port * skge )

static

Definition at line 1545 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         u16 ctrl;
 
         ctrl = gma_read16(hw, port, GM_GP_CTRL);
         ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
         gma_write16(hw, port, GM_GP_CTRL, ctrl);
 
         if (skge->flow_status == FLOW_STAT_REM_SEND) {
                 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
                 ctrl |= PHY_M_AN_ASP;
                 /* restore Asymmetric Pause bit */
                 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
         }
 
         skge_link_down(skge);
 
         yukon_init(hw, port);
 }

References ctrl, FLOW_STAT_REM_SEND, skge_port::flow_status, GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_read(), gm_phy_write(), gma_read16(), gma_write16(), skge_port::hw, PHY_M_AN_ASP, PHY_MARV_AUNE_ADV, port, skge_port::port, skge_link_down(), and yukon_init().

Referenced by yukon_phy_intr().

◆ yukon_phy_intr()

static void yukon_phy_intr ( struct skge_port * skge )

static

Definition at line 1567 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         int port = skge->port;
         const char *reason = NULL;
         u16 istatus, phystat;
 
         istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
         phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
 
         DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
              skge->netdev->name, istatus, phystat);
 
         if (istatus & PHY_M_IS_AN_COMPL) {
                 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
                     & PHY_M_AN_RF) {
                         reason = "remote fault";
                         goto failed;
                 }
 
                 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
                         reason = "master/slave fault";
                         goto failed;
                 }
 
                 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
                         reason = "speed/duplex";
                         goto failed;
                 }
 
                 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
                         ? DUPLEX_FULL : DUPLEX_HALF;
                 skge->speed = yukon_speed(hw, phystat);
 
                 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
                 switch (phystat & PHY_M_PS_PAUSE_MSK) {
                 case PHY_M_PS_PAUSE_MSK:
                         skge->flow_status = FLOW_STAT_SYMMETRIC;
                         break;
                 case PHY_M_PS_RX_P_EN:
                         skge->flow_status = FLOW_STAT_REM_SEND;
                         break;
                 case PHY_M_PS_TX_P_EN:
                         skge->flow_status = FLOW_STAT_LOC_SEND;
                         break;
                 default:
                         skge->flow_status = FLOW_STAT_NONE;
                 }
 
                 if (skge->flow_status == FLOW_STAT_NONE ||
                     (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
                         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
                 else
                         skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
                 yukon_link_up(skge);
                 return;
         }
 
         if (istatus & PHY_M_IS_LSP_CHANGE)
                 skge->speed = yukon_speed(hw, phystat);
 
         if (istatus & PHY_M_IS_DUP_CHANGE)
                 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
         if (istatus & PHY_M_IS_LST_CHANGE) {
                 if (phystat & PHY_M_PS_LINK_UP)
                         yukon_link_up(skge);
                 else
                         yukon_link_down(skge);
         }
         return;
  failed:
         DBG(PFX "%s: autonegotiation failed (%s)\n",
                skge->netdev->name, reason);
 
         /* XXX restart autonegotiation? */
 }

References DBG, DBGIO, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, gm_phy_read(), GMAC_CTRL, GMC_PAUSE_OFF, GMC_PAUSE_ON, skge_port::hw, net_device::name, skge_port::netdev, NULL, PFX, PHY_B_1000S_MSF, PHY_M_AN_RF, PHY_M_IS_AN_COMPL, PHY_M_IS_DUP_CHANGE, PHY_M_IS_LSP_CHANGE, PHY_M_IS_LST_CHANGE, PHY_M_PS_FULL_DUP, PHY_M_PS_LINK_UP, PHY_M_PS_PAUSE_MSK, PHY_M_PS_RX_P_EN, PHY_M_PS_SPDUP_RES, PHY_M_PS_TX_P_EN, PHY_MARV_1000T_STAT, PHY_MARV_AUNE_LP, PHY_MARV_INT_STAT, PHY_MARV_PHY_STAT, port, skge_port::port, reason, SK_REG, skge_write8(), skge_port::speed, SPEED_1000, yukon_link_down(), yukon_link_up(), and yukon_speed().

Referenced by skge_phyirq().

◆ skge_ramset()

static void skge_ramset	(	struct skge_hw *	hw,
		u16	q,
		u32	start,
		size_t	len
	)

static

Definition at line 1644 of file skge.c.

 {
         u32 end;
 
         start /= 8;
         len /= 8;
         end = start + len - 1;
 
         skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
         skge_write32(hw, RB_ADDR(q, RB_START), start);
         skge_write32(hw, RB_ADDR(q, RB_WP), start);
         skge_write32(hw, RB_ADDR(q, RB_RP), start);
         skge_write32(hw, RB_ADDR(q, RB_END), end);
 
         if (q == Q_R1 || q == Q_R2) {
                 /* Set thresholds on receive queue's */
                 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
                              start + (2*len)/3);
                 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
                              start + (len/3));
         } else {
                 /* Enable store & forward on Tx queue's because
                  * Tx FIFO is only 4K on Genesis and 1K on Yukon
                  */
                 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
         }
 
         skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
 }

References end, len, Q_R1, Q_R2, RB_ADDR, RB_CTRL, RB_ENA_OP_MD, RB_ENA_STFWD, RB_END, RB_RP, RB_RST_CLR, RB_RX_LTPP, RB_RX_UTPP, RB_START, RB_WP, skge_write32(), skge_write8(), and start.

Referenced by skge_up().

◆ skge_qset()

static void skge_qset	(	struct skge_port *	skge,
		u16	q,
		const struct skge_element *	e
	)

static

Definition at line 1675 of file skge.c.

 {
         struct skge_hw *hw = skge->hw;
         u32 watermark = 0x600;
         u64 base = skge->dma + (e->desc - skge->mem);
 
         /* optimization to reduce window on 32bit/33mhz */
         if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
                 watermark /= 2;
 
         skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
         skge_write32(hw, Q_ADDR(q, Q_F), watermark);
         skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
         skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
 }

References B0_CTST, base, CS_BUS_CLOCK, CS_BUS_SLOT_SZ, CSR_CLR_RESET, skge_element::desc, skge_port::dma, skge_port::hw, skge_port::mem, Q_ADDR, Q_CSR, Q_DA_H, Q_DA_L, Q_F, skge_read16(), and skge_write32().

Referenced by skge_up().

◆ skge_free()

void skge_free ( struct net_device * dev )

Definition at line 1692 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
 
         free(skge->rx_ring.start);
         skge->rx_ring.start = NULL;
 
         free(skge->tx_ring.start);
         skge->tx_ring.start = NULL;
 
         free_phys(skge->mem, RING_SIZE);
         skge->mem = NULL;
         skge->dma = 0;
 }

References skge_port::dma, free, free_phys(), skge_port::mem, NULL, net_device::priv, RING_SIZE, skge_port::rx_ring, skge_ring::start, and skge_port::tx_ring.

Referenced by skge_down(), and skge_up().

◆ skge_rx_stop()

static void skge_rx_stop	(	struct skge_hw *	hw,
		int	port
	)

static

Definition at line 1782 of file skge.c.

 {
         skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
         skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
                      RB_RST_SET|RB_DIS_OP_MD);
         skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
 }

References CSR_SET_RESET, CSR_STOP, port, Q_ADDR, Q_CSR, Q_R1, Q_R2, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, RB_RST_SET, rxqaddr, skge_write32(), and skge_write8().

Referenced by skge_down().

◆ skge_tx_avail()

static int skge_tx_avail ( const struct skge_ring * ring )

inlinestatic

Definition at line 1856 of file skge.c.

 {
         mb();
         return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC)
                 + (ring->to_clean - ring->to_use) - 1;
 }

References mb(), NUM_TX_DESC, skge_ring::to_clean, and skge_ring::to_use.

Referenced by skge_xmit_frame().

◆ phy_length()

static u16 phy_length	(	const struct skge_hw *	hw,
		u32	status
	)

inlinestatic

Definition at line 1922 of file skge.c.

 {
         if (hw->chip_id == CHIP_ID_GENESIS)
                 return status >> XMR_FS_LEN_SHIFT;
         else
                 return status >> GMR_FS_LEN_SHIFT;
 }

References CHIP_ID_GENESIS, GMR_FS_LEN_SHIFT, status, and XMR_FS_LEN_SHIFT.

Referenced by skge_rx_done().

◆ bad_phy_status()

static int bad_phy_status	(	const struct skge_hw *	hw,
		u32	status
	)

inlinestatic

Definition at line 1930 of file skge.c.

 {
         if (hw->chip_id == CHIP_ID_GENESIS)
                 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
         else
                 return (status & GMR_FS_ANY_ERR) ||
                         (status & GMR_FS_RX_OK) == 0;
 }

References CHIP_ID_GENESIS, GMR_FS_ANY_ERR, GMR_FS_RX_OK, status, XMR_FS_2L_VLAN, and XMR_FS_ERR.

Referenced by skge_rx_done().

◆ skge_tx_done()

static void skge_tx_done ( struct net_device * dev )

static

Definition at line 1940 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_ring *ring = &skge->tx_ring;
         struct skge_element *e;
 
         skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
 
         for (e = ring->to_clean; e != ring->to_use; e = e->next) {
                 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
 
                 if (control & BMU_OWN)
                         break;
 
                 netdev_tx_complete(dev, e->iob);
         }
         skge->tx_ring.to_clean = e;
 
         /* Can run lockless until we need to synchronize to restart queue. */
         mb();
 }

References BMU_OWN, control, CSR_IRQ_CL_F, skge_element::desc, skge_port::hw, skge_element::iob, mb(), netdev_tx_complete(), skge_element::next, skge_port::port, net_device::priv, Q_ADDR, Q_CSR, skge_write8(), skge_ring::to_clean, skge_ring::to_use, skge_port::tx_ring, and txqaddr.

Referenced by skge_poll().

◆ skge_rx_done()

static void skge_rx_done ( struct net_device * dev )

static

Definition at line 2004 of file skge.c.

 {
         struct skge_port *skge = dev->priv;
         struct skge_ring *ring = &skge->rx_ring;
         struct skge_rx_desc *rd;
         struct skge_element *e;
         struct io_buffer *iob;
         u32 control;
         u16 len;
         int i;
 
         e = ring->to_clean;
         for (i = 0; i < NUM_RX_DESC; i++) {
                 iob = e->iob;
                 rd = e->desc;
 
                 rmb();
                 control = rd->control;
 
                 if ((control & BMU_OWN))
                         break;
 
                 if (!iob)
                         continue;
 
                 len = control & BMU_BBC;
 
                 /* catch RX errors */
                 if ((bad_phy_status(skge->hw, rd->status)) ||
                    (phy_length(skge->hw, rd->status) != len)) {
                         /* report receive errors */
                         DBG("rx error\n");
                         netdev_rx_err(dev, iob, -EIO);
                 } else {
                         DBG2("received packet, len %d\n", len);
                         iob_put(iob, len);
                         netdev_rx(dev, iob);
                 }
 
                 /* io_buffer passed to core, make sure we don't reuse it */
                 e->iob = NULL;
 
                 e = e->next;
         }
         skge_rx_refill(dev);
 }

References bad_phy_status(), BMU_BBC, BMU_OWN, control, skge_rx_desc::control, DBG, DBG2, skge_element::desc, EIO, skge_port::hw, skge_element::iob, iob_put, len, netdev_rx(), netdev_rx_err(), skge_element::next, NULL, NUM_RX_DESC, phy_length(), net_device::priv, rmb, skge_port::rx_ring, skge_rx_refill(), skge_rx_desc::status, and skge_ring::to_clean.

Referenced by skge_poll().

◆ skge_board_name()

static const char* skge_board_name ( const struct skge_hw * hw )

static

Definition at line 2111 of file skge.c.

 {
         unsigned int i;
         static char buf[16];
 
         for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
                 if (skge_chips[i].id == hw->chip_id)
                         return skge_chips[i].name;
 
         snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
         return buf;
 }

References ARRAY_SIZE, skge_chips, and snprintf().

Referenced by skge_probe().

◆ skge_reset()

static int skge_reset ( struct skge_hw * hw )

static

Definition at line 2129 of file skge.c.

 {
         u32 reg;
         u16 ctst, pci_status;
         u8 t8, mac_cfg, pmd_type;
         int i;
 
         ctst = skge_read16(hw, B0_CTST);
 
         /* do a SW reset */
         skge_write8(hw, B0_CTST, CS_RST_SET);
         skge_write8(hw, B0_CTST, CS_RST_CLR);
 
         /* clear PCI errors, if any */
         skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
         skge_write8(hw, B2_TST_CTRL2, 0);
 
         pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
         pci_write_config_word(hw->pdev, PCI_STATUS,
                               pci_status | PCI_STATUS_ERROR_BITS);
         skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
         skge_write8(hw, B0_CTST, CS_MRST_CLR);
 
         /* restore CLK_RUN bits (for Yukon-Lite) */
         skge_write16(hw, B0_CTST,
                      ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
 
         hw->chip_id = skge_read8(hw, B2_CHIP_ID);
         hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
         pmd_type = skge_read8(hw, B2_PMD_TYP);
         hw->copper = (pmd_type == 'T' || pmd_type == '1');
 
         switch (hw->chip_id) {
         case CHIP_ID_GENESIS:
                 switch (hw->phy_type) {
                 case SK_PHY_XMAC:
                         hw->phy_addr = PHY_ADDR_XMAC;
                         break;
                 case SK_PHY_BCOM:
                         hw->phy_addr = PHY_ADDR_BCOM;
                         break;
                 default:
                         DBG(PFX "unsupported phy type 0x%x\n",
                                hw->phy_type);
                         return -EOPNOTSUPP;
                 }
                 break;
 
         case CHIP_ID_YUKON:
         case CHIP_ID_YUKON_LITE:
         case CHIP_ID_YUKON_LP:
                 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
                         hw->copper = 1;
 
                 hw->phy_addr = PHY_ADDR_MARV;
                 break;
 
         default:
                 DBG(PFX "unsupported chip type 0x%x\n",
                        hw->chip_id);
                 return -EOPNOTSUPP;
         }
 
         mac_cfg = skge_read8(hw, B2_MAC_CFG);
         hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
         hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
 
         /* read the adapters RAM size */
         t8 = skge_read8(hw, B2_E_0);
         if (hw->chip_id == CHIP_ID_GENESIS) {
                 if (t8 == 3) {
                         /* special case: 4 x 64k x 36, offset = 0x80000 */
                         hw->ram_size = 0x100000;
                         hw->ram_offset = 0x80000;
                 } else
                         hw->ram_size = t8 * 512;
         }
         else if (t8 == 0)
                 hw->ram_size = 0x20000;
         else
                 hw->ram_size = t8 * 4096;
 
         hw->intr_mask = IS_HW_ERR;
 
         /* Use PHY IRQ for all but fiber based Genesis board */
         if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
                 hw->intr_mask |= IS_EXT_REG;
 
         if (hw->chip_id == CHIP_ID_GENESIS)
                 genesis_init(hw);
         else {
                 /* switch power to VCC (WA for VAUX problem) */
                 skge_write8(hw, B0_POWER_CTRL,
                             PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
 
                 /* avoid boards with stuck Hardware error bits */
                 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
                     (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
                         DBG(PFX "stuck hardware sensor bit\n");
                         hw->intr_mask &= ~IS_HW_ERR;
                 }
 
                 /* Clear PHY COMA */
                 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
                 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
                 reg &= ~PCI_PHY_COMA;
                 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
                 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 
 
                 for (i = 0; i < hw->ports; i++) {
                         skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
                         skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
                 }
         }
 
         /* turn off hardware timer (unused) */
         skge_write8(hw, B2_TI_CTRL, TIM_STOP);
         skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
         skge_write8(hw, B0_LED, LED_STAT_ON);
 
         /* enable the Tx Arbiters */
         for (i = 0; i < hw->ports; i++)
                 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
 
         /* Initialize ram interface */
         skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
 
         skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
         skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
         skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
         skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
         skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
 
         skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
 
         /* Set interrupt moderation for Transmit only
          * Receive interrupts avoided by NAPI
          */
         skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
         skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
         skge_write32(hw, B2_IRQM_CTRL, TIM_START);
 
         skge_write32(hw, B0_IMSK, hw->intr_mask);
 
         for (i = 0; i < hw->ports; i++) {
                 if (hw->chip_id == CHIP_ID_GENESIS)
                         genesis_reset(hw, i);
                 else
                         yukon_reset(hw, i);
         }
 
         return 0;
 }

References B0_CTST, B0_HWE_IMSK, B0_HWE_ISRC, B0_IMSK, B0_ISRC, B0_LED, B0_POWER_CTRL, B2_CHIP_ID, B2_E_0, B2_E_1, B2_IRQM_CTRL, B2_IRQM_INI, B2_IRQM_MSK, B2_MAC_CFG, B2_PMD_TYP, B2_TI_CTRL, B2_TST_CTRL1, B2_TST_CTRL2, B3_RI_CTRL, B3_RI_RTO_R1, B3_RI_RTO_R2, B3_RI_RTO_XA1, B3_RI_RTO_XA2, B3_RI_RTO_XS1, B3_RI_RTO_XS2, B3_RI_WTO_R1, B3_RI_WTO_R2, B3_RI_WTO_XA1, B3_RI_WTO_XA2, B3_RI_WTO_XS1, B3_RI_WTO_XS2, CFG_CHIP_R_MSK, CFG_SNG_MAC, CHIP_ID_GENESIS, CHIP_ID_YUKON, CHIP_ID_YUKON_LITE, CHIP_ID_YUKON_LP, CS_CLK_RUN_ENA, CS_CLK_RUN_HOT, CS_CLK_RUN_RST, CS_MRST_CLR, CS_RST_CLR, CS_RST_SET, DBG, EOPNOTSUPP, genesis_init(), genesis_reset(), GMAC_LINK_CTRL, GMLC_RST_CLR, GMLC_RST_SET, IS_ERR_MSK, IS_EXT_REG, IS_HW_ERR, IS_IRQ_SENSOR, IS_XA1_F, IS_XA2_F, LED_STAT_ON, PC_VAUX_ENA, PC_VAUX_OFF, PC_VCC_ENA, PC_VCC_ON, PCI_DEV_REG1, PCI_PHY_COMA, pci_read_config_dword(), pci_read_config_word(), PCI_STATUS, PCI_STATUS_ERROR_BITS, pci_write_config_dword(), pci_write_config_word(), PFX, PHY_ADDR_BCOM, PHY_ADDR_MARV, PHY_ADDR_XMAC, reg, RI_RST_CLR, SK_PHY_BCOM, SK_PHY_MARV_COPPER, SK_PHY_XMAC, SK_REG, SK_RI_TO_53, skge_read16(), skge_read32(), skge_read8(), skge_usecs2clk(), skge_write16(), skge_write32(), skge_write8(), TIM_CLR_IRQ, TIM_START, TIM_STOP, TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, TXA_CTRL, TXA_ENA_ARB, and yukon_reset().

Referenced by skge_probe().

◆ skge_devinit()

static struct net_device* skge_devinit	(	struct skge_hw *	hw,
		int	port,
		int highmem	__unused
	)

static

Definition at line 2292 of file skge.c.

 {
         struct skge_port *skge;
         struct net_device *dev = alloc_etherdev(sizeof(*skge));
 
         if (!dev) {
                 DBG(PFX "etherdev alloc failed\n");
                 return NULL;
         }
 
         dev->dev = &hw->pdev->dev;
 
         skge = dev->priv;
         skge->netdev = dev;
         skge->hw = hw;
 
         /* Auto speed and flow control */
         skge->autoneg = AUTONEG_ENABLE;
         skge->flow_control = FLOW_MODE_SYM_OR_REM;
         skge->duplex = -1;
         skge->speed = -1;
         skge->advertising = skge_supported_modes(hw);
 
         hw->dev[port] = dev;
 
         skge->port = port;
 
         /* read the mac address */
         memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN);
 
         return dev;
 }

References skge_port::advertising, alloc_etherdev(), skge_port::autoneg, AUTONEG_ENABLE, B2_MAC_1, DBG, net_device::dev, skge_port::duplex, ETH_ALEN, skge_port::flow_control, FLOW_MODE_SYM_OR_REM, skge_port::hw, memcpy(), skge_port::netdev, NULL, PFX, port, skge_port::port, skge_supported_modes(), and skge_port::speed.

Referenced by skge_probe().

◆ skge_show_addr()

static void skge_show_addr ( struct net_device * dev )

static

Definition at line 2326 of file skge.c.

 {
         DBG2(PFX "%s: addr %s\n",
              dev->name, netdev_addr(dev));
 }

References DBG2, net_device::dev, device::name, netdev_addr(), and PFX.

Referenced by skge_probe().

◆ skge_probe()

static int skge_probe ( struct pci_device * pdev )

static

Definition at line 2332 of file skge.c.

 {
         struct net_device *dev, *dev1;
         struct skge_hw *hw;
         int err, using_dac = 0;
 
         adjust_pci_device(pdev);
 
         err = -ENOMEM;
         hw = zalloc(sizeof(*hw));
         if (!hw) {
                 DBG(PFX "cannot allocate hardware struct\n");
                 goto err_out_free_regions;
         }
 
         hw->pdev = pdev;
 
         hw->regs = (unsigned long)pci_ioremap(pdev,
                                               pci_bar_start(pdev, PCI_BASE_ADDRESS_0),
                                               SKGE_REG_SIZE);
         if (!hw->regs) {
                 DBG(PFX "cannot map device registers\n");
                 goto err_out_free_hw;
         }
 
         err = skge_reset(hw);
         if (err)
                 goto err_out_iounmap;
 
         DBG(PFX " addr 0x%llx irq %d chip %s rev %d\n",
             (unsigned long long)pdev->ioaddr, pdev->irq,
             skge_board_name(hw), hw->chip_rev);
 
         dev = skge_devinit(hw, 0, using_dac);
         if (!dev)
                 goto err_out_led_off;
 
         netdev_init ( dev, &skge_operations );
 
         err = register_netdev(dev);
         if (err) {
                 DBG(PFX "cannot register net device\n");
                 goto err_out_free_netdev;
         }
 
         skge_show_addr(dev);
 
         if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
                 if (register_netdev(dev1) == 0)
                         skge_show_addr(dev1);
                 else {
                         /* Failure to register second port need not be fatal */
                         DBG(PFX "register of second port failed\n");
                         hw->dev[1] = NULL;
                         netdev_nullify(dev1);
                         netdev_put(dev1);
                 }
         }
         pci_set_drvdata(pdev, hw);
 
         return 0;
 
 err_out_free_netdev:
         netdev_nullify(dev);
         netdev_put(dev);
 err_out_led_off:
         skge_write16(hw, B0_LED, LED_STAT_OFF);
 err_out_iounmap:
         iounmap((void*)hw->regs);
 err_out_free_hw:
         free(hw);
 err_out_free_regions:
         pci_set_drvdata(pdev, NULL);
         return err;
 }

References adjust_pci_device(), B0_LED, DBG, net_device::dev, skge_hw::dev, ENOMEM, free, pci_device::ioaddr, iounmap(), pci_device::irq, LED_STAT_OFF, netdev_init(), netdev_nullify(), netdev_put(), NULL, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_ioremap(), pci_set_drvdata(), skge_hw::pdev, PFX, register_netdev(), skge_board_name(), skge_devinit(), skge_operations, SKGE_REG_SIZE, skge_reset(), skge_show_addr(), skge_write16(), and zalloc().

◆ skge_remove()

static void skge_remove ( struct pci_device * pdev )

static

Definition at line 2408 of file skge.c.

 {
         struct skge_hw *hw  = pci_get_drvdata(pdev);
         struct net_device *dev0, *dev1;
 
         if (!hw)
                 return;
 
         if ((dev1 = hw->dev[1]))
                 unregister_netdev(dev1);
         dev0 = hw->dev[0];
         unregister_netdev(dev0);
 
         hw->intr_mask = 0;
         skge_write32(hw, B0_IMSK, 0);
         skge_read32(hw, B0_IMSK);
 
         skge_write16(hw, B0_LED, LED_STAT_OFF);
         skge_write8(hw, B0_CTST, CS_RST_SET);
 
         if (dev1) {
                 netdev_nullify(dev1);
                 netdev_put(dev1);
         }
         netdev_nullify(dev0);
         netdev_put(dev0);
 
         iounmap((void*)hw->regs);
         free(hw);
         pci_set_drvdata(pdev, NULL);
 }

References B0_CTST, B0_IMSK, B0_LED, CS_RST_SET, free, iounmap(), LED_STAT_OFF, netdev_nullify(), netdev_put(), NULL, pci_get_drvdata(), pci_set_drvdata(), skge_hw::pdev, skge_read32(), skge_write16(), skge_write32(), skge_write8(), and unregister_netdev().

Variable Documentation

◆ skge_id_table

struct pci_device_id skge_id_table[]

static

Initial value:

= {
        PCI_ROM(0x10b7, 0x1700,     "3C940",     "3COM 3C940", 0),
        PCI_ROM(0x10b7, 0x80eb,     "3C940B",    "3COM 3C940", 0),
        PCI_ROM(0x1148, 0x4300,     "GE",        "Syskonnect GE", 0),
        PCI_ROM(0x1148, 0x4320,     "YU",        "Syskonnect YU", 0),
        PCI_ROM(0x1186, 0x4C00,     "DGE510T",   "DLink DGE-510T", 0),
        PCI_ROM(0x1186, 0x4b01,     "DGE530T",   "DLink DGE-530T", 0),
        PCI_ROM(0x11ab, 0x4320,     "id4320",    "Marvell id4320", 0),
        PCI_ROM(0x11ab, 0x5005,     "id5005",    "Marvell id5005", 0), 
        PCI_ROM(0x1371, 0x434e,     "Gigacard",  "CNET Gigacard", 0),
        PCI_ROM(0x1737, 0x1064,     "EG1064",    "Linksys EG1064", 0),
}

Definition at line 46 of file skge.c.

◆ skge_operations

struct net_device_operations skge_operations

static

Initial value:

= {
        .open     = skge_up,
        .close    = skge_down,
        .transmit = skge_xmit_frame,
        .poll     = skge_poll,
        .irq      = skge_net_irq
}

Definition at line 76 of file skge.c.

Referenced by skge_probe().

◆ txqaddr

const int txqaddr[] = { Q_XA1, Q_XA2 }

static

Definition at line 85 of file skge.c.

Referenced by skge_down(), skge_tx_done(), skge_up(), and skge_xmit_frame().

◆ rxqaddr

const int rxqaddr[] = { Q_R1, Q_R2 }

static

Definition at line 86 of file skge.c.

Referenced by skge_poll(), skge_rx_stop(), and skge_up().

◆ portmask

const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }

static

Definition at line 87 of file skge.c.

Referenced by skge_down(), skge_net_irq(), and skge_up().

◆ phy_pause_map

const u16 phy_pause_map[]

static

Initial value:

= {
        [FLOW_MODE_NONE] =      0,
        [FLOW_MODE_LOC_SEND] =  PHY_AN_PAUSE_ASYM,
        [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
        [FLOW_MODE_SYM_OR_REM]  = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
}

Definition at line 536 of file skge.c.

Referenced by bcom_phy_init(), and yukon_init().

◆ fiber_pause_map

const u16 fiber_pause_map[]

static

Initial value:

= {
        [FLOW_MODE_NONE]        = PHY_X_P_NO_PAUSE,
        [FLOW_MODE_LOC_SEND]    = PHY_X_P_ASYM_MD,
        [FLOW_MODE_SYMMETRIC]   = PHY_X_P_SYM_MD,
        [FLOW_MODE_SYM_OR_REM]  = PHY_X_P_BOTH_MD,
}

Definition at line 544 of file skge.c.

Referenced by xm_phy_init(), and yukon_init().

◆ id

u8 id

Definition at line 2102 of file skge.c.

◆ name

const char* name

Definition at line 2103 of file skge.c.

◆ skge_chips

const { ... } skge_chips[]

Initial value:

= {
        { CHIP_ID_GENESIS,      "Genesis" },
        { CHIP_ID_YUKON,         "Yukon" },
        { CHIP_ID_YUKON_LITE,    "Yukon-Lite"},
        { CHIP_ID_YUKON_LP,      "Yukon-LP"},
}

Referenced by skge_board_name().

◆ __pci_driver

struct pci_driver skge_driver __pci_driver

Initial value:

= {
        .ids      = skge_id_table,
        .id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),
        .probe    = skge_probe,
        .remove   = skge_remove
}

Definition at line 2459 of file skge.c.

Enumerations

Functions

Variables

Enumeration Type Documentation

◆ led_mode

Function Documentation

◆ FILE_LICENCE()

◆ skge_up()

◆ skge_down()

◆ skge_tx_clean()

◆ xm_phy_write()

◆ gm_phy_write()

◆ yukon_init()

◆ genesis_mac_init()

◆ genesis_link_up()

◆ skge_phyirq()

◆ skge_poll()

◆ skge_xmit_frame()

◆ skge_net_irq()

◆ skge_rx_refill()

◆ skge_supported_modes()

◆ hwkhz()

◆ skge_usecs2clk()

◆ skge_led()

◆ skge_ring_alloc()

◆ skge_rx_setup()

◆ skge_rx_reuse()

◆ skge_rx_clean()

◆ skge_link_up()

◆ skge_link_down()

◆ xm_link_down()

◆ __xm_phy_read()

◆ xm_phy_read()

◆ genesis_init()

◆ genesis_reset()

◆ bcom_check_link()

◆ bcom_phy_init()

◆ xm_phy_init()

◆ xm_check_link()

◆ xm_link_timer()

◆ genesis_stop()

◆ bcom_phy_intr()

◆ __gm_phy_read()

◆ gm_phy_read()

◆ yukon_reset()

◆ is_yukon_lite_a0()

◆ yukon_mac_init()

◆ yukon_suspend()

◆ yukon_stop()

◆ yukon_speed()

◆ yukon_link_up()

◆ yukon_link_down()

◆ yukon_phy_intr()

◆ skge_ramset()

◆ skge_qset()

◆ skge_free()

◆ skge_rx_stop()

◆ skge_tx_avail()

◆ phy_length()

◆ bad_phy_status()

◆ skge_tx_done()

◆ skge_rx_done()

◆ skge_board_name()

◆ skge_reset()

◆ skge_devinit()

◆ skge_show_addr()

◆ skge_probe()

◆ skge_remove()

Variable Documentation

◆ skge_id_table

◆ skge_operations

◆ txqaddr

◆ rxqaddr

◆ portmask

◆ phy_pause_map

◆ fiber_pause_map

◆ id

◆ name

◆ skge_chips

◆ __pci_driver