iPXE
tg3_phy.c
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1 
2 #include <mii.h>
3 #include <stdio.h>
4 #include <errno.h>
5 #include <unistd.h>
6 #include <byteswap.h>
7 #include <ipxe/pci.h>
8 
9 #include "tg3.h"
10 
11 static void tg3_link_report(struct tg3 *tp);
12 
13 void tg3_mdio_init(struct tg3 *tp)
14 { DBGP("%s\n", __func__);
15 
16  if (tg3_flag(tp, 5717_PLUS)) {
17  u32 is_serdes;
18 
19  tp->phy_addr = PCI_FUNC(tp->pdev->busdevfn) + 1;
20 
21  if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
22  is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
23  else
24  is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
25  TG3_CPMU_PHY_STRAP_IS_SERDES;
26  if (is_serdes)
27  tp->phy_addr += 7;
28  } else
29  tp->phy_addr = TG3_PHY_MII_ADDR;
30 }
31 
32 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
33 { DBGP("%s\n", __func__);
34 
35  int i;
36  u32 val;
37 
38  tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
39  tw32(OTP_CTRL, cmd);
40 
41  /* Wait for up to 1 ms for command to execute. */
42  for (i = 0; i < 100; i++) {
43  val = tr32(OTP_STATUS);
44  if (val & OTP_STATUS_CMD_DONE)
45  break;
46  udelay(10);
47  }
48 
49  return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
50 }
51 
52 /* Read the gphy configuration from the OTP region of the chip. The gphy
53  * configuration is a 32-bit value that straddles the alignment boundary.
54  * We do two 32-bit reads and then shift and merge the results.
55  */
56 u32 tg3_read_otp_phycfg(struct tg3 *tp)
57 { DBGP("%s\n", __func__);
58 
59  u32 bhalf_otp, thalf_otp;
60 
61  tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
62 
63  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
64  return 0;
65 
66  tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
67 
68  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
69  return 0;
70 
71  thalf_otp = tr32(OTP_READ_DATA);
72 
73  tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
74 
75  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
76  return 0;
77 
78  bhalf_otp = tr32(OTP_READ_DATA);
79 
80  return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
81 }
82 
83 #define PHY_BUSY_LOOPS 5000
84 
85 int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
86 { DBGP("%s\n", __func__);
87 
88  u32 frame_val;
89  unsigned int loops;
90  int ret;
91 
92  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
93  tw32_f(MAC_MI_MODE,
94  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
95  udelay(80);
96  }
97 
98  *val = 0x0;
99 
100  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
101  MI_COM_PHY_ADDR_MASK);
102  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
103  MI_COM_REG_ADDR_MASK);
104  frame_val |= (MI_COM_CMD_READ | MI_COM_START);
105 
106  tw32_f(MAC_MI_COM, frame_val);
107 
108  loops = PHY_BUSY_LOOPS;
109  while (loops != 0) {
110  udelay(10);
111  frame_val = tr32(MAC_MI_COM);
112 
113  if ((frame_val & MI_COM_BUSY) == 0) {
114  udelay(5);
115  frame_val = tr32(MAC_MI_COM);
116  break;
117  }
118  loops -= 1;
119  }
120 
121  ret = -EBUSY;
122  if (loops != 0) {
123  *val = frame_val & MI_COM_DATA_MASK;
124  ret = 0;
125  }
126 
127  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
128  tw32_f(MAC_MI_MODE, tp->mi_mode);
129  udelay(80);
130  }
131 
132  return ret;
133 }
134 
135 struct subsys_tbl_ent {
136  u16 subsys_vendor, subsys_devid;
137  u32 phy_id;
138 };
139 
140 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
141  /* Broadcom boards. */
142  { TG3PCI_SUBVENDOR_ID_BROADCOM,
143  TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
144  { TG3PCI_SUBVENDOR_ID_BROADCOM,
145  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
146  { TG3PCI_SUBVENDOR_ID_BROADCOM,
147  TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
148  { TG3PCI_SUBVENDOR_ID_BROADCOM,
149  TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
150  { TG3PCI_SUBVENDOR_ID_BROADCOM,
151  TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
152  { TG3PCI_SUBVENDOR_ID_BROADCOM,
153  TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
154  { TG3PCI_SUBVENDOR_ID_BROADCOM,
155  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
156  { TG3PCI_SUBVENDOR_ID_BROADCOM,
157  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
158  { TG3PCI_SUBVENDOR_ID_BROADCOM,
159  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
160  { TG3PCI_SUBVENDOR_ID_BROADCOM,
161  TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
162  { TG3PCI_SUBVENDOR_ID_BROADCOM,
163  TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
164 
165  /* 3com boards. */
166  { TG3PCI_SUBVENDOR_ID_3COM,
167  TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
168  { TG3PCI_SUBVENDOR_ID_3COM,
169  TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
170  { TG3PCI_SUBVENDOR_ID_3COM,
171  TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
172  { TG3PCI_SUBVENDOR_ID_3COM,
173  TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
174  { TG3PCI_SUBVENDOR_ID_3COM,
175  TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
176 
177  /* DELL boards. */
178  { TG3PCI_SUBVENDOR_ID_DELL,
179  TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
180  { TG3PCI_SUBVENDOR_ID_DELL,
181  TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
182  { TG3PCI_SUBVENDOR_ID_DELL,
183  TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
184  { TG3PCI_SUBVENDOR_ID_DELL,
185  TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
186 
187  /* Compaq boards. */
188  { TG3PCI_SUBVENDOR_ID_COMPAQ,
189  TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
190  { TG3PCI_SUBVENDOR_ID_COMPAQ,
191  TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
192  { TG3PCI_SUBVENDOR_ID_COMPAQ,
193  TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
194  { TG3PCI_SUBVENDOR_ID_COMPAQ,
195  TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
196  { TG3PCI_SUBVENDOR_ID_COMPAQ,
197  TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
198 
199  /* IBM boards. */
200  { TG3PCI_SUBVENDOR_ID_IBM,
201  TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
202 };
203 
204 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
205 { DBGP("%s\n", __func__);
206 
207  int i;
208 
209  DBGC(tp->dev, "Matching with: %x:%x\n", tp->subsystem_vendor, tp->subsystem_device);
210 
211  for (i = 0; i < (int) ARRAY_SIZE(subsys_id_to_phy_id); i++) {
212  if ((subsys_id_to_phy_id[i].subsys_vendor ==
213  tp->subsystem_vendor) &&
214  (subsys_id_to_phy_id[i].subsys_devid ==
215  tp->subsystem_device))
216  return &subsys_id_to_phy_id[i];
217  }
218  return NULL;
219 }
220 
221 int tg3_writephy(struct tg3 *tp, int reg, u32 val)
222 { DBGP("%s\n", __func__);
223 
224  u32 frame_val;
225  unsigned int loops;
226  int ret;
227 
228  if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
229  (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
230  return 0;
231 
232  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
233  tw32_f(MAC_MI_MODE,
234  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
235  udelay(80);
236  }
237 
238  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
239  MI_COM_PHY_ADDR_MASK);
240  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
241  MI_COM_REG_ADDR_MASK);
242  frame_val |= (val & MI_COM_DATA_MASK);
243  frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
244 
245  tw32_f(MAC_MI_COM, frame_val);
246 
247  loops = PHY_BUSY_LOOPS;
248  while (loops != 0) {
249  udelay(10);
250  frame_val = tr32(MAC_MI_COM);
251  if ((frame_val & MI_COM_BUSY) == 0) {
252  udelay(5);
253  frame_val = tr32(MAC_MI_COM);
254  break;
255  }
256  loops -= 1;
257  }
258 
259  ret = -EBUSY;
260  if (loops != 0)
261  ret = 0;
262 
263  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
264  tw32_f(MAC_MI_MODE, tp->mi_mode);
265  udelay(80);
266  }
267 
268  return ret;
269 }
270 
271 static int tg3_bmcr_reset(struct tg3 *tp)
272 { DBGP("%s\n", __func__);
273 
274  u32 phy_control;
275  int limit, err;
276 
277  /* OK, reset it, and poll the BMCR_RESET bit until it
278  * clears or we time out.
279  */
280  phy_control = BMCR_RESET;
281  err = tg3_writephy(tp, MII_BMCR, phy_control);
282  if (err != 0)
283  return -EBUSY;
284 
285  limit = 5000;
286  while (limit--) {
287  err = tg3_readphy(tp, MII_BMCR, &phy_control);
288  if (err != 0)
289  return -EBUSY;
290 
291  if ((phy_control & BMCR_RESET) == 0) {
292  udelay(40);
293  break;
294  }
295  udelay(10);
296  }
297  if (limit < 0)
298  return -EBUSY;
299 
300  return 0;
301 }
302 
303 static int tg3_wait_macro_done(struct tg3 *tp)
304 { DBGP("%s\n", __func__);
305 
306  int limit = 100;
307 
308  while (limit--) {
309  u32 tmp32;
310 
311  if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
312  if ((tmp32 & 0x1000) == 0)
313  break;
314  }
315  }
316  if (limit < 0)
317  return -EBUSY;
318 
319  return 0;
320 }
321 
322 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
323 { DBGP("%s\n", __func__);
324 
325  static const u32 test_pat[4][6] = {
326  { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
327  { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
328  { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
329  { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
330  };
331  int chan;
332 
333  for (chan = 0; chan < 4; chan++) {
334  int i;
335 
336  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
337  (chan * 0x2000) | 0x0200);
338  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
339 
340  for (i = 0; i < 6; i++)
341  tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
342  test_pat[chan][i]);
343 
344  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
345  if (tg3_wait_macro_done(tp)) {
346  *resetp = 1;
347  return -EBUSY;
348  }
349 
350  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
351  (chan * 0x2000) | 0x0200);
352  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
353  if (tg3_wait_macro_done(tp)) {
354  *resetp = 1;
355  return -EBUSY;
356  }
357 
358  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
359  if (tg3_wait_macro_done(tp)) {
360  *resetp = 1;
361  return -EBUSY;
362  }
363 
364  for (i = 0; i < 6; i += 2) {
365  u32 low, high;
366 
367  if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
368  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
369  tg3_wait_macro_done(tp)) {
370  *resetp = 1;
371  return -EBUSY;
372  }
373  low &= 0x7fff;
374  high &= 0x000f;
375  if (low != test_pat[chan][i] ||
376  high != test_pat[chan][i+1]) {
377  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
378  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
379  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
380 
381  return -EBUSY;
382  }
383  }
384  }
385 
386  return 0;
387 }
388 
389 static int tg3_phy_reset_chanpat(struct tg3 *tp)
390 { DBGP("%s\n", __func__);
391 
392  int chan;
393 
394  for (chan = 0; chan < 4; chan++) {
395  int i;
396 
397  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
398  (chan * 0x2000) | 0x0200);
399  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
400  for (i = 0; i < 6; i++)
401  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
402  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
403  if (tg3_wait_macro_done(tp))
404  return -EBUSY;
405  }
406 
407  return 0;
408 }
409 
410 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
411 { DBGP("%s\n", __func__);
412 
413  int err;
414 
415  err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
416  if (!err)
417  err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
418 
419  return err;
420 }
421 
422 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
423 { DBGP("%s\n", __func__);
424 
425  if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
426  set |= MII_TG3_AUXCTL_MISC_WREN;
427 
428  return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
429 }
430 
431 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
432  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
433  MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
434  MII_TG3_AUXCTL_ACTL_TX_6DB)
435 
436 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
437  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
438  MII_TG3_AUXCTL_ACTL_TX_6DB);
439 
440 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
441 { DBGP("%s\n", __func__);
442 
443  u32 reg32, phy9_orig;
444  int retries, do_phy_reset, err;
445 
446  retries = 10;
447  do_phy_reset = 1;
448  do {
449  if (do_phy_reset) {
450  err = tg3_bmcr_reset(tp);
451  if (err)
452  return err;
453  do_phy_reset = 0;
454  }
455 
456  /* Disable transmitter and interrupt. */
457  if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
458  continue;
459 
460  reg32 |= 0x3000;
461  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
462 
463  /* Set full-duplex, 1000 mbps. */
464  tg3_writephy(tp, MII_BMCR,
465  BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
466 
467  /* Set to master mode. */
468  if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
469  continue;
470 
471  tg3_writephy(tp, MII_TG3_CTRL,
472  (MII_TG3_CTRL_AS_MASTER |
473  MII_TG3_CTRL_ENABLE_AS_MASTER));
474 
475  err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
476  if (err)
477  return err;
478 
479  /* Block the PHY control access. */
480  tg3_phydsp_write(tp, 0x8005, 0x0800);
481 
482  err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
483  if (!err)
484  break;
485  } while (--retries);
486 
487  err = tg3_phy_reset_chanpat(tp);
488  if (err)
489  return err;
490 
491  tg3_phydsp_write(tp, 0x8005, 0x0000);
492 
493  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
494  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
495 
496  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
497 
498  tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
499 
500  if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
501  reg32 &= ~0x3000;
502  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
503  } else if (!err)
504  err = -EBUSY;
505 
506  return err;
507 }
508 
509 static void tg3_phy_apply_otp(struct tg3 *tp)
510 { DBGP("%s\n", __func__);
511 
512  u32 otp, phy;
513 
514  if (!tp->phy_otp)
515  return;
516 
517  otp = tp->phy_otp;
518 
519  if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
520  return;
521 
522  phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
523  phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
524  tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
525 
526  phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
527  ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
528  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
529 
530  phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
531  phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
532  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
533 
534  phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
535  tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
536 
537  phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
538  tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
539 
540  phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
541  ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
542  tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
543 
544  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
545 }
546 
547 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
548 { DBGP("%s\n", __func__);
549 
550  int err;
551 
552  err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
553  (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
554  MII_TG3_AUXCTL_SHDWSEL_MISC);
555  if (!err)
556  err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
557 
558  return err;
559 }
560 
561 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
562 { DBGP("%s\n", __func__);
563 
564  u32 phy;
565 
566  if (!tg3_flag(tp, 5705_PLUS) ||
567  (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
568  return;
569 
570  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
571  u32 ephy;
572 
573  if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
574  u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
575 
576  tg3_writephy(tp, MII_TG3_FET_TEST,
577  ephy | MII_TG3_FET_SHADOW_EN);
578  if (!tg3_readphy(tp, reg, &phy)) {
579  if (enable)
580  phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
581  else
582  phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
583  tg3_writephy(tp, reg, phy);
584  }
585  tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
586  }
587  } else {
588  int ret;
589 
590  ret = tg3_phy_auxctl_read(tp,
591  MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
592  if (!ret) {
593  if (enable)
594  phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
595  else
596  phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
597  tg3_phy_auxctl_write(tp,
598  MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
599  }
600  }
601 }
602 
603 static void tg3_phy_set_wirespeed(struct tg3 *tp)
604 { DBGP("%s\n", __func__);
605 
606  int ret;
607  u32 val;
608 
609  if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
610  return;
611 
612  ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
613  if (!ret)
614  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
615  val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
616 }
617 
618 /* This will reset the tigon3 PHY if there is no valid
619  * link unless the FORCE argument is non-zero.
620  */
621 int tg3_phy_reset(struct tg3 *tp)
622 { DBGP("%s\n", __func__);
623 
624  u32 val, cpmuctrl;
625  int err;
626 
627  DBGCP(&tp->pdev->dev, "%s\n", __func__);
628 
629  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
630  val = tr32(GRC_MISC_CFG);
631  tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
632  udelay(40);
633  }
634  err = tg3_readphy(tp, MII_BMSR, &val);
635  err |= tg3_readphy(tp, MII_BMSR, &val);
636  if (err != 0)
637  return -EBUSY;
638 
639  netdev_link_down(tp->dev);
640  tg3_link_report(tp);
641 
642  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
643  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
644  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
645  err = tg3_phy_reset_5703_4_5(tp);
646  if (err)
647  return err;
648  goto out;
649  }
650 
651  cpmuctrl = 0;
652  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
653  GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
654  cpmuctrl = tr32(TG3_CPMU_CTRL);
655  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
656  tw32(TG3_CPMU_CTRL,
657  cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
658  }
659 
660  err = tg3_bmcr_reset(tp);
661  if (err)
662  return err;
663 
664  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
665  val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
666  tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
667 
668  tw32(TG3_CPMU_CTRL, cpmuctrl);
669  }
670 
671  if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
672  GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
673  val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
674  if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
675  CPMU_LSPD_1000MB_MACCLK_12_5) {
676  val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
677  udelay(40);
678  tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
679  }
680  }
681 
682  if (tg3_flag(tp, 5717_PLUS) &&
683  (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
684  return 0;
685 
686  tg3_phy_apply_otp(tp);
687 
688 out:
689  if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
690  !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
691  tg3_phydsp_write(tp, 0x201f, 0x2aaa);
692  tg3_phydsp_write(tp, 0x000a, 0x0323);
693  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
694  }
695 
696  if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
697  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
698  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
699  }
700 
701  if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
702  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
703  tg3_phydsp_write(tp, 0x000a, 0x310b);
704  tg3_phydsp_write(tp, 0x201f, 0x9506);
705  tg3_phydsp_write(tp, 0x401f, 0x14e2);
706  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
707  }
708  } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
709  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
710  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
711  if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
712  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
713  tg3_writephy(tp, MII_TG3_TEST1,
714  MII_TG3_TEST1_TRIM_EN | 0x4);
715  } else
716  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
717 
718  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
719  }
720  }
721 
722  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
723  /* Cannot do read-modify-write on 5401 */
724  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
725  }
726 
727  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
728  /* adjust output voltage */
729  tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
730  }
731 
732  tg3_phy_toggle_automdix(tp, 1);
733  tg3_phy_set_wirespeed(tp);
734  return 0;
735 }
736 
737 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
738 { DBGP("%s\n", __func__);
739 
740  u32 adv_reg, all_mask = 0;
741 
742  if (mask & ADVERTISED_10baseT_Half)
743  all_mask |= ADVERTISE_10HALF;
744  if (mask & ADVERTISED_10baseT_Full)
745  all_mask |= ADVERTISE_10FULL;
746  if (mask & ADVERTISED_100baseT_Half)
747  all_mask |= ADVERTISE_100HALF;
748  if (mask & ADVERTISED_100baseT_Full)
749  all_mask |= ADVERTISE_100FULL;
750 
751  if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
752  return 0;
753 
754  if ((adv_reg & all_mask) != all_mask)
755  return 0;
756  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
757  u32 tg3_ctrl;
758 
759  all_mask = 0;
760  if (mask & ADVERTISED_1000baseT_Half)
761  all_mask |= ADVERTISE_1000HALF;
762  if (mask & ADVERTISED_1000baseT_Full)
763  all_mask |= ADVERTISE_1000FULL;
764 
765  if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
766  return 0;
767 
768  if ((tg3_ctrl & all_mask) != all_mask)
769  return 0;
770  }
771  return 1;
772 }
773 
774 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
775 { DBGP("%s\n", __func__);
776 
777  u16 miireg;
778 
779  if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
780  miireg = ADVERTISE_PAUSE_CAP;
781  else if (flow_ctrl & FLOW_CTRL_TX)
782  miireg = ADVERTISE_PAUSE_ASYM;
783  else if (flow_ctrl & FLOW_CTRL_RX)
784  miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
785  else
786  miireg = 0;
787 
788  return miireg;
789 }
790 
791 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
792 { DBGP("%s\n", __func__);
793 
794  int err = 0;
795  u32 val __unused, new_adv;
796 
797  new_adv = ADVERTISE_CSMA;
798  if (advertise & ADVERTISED_10baseT_Half)
799  new_adv |= ADVERTISE_10HALF;
800  if (advertise & ADVERTISED_10baseT_Full)
801  new_adv |= ADVERTISE_10FULL;
802  if (advertise & ADVERTISED_100baseT_Half)
803  new_adv |= ADVERTISE_100HALF;
804  if (advertise & ADVERTISED_100baseT_Full)
805  new_adv |= ADVERTISE_100FULL;
806 
807  new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
808 
809  err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
810  if (err)
811  goto done;
812 
813  if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
814  goto done;
815 
816  new_adv = 0;
817  if (advertise & ADVERTISED_1000baseT_Half)
818  new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
819  if (advertise & ADVERTISED_1000baseT_Full)
820  new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
821 
822  if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
823  tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
824  new_adv |= (MII_TG3_CTRL_AS_MASTER |
825  MII_TG3_CTRL_ENABLE_AS_MASTER);
826 
827  err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
828  if (err)
829  goto done;
830 
831  if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
832  goto done;
833 
834 done:
835  return err;
836 }
837 
838 static int tg3_init_5401phy_dsp(struct tg3 *tp)
839 { DBGP("%s\n", __func__);
840 
841  int err;
842 
843  /* Turn off tap power management. */
844  /* Set Extended packet length bit */
845  err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
846 
847  err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
848  err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
849  err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
850  err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
851  err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
852 
853  udelay(40);
854 
855  return err;
856 }
857 
858 #define ADVERTISED_Autoneg (1 << 6)
859 #define ADVERTISED_Pause (1 << 13)
860 #define ADVERTISED_TP (1 << 7)
861 #define ADVERTISED_FIBRE (1 << 10)
862 
863 #define AUTONEG_ENABLE 0x01
864 
865 static void tg3_phy_init_link_config(struct tg3 *tp)
866 { DBGP("%s\n", __func__);
867 
868  u32 adv = ADVERTISED_Autoneg |
869  ADVERTISED_Pause;
870 
871 
872  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
873  adv |= ADVERTISED_1000baseT_Half |
874  ADVERTISED_1000baseT_Full;
875  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
876  adv |= ADVERTISED_100baseT_Half |
877  ADVERTISED_100baseT_Full |
878  ADVERTISED_10baseT_Half |
879  ADVERTISED_10baseT_Full |
880  ADVERTISED_TP;
881  else
882  adv |= ADVERTISED_FIBRE;
883 
884  tp->link_config.advertising = adv;
885  tp->link_config.speed = SPEED_INVALID;
886  tp->link_config.duplex = DUPLEX_INVALID;
887  tp->link_config.autoneg = AUTONEG_ENABLE;
888  tp->link_config.active_speed = SPEED_INVALID;
889  tp->link_config.active_duplex = DUPLEX_INVALID;
890  tp->link_config.orig_speed = SPEED_INVALID;
891  tp->link_config.orig_duplex = DUPLEX_INVALID;
892  tp->link_config.orig_autoneg = AUTONEG_INVALID;
893 }
894 
895 int tg3_phy_probe(struct tg3 *tp)
896 { DBGP("%s\n", __func__);
897 
898  u32 hw_phy_id_1, hw_phy_id_2;
899  u32 hw_phy_id, hw_phy_id_masked;
900  int err;
901 
902  /* flow control autonegotiation is default behavior */
903  tg3_flag_set(tp, PAUSE_AUTONEG);
904  tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
905 
906  /* Reading the PHY ID register can conflict with ASF
907  * firmware access to the PHY hardware.
908  */
909  err = 0;
910  if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
911  hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
912  } else {
913  /* Now read the physical PHY_ID from the chip and verify
914  * that it is sane. If it doesn't look good, we fall back
915  * to either the hard-coded table based PHY_ID and failing
916  * that the value found in the eeprom area.
917  */
918  err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
919  err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
920 
921  hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
922  hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
923  hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
924 
925  hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
926  }
927 
928  if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
929  tp->phy_id = hw_phy_id;
930  if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
931  tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
932  else
933  tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
934  } else {
935  if (tp->phy_id != TG3_PHY_ID_INVALID) {
936  /* Do nothing, phy ID already set up in
937  * tg3_get_eeprom_hw_cfg().
938  */
939  } else {
940  struct subsys_tbl_ent *p;
941 
942  /* No eeprom signature? Try the hardcoded
943  * subsys device table.
944  */
945  p = tg3_lookup_by_subsys(tp);
946  if (!p) {
947  DBGC(&tp->pdev->dev, "lookup by subsys failed\n");
948  return -ENODEV;
949  }
950 
951  tp->phy_id = p->phy_id;
952  if (!tp->phy_id ||
953  tp->phy_id == TG3_PHY_ID_BCM8002)
954  tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
955  }
956  }
957 
958  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
959  ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
960  tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
961  (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
962  tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
963  tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
964 
965  tg3_phy_init_link_config(tp);
966 
967  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
968  !tg3_flag(tp, ENABLE_APE) &&
969  !tg3_flag(tp, ENABLE_ASF)) {
970  u32 bmsr;
971  u32 mask;
972 
973  tg3_readphy(tp, MII_BMSR, &bmsr);
974  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
975  (bmsr & BMSR_LSTATUS))
976  goto skip_phy_reset;
977 
978  err = tg3_phy_reset(tp);
979  if (err)
980  return err;
981 
982  tg3_phy_set_wirespeed(tp);
983 
984  mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
985  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
986  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
987  if (!tg3_copper_is_advertising_all(tp, mask)) {
988  tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
989  tp->link_config.flowctrl);
990 
991  tg3_writephy(tp, MII_BMCR,
992  BMCR_ANENABLE | BMCR_ANRESTART);
993  }
994  }
995 
996 skip_phy_reset:
997  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
998  err = tg3_init_5401phy_dsp(tp);
999  if (err)
1000  return err;
1001 
1002  err = tg3_init_5401phy_dsp(tp);
1003  }
1004 
1005  return err;
1006 }
1007 
1008 void tg3_poll_link(struct tg3 *tp)
1009 { DBGP("%s\n", __func__);
1010 
1011  if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
1012  DBGC(tp->dev,"link_changed\n");
1013  tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
1014  tg3_setup_phy(tp, 0);
1015  }
1016 }
1017 
1018 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1019 { DBGP("%s\n", __func__);
1020 
1021  switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1022  case MII_TG3_AUX_STAT_10HALF:
1023  *speed = SPEED_10;
1024  *duplex = DUPLEX_HALF;
1025  break;
1026 
1027  case MII_TG3_AUX_STAT_10FULL:
1028  *speed = SPEED_10;
1029  *duplex = DUPLEX_FULL;
1030  break;
1031 
1032  case MII_TG3_AUX_STAT_100HALF:
1033  *speed = SPEED_100;
1034  *duplex = DUPLEX_HALF;
1035  break;
1036 
1037  case MII_TG3_AUX_STAT_100FULL:
1038  *speed = SPEED_100;
1039  *duplex = DUPLEX_FULL;
1040  break;
1041 
1042  case MII_TG3_AUX_STAT_1000HALF:
1043  *speed = SPEED_1000;
1044  *duplex = DUPLEX_HALF;
1045  break;
1046 
1047  case MII_TG3_AUX_STAT_1000FULL:
1048  *speed = SPEED_1000;
1049  *duplex = DUPLEX_FULL;
1050  break;
1051 
1052  default:
1053  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1054  *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1055  SPEED_10;
1056  *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1057  DUPLEX_HALF;
1058  break;
1059  }
1060  *speed = SPEED_INVALID;
1061  *duplex = DUPLEX_INVALID;
1062  break;
1063  }
1064 }
1065 
1066 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
1067 { DBGP("%s\n", __func__);
1068 
1069  u32 curadv, reqadv;
1070 
1071  if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
1072  return 1;
1073 
1074  curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1075  reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1076 
1077  if (tp->link_config.active_duplex == DUPLEX_FULL) {
1078  if (curadv != reqadv)
1079  return 0;
1080 
1081  if (tg3_flag(tp, PAUSE_AUTONEG))
1082  tg3_readphy(tp, MII_LPA, rmtadv);
1083  } else {
1084  /* Reprogram the advertisement register, even if it
1085  * does not affect the current link. If the link
1086  * gets renegotiated in the future, we can save an
1087  * additional renegotiation cycle by advertising
1088  * it correctly in the first place.
1089  */
1090  if (curadv != reqadv) {
1091  *lcladv &= ~(ADVERTISE_PAUSE_CAP |
1092  ADVERTISE_PAUSE_ASYM);
1093  tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
1094  }
1095  }
1096 
1097  return 1;
1098 }
1099 
1100 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1101 { DBGP("%s\n", __func__);
1102 
1103  u8 cap = 0;
1104 
1105  if (lcladv & ADVERTISE_1000XPAUSE) {
1106  if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1107  if (rmtadv & LPA_1000XPAUSE)
1108  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1109  else if (rmtadv & LPA_1000XPAUSE_ASYM)
1110  cap = FLOW_CTRL_RX;
1111  } else {
1112  if (rmtadv & LPA_1000XPAUSE)
1113  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1114  }
1115  } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1116  if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1117  cap = FLOW_CTRL_TX;
1118  }
1119 
1120  return cap;
1121 }
1122 
1123 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1124 { DBGP("%s\n", __func__);
1125 
1126  u8 flowctrl = 0;
1127  u32 old_rx_mode = tp->rx_mode;
1128  u32 old_tx_mode = tp->tx_mode;
1129 
1130  if (tg3_flag(tp, PAUSE_AUTONEG)) {
1131  if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1132  flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1133  else
1134  flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1135  } else
1136  flowctrl = tp->link_config.flowctrl;
1137 
1138  tp->link_config.active_flowctrl = flowctrl;
1139 
1140  if (flowctrl & FLOW_CTRL_RX)
1141  tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1142  else
1143  tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1144 
1145  if (old_rx_mode != tp->rx_mode)
1146  tw32_f(MAC_RX_MODE, tp->rx_mode);
1147 
1148  if (flowctrl & FLOW_CTRL_TX)
1149  tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1150  else
1151  tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1152 
1153  if (old_tx_mode != tp->tx_mode)
1154  tw32_f(MAC_TX_MODE, tp->tx_mode);
1155 }
1156 
1157 static void tg3_phy_copper_begin(struct tg3 *tp)
1158 { DBGP("%s\n", __func__);
1159 
1160  u32 new_adv;
1161 
1162  if (tp->link_config.speed == SPEED_INVALID) {
1163  if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1164  tp->link_config.advertising &=
1165  ~(ADVERTISED_1000baseT_Half |
1166  ADVERTISED_1000baseT_Full);
1167 
1168  tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
1169  tp->link_config.flowctrl);
1170  } else {
1171  /* Asking for a specific link mode. */
1172  if (tp->link_config.speed == SPEED_1000) {
1173  if (tp->link_config.duplex == DUPLEX_FULL)
1174  new_adv = ADVERTISED_1000baseT_Full;
1175  else
1176  new_adv = ADVERTISED_1000baseT_Half;
1177  } else if (tp->link_config.speed == SPEED_100) {
1178  if (tp->link_config.duplex == DUPLEX_FULL)
1179  new_adv = ADVERTISED_100baseT_Full;
1180  else
1181  new_adv = ADVERTISED_100baseT_Half;
1182  } else {
1183  if (tp->link_config.duplex == DUPLEX_FULL)
1184  new_adv = ADVERTISED_10baseT_Full;
1185  else
1186  new_adv = ADVERTISED_10baseT_Half;
1187  }
1188 
1189  tg3_phy_autoneg_cfg(tp, new_adv,
1190  tp->link_config.flowctrl);
1191  }
1192 
1193  tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1194 }
1195 
1196 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1197 { DBGP("%s\n", __func__);
1198 
1199  if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1200  return 1;
1201  else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
1202  if (speed != SPEED_10)
1203  return 1;
1204  } else if (speed == SPEED_10)
1205  return 1;
1206 
1207  return 0;
1208 }
1209 
1210 #if 1
1211 
1212 static void tg3_ump_link_report(struct tg3 *tp)
1213 { DBGP("%s\n", __func__);
1214 
1215  u32 reg;
1216  u32 val;
1217 
1218  if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1219  return;
1220 
1221  tg3_wait_for_event_ack(tp);
1222 
1223  tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1224 
1225  tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1226 
1227  val = 0;
1228  if (!tg3_readphy(tp, MII_BMCR, &reg))
1229  val = reg << 16;
1230  if (!tg3_readphy(tp, MII_BMSR, &reg))
1231  val |= (reg & 0xffff);
1232  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1233 
1234  val = 0;
1235  if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1236  val = reg << 16;
1237  if (!tg3_readphy(tp, MII_LPA, &reg))
1238  val |= (reg & 0xffff);
1239  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1240 
1241  val = 0;
1242  if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1243  if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1244  val = reg << 16;
1245  if (!tg3_readphy(tp, MII_STAT1000, &reg))
1246  val |= (reg & 0xffff);
1247  }
1248  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1249 
1250  if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1251  val = reg << 16;
1252  else
1253  val = 0;
1254  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1255 
1256  tg3_generate_fw_event(tp);
1257 }
1258 
1259 /* NOTE: Debugging only code */
1260 static void tg3_link_report(struct tg3 *tp)
1261 { DBGP("%s\n", __func__);
1262 
1263  if (!netdev_link_ok(tp->dev)) {
1264  DBGC(tp->dev, "Link is down\n");
1265  tg3_ump_link_report(tp);
1266  } else {
1267  DBGC(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1268  (tp->link_config.active_speed == SPEED_1000 ?
1269  1000 :
1270  (tp->link_config.active_speed == SPEED_100 ?
1271  100 : 10)),
1272  (tp->link_config.active_duplex == DUPLEX_FULL ?
1273  "full" : "half"));
1274 
1275  DBGC(tp->dev, "Flow control is %s for TX and %s for RX\n",
1276  (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1277  "on" : "off",
1278  (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1279  "on" : "off");
1280 
1281  if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1282  DBGC(tp->dev, "EEE is %s\n",
1283  tp->setlpicnt ? "enabled" : "disabled");
1284 
1285  tg3_ump_link_report(tp);
1286  }
1287 }
1288 #endif
1289 
1290 struct tg3_fiber_aneginfo {
1291  int state;
1292 #define ANEG_STATE_UNKNOWN 0
1293 #define ANEG_STATE_AN_ENABLE 1
1294 #define ANEG_STATE_RESTART_INIT 2
1295 #define ANEG_STATE_RESTART 3
1296 #define ANEG_STATE_DISABLE_LINK_OK 4
1297 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1298 #define ANEG_STATE_ABILITY_DETECT 6
1299 #define ANEG_STATE_ACK_DETECT_INIT 7
1300 #define ANEG_STATE_ACK_DETECT 8
1301 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1302 #define ANEG_STATE_COMPLETE_ACK 10
1303 #define ANEG_STATE_IDLE_DETECT_INIT 11
1304 #define ANEG_STATE_IDLE_DETECT 12
1305 #define ANEG_STATE_LINK_OK 13
1306 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1307 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1308 
1309  u32 flags;
1310 #define MR_AN_ENABLE 0x00000001
1311 #define MR_RESTART_AN 0x00000002
1312 #define MR_AN_COMPLETE 0x00000004
1313 #define MR_PAGE_RX 0x00000008
1314 #define MR_NP_LOADED 0x00000010
1315 #define MR_TOGGLE_TX 0x00000020
1316 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1317 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1318 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1319 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1320 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1321 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1322 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1323 #define MR_TOGGLE_RX 0x00002000
1324 #define MR_NP_RX 0x00004000
1325 
1326 #define MR_LINK_OK 0x80000000
1327 
1328  unsigned long link_time, cur_time;
1329 
1330  u32 ability_match_cfg;
1331  int ability_match_count;
1332 
1333  char ability_match, idle_match, ack_match;
1334 
1335  u32 txconfig, rxconfig;
1336 #define ANEG_CFG_NP 0x00000080
1337 #define ANEG_CFG_ACK 0x00000040
1338 #define ANEG_CFG_RF2 0x00000020
1339 #define ANEG_CFG_RF1 0x00000010
1340 #define ANEG_CFG_PS2 0x00000001
1341 #define ANEG_CFG_PS1 0x00008000
1342 #define ANEG_CFG_HD 0x00004000
1343 #define ANEG_CFG_FD 0x00002000
1344 #define ANEG_CFG_INVAL 0x00001f06
1345 
1346 };
1347 #define ANEG_OK 0
1348 #define ANEG_DONE 1
1349 #define ANEG_TIMER_ENAB 2
1350 #define ANEG_FAILED -1
1351 
1352 #define ANEG_STATE_SETTLE_TIME 10000
1353 
1354 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1355 {
1356  u16 miireg;
1357 
1358  if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1359  miireg = ADVERTISE_1000XPAUSE;
1360  else if (flow_ctrl & FLOW_CTRL_TX)
1361  miireg = ADVERTISE_1000XPSE_ASYM;
1362  else if (flow_ctrl & FLOW_CTRL_RX)
1363  miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1364  else
1365  miireg = 0;
1366 
1367  return miireg;
1368 }
1369 
1370 static void tg3_init_bcm8002(struct tg3 *tp)
1371 {
1372  u32 mac_status = tr32(MAC_STATUS);
1373  int i;
1374 
1375  /* Reset when initting first time or we have a link. */
1376  if (tg3_flag(tp, INIT_COMPLETE) &&
1377  !(mac_status & MAC_STATUS_PCS_SYNCED))
1378  return;
1379 
1380  /* Set PLL lock range. */
1381  tg3_writephy(tp, 0x16, 0x8007);
1382 
1383  /* SW reset */
1384  tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1385 
1386  /* Wait for reset to complete. */
1387  /* XXX schedule_timeout() ... */
1388  for (i = 0; i < 500; i++)
1389  udelay(10);
1390 
1391  /* Config mode; select PMA/Ch 1 regs. */
1392  tg3_writephy(tp, 0x10, 0x8411);
1393 
1394  /* Enable auto-lock and comdet, select txclk for tx. */
1395  tg3_writephy(tp, 0x11, 0x0a10);
1396 
1397  tg3_writephy(tp, 0x18, 0x00a0);
1398  tg3_writephy(tp, 0x16, 0x41ff);
1399 
1400  /* Assert and deassert POR. */
1401  tg3_writephy(tp, 0x13, 0x0400);
1402  udelay(40);
1403  tg3_writephy(tp, 0x13, 0x0000);
1404 
1405  tg3_writephy(tp, 0x11, 0x0a50);
1406  udelay(40);
1407  tg3_writephy(tp, 0x11, 0x0a10);
1408 
1409  /* Wait for signal to stabilize */
1410  /* XXX schedule_timeout() ... */
1411  for (i = 0; i < 15000; i++)
1412  udelay(10);
1413 
1414  /* Deselect the channel register so we can read the PHYID
1415  * later.
1416  */
1417  tg3_writephy(tp, 0x10, 0x8011);
1418 }
1419 
1420 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1421 {
1422  u16 flowctrl;
1423  int current_link_up;
1424  u32 sg_dig_ctrl, sg_dig_status;
1425  u32 serdes_cfg, expected_sg_dig_ctrl;
1426  int workaround, port_a;
1427 
1428  serdes_cfg = 0;
1429  expected_sg_dig_ctrl = 0;
1430  workaround = 0;
1431  port_a = 1;
1432  current_link_up = 0;
1433 
1434  if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
1435  tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
1436  workaround = 1;
1437  if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
1438  port_a = 0;
1439 
1440  /* preserve bits 0-11,13,14 for signal pre-emphasis */
1441  /* preserve bits 20-23 for voltage regulator */
1442  serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
1443  }
1444 
1445  sg_dig_ctrl = tr32(SG_DIG_CTRL);
1446 
1447  if (tp->link_config.autoneg != AUTONEG_ENABLE) {
1448  if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1449  if (workaround) {
1450  u32 val = serdes_cfg;
1451 
1452  if (port_a)
1453  val |= 0xc010000;
1454  else
1455  val |= 0x4010000;
1456  tw32_f(MAC_SERDES_CFG, val);
1457  }
1458 
1459  tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1460  }
1461  if (mac_status & MAC_STATUS_PCS_SYNCED) {
1462  tg3_setup_flow_control(tp, 0, 0);
1463  current_link_up = 1;
1464  }
1465  goto out;
1466  }
1467 
1468  /* Want auto-negotiation. */
1469  expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1470 
1471  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
1472  if (flowctrl & ADVERTISE_1000XPAUSE)
1473  expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
1474  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
1475  expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1476 
1477  if (sg_dig_ctrl != expected_sg_dig_ctrl) {
1478  if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
1479  tp->serdes_counter &&
1480  ((mac_status & (MAC_STATUS_PCS_SYNCED |
1481  MAC_STATUS_RCVD_CFG)) ==
1482  MAC_STATUS_PCS_SYNCED)) {
1483  tp->serdes_counter--;
1484  current_link_up = 1;
1485  goto out;
1486  }
1487 restart_autoneg:
1488  if (workaround)
1489  tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
1490  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1491  udelay(5);
1492  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
1493 
1494  tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
1495  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1496  } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
1497  MAC_STATUS_SIGNAL_DET)) {
1498  sg_dig_status = tr32(SG_DIG_STATUS);
1499  mac_status = tr32(MAC_STATUS);
1500 
1501  if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1502  (mac_status & MAC_STATUS_PCS_SYNCED)) {
1503  u32 local_adv = 0, remote_adv = 0;
1504 
1505  if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
1506  local_adv |= ADVERTISE_1000XPAUSE;
1507  if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
1508  local_adv |= ADVERTISE_1000XPSE_ASYM;
1509 
1510  if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
1511  remote_adv |= LPA_1000XPAUSE;
1512  if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
1513  remote_adv |= LPA_1000XPAUSE_ASYM;
1514 
1515  tp->link_config.rmt_adv =
1516  mii_adv_to_ethtool_adv_x(remote_adv);
1517 
1518  tg3_setup_flow_control(tp, local_adv, remote_adv);
1519  current_link_up = 1;
1520  tp->serdes_counter = 0;
1521  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1522  } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
1523  if (tp->serdes_counter)
1524  tp->serdes_counter--;
1525  else {
1526  if (workaround) {
1527  u32 val = serdes_cfg;
1528 
1529  if (port_a)
1530  val |= 0xc010000;
1531  else
1532  val |= 0x4010000;
1533 
1534  tw32_f(MAC_SERDES_CFG, val);
1535  }
1536 
1537  tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1538  udelay(40);
1539 
1540  /* Link parallel detection - link is up */
1541  /* only if we have PCS_SYNC and not */
1542  /* receiving config code words */
1543  mac_status = tr32(MAC_STATUS);
1544  if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
1545  !(mac_status & MAC_STATUS_RCVD_CFG)) {
1546  tg3_setup_flow_control(tp, 0, 0);
1547  current_link_up = 1;
1548  tp->phy_flags |=
1549  TG3_PHYFLG_PARALLEL_DETECT;
1550  tp->serdes_counter =
1551  SERDES_PARALLEL_DET_TIMEOUT;
1552  } else
1553  goto restart_autoneg;
1554  }
1555  }
1556  } else {
1557  tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
1558  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1559  }
1560 
1561 out:
1562  return current_link_up;
1563 }
1564 
1565 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1566  struct tg3_fiber_aneginfo *ap)
1567 {
1568  u16 flowctrl;
1569  unsigned long delta;
1570  u32 rx_cfg_reg;
1571  int ret;
1572 
1573  if (ap->state == ANEG_STATE_UNKNOWN) {
1574  ap->rxconfig = 0;
1575  ap->link_time = 0;
1576  ap->cur_time = 0;
1577  ap->ability_match_cfg = 0;
1578  ap->ability_match_count = 0;
1579  ap->ability_match = 0;
1580  ap->idle_match = 0;
1581  ap->ack_match = 0;
1582  }
1583  ap->cur_time++;
1584 
1585  if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1586  rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1587 
1588  if (rx_cfg_reg != ap->ability_match_cfg) {
1589  ap->ability_match_cfg = rx_cfg_reg;
1590  ap->ability_match = 0;
1591  ap->ability_match_count = 0;
1592  } else {
1593  if (++ap->ability_match_count > 1) {
1594  ap->ability_match = 1;
1595  ap->ability_match_cfg = rx_cfg_reg;
1596  }
1597  }
1598  if (rx_cfg_reg & ANEG_CFG_ACK)
1599  ap->ack_match = 1;
1600  else
1601  ap->ack_match = 0;
1602 
1603  ap->idle_match = 0;
1604  } else {
1605  ap->idle_match = 1;
1606  ap->ability_match_cfg = 0;
1607  ap->ability_match_count = 0;
1608  ap->ability_match = 0;
1609  ap->ack_match = 0;
1610 
1611  rx_cfg_reg = 0;
1612  }
1613 
1614  ap->rxconfig = rx_cfg_reg;
1615  ret = ANEG_OK;
1616 
1617  switch (ap->state) {
1618  case ANEG_STATE_UNKNOWN:
1619  if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1620  ap->state = ANEG_STATE_AN_ENABLE;
1621 
1622  /* fallthru */
1623  case ANEG_STATE_AN_ENABLE:
1624  ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1625  if (ap->flags & MR_AN_ENABLE) {
1626  ap->link_time = 0;
1627  ap->cur_time = 0;
1628  ap->ability_match_cfg = 0;
1629  ap->ability_match_count = 0;
1630  ap->ability_match = 0;
1631  ap->idle_match = 0;
1632  ap->ack_match = 0;
1633 
1634  ap->state = ANEG_STATE_RESTART_INIT;
1635  } else {
1636  ap->state = ANEG_STATE_DISABLE_LINK_OK;
1637  }
1638  break;
1639 
1640  case ANEG_STATE_RESTART_INIT:
1641  ap->link_time = ap->cur_time;
1642  ap->flags &= ~(MR_NP_LOADED);
1643  ap->txconfig = 0;
1644  tw32(MAC_TX_AUTO_NEG, 0);
1645  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1646  tw32_f(MAC_MODE, tp->mac_mode);
1647  udelay(40);
1648 
1649  ret = ANEG_TIMER_ENAB;
1650  ap->state = ANEG_STATE_RESTART;
1651 
1652  /* fallthru */
1653  case ANEG_STATE_RESTART:
1654  delta = ap->cur_time - ap->link_time;
1655  if (delta > ANEG_STATE_SETTLE_TIME)
1656  ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1657  else
1658  ret = ANEG_TIMER_ENAB;
1659  break;
1660 
1661  case ANEG_STATE_DISABLE_LINK_OK:
1662  ret = ANEG_DONE;
1663  break;
1664 
1665  case ANEG_STATE_ABILITY_DETECT_INIT:
1666  ap->flags &= ~(MR_TOGGLE_TX);
1667  ap->txconfig = ANEG_CFG_FD;
1668  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
1669  if (flowctrl & ADVERTISE_1000XPAUSE)
1670  ap->txconfig |= ANEG_CFG_PS1;
1671  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
1672  ap->txconfig |= ANEG_CFG_PS2;
1673  tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1674  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1675  tw32_f(MAC_MODE, tp->mac_mode);
1676  udelay(40);
1677 
1678  ap->state = ANEG_STATE_ABILITY_DETECT;
1679  break;
1680 
1681  case ANEG_STATE_ABILITY_DETECT:
1682  if (ap->ability_match != 0 && ap->rxconfig != 0)
1683  ap->state = ANEG_STATE_ACK_DETECT_INIT;
1684  break;
1685 
1686  case ANEG_STATE_ACK_DETECT_INIT:
1687  ap->txconfig |= ANEG_CFG_ACK;
1688  tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1689  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1690  tw32_f(MAC_MODE, tp->mac_mode);
1691  udelay(40);
1692 
1693  ap->state = ANEG_STATE_ACK_DETECT;
1694 
1695  /* fallthru */
1696  case ANEG_STATE_ACK_DETECT:
1697  if (ap->ack_match != 0) {
1698  if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1699  (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1700  ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1701  } else {
1702  ap->state = ANEG_STATE_AN_ENABLE;
1703  }
1704  } else if (ap->ability_match != 0 &&
1705  ap->rxconfig == 0) {
1706  ap->state = ANEG_STATE_AN_ENABLE;
1707  }
1708  break;
1709 
1710  case ANEG_STATE_COMPLETE_ACK_INIT:
1711  if (ap->rxconfig & ANEG_CFG_INVAL) {
1712  ret = ANEG_FAILED;
1713  break;
1714  }
1715  ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1716  MR_LP_ADV_HALF_DUPLEX |
1717  MR_LP_ADV_SYM_PAUSE |
1718  MR_LP_ADV_ASYM_PAUSE |
1719  MR_LP_ADV_REMOTE_FAULT1 |
1720  MR_LP_ADV_REMOTE_FAULT2 |
1721  MR_LP_ADV_NEXT_PAGE |
1722  MR_TOGGLE_RX |
1723  MR_NP_RX);
1724  if (ap->rxconfig & ANEG_CFG_FD)
1725  ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1726  if (ap->rxconfig & ANEG_CFG_HD)
1727  ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1728  if (ap->rxconfig & ANEG_CFG_PS1)
1729  ap->flags |= MR_LP_ADV_SYM_PAUSE;
1730  if (ap->rxconfig & ANEG_CFG_PS2)
1731  ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1732  if (ap->rxconfig & ANEG_CFG_RF1)
1733  ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1734  if (ap->rxconfig & ANEG_CFG_RF2)
1735  ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1736  if (ap->rxconfig & ANEG_CFG_NP)
1737  ap->flags |= MR_LP_ADV_NEXT_PAGE;
1738 
1739  ap->link_time = ap->cur_time;
1740 
1741  ap->flags ^= (MR_TOGGLE_TX);
1742  if (ap->rxconfig & 0x0008)
1743  ap->flags |= MR_TOGGLE_RX;
1744  if (ap->rxconfig & ANEG_CFG_NP)
1745  ap->flags |= MR_NP_RX;
1746  ap->flags |= MR_PAGE_RX;
1747 
1748  ap->state = ANEG_STATE_COMPLETE_ACK;
1749  ret = ANEG_TIMER_ENAB;
1750  break;
1751 
1752  case ANEG_STATE_COMPLETE_ACK:
1753  if (ap->ability_match != 0 &&
1754  ap->rxconfig == 0) {
1755  ap->state = ANEG_STATE_AN_ENABLE;
1756  break;
1757  }
1758  delta = ap->cur_time - ap->link_time;
1759  if (delta > ANEG_STATE_SETTLE_TIME) {
1760  if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1761  ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1762  } else {
1763  if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1764  !(ap->flags & MR_NP_RX)) {
1765  ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1766  } else {
1767  ret = ANEG_FAILED;
1768  }
1769  }
1770  }
1771  break;
1772 
1773  case ANEG_STATE_IDLE_DETECT_INIT:
1774  ap->link_time = ap->cur_time;
1775  tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1776  tw32_f(MAC_MODE, tp->mac_mode);
1777  udelay(40);
1778 
1779  ap->state = ANEG_STATE_IDLE_DETECT;
1780  ret = ANEG_TIMER_ENAB;
1781  break;
1782 
1783  case ANEG_STATE_IDLE_DETECT:
1784  if (ap->ability_match != 0 &&
1785  ap->rxconfig == 0) {
1786  ap->state = ANEG_STATE_AN_ENABLE;
1787  break;
1788  }
1789  delta = ap->cur_time - ap->link_time;
1790  if (delta > ANEG_STATE_SETTLE_TIME) {
1791  /* XXX another gem from the Broadcom driver :( */
1792  ap->state = ANEG_STATE_LINK_OK;
1793  }
1794  break;
1795 
1796  case ANEG_STATE_LINK_OK:
1797  ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1798  ret = ANEG_DONE;
1799  break;
1800 
1801  case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1802  /* ??? unimplemented */
1803  break;
1804 
1805  case ANEG_STATE_NEXT_PAGE_WAIT:
1806  /* ??? unimplemented */
1807  break;
1808 
1809  default:
1810  ret = ANEG_FAILED;
1811  break;
1812  }
1813 
1814  return ret;
1815 }
1816 
1817 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1818 {
1819  int res = 0;
1820  struct tg3_fiber_aneginfo aninfo;
1821  int status = ANEG_FAILED;
1822  unsigned int tick;
1823  u32 tmp;
1824 
1825  tw32_f(MAC_TX_AUTO_NEG, 0);
1826 
1827  tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1828  tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1829  udelay(40);
1830 
1831  tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1832  udelay(40);
1833 
1834  memset(&aninfo, 0, sizeof(aninfo));
1835  aninfo.flags |= MR_AN_ENABLE;
1836  aninfo.state = ANEG_STATE_UNKNOWN;
1837  aninfo.cur_time = 0;
1838  tick = 0;
1839  while (++tick < 195000) {
1840  status = tg3_fiber_aneg_smachine(tp, &aninfo);
1841  if (status == ANEG_DONE || status == ANEG_FAILED)
1842  break;
1843 
1844  udelay(1);
1845  }
1846 
1847  tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1848  tw32_f(MAC_MODE, tp->mac_mode);
1849  udelay(40);
1850 
1851  *txflags = aninfo.txconfig;
1852  *rxflags = aninfo.flags;
1853 
1854  if (status == ANEG_DONE &&
1855  (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
1856  MR_LP_ADV_FULL_DUPLEX)))
1857  res = 1;
1858 
1859  return res;
1860 }
1861 
1862 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1863 {
1864  int current_link_up = 0;
1865 
1866  if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1867  goto out;
1868 
1869  if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1870  u32 txflags, rxflags;
1871  int i;
1872 
1873  if (fiber_autoneg(tp, &txflags, &rxflags)) {
1874  u32 local_adv = 0, remote_adv = 0;
1875 
1876  if (txflags & ANEG_CFG_PS1)
1877  local_adv |= ADVERTISE_1000XPAUSE;
1878  if (txflags & ANEG_CFG_PS2)
1879  local_adv |= ADVERTISE_1000XPSE_ASYM;
1880 
1881  if (rxflags & MR_LP_ADV_SYM_PAUSE)
1882  remote_adv |= LPA_1000XPAUSE;
1883  if (rxflags & MR_LP_ADV_ASYM_PAUSE)
1884  remote_adv |= LPA_1000XPAUSE_ASYM;
1885 
1886  tp->link_config.rmt_adv =
1887  mii_adv_to_ethtool_adv_x(remote_adv);
1888 
1889  tg3_setup_flow_control(tp, local_adv, remote_adv);
1890 
1891  current_link_up = 1;
1892  }
1893  for (i = 0; i < 30; i++) {
1894  udelay(20);
1895  tw32_f(MAC_STATUS,
1896  (MAC_STATUS_SYNC_CHANGED |
1897  MAC_STATUS_CFG_CHANGED));
1898  udelay(40);
1899  if ((tr32(MAC_STATUS) &
1900  (MAC_STATUS_SYNC_CHANGED |
1901  MAC_STATUS_CFG_CHANGED)) == 0)
1902  break;
1903  }
1904 
1905  mac_status = tr32(MAC_STATUS);
1906  if (!current_link_up &&
1907  (mac_status & MAC_STATUS_PCS_SYNCED) &&
1908  !(mac_status & MAC_STATUS_RCVD_CFG))
1909  current_link_up = 1;
1910  } else {
1911  tg3_setup_flow_control(tp, 0, 0);
1912 
1913  /* Forcing 1000FD link up. */
1914  current_link_up = 1;
1915 
1916  tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
1917  udelay(40);
1918 
1919  tw32_f(MAC_MODE, tp->mac_mode);
1920  udelay(40);
1921  }
1922 
1923 out:
1924  return current_link_up;
1925 }
1926 
1927 static int tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
1928 {
1929  if (curr_link_up != tp->link_up) {
1930  if (curr_link_up) {
1931  netdev_link_up(tp->dev);
1932  } else {
1933  netdev_link_down(tp->dev);
1934  if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
1935  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1936  }
1937 
1938  tg3_link_report(tp);
1939  return 1;
1940  }
1941 
1942  return 0;
1943 }
1944 
1945 static void tg3_clear_mac_status(struct tg3 *tp)
1946 {
1947  tw32(MAC_EVENT, 0);
1948 
1949  tw32_f(MAC_STATUS,
1950  MAC_STATUS_SYNC_CHANGED |
1951  MAC_STATUS_CFG_CHANGED |
1952  MAC_STATUS_MI_COMPLETION |
1953  MAC_STATUS_LNKSTATE_CHANGED);
1954  udelay(40);
1955 }
1956 
1957 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
1958 {
1959  u32 orig_pause_cfg;
1960  u16 orig_active_speed;
1961  u8 orig_active_duplex;
1962  u32 mac_status;
1963  int current_link_up = force_reset;
1964  int i;
1965 
1966  orig_pause_cfg = tp->link_config.active_flowctrl;
1967  orig_active_speed = tp->link_config.active_speed;
1968  orig_active_duplex = tp->link_config.active_duplex;
1969 
1970  if (!tg3_flag(tp, HW_AUTONEG) &&
1971  tp->link_up &&
1972  tg3_flag(tp, INIT_COMPLETE)) {
1973  mac_status = tr32(MAC_STATUS);
1974  mac_status &= (MAC_STATUS_PCS_SYNCED |
1975  MAC_STATUS_SIGNAL_DET |
1976  MAC_STATUS_CFG_CHANGED |
1977  MAC_STATUS_RCVD_CFG);
1978  if (mac_status == (MAC_STATUS_PCS_SYNCED |
1979  MAC_STATUS_SIGNAL_DET)) {
1980  tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
1981  MAC_STATUS_CFG_CHANGED));
1982  return 0;
1983  }
1984  }
1985 
1986  tw32_f(MAC_TX_AUTO_NEG, 0);
1987 
1988  tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1989  tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1990  tw32_f(MAC_MODE, tp->mac_mode);
1991  udelay(40);
1992 
1993  if (tp->phy_id == TG3_PHY_ID_BCM8002)
1994  tg3_init_bcm8002(tp);
1995 
1996  /* Enable link change event even when serdes polling. */
1997  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1998  udelay(40);
1999 
2000  current_link_up = 0;
2001  tp->link_config.rmt_adv = 0;
2002  mac_status = tr32(MAC_STATUS);
2003 
2004  if (tg3_flag(tp, HW_AUTONEG))
2005  current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2006  else
2007  current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2008 
2009  tp->hw_status->status =
2010  (SD_STATUS_UPDATED |
2011  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2012 
2013  for (i = 0; i < 100; i++) {
2014  tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2015  MAC_STATUS_CFG_CHANGED));
2016  udelay(5);
2017  if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2018  MAC_STATUS_CFG_CHANGED |
2019  MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2020  break;
2021  }
2022 
2023  mac_status = tr32(MAC_STATUS);
2024  if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2025  current_link_up = 0;
2026  if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2027  tp->serdes_counter == 0) {
2028  tw32_f(MAC_MODE, (tp->mac_mode |
2029  MAC_MODE_SEND_CONFIGS));
2030  udelay(1);
2031  tw32_f(MAC_MODE, tp->mac_mode);
2032  }
2033  }
2034 
2035  if (current_link_up) {
2036  tp->link_config.active_speed = SPEED_1000;
2037  tp->link_config.active_duplex = DUPLEX_FULL;
2038  tw32(MAC_LED_CTRL, (tp->led_ctrl |
2039  LED_CTRL_LNKLED_OVERRIDE |
2040  LED_CTRL_1000MBPS_ON));
2041  } else {
2042  tp->link_config.active_speed = SPEED_UNKNOWN;
2043  tp->link_config.active_duplex = DUPLEX_UNKNOWN;
2044  tw32(MAC_LED_CTRL, (tp->led_ctrl |
2045  LED_CTRL_LNKLED_OVERRIDE |
2046  LED_CTRL_TRAFFIC_OVERRIDE));
2047  }
2048 
2049  if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
2050  u32 now_pause_cfg = tp->link_config.active_flowctrl;
2051  if (orig_pause_cfg != now_pause_cfg ||
2052  orig_active_speed != tp->link_config.active_speed ||
2053  orig_active_duplex != tp->link_config.active_duplex)
2054  tg3_link_report(tp);
2055  }
2056 
2057  return 0;
2058 }
2059 
2060 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2061 {
2062  int err = 0;
2063  u32 bmsr, bmcr;
2064  u16 current_speed = SPEED_UNKNOWN;
2065  u8 current_duplex = DUPLEX_UNKNOWN;
2066  int current_link_up = 0;
2067  u32 local_adv, remote_adv, sgsr;
2068 
2069  if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2070  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2071  !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
2072  (sgsr & SERDES_TG3_SGMII_MODE)) {
2073 
2074  if (force_reset)
2075  tg3_phy_reset(tp);
2076 
2077  tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2078 
2079  if (!(sgsr & SERDES_TG3_LINK_UP)) {
2080  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2081  } else {
2082  current_link_up = 1;
2083  if (sgsr & SERDES_TG3_SPEED_1000) {
2084  current_speed = SPEED_1000;
2085  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2086  } else if (sgsr & SERDES_TG3_SPEED_100) {
2087  current_speed = SPEED_100;
2088  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2089  } else {
2090  current_speed = SPEED_10;
2091  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2092  }
2093 
2094  if (sgsr & SERDES_TG3_FULL_DUPLEX)
2095  current_duplex = DUPLEX_FULL;
2096  else
2097  current_duplex = DUPLEX_HALF;
2098  }
2099 
2100  tw32_f(MAC_MODE, tp->mac_mode);
2101  udelay(40);
2102 
2103  tg3_clear_mac_status(tp);
2104 
2105  goto fiber_setup_done;
2106  }
2107 
2108  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2109  tw32_f(MAC_MODE, tp->mac_mode);
2110  udelay(40);
2111 
2112  tg3_clear_mac_status(tp);
2113 
2114  if (force_reset)
2115  tg3_phy_reset(tp);
2116 
2117  tp->link_config.rmt_adv = 0;
2118 
2119  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2120  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2121  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2122  if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2123  bmsr |= BMSR_LSTATUS;
2124  else
2125  bmsr &= ~BMSR_LSTATUS;
2126  }
2127 
2128  err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2129 
2130  if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2131  (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
2132  /* do nothing, just check for link up at the end */
2133  } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2134  u32 adv, newadv;
2135 
2136  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2137  newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2138  ADVERTISE_1000XPAUSE |
2139  ADVERTISE_1000XPSE_ASYM |
2140  ADVERTISE_SLCT);
2141 
2142  newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2143  newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
2144 
2145  if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
2146  tg3_writephy(tp, MII_ADVERTISE, newadv);
2147  bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2148  tg3_writephy(tp, MII_BMCR, bmcr);
2149 
2150  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2151  tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2152  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
2153 
2154  return err;
2155  }
2156  } else {
2157  u32 new_bmcr;
2158 
2159  bmcr &= ~BMCR_SPEED1000;
2160  new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2161 
2162  if (tp->link_config.duplex == DUPLEX_FULL)
2163  new_bmcr |= BMCR_FULLDPLX;
2164 
2165  if (new_bmcr != bmcr) {
2166  /* BMCR_SPEED1000 is a reserved bit that needs
2167  * to be set on write.
2168  */
2169  new_bmcr |= BMCR_SPEED1000;
2170 
2171  /* Force a linkdown */
2172  if (tp->link_up) {
2173  u32 adv;
2174 
2175  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2176  adv &= ~(ADVERTISE_1000XFULL |
2177  ADVERTISE_1000XHALF |
2178  ADVERTISE_SLCT);
2179  tg3_writephy(tp, MII_ADVERTISE, adv);
2180  tg3_writephy(tp, MII_BMCR, bmcr |
2181  BMCR_ANRESTART |
2182  BMCR_ANENABLE);
2183  udelay(10);
2184  netdev_link_down(tp->dev);
2185  }
2186  tg3_writephy(tp, MII_BMCR, new_bmcr);
2187  bmcr = new_bmcr;
2188  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2189  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2190  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2191  if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2192  bmsr |= BMSR_LSTATUS;
2193  else
2194  bmsr &= ~BMSR_LSTATUS;
2195  }
2196  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
2197  }
2198  }
2199 
2200  if (bmsr & BMSR_LSTATUS) {
2201  current_speed = SPEED_1000;
2202  current_link_up = 1;
2203  if (bmcr & BMCR_FULLDPLX)
2204  current_duplex = DUPLEX_FULL;
2205  else
2206  current_duplex = DUPLEX_HALF;
2207 
2208  local_adv = 0;
2209  remote_adv = 0;
2210 
2211  if (bmcr & BMCR_ANENABLE) {
2212  u32 common;
2213 
2214  err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2215  err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2216  common = local_adv & remote_adv;
2217  if (common & (ADVERTISE_1000XHALF |
2218  ADVERTISE_1000XFULL)) {
2219  if (common & ADVERTISE_1000XFULL)
2220  current_duplex = DUPLEX_FULL;
2221  else
2222  current_duplex = DUPLEX_HALF;
2223 
2224  tp->link_config.rmt_adv =
2225  mii_adv_to_ethtool_adv_x(remote_adv);
2226  } else if (!tg3_flag(tp, 5780_CLASS)) {
2227  /* Link is up via parallel detect */
2228  } else {
2229  current_link_up = 0;
2230  }
2231  }
2232  }
2233 
2234 fiber_setup_done:
2235  if (current_link_up && current_duplex == DUPLEX_FULL)
2236  tg3_setup_flow_control(tp, local_adv, remote_adv);
2237 
2238  tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2239  if (tp->link_config.active_duplex == DUPLEX_HALF)
2240  tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2241 
2242  tw32_f(MAC_MODE, tp->mac_mode);
2243  udelay(40);
2244 
2245  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2246 
2247  tp->link_config.active_speed = current_speed;
2248  tp->link_config.active_duplex = current_duplex;
2249 
2250  tg3_test_and_report_link_chg(tp, current_link_up);
2251  return err;
2252 }
2253 
2254 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2255 { DBGP("%s\n", __func__);
2256 
2257  int current_link_up;
2258  u32 bmsr, val;
2259  u32 lcl_adv, rmt_adv;
2260  u16 current_speed;
2261  u8 current_duplex;
2262  int i, err;
2263 
2264  tw32(MAC_EVENT, 0);
2265 
2266  tw32_f(MAC_STATUS,
2267  (MAC_STATUS_SYNC_CHANGED |
2268  MAC_STATUS_CFG_CHANGED |
2269  MAC_STATUS_MI_COMPLETION |
2270  MAC_STATUS_LNKSTATE_CHANGED));
2271  udelay(40);
2272 
2273  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2274  tw32_f(MAC_MI_MODE,
2275  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2276  udelay(80);
2277  }
2278 
2279  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
2280 
2281  /* Some third-party PHYs need to be reset on link going
2282  * down.
2283  */
2284  if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2285  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2286  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2287  netdev_link_ok(tp->dev)) {
2288  tg3_readphy(tp, MII_BMSR, &bmsr);
2289  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2290  !(bmsr & BMSR_LSTATUS))
2291  force_reset = 1;
2292  }
2293  if (force_reset)
2294  tg3_phy_reset(tp);
2295 
2296  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2297  tg3_readphy(tp, MII_BMSR, &bmsr);
2298  if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2299  !tg3_flag(tp, INIT_COMPLETE))
2300  bmsr = 0;
2301 
2302  if (!(bmsr & BMSR_LSTATUS)) {
2303  err = tg3_init_5401phy_dsp(tp);
2304  if (err)
2305  return err;
2306 
2307  tg3_readphy(tp, MII_BMSR, &bmsr);
2308  for (i = 0; i < 1000; i++) {
2309  udelay(10);
2310  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2311  (bmsr & BMSR_LSTATUS)) {
2312  udelay(40);
2313  break;
2314  }
2315  }
2316 
2317  if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
2318  TG3_PHY_REV_BCM5401_B0 &&
2319  !(bmsr & BMSR_LSTATUS) &&
2320  tp->link_config.active_speed == SPEED_1000) {
2321  err = tg3_phy_reset(tp);
2322  if (!err)
2323  err = tg3_init_5401phy_dsp(tp);
2324  if (err)
2325  return err;
2326  }
2327  }
2328  } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2329  tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2330  /* 5701 {A0,B0} CRC bug workaround */
2331  tg3_writephy(tp, 0x15, 0x0a75);
2332  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
2333  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2334  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
2335  }
2336 
2337  /* Clear pending interrupts... */
2338  tg3_readphy(tp, MII_TG3_ISTAT, &val);
2339  tg3_readphy(tp, MII_TG3_ISTAT, &val);
2340 
2341  if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
2342  tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2343  else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
2344  tg3_writephy(tp, MII_TG3_IMASK, ~0);
2345 
2346  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2347  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2348  if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2349  tg3_writephy(tp, MII_TG3_EXT_CTRL,
2350  MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2351  else
2352  tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2353  }
2354 
2355  current_link_up = 0;
2356  current_speed = SPEED_INVALID;
2357  current_duplex = DUPLEX_INVALID;
2358 
2359  if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
2360  err = tg3_phy_auxctl_read(tp,
2361  MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
2362  &val);
2363  if (!err && !(val & (1 << 10))) {
2364  tg3_phy_auxctl_write(tp,
2365  MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
2366  val | (1 << 10));
2367  goto relink;
2368  }
2369  }
2370 
2371  bmsr = 0;
2372  for (i = 0; i < 100; i++) {
2373  tg3_readphy(tp, MII_BMSR, &bmsr);
2374  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2375  (bmsr & BMSR_LSTATUS))
2376  break;
2377  udelay(40);
2378  }
2379 
2380  if (bmsr & BMSR_LSTATUS) {
2381  u32 aux_stat, bmcr;
2382 
2383  tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2384  for (i = 0; i < 2000; i++) {
2385  udelay(10);
2386  if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2387  aux_stat)
2388  break;
2389  }
2390 
2391  tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2392  &current_speed,
2393  &current_duplex);
2394 
2395  bmcr = 0;
2396  for (i = 0; i < 200; i++) {
2397  tg3_readphy(tp, MII_BMCR, &bmcr);
2398  if (tg3_readphy(tp, MII_BMCR, &bmcr))
2399  continue;
2400  if (bmcr && bmcr != 0x7fff)
2401  break;
2402  udelay(10);
2403  }
2404 
2405  lcl_adv = 0;
2406  rmt_adv = 0;
2407 
2408  tp->link_config.active_speed = current_speed;
2409  tp->link_config.active_duplex = current_duplex;
2410 
2411  if ((bmcr & BMCR_ANENABLE) &&
2412  tg3_copper_is_advertising_all(tp,
2413  tp->link_config.advertising)) {
2414  if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2415  &rmt_adv)) {
2416  current_link_up = 1;
2417  }
2418  }
2419 
2420  if (current_link_up == 1 &&
2421  tp->link_config.active_duplex == DUPLEX_FULL)
2422  tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2423  }
2424 
2425 relink:
2426  if (current_link_up == 0) {
2427  tg3_phy_copper_begin(tp);
2428 
2429  tg3_readphy(tp, MII_BMSR, &bmsr);
2430  if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
2431  (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
2432  current_link_up = 1;
2433  }
2434 
2435  tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2436  if (current_link_up == 1) {
2437  if (tp->link_config.active_speed == SPEED_100 ||
2438  tp->link_config.active_speed == SPEED_10)
2439  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2440  else
2441  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2442  } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2443  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2444  else
2445  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2446 
2447  tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2448  if (tp->link_config.active_duplex == DUPLEX_HALF)
2449  tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2450 
2451  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2452  if (current_link_up == 1 &&
2453  tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2454  tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2455  else
2456  tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2457  }
2458 
2459  /* ??? Without this setting Netgear GA302T PHY does not
2460  * ??? send/receive packets...
2461  */
2462  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
2463  tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2464  tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2465  tw32_f(MAC_MI_MODE, tp->mi_mode);
2466  udelay(80);
2467  }
2468 
2469  tw32_f(MAC_MODE, tp->mac_mode);
2470  udelay(40);
2471 
2472  /* Enabled attention when the link has changed state. */
2473  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2474  udelay(40);
2475 
2476  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2477  current_link_up == 1 &&
2478  tp->link_config.active_speed == SPEED_1000 &&
2479  (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
2480  udelay(120);
2481  /* NOTE: this freezes for mdc? */
2482  tw32_f(MAC_STATUS,
2483  (MAC_STATUS_SYNC_CHANGED |
2484  MAC_STATUS_CFG_CHANGED));
2485  udelay(40);
2486  tg3_write_mem(tp,
2487  NIC_SRAM_FIRMWARE_MBOX,
2488  NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2489  }
2490 
2491  /* Prevent send BD corruption. */
2492  if (tg3_flag(tp, CLKREQ_BUG)) {
2493  u16 oldlnkctl, newlnkctl;
2494 
2495  pci_read_config_word(tp->pdev,
2496  tp->pcie_cap + PCI_EXP_LNKCTL,
2497  &oldlnkctl);
2498  if (tp->link_config.active_speed == SPEED_100 ||
2499  tp->link_config.active_speed == SPEED_10)
2500  newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2501  else
2502  newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2503  if (newlnkctl != oldlnkctl)
2504  pci_write_config_word(tp->pdev,
2505  tp->pcie_cap + PCI_EXP_LNKCTL,
2506  newlnkctl);
2507  }
2508 
2509  if (current_link_up != netdev_link_ok(tp->dev)) {
2510  if (current_link_up)
2511  netdev_link_up(tp->dev);
2512  else
2513  netdev_link_down(tp->dev);
2514  tg3_link_report(tp);
2515  }
2516 
2517  return 0;
2518 }
2519 
2520 int tg3_setup_phy(struct tg3 *tp, int force_reset)
2521 { DBGP("%s\n", __func__);
2522 
2523  u32 val;
2524  int err;
2525 
2526  if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
2527  err = tg3_setup_fiber_phy(tp, force_reset);
2528  else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2529  err = tg3_setup_fiber_mii_phy(tp, force_reset);
2530  else
2531  err = tg3_setup_copper_phy(tp, force_reset);
2532 
2533  val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2534  (6 << TX_LENGTHS_IPG_SHIFT);
2535  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
2536  val |= tr32(MAC_TX_LENGTHS) &
2537  (TX_LENGTHS_JMB_FRM_LEN_MSK |
2538  TX_LENGTHS_CNT_DWN_VAL_MSK);
2539 
2540  if (tp->link_config.active_speed == SPEED_1000 &&
2541  tp->link_config.active_duplex == DUPLEX_HALF)
2542  tw32(MAC_TX_LENGTHS, val |
2543  (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
2544  else
2545  tw32(MAC_TX_LENGTHS, val |
2546  (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
2547 
2548  if (!tg3_flag(tp, 5705_PLUS)) {
2549  if (netdev_link_ok(tp->dev)) {
2550  tw32(HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS);
2551  } else {
2552  tw32(HOSTCC_STAT_COAL_TICKS, 0);
2553  }
2554  }
2555 
2556  val = tr32(PCIE_PWR_MGMT_THRESH);
2557  if (!netdev_link_ok(tp->dev))
2558  val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK);
2559  else
2560  val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
2561  tw32(PCIE_PWR_MGMT_THRESH, val);
2562 
2563  return err;
2564 }
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Definition: tg3_phy.c:858
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#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT
Definition: tg3.h:231
ANEG_DONE
#define ANEG_DONE
Definition: tg3_phy.c:1348
CHIPREV_ID_5701_B0
#define CHIPREV_ID_5701_B0
Definition: tg3.h:268
MAC_MODE_PORT_MODE_MASK
#define MAC_MODE_PORT_MODE_MASK
Definition: tg3.h:504
ASIC_REV_5700
#define ASIC_REV_5700
Definition: tg3.h:299
tg3_phy_auxctl_write
static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
Definition: tg3_phy.c:422
NIC_SRAM_FW_CMD_MBOX
#define NIC_SRAM_FW_CMD_MBOX
Definition: tg3.h:2234
ASIC_REV_5906
#define ASIC_REV_5906
Definition: tg3.h:310
TG3_PHY_ID_REV_MASK
#define TG3_PHY_ID_REV_MASK
Definition: tg3.h:3214
ANEG_CFG_PS1
#define ANEG_CFG_PS1
Definition: tg3_phy.c:1341
PHY_BUSY_LOOPS
#define PHY_BUSY_LOOPS
Definition: tg3_phy.c:83
BMCR_ANRESTART
#define BMCR_ANRESTART
Definition: mii.h:46
MR_AN_ENABLE
#define MR_AN_ENABLE
Definition: tg3_phy.c:1310
MI_COM_PHY_ADDR_SHIFT
#define MI_COM_PHY_ADDR_SHIFT
Definition: tg3.h:611
MAC_STATUS_MI_COMPLETION
#define MAC_STATUS_MI_COMPLETION
Definition: tg3.h:538
LPA_1000XPAUSE
#define LPA_1000XPAUSE
Definition: mii.h:102
tg3_fiber_aneginfo::idle_match
char idle_match
Definition: tg3_phy.c:1333
MII_TG3_AUXCTL_MISC_WIRESPD_EN
#define MII_TG3_AUXCTL_MISC_WIRESPD_EN
Definition: tg3.h:2372
tg3_poll_link
void tg3_poll_link(struct tg3 *tp)
Definition: tg3_phy.c:1008
ADVERTISE_100FULL
#define ADVERTISE_100FULL
Definition: mii.h:80
MII_TG3_DSP_RW_PORT
#define MII_TG3_DSP_RW_PORT
Definition: tg3.h:2332
SERDES_TG3_SGMII_MODE
#define SERDES_TG3_SGMII_MODE
Definition: tg3.h:2443
MII_TG3_AUXCTL_SHDWSEL_MISC
#define MII_TG3_AUXCTL_SHDWSEL_MISC
Definition: tg3.h:2371
MII_TG3_IMASK
#define MII_TG3_IMASK
Definition: tg3.h:2392
TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
Definition: tg3.h:235
TG3_CPMU_PHY_STRAP_IS_SERDES
#define TG3_CPMU_PHY_STRAP_IS_SERDES
Definition: tg3.h:1263
SERDES_TG3_SPEED_1000
#define SERDES_TG3_SPEED_1000
Definition: tg3.h:2447
OTP_MODE
#define OTP_MODE
Definition: tg3.h:2065
MII_TG3_AUXCTL_MISC_FORCE_AMDIX
#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX
Definition: tg3.h:2373
pci_read_config_word
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
OTP_CTRL_OTP_CMD_INIT
#define OTP_CTRL_OTP_CMD_INIT
Definition: tg3.h:2070
netdev_link_down
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:230
SERDES_AN_TIMEOUT_5714S
#define SERDES_AN_TIMEOUT_5714S
Definition: tg3.h:3152
SG_DIG_AUTONEG_COMPLETE
#define SG_DIG_AUTONEG_COMPLETE
Definition: tg3.h:909
ASIC_REV_5720
#define ASIC_REV_5720
Definition: tg3.h:320
MAC_MODE_LINK_POLARITY
#define MAC_MODE_LINK_POLARITY
Definition: tg3.h:513
tulip_private::advertising
u16 advertising[4]
Definition: tulip.c:418
tg3_advert_flowctrl_1000X
static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
Definition: tg3_phy.c:1354
TG3PCI_DEVICE_TIGON3_5718
#define TG3PCI_DEVICE_TIGON3_5718
Definition: tg3.h:198
tg3_adv_1000T_flowctrl_ok
static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
Definition: tg3_phy.c:1066
MII_TG3_AUX_STAT_10FULL
#define MII_TG3_AUX_STAT_10FULL
Definition: tg3.h:2382
SG_DIG_STATUS
#define SG_DIG_STATUS
Definition: tg3.h:897
ADVERTISED_FIBRE
#define ADVERTISED_FIBRE
Definition: tg3_phy.c:861
MAC_STATUS_CFG_CHANGED
#define MAC_STATUS_CFG_CHANGED
Definition: tg3.h:534
flowctrl
static int flowctrl
Definition: sundance.c:75
TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
Definition: tg3.h:236
MR_RESTART_AN
#define MR_RESTART_AN
Definition: tg3_phy.c:1311
MR_NP_RX
#define MR_NP_RX
Definition: tg3_phy.c:1324
TX_LENGTHS_JMB_FRM_LEN_MSK
#define TX_LENGTHS_JMB_FRM_LEN_MSK
Definition: tg3.h:649
TG3_OTP_HPFFLTR_MASK
#define TG3_OTP_HPFFLTR_MASK
Definition: tg3.h:2123
SG_DIG_SOFT_RESET
#define SG_DIG_SOFT_RESET
Definition: tg3.h:865
SPEED_10
#define SPEED_10
Definition: atl1e.h:50
TG3PCI_DUAL_MAC_CTRL
#define TG3PCI_DUAL_MAC_CTRL
Definition: tg3.h:415
ADVERTISED_TP
#define ADVERTISED_TP
Definition: tg3_phy.c:860
LED_CTRL_TRAFFIC_OVERRIDE
#define LED_CTRL_TRAFFIC_OVERRIDE
Definition: tg3.h:558
tg3_phy_reset_chanpat
static int tg3_phy_reset_chanpat(struct tg3 *tp)
Definition: tg3_phy.c:389
TG3PCI_SUBDEVICE_ID_3COM_3C996T
#define TG3PCI_SUBDEVICE_ID_3COM_3C996T
Definition: tg3.h:223
MII_TG3_FET_SHADOW_EN
#define MII_TG3_FET_SHADOW_EN
Definition: tg3.h:2430
SG_DIG_PARTNER_PAUSE_CAPABLE
#define SG_DIG_PARTNER_PAUSE_CAPABLE
Definition: tg3.h:901
MAC_MODE_PORT_MODE_TBI
#define MAC_MODE_PORT_MODE_TBI
Definition: tg3.h:505
ANEG_CFG_RF2
#define ANEG_CFG_RF2
Definition: tg3_phy.c:1338
CHIPREV_ID_5704_A1
#define CHIPREV_ID_5704_A1
Definition: tg3.h:276
TG3_OTP_ROFF_MASK
#define TG3_OTP_ROFF_MASK
Definition: tg3.h:2133
MII_TG3_DSP_EXP75
#define MII_TG3_DSP_EXP75
Definition: tg3.h:2351
GET_ASIC_REV
#define GET_ASIC_REV(CHIP_REV_ID)
Definition: tg3.h:298
tg3_setup_fiber_mii_phy
static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2060
CHIPREV_ID_57765_A0
#define CHIPREV_ID_57765_A0
Definition: tg3.h:295
MII_TG3_AUX_STAT_SPDMASK
#define MII_TG3_AUX_STAT_SPDMASK
Definition: tg3.h:2380
ANEG_STATE_NEXT_PAGE_WAIT
#define ANEG_STATE_NEXT_PAGE_WAIT
Definition: tg3_phy.c:1307
tg3_phydsp_write
static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
Definition: tg3_phy.c:410
out
__be32 out[4]
Definition: CIB_PRM.h:36
CPMU_CTRL_GPHY_10MB_RXONLY
#define CPMU_CTRL_GPHY_10MB_RXONLY
Definition: tg3.h:1223
MAC_STATUS_SIGNAL_DET
#define MAC_STATUS_SIGNAL_DET
Definition: tg3.h:532
tg3_setup_phy
int tg3_setup_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2520
TX_LENGTHS_CNT_DWN_VAL_MSK
#define TX_LENGTHS_CNT_DWN_VAL_MSK
Definition: tg3.h:650
TX_STATUS_LINK_UP
#define TX_STATUS_LINK_UP
Definition: tg3.h:639
FLOW_CTRL_TX
#define FLOW_CTRL_TX
Definition: bnx2.h:4152
TG3_PHYFLG_PHY_SERDES
#define TG3_PHYFLG_PHY_SERDES
Definition: tg3.h:3237
ANEG_STATE_IDLE_DETECT_INIT
#define ANEG_STATE_IDLE_DETECT_INIT
Definition: tg3_phy.c:1303
ADVERTISED_1000baseT_Half
#define ADVERTISED_1000baseT_Half
Definition: bnx2.h:46
tg3_fiber_aneg_smachine
static int tg3_fiber_aneg_smachine(struct tg3 *tp, struct tg3_fiber_aneginfo *ap)
Definition: tg3_phy.c:1565
TG3_PHYFLG_MII_SERDES
#define TG3_PHYFLG_MII_SERDES
Definition: tg3.h:3238
TG3_PHY_REV_BCM5401_B0
#define TG3_PHY_REV_BCM5401_B0
Definition: tg3.h:3215
MII_TG3_INT_LINKCHG
#define MII_TG3_INT_LINKCHG
Definition: tg3.h:2395
subsys_tbl_ent::subsys_devid
u16 subsys_devid
Definition: tg3_phy.c:136
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
Definition: tg3.h:218
tmp
unsigned long tmp
Definition: linux_pci.h:53
BMCR_SPEED1000
#define BMCR_SPEED1000
Definition: mii.h:43
TG3_PHY_AUXCTL_SMDSP_ENABLE
#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)
Definition: tg3_phy.c:431
status
uint8_t status
Status.
Definition: ena.h:16
SPEED_100
#define SPEED_100
Definition: atl1e.h:51
MII_TG3_AUX_STAT
#define MII_TG3_AUX_STAT
Definition: tg3.h:2378
TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
Definition: tg3.h:238
TG3_PHY_MII_ADDR
#define TG3_PHY_MII_ADDR
Definition: tg3.h:2306
MII_TG3_TEST1_TRIM_EN
#define MII_TG3_TEST1_TRIM_EN
Definition: tg3.h:2415
TX_MODE_FLOW_CTRL_ENABLE
#define TX_MODE_FLOW_CTRL_ENABLE
Definition: tg3.h:629
MII_TG3_FET_SHDW_MISCCTRL_MDIX
#define MII_TG3_FET_SHDW_MISCCTRL_MDIX
Definition: tg3.h:2433
tg3_setup_flow_control
static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Definition: tg3_phy.c:1123
TG3_PHYFLG_CAPACITIVE_COUPLING
#define TG3_PHYFLG_CAPACITIVE_COUPLING
Definition: tg3.h:3244
MR_AN_COMPLETE
#define MR_AN_COMPLETE
Definition: tg3_phy.c:1312
ADVERTISE_1000XHALF
#define ADVERTISE_1000XHALF
Definition: mii.h:77
TG3_PHYFLG_ANY_SERDES
#define TG3_PHYFLG_ANY_SERDES
Definition: tg3.h:3239
fiber_autoneg
static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Definition: tg3_phy.c:1817
DUAL_MAC_CTRL_ID
#define DUAL_MAC_CTRL_ID
Definition: tg3.h:417
OTP_CTRL
#define OTP_CTRL
Definition: tg3.h:2067
TG3_OTP_LPFDIS_SHIFT
#define TG3_OTP_LPFDIS_SHIFT
Definition: tg3.h:2128
tg3_fiber_aneginfo::link_time
unsigned long link_time
Definition: tg3_phy.c:1328
tg3_phy_reset
int tg3_phy_reset(struct tg3 *tp)
Definition: tg3_phy.c:621
MII_TG3_AUX_STAT_100HALF
#define MII_TG3_AUX_STAT_100HALF
Definition: tg3.h:2383
tg3_phy_init_link_config
static void tg3_phy_init_link_config(struct tg3 *tp)
Definition: tg3_phy.c:865
mii_adv_to_ethtool_adv_x
static u32 mii_adv_to_ethtool_adv_x(u32 adv)
Definition: tg3.h:3436
TG3_PHY_ID_BCM5701
#define TG3_PHY_ID_BCM5701
Definition: tg3.h:3189
TG3_PHYFLG_IS_FET
#define TG3_PHYFLG_IS_FET
Definition: tg3.h:3241
TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
Definition: tg3.h:234
LPA_1000XPAUSE_ASYM
#define LPA_1000XPAUSE_ASYM
Definition: mii.h:104
TG3PCI_SUBDEVICE_ID_3COM_3C1000T
#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T
Definition: tg3.h:226
TG3_PHY_ID_BCM8002
#define TG3_PHY_ID_BCM8002
Definition: tg3.h:3208
TG3_OTP_VDAC_MASK
#define TG3_OTP_VDAC_MASK
Definition: tg3.h:2129
DBGP
#define DBGP(...)
Definition: compiler.h:532
MII_TG3_CTRL_ENABLE_AS_MASTER
#define MII_TG3_CTRL_ENABLE_AS_MASTER
Definition: tg3.h:2316
MAC_TX_LENGTHS
#define MAC_TX_LENGTHS
Definition: tg3.h:642
ADVERTISE_SLCT
#define ADVERTISE_SLCT
Definition: mii.h:72
TG3_OTP_VDAC_SHIFT
#define TG3_OTP_VDAC_SHIFT
Definition: tg3.h:2130
TG3_OTP_HPFOVER_SHIFT
#define TG3_OTP_HPFOVER_SHIFT
Definition: tg3.h:2126
ANEG_FAILED
#define ANEG_FAILED
Definition: tg3_phy.c:1350
MII_TG3_ISTAT
#define MII_TG3_ISTAT
Definition: tg3.h:2391
ANEG_CFG_RF1
#define ANEG_CFG_RF1
Definition: tg3_phy.c:1339
tg3_flag_set
#define tg3_flag_set(tp, flag)
Definition: tg3.h:3367
MII_TG3_FET_TEST
#define MII_TG3_FET_TEST
Definition: tg3.h:2429
MAC_STATUS_SYNC_CHANGED
#define MAC_STATUS_SYNC_CHANGED
Definition: tg3.h:535
DUPLEX_INVALID
#define DUPLEX_INVALID
Definition: bnx2.h:112
TX_LENGTHS_SLOT_TIME_SHIFT
#define TX_LENGTHS_SLOT_TIME_SHIFT
Definition: tg3.h:644
TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
Definition: tg3.h:237
MR_LP_ADV_REMOTE_FAULT1
#define MR_LP_ADV_REMOTE_FAULT1
Definition: tg3_phy.c:1320
NIC_SRAM_FW_CMD_DATA_MBOX
#define NIC_SRAM_FW_CMD_DATA_MBOX
Definition: tg3.h:2245
tg3_advert_flowctrl_1000T
static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
Definition: tg3_phy.c:774
netdev_link_up
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:774
SERDES_AN_TIMEOUT_5704S
#define SERDES_AN_TIMEOUT_5704S
Definition: tg3.h:3150
tg3_fiber_aneginfo::state
int state
Definition: tg3_phy.c:1291
NIC_SRAM_FW_CMD_LEN_MBOX
#define NIC_SRAM_FW_CMD_LEN_MBOX
Definition: tg3.h:2244
RX_MODE_FLOW_CTRL_ENABLE
#define RX_MODE_FLOW_CTRL_ENABLE
Definition: tg3.h:654
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
netdev_link_ok
static int netdev_link_ok(struct net_device *netdev)
Check link state of network device.
Definition: netdevice.h:636
TG3PCI_SUBDEVICE_ID_DELL_VIPER
#define TG3PCI_SUBDEVICE_ID_DELL_VIPER
Definition: tg3.h:229
ANEG_CFG_PS2
#define ANEG_CFG_PS2
Definition: tg3_phy.c:1340
TG3_PHYFLG_ADC_BUG
#define TG3_PHYFLG_ADC_BUG
Definition: tg3.h:3248
tg3_phy_autoneg_cfg
static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
Definition: tg3_phy.c:791
DUPLEX_FULL
#define DUPLEX_FULL
Definition: bnx2.h:111
DUPLEX_UNKNOWN
#define DUPLEX_UNKNOWN
Definition: tg3.h:156
LED_CTRL_MODE_PHY_1
#define LED_CTRL_MODE_PHY_1
Definition: tg3.h:566
MII_TG3_AUX_STAT_1000HALF
#define MII_TG3_AUX_STAT_1000HALF
Definition: tg3.h:2386
tg3_init_5401phy_dsp
static int tg3_init_5401phy_dsp(struct tg3 *tp)
Definition: tg3_phy.c:838
ethtool_adv_to_mii_adv_x
static u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
Definition: tg3.h:3452
TG3PCI_SUBDEVICE_ID_3COM_3C996BT
#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT
Definition: tg3.h:224
tp
static struct tulip_private * tp
Definition: tulip.c:441
MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
Definition: tg3.h:2374
SPEED_UNKNOWN
#define SPEED_UNKNOWN
Definition: tg3.h:150
MII_TG3_DSP_EXP8_REJ2MHz
#define MII_TG3_DSP_EXP8_REJ2MHz
Definition: tg3.h:2349
TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
Definition: tg3.h:227
TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
Definition: tg3.h:230
ASIC_REV_5704
#define ASIC_REV_5704
Definition: tg3.h:302
MII_CTRL1000
#define MII_CTRL1000
Definition: mii.h:24
tg3_bmcr_reset
static int tg3_bmcr_reset(struct tg3 *tp)
Definition: tg3_phy.c:271
MII_TG3_DSP_AADJ1CH0
#define MII_TG3_DSP_AADJ1CH0
Definition: tg3.h:2342
MII_TG3_DSP_EXP8_AEDW
#define MII_TG3_DSP_EXP8_AEDW
Definition: tg3.h:2350
tg3_fiber_aneginfo::flags
u32 flags
Definition: tg3_phy.c:1309
ASIC_REV_5705
#define ASIC_REV_5705
Definition: tg3.h:303
TG3_PHYFLG_ADJUST_TRIM
#define TG3_PHYFLG_ADJUST_TRIM
Definition: tg3.h:3247
MR_LINK_OK
#define MR_LINK_OK
Definition: tg3_phy.c:1326
ASIC_REV_5719
#define ASIC_REV_5719
Definition: tg3.h:319
ADVERTISE_1000XPSE_ASYM
#define ADVERTISE_1000XPSE_ASYM
Definition: mii.h:81
ASIC_REV_5703
#define ASIC_REV_5703
Definition: tg3.h:301
SD_STATUS_LINK_CHG
#define SD_STATUS_LINK_CHG
Definition: tg3.h:2673
tg3_setup_fiber_hw_autoneg
static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
Definition: tg3_phy.c:1420
high
uint32_t high
High 32 bits of address.
Definition: myson.h:20
tg3_init_bcm8002
static void tg3_init_bcm8002(struct tg3 *tp)
Definition: tg3_phy.c:1370
FWCMD_NICDRV_LINK_UPDATE
#define FWCMD_NICDRV_LINK_UPDATE
Definition: tg3.h:2241
MAC_MODE_PORT_INT_LPBACK
#define MAC_MODE_PORT_INT_LPBACK
Definition: tg3.h:509
OTP_ADDRESS_MAGIC1
#define OTP_ADDRESS_MAGIC1
Definition: tg3.h:2075
ANEG_STATE_ABILITY_DETECT_INIT
#define ANEG_STATE_ABILITY_DETECT_INIT
Definition: tg3_phy.c:1297
MII_TG3_MISC_SHDW
#define MII_TG3_MISC_SHDW
Definition: tg3.h:2400
MAC_MODE_PORT_MODE_MII
#define MAC_MODE_PORT_MODE_MII
Definition: tg3.h:507
MII_TG3_DSP_EXP8
#define MII_TG3_DSP_EXP8
Definition: tg3.h:2348
TG3_CPMU_CTRL
#define TG3_CPMU_CTRL
Definition: tg3.h:1219
SG_DIG_ASYM_PAUSE
#define SG_DIG_ASYM_PAUSE
Definition: tg3.h:880
ADVERTISE_PAUSE_ASYM
#define ADVERTISE_PAUSE_ASYM
Definition: mii.h:84
TG3_OTP_HPFOVER_MASK
#define TG3_OTP_HPFOVER_MASK
Definition: tg3.h:2125
limit
uint16_t limit
Limit.
Definition: librm.h:250
BMSR_LSTATUS
#define BMSR_LSTATUS
Definition: mii.h:57
MR_TOGGLE_RX
#define MR_TOGGLE_RX
Definition: tg3_phy.c:1323
ANEG_STATE_IDLE_DETECT
#define ANEG_STATE_IDLE_DETECT
Definition: tg3_phy.c:1304
tg3_flag
#define tg3_flag(tp, flag)
Definition: tg3.h:3365
SG_DIG_IS_SERDES
#define SG_DIG_IS_SERDES
Definition: tg3.h:906
MI_COM_CMD_READ
#define MI_COM_CMD_READ
Definition: tg3.h:606
MII_TG3_DSP_EXP96
#define MII_TG3_DSP_EXP96
Definition: tg3.h:2352
LED_CTRL_LNKLED_OVERRIDE
#define LED_CTRL_LNKLED_OVERRIDE
Definition: tg3.h:554
tg3_fiber_aneginfo::ability_match
char ability_match
Definition: tg3_phy.c:1333
TG3_PHY_ID_INVALID
#define TG3_PHY_ID_INVALID
Definition: tg3.h:3209
AUTONEG_ENABLE
#define AUTONEG_ENABLE
Definition: tg3_phy.c:863
GRC_MISC_CFG_EPHY_IDDQ
#define GRC_MISC_CFG_EPHY_IDDQ
Definition: tg3.h:1835
MII_TG3_FET_PTEST
#define MII_TG3_FET_PTEST
Definition: tg3.h:2425
tg3_test_and_report_link_chg
static int tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
Definition: tg3_phy.c:1927
pci.h
PCI bus.
LED_CTRL_1000MBPS_ON
#define LED_CTRL_1000MBPS_ON
Definition: tg3.h:555
MII_TG3_AUX_STAT_FULL
#define MII_TG3_AUX_STAT_FULL
Definition: tg3.h:2389
MII_TG3_AUXCTL_SHDWSEL_MISCTEST
#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST
Definition: tg3.h:2369
CHIPREV_ID_5700_ALTIMA
#define CHIPREV_ID_5700_ALTIMA
Definition: tg3.h:265
TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
Definition: tg3.h:216
ANEG_OK
#define ANEG_OK
Definition: tg3_phy.c:1347
MAC_MODE_PORT_MODE_GMII
#define MAC_MODE_PORT_MODE_GMII
Definition: tg3.h:506
SG_DIG_CTRL
#define SG_DIG_CTRL
Definition: tg3.h:863
MAC_EVENT_LNKSTATE_CHANGED
#define MAC_EVENT_LNKSTATE_CHANGED
Definition: tg3.h:546
TG3_OTP_AGCTGT_MASK
#define TG3_OTP_AGCTGT_MASK
Definition: tg3.h:2121
TG3_PHY_AUXCTL_SMDSP_DISABLE
#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp)
Definition: tg3_phy.c:436
MII_TG3_DSP_AADJ1CH3
#define MII_TG3_DSP_AADJ1CH3
Definition: tg3.h:2345
ENODEV
#define ENODEV
No such device.
Definition: errno.h:509
MI_COM_REG_ADDR_SHIFT
#define MI_COM_REG_ADDR_SHIFT
Definition: tg3.h:613
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
CHIPREV_5761_AX
#define CHIPREV_5761_AX
Definition: tg3.h:332
SERDES_PARALLEL_DET_TIMEOUT
#define SERDES_PARALLEL_DET_TIMEOUT
Definition: tg3.h:3151
MAC_MODE_HALF_DUPLEX
#define MAC_MODE_HALF_DUPLEX
Definition: tg3.h:503
SERDES_TG3_1000X_STATUS
#define SERDES_TG3_1000X_STATUS
Definition: tg3.h:2442
tg3_fiber_aneginfo::ability_match_count
int ability_match_count
Definition: tg3_phy.c:1331
MAC_EVENT
#define MAC_EVENT
Definition: tg3.h:544
SG_DIG_USING_HW_AUTONEG
#define SG_DIG_USING_HW_AUTONEG
Definition: tg3.h:864
tg3_fiber_aneginfo::ability_match_cfg
u32 ability_match_cfg
Definition: tg3_phy.c:1330
MII_BMCR
#define MII_BMCR
Definition: atl1e.h:871
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
Definition: tg3.h:217
TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
Definition: tg3.h:211
tw32_f
#define tw32_f(reg, val)
Definition: tg3.h:3333
MII_TG3_DSP_TAP1_AGCTGT_DFLT
#define MII_TG3_DSP_TAP1_AGCTGT_DFLT
Definition: tg3.h:2337
FLOW_CTRL_RX
#define FLOW_CTRL_RX
Definition: bnx2.h:4153
SERDES_TG3_FULL_DUPLEX
#define SERDES_TG3_FULL_DUPLEX
Definition: tg3.h:2445
ADVERTISE_1000HALF
#define ADVERTISE_1000HALF
Definition: mii.h:134
OTP_MODE_OTP_THRU_GRC
#define OTP_MODE_OTP_THRU_GRC
Definition: tg3.h:2066
TG3_OTP_10BTAMP_MASK
#define TG3_OTP_10BTAMP_MASK
Definition: tg3.h:2131
common
struct ib_cm_common common
Definition: ib_mad.h:11
ADVERTISE_CSMA
#define ADVERTISE_CSMA
Definition: mii.h:73
SG_DIG_PAUSE_CAP
#define SG_DIG_PAUSE_CAP
Definition: tg3.h:879
MII_TG3_EXT_CTRL
#define MII_TG3_EXT_CTRL
Definition: tg3.h:2322
MII_TG3_EXT_CTRL_LNK3_LED_MODE
#define MII_TG3_EXT_CTRL_LNK3_LED_MODE
Definition: tg3.h:2324
tg3_fiber_aneginfo::rxconfig
u32 rxconfig
Definition: tg3_phy.c:1335
MAC_LED_CTRL
#define MAC_LED_CTRL
Definition: tg3.h:553
tg3_5700_link_polarity
static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
Definition: tg3_phy.c:1196
tg3_phy_apply_otp
static void tg3_phy_apply_otp(struct tg3 *tp)
Definition: tg3_phy.c:509
val
void __asmcall int val
Definition: setjmp.h:28
LED_CTRL_MODE_PHY_2
#define LED_CTRL_MODE_PHY_2
Definition: tg3.h:567
tg3_fiber_aneginfo::cur_time
unsigned long cur_time
Definition: tg3_phy.c:1328
MR_LP_ADV_ASYM_PAUSE
#define MR_LP_ADV_ASYM_PAUSE
Definition: tg3_phy.c:1319
tg3_phy_auxctl_read
static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
Definition: tg3_phy.c:547
MAC_STATUS_PCS_SYNCED
#define MAC_STATUS_PCS_SYNCED
Definition: tg3.h:531
MII_TG3_AUX_STAT_10HALF
#define MII_TG3_AUX_STAT_10HALF
Definition: tg3.h:2381
tg3_fiber_aneginfo::ack_match
char ack_match
Definition: tg3_phy.c:1333
ANEG_STATE_SETTLE_TIME
#define ANEG_STATE_SETTLE_TIME
Definition: tg3_phy.c:1352
TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
Definition: tg3.h:213
TG3_OTP_RCOFF_MASK
#define TG3_OTP_RCOFF_MASK
Definition: tg3.h:2135
MAC_MI_MODE_AUTO_POLL
#define MAC_MI_MODE_AUTO_POLL
Definition: tg3.h:621
__unused
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
MII_TG3_CTRL_ADV_1000_HALF
#define MII_TG3_CTRL_ADV_1000_HALF
Definition: tg3.h:2313
HOSTCC_STAT_COAL_TICKS
#define HOSTCC_STAT_COAL_TICKS
Definition: tg3.h:1350
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
Definition: tg3.h:219
tg3_writephy
int tg3_writephy(struct tg3 *tp, int reg, u32 val)
Definition: tg3_phy.c:221
OTP_CTRL_OTP_CMD_START
#define OTP_CTRL_OTP_CMD_START
Definition: tg3.h:2071
duplex
duplex
Definition: nic.h:40
MAC_RX_AUTO_NEG
#define MAC_RX_AUTO_NEG
Definition: tg3.h:600
ANEG_STATE_NEXT_PAGE_WAIT_INIT
#define ANEG_STATE_NEXT_PAGE_WAIT_INIT
Definition: tg3_phy.c:1306
MI_COM_PHY_ADDR_MASK
#define MI_COM_PHY_ADDR_MASK
Definition: tg3.h:610
CPMU_LSPD_1000MB_MACCLK_MASK
#define CPMU_LSPD_1000MB_MACCLK_MASK
Definition: tg3.h:1232
MAC_STATUS
#define MAC_STATUS
Definition: tg3.h:530
CHIPREV_ID_5701_A0
#define CHIPREV_ID_5701_A0
Definition: tg3.h:267
SD_STATUS_UPDATED
#define SD_STATUS_UPDATED
Definition: tg3.h:2672
MII_TG3_DSP_ADDRESS
#define MII_TG3_DSP_ADDRESS
Definition: tg3.h:2334
TG3_CPMU_LSPD_1000MB_CLK
#define TG3_CPMU_LSPD_1000MB_CLK
Definition: tg3.h:1229
OTP_ADDRESS_MAGIC2
#define OTP_ADDRESS_MAGIC2
Definition: tg3.h:2076
tg3_write_mem
void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
Definition: tg3_hw.c:921
tg3_phy_set_wirespeed
static void tg3_phy_set_wirespeed(struct tg3 *tp)
Definition: tg3_phy.c:603
MII_TG3_AUXCTL_SHDWSEL_PWRCTL
#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL
Definition: tg3.h:2362
tg3_phy_probe
int tg3_phy_probe(struct tg3 *tp)
Definition: tg3_phy.c:895
mii.h
Media Independent Interface constants.
MR_LP_ADV_HALF_DUPLEX
#define MR_LP_ADV_HALF_DUPLEX
Definition: tg3_phy.c:1317
MII_PHYSID2
#define MII_PHYSID2
Definition: atl1e.h:874
TG3_PHYFLG_EEE_CAP
#define TG3_PHYFLG_EEE_CAP
Definition: tg3.h:3253
TG3_PHYFLG_JITTER_BUG
#define TG3_PHYFLG_JITTER_BUG
Definition: tg3.h:3246
ADVERTISE_10HALF
#define ADVERTISE_10HALF
Definition: mii.h:74
NIC_SRAM_FIRMWARE_MBOX_MAGIC2
#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2
Definition: tg3.h:2205
SG_DIG_PARTNER_ASYM_PAUSE
#define SG_DIG_PARTNER_ASYM_PAUSE
Definition: tg3.h:900
OTP_READ_DATA
#define OTP_READ_DATA
Definition: tg3.h:2079
tg3_setup_fiber_phy
static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:1957
MI_COM_START
#define MI_COM_START
Definition: tg3.h:608
MR_PAGE_RX
#define MR_PAGE_RX
Definition: tg3_phy.c:1313
ANEG_STATE_COMPLETE_ACK
#define ANEG_STATE_COMPLETE_ACK
Definition: tg3_phy.c:1302
BMCR_RESET
#define BMCR_RESET
Definition: mii.h:52
ANEG_STATE_RESTART_INIT
#define ANEG_STATE_RESTART_INIT
Definition: tg3_phy.c:1294
ADVERTISED_10baseT_Full
#define ADVERTISED_10baseT_Full
Definition: bnx2.h:43
SG_DIG_COMMON_SETUP
#define SG_DIG_COMMON_SETUP
Definition: tg3.h:892
ANEG_STATE_RESTART
#define ANEG_STATE_RESTART
Definition: tg3_phy.c:1295
tw32
#define tw32(reg, val)
Definition: tg3.h:3329
TG3_OTP_AGCTGT_SHIFT
#define TG3_OTP_AGCTGT_SHIFT
Definition: tg3.h:2122
TG3_PHY_ID_BCM5703
#define TG3_PHY_ID_BCM5703
Definition: tg3.h:3190
TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
Definition: tg3.h:214
tg3_phy_write_and_check_testpat
static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
Definition: tg3_phy.c:322
DBGCP
#define DBGCP(...)
Definition: compiler.h:539
MI_COM_DATA_MASK
#define MI_COM_DATA_MASK
Definition: tg3.h:614
MII_TG3_AUX_STAT_1000FULL
#define MII_TG3_AUX_STAT_1000FULL
Definition: tg3.h:2387
MAC_MI_MODE
#define MAC_MI_MODE
Definition: tg3.h:618
MII_TG3_DSP_CONTROL
#define MII_TG3_DSP_CONTROL
Definition: tg3.h:2333
TG3_OTP_ROFF_SHIFT
#define TG3_OTP_ROFF_SHIFT
Definition: tg3.h:2134
MII_TG3_DSP_AADJ1CH3_ADCCKADJ
#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ
Definition: tg3.h:2346
GRC_MISC_CFG
#define GRC_MISC_CFG
Definition: tg3.h:1819
MR_TOGGLE_TX
#define MR_TOGGLE_TX
Definition: tg3_phy.c:1315
ANEG_STATE_COMPLETE_ACK_INIT
#define ANEG_STATE_COMPLETE_ACK_INIT
Definition: tg3_phy.c:1301
ANEG_STATE_ACK_DETECT
#define ANEG_STATE_ACK_DETECT
Definition: tg3_phy.c:1300
ASIC_REV_5714
#define ASIC_REV_5714
Definition: tg3.h:307
ADVERTISE_PAUSE_CAP
#define ADVERTISE_PAUSE_CAP
Definition: mii.h:83
TG3PCI_SUBVENDOR_ID_DELL
#define TG3PCI_SUBVENDOR_ID_DELL
Definition: tg3.h:228
tg3_setup_copper_phy
static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2254
MII_TG3_AUX_STAT_100
#define MII_TG3_AUX_STAT_100
Definition: tg3.h:2388
ADVERTISE_100HALF
#define ADVERTISE_100HALF
Definition: mii.h:78
GET_CHIP_REV
#define GET_CHIP_REV(CHIP_REV_ID)
Definition: tg3.h:321
TG3_BMCR_SPEED1000
#define TG3_BMCR_SPEED1000
Definition: tg3.h:2310
CHIPREV_ID_5704_A0
#define CHIPREV_ID_5704_A0
Definition: tg3.h:275
tg3_phy_toggle_automdix
static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
Definition: tg3_phy.c:561
tg3_aux_stat_to_speed_duplex
static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
Definition: tg3_phy.c:1018
ANEG_TIMER_ENAB
#define ANEG_TIMER_ENAB
Definition: tg3_phy.c:1349
CHIPREV_ID_5717_A0
#define CHIPREV_ID_5717_A0
Definition: tg3.h:294
MR_LP_ADV_NEXT_PAGE
#define MR_LP_ADV_NEXT_PAGE
Definition: tg3_phy.c:1322
ANEG_CFG_FD
#define ANEG_CFG_FD
Definition: tg3_phy.c:1343
PCIE_PWR_MGMT_THRESH
#define PCIE_PWR_MGMT_THRESH
Definition: tg3.h:2087
BMCR_ANENABLE
#define BMCR_ANENABLE
Definition: mii.h:49
ANEG_STATE_DISABLE_LINK_OK
#define ANEG_STATE_DISABLE_LINK_OK
Definition: tg3_phy.c:1296
tg3_copper_is_advertising_all
static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
Definition: tg3_phy.c:737
MII_BMSR
#define MII_BMSR
Definition: atl1e.h:872
MII_PHYSID1
#define MII_PHYSID1
Definition: atl1e.h:873
ANEG_CFG_ACK
#define ANEG_CFG_ACK
Definition: tg3_phy.c:1337
MR_LP_ADV_FULL_DUPLEX
#define MR_LP_ADV_FULL_DUPLEX
Definition: tg3_phy.c:1316
MII_TG3_TEST1
#define MII_TG3_TEST1
Definition: tg3.h:2414
MAC_MODE
#define MAC_MODE
Definition: tg3.h:501
TX_LENGTHS_IPG_CRS_SHIFT
#define TX_LENGTHS_IPG_CRS_SHIFT
Definition: tg3.h:648
MI_COM_BUSY
#define MI_COM_BUSY
Definition: tg3.h:609
ANEG_STATE_ACK_DETECT_INIT
#define ANEG_STATE_ACK_DETECT_INIT
Definition: tg3_phy.c:1299
MAC_STATUS_LNKSTATE_CHANGED
#define MAC_STATUS_LNKSTATE_CHANGED
Definition: tg3.h:537
DEFAULT_STAT_COAL_TICKS
#define DEFAULT_STAT_COAL_TICKS
Definition: tg3.h:1351
TG3PCI_SUBVENDOR_ID_3COM
#define TG3PCI_SUBVENDOR_ID_3COM
Definition: tg3.h:222
ADVERTISED_1000baseT_Full
#define ADVERTISED_1000baseT_Full
Definition: bnx2.h:47
tg3_mdio_init
void tg3_mdio_init(struct tg3 *tp)
Definition: tg3_phy.c:13
MII_TG3_CTRL
#define MII_TG3_CTRL
Definition: tg3.h:2312
ANEG_STATE_ABILITY_DETECT
#define ANEG_STATE_ABILITY_DETECT
Definition: tg3_phy.c:1298
TG3_PHYFLG_PARALLEL_DETECT
#define TG3_PHYFLG_PARALLEL_DETECT
Definition: tg3.h:3252
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
cmd
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
tg3_read_otp_phycfg
u32 tg3_read_otp_phycfg(struct tg3 *tp)
int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
Definition: tg3_phy.c:56
ADVERTISED_100baseT_Full
#define ADVERTISED_100baseT_Full
Definition: bnx2.h:45
tg3_wait_macro_done
static int tg3_wait_macro_done(struct tg3 *tp)
Definition: tg3_phy.c:303
PCI_EXP_LNKCTL_CLKREQ_EN
#define PCI_EXP_LNKCTL_CLKREQ_EN
Definition: tg3.h:18
TG3PCI_SUBVENDOR_ID_BROADCOM
#define TG3PCI_SUBVENDOR_ID_BROADCOM
Definition: tg3.h:210
MII_TG3_CTRL_AS_MASTER
#define MII_TG3_CTRL_AS_MASTER
Definition: tg3.h:2315
done
struct bofm_section_header done
Definition: bofm_test.c:46
ADVERTISED_10baseT_Half
#define ADVERTISED_10baseT_Half
Definition: bnx2.h:42
u8
uint8_t u8
Definition: stdint.h:19
u32
uint32_t u32
Definition: stdint.h:23
OTP_STATUS_CMD_DONE
#define OTP_STATUS_CMD_DONE
Definition: tg3.h:2073
TG3_PHY_ID_MASK
#define TG3_PHY_ID_MASK
Definition: tg3.h:3185
MII_TG3_AUXCTL_SHDWSEL_AUXCTL
#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL
Definition: tg3.h:2357
TG3_PHY_ID_BCM5401
#define TG3_PHY_ID_BCM5401
Definition: tg3.h:3187
BMCR_FULLDPLX
#define BMCR_FULLDPLX
Definition: mii.h:45
MAC_SERDES_CFG
#define MAC_SERDES_CFG
Definition: tg3.h:743
TG3_PHYFLG_NO_ETH_WIRE_SPEED
#define TG3_PHYFLG_NO_ETH_WIRE_SPEED
Definition: tg3.h:3245
MAC_TX_STATUS
#define MAC_TX_STATUS
Definition: tg3.h:635
NIC_SRAM_FIRMWARE_MBOX
#define NIC_SRAM_FIRMWARE_MBOX
Definition: tg3.h:2203
TG3PCI_SUBVENDOR_ID_IBM
#define TG3PCI_SUBVENDOR_ID_IBM
Definition: tg3.h:239
MAC_RX_MODE
#define MAC_RX_MODE
Definition: tg3.h:651
ADVERTISE_1000XFULL
#define ADVERTISE_1000XFULL
Definition: mii.h:75
DUPLEX_HALF
#define DUPLEX_HALF
Definition: bnx2.h:110
MR_LP_ADV_REMOTE_FAULT2
#define MR_LP_ADV_REMOTE_FAULT2
Definition: tg3_phy.c:1321
MII_STAT1000
#define MII_STAT1000
Definition: mii.h:25
tg3_wait_for_event_ack
void tg3_wait_for_event_ack(struct tg3 *tp)
Definition: tg3_hw.c:908
memset
void * memset(void *dest, int character, size_t len) __nonnull
tg3_setup_fiber_by_hand
static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
Definition: tg3_phy.c:1862
ASIC_REV_5701
#define ASIC_REV_5701
Definition: tg3.h:300
ANEG_STATE_LINK_OK
#define ANEG_STATE_LINK_OK
Definition: tg3_phy.c:1305
TG3_KNOWN_PHY_ID
#define TG3_KNOWN_PHY_ID(X)
Definition: tg3.h:3220
ASIC_REV_57765
#define ASIC_REV_57765
Definition: tg3.h:317
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