iPXE
tg3_phy.c
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1 
2 #include <mii.h>
3 #include <stdio.h>
4 #include <string.h>
5 #include <errno.h>
6 #include <unistd.h>
7 #include <byteswap.h>
8 #include <ipxe/pci.h>
9 
10 #include "tg3.h"
11 
12 static void tg3_link_report(struct tg3 *tp);
13 
14 void tg3_mdio_init(struct tg3 *tp)
15 { DBGP("%s\n", __func__);
16 
17  if (tg3_flag(tp, 5717_PLUS)) {
18  u32 is_serdes;
19 
20  tp->phy_addr = PCI_FUNC(tp->pdev->busdevfn) + 1;
21 
22  if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
23  is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
24  else
25  is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
26  TG3_CPMU_PHY_STRAP_IS_SERDES;
27  if (is_serdes)
28  tp->phy_addr += 7;
29  } else
30  tp->phy_addr = TG3_PHY_MII_ADDR;
31 }
32 
33 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
34 { DBGP("%s\n", __func__);
35 
36  int i;
37  u32 val;
38 
39  tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
40  tw32(OTP_CTRL, cmd);
41 
42  /* Wait for up to 1 ms for command to execute. */
43  for (i = 0; i < 100; i++) {
44  val = tr32(OTP_STATUS);
45  if (val & OTP_STATUS_CMD_DONE)
46  break;
47  udelay(10);
48  }
49 
50  return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
51 }
52 
53 /* Read the gphy configuration from the OTP region of the chip. The gphy
54  * configuration is a 32-bit value that straddles the alignment boundary.
55  * We do two 32-bit reads and then shift and merge the results.
56  */
57 u32 tg3_read_otp_phycfg(struct tg3 *tp)
58 { DBGP("%s\n", __func__);
59 
60  u32 bhalf_otp, thalf_otp;
61 
62  tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
63 
64  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
65  return 0;
66 
67  tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
68 
69  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
70  return 0;
71 
72  thalf_otp = tr32(OTP_READ_DATA);
73 
74  tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
75 
76  if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
77  return 0;
78 
79  bhalf_otp = tr32(OTP_READ_DATA);
80 
81  return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
82 }
83 
84 #define PHY_BUSY_LOOPS 5000
85 
86 int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
87 { DBGP("%s\n", __func__);
88 
89  u32 frame_val;
90  unsigned int loops;
91  int ret;
92 
93  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
94  tw32_f(MAC_MI_MODE,
95  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
96  udelay(80);
97  }
98 
99  *val = 0x0;
100 
101  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
102  MI_COM_PHY_ADDR_MASK);
103  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
104  MI_COM_REG_ADDR_MASK);
105  frame_val |= (MI_COM_CMD_READ | MI_COM_START);
106 
107  tw32_f(MAC_MI_COM, frame_val);
108 
109  loops = PHY_BUSY_LOOPS;
110  while (loops != 0) {
111  udelay(10);
112  frame_val = tr32(MAC_MI_COM);
113 
114  if ((frame_val & MI_COM_BUSY) == 0) {
115  udelay(5);
116  frame_val = tr32(MAC_MI_COM);
117  break;
118  }
119  loops -= 1;
120  }
121 
122  ret = -EBUSY;
123  if (loops != 0) {
124  *val = frame_val & MI_COM_DATA_MASK;
125  ret = 0;
126  }
127 
128  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
129  tw32_f(MAC_MI_MODE, tp->mi_mode);
130  udelay(80);
131  }
132 
133  return ret;
134 }
135 
136 struct subsys_tbl_ent {
137  u16 subsys_vendor, subsys_devid;
138  u32 phy_id;
139 };
140 
141 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
142  /* Broadcom boards. */
143  { TG3PCI_SUBVENDOR_ID_BROADCOM,
144  TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
145  { TG3PCI_SUBVENDOR_ID_BROADCOM,
146  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
147  { TG3PCI_SUBVENDOR_ID_BROADCOM,
148  TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
149  { TG3PCI_SUBVENDOR_ID_BROADCOM,
150  TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
151  { TG3PCI_SUBVENDOR_ID_BROADCOM,
152  TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
153  { TG3PCI_SUBVENDOR_ID_BROADCOM,
154  TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
155  { TG3PCI_SUBVENDOR_ID_BROADCOM,
156  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
157  { TG3PCI_SUBVENDOR_ID_BROADCOM,
158  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
159  { TG3PCI_SUBVENDOR_ID_BROADCOM,
160  TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
161  { TG3PCI_SUBVENDOR_ID_BROADCOM,
162  TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
163  { TG3PCI_SUBVENDOR_ID_BROADCOM,
164  TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
165 
166  /* 3com boards. */
167  { TG3PCI_SUBVENDOR_ID_3COM,
168  TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
169  { TG3PCI_SUBVENDOR_ID_3COM,
170  TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
171  { TG3PCI_SUBVENDOR_ID_3COM,
172  TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
173  { TG3PCI_SUBVENDOR_ID_3COM,
174  TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
175  { TG3PCI_SUBVENDOR_ID_3COM,
176  TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
177 
178  /* DELL boards. */
179  { TG3PCI_SUBVENDOR_ID_DELL,
180  TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
181  { TG3PCI_SUBVENDOR_ID_DELL,
182  TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
183  { TG3PCI_SUBVENDOR_ID_DELL,
184  TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
185  { TG3PCI_SUBVENDOR_ID_DELL,
186  TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
187 
188  /* Compaq boards. */
189  { TG3PCI_SUBVENDOR_ID_COMPAQ,
190  TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
191  { TG3PCI_SUBVENDOR_ID_COMPAQ,
192  TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
193  { TG3PCI_SUBVENDOR_ID_COMPAQ,
194  TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
195  { TG3PCI_SUBVENDOR_ID_COMPAQ,
196  TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
197  { TG3PCI_SUBVENDOR_ID_COMPAQ,
198  TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
199 
200  /* IBM boards. */
201  { TG3PCI_SUBVENDOR_ID_IBM,
202  TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
203 };
204 
205 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
206 { DBGP("%s\n", __func__);
207 
208  int i;
209 
210  DBGC(tp->dev, "Matching with: %x:%x\n", tp->subsystem_vendor, tp->subsystem_device);
211 
212  for (i = 0; i < (int) ARRAY_SIZE(subsys_id_to_phy_id); i++) {
213  if ((subsys_id_to_phy_id[i].subsys_vendor ==
214  tp->subsystem_vendor) &&
215  (subsys_id_to_phy_id[i].subsys_devid ==
216  tp->subsystem_device))
217  return &subsys_id_to_phy_id[i];
218  }
219  return NULL;
220 }
221 
222 int tg3_writephy(struct tg3 *tp, int reg, u32 val)
223 { DBGP("%s\n", __func__);
224 
225  u32 frame_val;
226  unsigned int loops;
227  int ret;
228 
229  if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
230  (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
231  return 0;
232 
233  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
234  tw32_f(MAC_MI_MODE,
235  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
236  udelay(80);
237  }
238 
239  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
240  MI_COM_PHY_ADDR_MASK);
241  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
242  MI_COM_REG_ADDR_MASK);
243  frame_val |= (val & MI_COM_DATA_MASK);
244  frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
245 
246  tw32_f(MAC_MI_COM, frame_val);
247 
248  loops = PHY_BUSY_LOOPS;
249  while (loops != 0) {
250  udelay(10);
251  frame_val = tr32(MAC_MI_COM);
252  if ((frame_val & MI_COM_BUSY) == 0) {
253  udelay(5);
254  frame_val = tr32(MAC_MI_COM);
255  break;
256  }
257  loops -= 1;
258  }
259 
260  ret = -EBUSY;
261  if (loops != 0)
262  ret = 0;
263 
264  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
265  tw32_f(MAC_MI_MODE, tp->mi_mode);
266  udelay(80);
267  }
268 
269  return ret;
270 }
271 
272 static int tg3_bmcr_reset(struct tg3 *tp)
273 { DBGP("%s\n", __func__);
274 
275  u32 phy_control;
276  int limit, err;
277 
278  /* OK, reset it, and poll the BMCR_RESET bit until it
279  * clears or we time out.
280  */
281  phy_control = BMCR_RESET;
282  err = tg3_writephy(tp, MII_BMCR, phy_control);
283  if (err != 0)
284  return -EBUSY;
285 
286  limit = 5000;
287  while (limit--) {
288  err = tg3_readphy(tp, MII_BMCR, &phy_control);
289  if (err != 0)
290  return -EBUSY;
291 
292  if ((phy_control & BMCR_RESET) == 0) {
293  udelay(40);
294  break;
295  }
296  udelay(10);
297  }
298  if (limit < 0)
299  return -EBUSY;
300 
301  return 0;
302 }
303 
304 static int tg3_wait_macro_done(struct tg3 *tp)
305 { DBGP("%s\n", __func__);
306 
307  int limit = 100;
308 
309  while (limit--) {
310  u32 tmp32;
311 
312  if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
313  if ((tmp32 & 0x1000) == 0)
314  break;
315  }
316  }
317  if (limit < 0)
318  return -EBUSY;
319 
320  return 0;
321 }
322 
323 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
324 { DBGP("%s\n", __func__);
325 
326  static const u32 test_pat[4][6] = {
327  { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
328  { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
329  { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
330  { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
331  };
332  int chan;
333 
334  for (chan = 0; chan < 4; chan++) {
335  int i;
336 
337  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
338  (chan * 0x2000) | 0x0200);
339  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
340 
341  for (i = 0; i < 6; i++)
342  tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
343  test_pat[chan][i]);
344 
345  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
346  if (tg3_wait_macro_done(tp)) {
347  *resetp = 1;
348  return -EBUSY;
349  }
350 
351  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
352  (chan * 0x2000) | 0x0200);
353  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
354  if (tg3_wait_macro_done(tp)) {
355  *resetp = 1;
356  return -EBUSY;
357  }
358 
359  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
360  if (tg3_wait_macro_done(tp)) {
361  *resetp = 1;
362  return -EBUSY;
363  }
364 
365  for (i = 0; i < 6; i += 2) {
366  u32 low, high;
367 
368  if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
369  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
370  tg3_wait_macro_done(tp)) {
371  *resetp = 1;
372  return -EBUSY;
373  }
374  low &= 0x7fff;
375  high &= 0x000f;
376  if (low != test_pat[chan][i] ||
377  high != test_pat[chan][i+1]) {
378  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
379  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
380  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
381 
382  return -EBUSY;
383  }
384  }
385  }
386 
387  return 0;
388 }
389 
390 static int tg3_phy_reset_chanpat(struct tg3 *tp)
391 { DBGP("%s\n", __func__);
392 
393  int chan;
394 
395  for (chan = 0; chan < 4; chan++) {
396  int i;
397 
398  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
399  (chan * 0x2000) | 0x0200);
400  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
401  for (i = 0; i < 6; i++)
402  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
403  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
404  if (tg3_wait_macro_done(tp))
405  return -EBUSY;
406  }
407 
408  return 0;
409 }
410 
411 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
412 { DBGP("%s\n", __func__);
413 
414  int err;
415 
416  err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
417  if (!err)
418  err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
419 
420  return err;
421 }
422 
423 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
424 { DBGP("%s\n", __func__);
425 
426  if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
427  set |= MII_TG3_AUXCTL_MISC_WREN;
428 
429  return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
430 }
431 
432 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
433  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
434  MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
435  MII_TG3_AUXCTL_ACTL_TX_6DB)
436 
437 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
438  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
439  MII_TG3_AUXCTL_ACTL_TX_6DB);
440 
441 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
442 { DBGP("%s\n", __func__);
443 
444  u32 reg32, phy9_orig;
445  int retries, do_phy_reset, err;
446 
447  retries = 10;
448  do_phy_reset = 1;
449  do {
450  if (do_phy_reset) {
451  err = tg3_bmcr_reset(tp);
452  if (err)
453  return err;
454  do_phy_reset = 0;
455  }
456 
457  /* Disable transmitter and interrupt. */
458  if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
459  continue;
460 
461  reg32 |= 0x3000;
462  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
463 
464  /* Set full-duplex, 1000 mbps. */
465  tg3_writephy(tp, MII_BMCR,
466  BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
467 
468  /* Set to master mode. */
469  if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
470  continue;
471 
472  tg3_writephy(tp, MII_TG3_CTRL,
473  (MII_TG3_CTRL_AS_MASTER |
474  MII_TG3_CTRL_ENABLE_AS_MASTER));
475 
476  err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
477  if (err)
478  return err;
479 
480  /* Block the PHY control access. */
481  tg3_phydsp_write(tp, 0x8005, 0x0800);
482 
483  err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
484  if (!err)
485  break;
486  } while (--retries);
487 
488  err = tg3_phy_reset_chanpat(tp);
489  if (err)
490  return err;
491 
492  tg3_phydsp_write(tp, 0x8005, 0x0000);
493 
494  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
495  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
496 
497  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
498 
499  tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
500 
501  if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
502  reg32 &= ~0x3000;
503  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
504  } else if (!err)
505  err = -EBUSY;
506 
507  return err;
508 }
509 
510 static void tg3_phy_apply_otp(struct tg3 *tp)
511 { DBGP("%s\n", __func__);
512 
513  u32 otp, phy;
514 
515  if (!tp->phy_otp)
516  return;
517 
518  otp = tp->phy_otp;
519 
520  if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
521  return;
522 
523  phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
524  phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
525  tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
526 
527  phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
528  ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
529  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
530 
531  phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
532  phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
533  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
534 
535  phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
536  tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
537 
538  phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
539  tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
540 
541  phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
542  ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
543  tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
544 
545  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
546 }
547 
548 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
549 { DBGP("%s\n", __func__);
550 
551  int err;
552 
553  err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
554  (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
555  MII_TG3_AUXCTL_SHDWSEL_MISC);
556  if (!err)
557  err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
558 
559  return err;
560 }
561 
562 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
563 { DBGP("%s\n", __func__);
564 
565  u32 phy;
566 
567  if (!tg3_flag(tp, 5705_PLUS) ||
568  (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
569  return;
570 
571  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
572  u32 ephy;
573 
574  if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
575  u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
576 
577  tg3_writephy(tp, MII_TG3_FET_TEST,
578  ephy | MII_TG3_FET_SHADOW_EN);
579  if (!tg3_readphy(tp, reg, &phy)) {
580  if (enable)
581  phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
582  else
583  phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
584  tg3_writephy(tp, reg, phy);
585  }
586  tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
587  }
588  } else {
589  int ret;
590 
591  ret = tg3_phy_auxctl_read(tp,
592  MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
593  if (!ret) {
594  if (enable)
595  phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
596  else
597  phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
598  tg3_phy_auxctl_write(tp,
599  MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
600  }
601  }
602 }
603 
604 static void tg3_phy_set_wirespeed(struct tg3 *tp)
605 { DBGP("%s\n", __func__);
606 
607  int ret;
608  u32 val;
609 
610  if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
611  return;
612 
613  ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
614  if (!ret)
615  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
616  val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
617 }
618 
619 /* This will reset the tigon3 PHY if there is no valid
620  * link unless the FORCE argument is non-zero.
621  */
622 int tg3_phy_reset(struct tg3 *tp)
623 { DBGP("%s\n", __func__);
624 
625  u32 val, cpmuctrl;
626  int err;
627 
628  DBGCP(&tp->pdev->dev, "%s\n", __func__);
629 
630  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
631  val = tr32(GRC_MISC_CFG);
632  tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
633  udelay(40);
634  }
635  err = tg3_readphy(tp, MII_BMSR, &val);
636  err |= tg3_readphy(tp, MII_BMSR, &val);
637  if (err != 0)
638  return -EBUSY;
639 
640  netdev_link_down(tp->dev);
641  tg3_link_report(tp);
642 
643  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
644  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
645  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
646  err = tg3_phy_reset_5703_4_5(tp);
647  if (err)
648  return err;
649  goto out;
650  }
651 
652  cpmuctrl = 0;
653  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
654  GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
655  cpmuctrl = tr32(TG3_CPMU_CTRL);
656  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
657  tw32(TG3_CPMU_CTRL,
658  cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
659  }
660 
661  err = tg3_bmcr_reset(tp);
662  if (err)
663  return err;
664 
665  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
666  val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
667  tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
668 
669  tw32(TG3_CPMU_CTRL, cpmuctrl);
670  }
671 
672  if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
673  GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
674  val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
675  if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
676  CPMU_LSPD_1000MB_MACCLK_12_5) {
677  val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
678  udelay(40);
679  tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
680  }
681  }
682 
683  if (tg3_flag(tp, 5717_PLUS) &&
684  (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
685  return 0;
686 
687  tg3_phy_apply_otp(tp);
688 
689 out:
690  if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
691  !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
692  tg3_phydsp_write(tp, 0x201f, 0x2aaa);
693  tg3_phydsp_write(tp, 0x000a, 0x0323);
694  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
695  }
696 
697  if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
698  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
699  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
700  }
701 
702  if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
703  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
704  tg3_phydsp_write(tp, 0x000a, 0x310b);
705  tg3_phydsp_write(tp, 0x201f, 0x9506);
706  tg3_phydsp_write(tp, 0x401f, 0x14e2);
707  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
708  }
709  } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
710  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
711  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
712  if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
713  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
714  tg3_writephy(tp, MII_TG3_TEST1,
715  MII_TG3_TEST1_TRIM_EN | 0x4);
716  } else
717  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
718 
719  TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
720  }
721  }
722 
723  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
724  /* Cannot do read-modify-write on 5401 */
725  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
726  }
727 
728  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
729  /* adjust output voltage */
730  tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
731  }
732 
733  tg3_phy_toggle_automdix(tp, 1);
734  tg3_phy_set_wirespeed(tp);
735  return 0;
736 }
737 
738 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
739 { DBGP("%s\n", __func__);
740 
741  u32 adv_reg, all_mask = 0;
742 
743  if (mask & ADVERTISED_10baseT_Half)
744  all_mask |= ADVERTISE_10HALF;
745  if (mask & ADVERTISED_10baseT_Full)
746  all_mask |= ADVERTISE_10FULL;
747  if (mask & ADVERTISED_100baseT_Half)
748  all_mask |= ADVERTISE_100HALF;
749  if (mask & ADVERTISED_100baseT_Full)
750  all_mask |= ADVERTISE_100FULL;
751 
752  if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
753  return 0;
754 
755  if ((adv_reg & all_mask) != all_mask)
756  return 0;
757  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
758  u32 tg3_ctrl;
759 
760  all_mask = 0;
761  if (mask & ADVERTISED_1000baseT_Half)
762  all_mask |= ADVERTISE_1000HALF;
763  if (mask & ADVERTISED_1000baseT_Full)
764  all_mask |= ADVERTISE_1000FULL;
765 
766  if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
767  return 0;
768 
769  if ((tg3_ctrl & all_mask) != all_mask)
770  return 0;
771  }
772  return 1;
773 }
774 
775 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
776 { DBGP("%s\n", __func__);
777 
778  u16 miireg;
779 
780  if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
781  miireg = ADVERTISE_PAUSE_CAP;
782  else if (flow_ctrl & FLOW_CTRL_TX)
783  miireg = ADVERTISE_PAUSE_ASYM;
784  else if (flow_ctrl & FLOW_CTRL_RX)
785  miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
786  else
787  miireg = 0;
788 
789  return miireg;
790 }
791 
792 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
793 { DBGP("%s\n", __func__);
794 
795  int err = 0;
796  u32 val __unused, new_adv;
797 
798  new_adv = ADVERTISE_CSMA;
799  if (advertise & ADVERTISED_10baseT_Half)
800  new_adv |= ADVERTISE_10HALF;
801  if (advertise & ADVERTISED_10baseT_Full)
802  new_adv |= ADVERTISE_10FULL;
803  if (advertise & ADVERTISED_100baseT_Half)
804  new_adv |= ADVERTISE_100HALF;
805  if (advertise & ADVERTISED_100baseT_Full)
806  new_adv |= ADVERTISE_100FULL;
807 
808  new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
809 
810  err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
811  if (err)
812  goto done;
813 
814  if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
815  goto done;
816 
817  new_adv = 0;
818  if (advertise & ADVERTISED_1000baseT_Half)
819  new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
820  if (advertise & ADVERTISED_1000baseT_Full)
821  new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
822 
823  if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
824  tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
825  new_adv |= (MII_TG3_CTRL_AS_MASTER |
826  MII_TG3_CTRL_ENABLE_AS_MASTER);
827 
828  err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
829  if (err)
830  goto done;
831 
832  if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
833  goto done;
834 
835 done:
836  return err;
837 }
838 
839 static int tg3_init_5401phy_dsp(struct tg3 *tp)
840 { DBGP("%s\n", __func__);
841 
842  int err;
843 
844  /* Turn off tap power management. */
845  /* Set Extended packet length bit */
846  err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
847 
848  err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
849  err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
850  err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
851  err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
852  err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
853 
854  udelay(40);
855 
856  return err;
857 }
858 
859 #define ADVERTISED_Autoneg (1 << 6)
860 #define ADVERTISED_Pause (1 << 13)
861 #define ADVERTISED_TP (1 << 7)
862 #define ADVERTISED_FIBRE (1 << 10)
863 
864 #define AUTONEG_ENABLE 0x01
865 
866 static void tg3_phy_init_link_config(struct tg3 *tp)
867 { DBGP("%s\n", __func__);
868 
869  u32 adv = ADVERTISED_Autoneg |
870  ADVERTISED_Pause;
871 
872 
873  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
874  adv |= ADVERTISED_1000baseT_Half |
875  ADVERTISED_1000baseT_Full;
876  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
877  adv |= ADVERTISED_100baseT_Half |
878  ADVERTISED_100baseT_Full |
879  ADVERTISED_10baseT_Half |
880  ADVERTISED_10baseT_Full |
881  ADVERTISED_TP;
882  else
883  adv |= ADVERTISED_FIBRE;
884 
885  tp->link_config.advertising = adv;
886  tp->link_config.speed = SPEED_INVALID;
887  tp->link_config.duplex = DUPLEX_INVALID;
888  tp->link_config.autoneg = AUTONEG_ENABLE;
889  tp->link_config.active_speed = SPEED_INVALID;
890  tp->link_config.active_duplex = DUPLEX_INVALID;
891  tp->link_config.orig_speed = SPEED_INVALID;
892  tp->link_config.orig_duplex = DUPLEX_INVALID;
893  tp->link_config.orig_autoneg = AUTONEG_INVALID;
894 }
895 
896 int tg3_phy_probe(struct tg3 *tp)
897 { DBGP("%s\n", __func__);
898 
899  u32 hw_phy_id_1, hw_phy_id_2;
900  u32 hw_phy_id, hw_phy_id_masked;
901  int err;
902 
903  /* flow control autonegotiation is default behavior */
904  tg3_flag_set(tp, PAUSE_AUTONEG);
905  tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
906 
907  /* Reading the PHY ID register can conflict with ASF
908  * firmware access to the PHY hardware.
909  */
910  err = 0;
911  if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
912  hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
913  } else {
914  /* Now read the physical PHY_ID from the chip and verify
915  * that it is sane. If it doesn't look good, we fall back
916  * to either the hard-coded table based PHY_ID and failing
917  * that the value found in the eeprom area.
918  */
919  err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
920  err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
921 
922  hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
923  hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
924  hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
925 
926  hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
927  }
928 
929  if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
930  tp->phy_id = hw_phy_id;
931  if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
932  tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
933  else
934  tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
935  } else {
936  if (tp->phy_id != TG3_PHY_ID_INVALID) {
937  /* Do nothing, phy ID already set up in
938  * tg3_get_eeprom_hw_cfg().
939  */
940  } else {
941  struct subsys_tbl_ent *p;
942 
943  /* No eeprom signature? Try the hardcoded
944  * subsys device table.
945  */
946  p = tg3_lookup_by_subsys(tp);
947  if (!p) {
948  DBGC(&tp->pdev->dev, "lookup by subsys failed\n");
949  return -ENODEV;
950  }
951 
952  tp->phy_id = p->phy_id;
953  if (!tp->phy_id ||
954  tp->phy_id == TG3_PHY_ID_BCM8002)
955  tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
956  }
957  }
958 
959  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
960  ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
961  tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
962  (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
963  tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
964  tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
965 
966  tg3_phy_init_link_config(tp);
967 
968  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
969  !tg3_flag(tp, ENABLE_APE) &&
970  !tg3_flag(tp, ENABLE_ASF)) {
971  u32 bmsr;
972  u32 mask;
973 
974  tg3_readphy(tp, MII_BMSR, &bmsr);
975  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
976  (bmsr & BMSR_LSTATUS))
977  goto skip_phy_reset;
978 
979  err = tg3_phy_reset(tp);
980  if (err)
981  return err;
982 
983  tg3_phy_set_wirespeed(tp);
984 
985  mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
986  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
987  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
988  if (!tg3_copper_is_advertising_all(tp, mask)) {
989  tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
990  tp->link_config.flowctrl);
991 
992  tg3_writephy(tp, MII_BMCR,
993  BMCR_ANENABLE | BMCR_ANRESTART);
994  }
995  }
996 
997 skip_phy_reset:
998  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
999  err = tg3_init_5401phy_dsp(tp);
1000  if (err)
1001  return err;
1002 
1003  err = tg3_init_5401phy_dsp(tp);
1004  }
1005 
1006  return err;
1007 }
1008 
1009 void tg3_poll_link(struct tg3 *tp)
1010 { DBGP("%s\n", __func__);
1011 
1012  if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
1013  DBGC(tp->dev,"link_changed\n");
1014  tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
1015  tg3_setup_phy(tp, 0);
1016  }
1017 }
1018 
1019 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1020 { DBGP("%s\n", __func__);
1021 
1022  switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1023  case MII_TG3_AUX_STAT_10HALF:
1024  *speed = SPEED_10;
1025  *duplex = DUPLEX_HALF;
1026  break;
1027 
1028  case MII_TG3_AUX_STAT_10FULL:
1029  *speed = SPEED_10;
1030  *duplex = DUPLEX_FULL;
1031  break;
1032 
1033  case MII_TG3_AUX_STAT_100HALF:
1034  *speed = SPEED_100;
1035  *duplex = DUPLEX_HALF;
1036  break;
1037 
1038  case MII_TG3_AUX_STAT_100FULL:
1039  *speed = SPEED_100;
1040  *duplex = DUPLEX_FULL;
1041  break;
1042 
1043  case MII_TG3_AUX_STAT_1000HALF:
1044  *speed = SPEED_1000;
1045  *duplex = DUPLEX_HALF;
1046  break;
1047 
1048  case MII_TG3_AUX_STAT_1000FULL:
1049  *speed = SPEED_1000;
1050  *duplex = DUPLEX_FULL;
1051  break;
1052 
1053  default:
1054  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1055  *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1056  SPEED_10;
1057  *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1058  DUPLEX_HALF;
1059  break;
1060  }
1061  *speed = SPEED_INVALID;
1062  *duplex = DUPLEX_INVALID;
1063  break;
1064  }
1065 }
1066 
1067 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
1068 { DBGP("%s\n", __func__);
1069 
1070  u32 curadv, reqadv;
1071 
1072  if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
1073  return 1;
1074 
1075  curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1076  reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1077 
1078  if (tp->link_config.active_duplex == DUPLEX_FULL) {
1079  if (curadv != reqadv)
1080  return 0;
1081 
1082  if (tg3_flag(tp, PAUSE_AUTONEG))
1083  tg3_readphy(tp, MII_LPA, rmtadv);
1084  } else {
1085  /* Reprogram the advertisement register, even if it
1086  * does not affect the current link. If the link
1087  * gets renegotiated in the future, we can save an
1088  * additional renegotiation cycle by advertising
1089  * it correctly in the first place.
1090  */
1091  if (curadv != reqadv) {
1092  *lcladv &= ~(ADVERTISE_PAUSE_CAP |
1093  ADVERTISE_PAUSE_ASYM);
1094  tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
1095  }
1096  }
1097 
1098  return 1;
1099 }
1100 
1101 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1102 { DBGP("%s\n", __func__);
1103 
1104  u8 cap = 0;
1105 
1106  if (lcladv & ADVERTISE_1000XPAUSE) {
1107  if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1108  if (rmtadv & LPA_1000XPAUSE)
1109  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1110  else if (rmtadv & LPA_1000XPAUSE_ASYM)
1111  cap = FLOW_CTRL_RX;
1112  } else {
1113  if (rmtadv & LPA_1000XPAUSE)
1114  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1115  }
1116  } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1117  if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1118  cap = FLOW_CTRL_TX;
1119  }
1120 
1121  return cap;
1122 }
1123 
1124 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1125 { DBGP("%s\n", __func__);
1126 
1127  u8 flowctrl = 0;
1128  u32 old_rx_mode = tp->rx_mode;
1129  u32 old_tx_mode = tp->tx_mode;
1130 
1131  if (tg3_flag(tp, PAUSE_AUTONEG)) {
1132  if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1133  flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1134  else
1135  flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1136  } else
1137  flowctrl = tp->link_config.flowctrl;
1138 
1139  tp->link_config.active_flowctrl = flowctrl;
1140 
1141  if (flowctrl & FLOW_CTRL_RX)
1142  tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1143  else
1144  tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1145 
1146  if (old_rx_mode != tp->rx_mode)
1147  tw32_f(MAC_RX_MODE, tp->rx_mode);
1148 
1149  if (flowctrl & FLOW_CTRL_TX)
1150  tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1151  else
1152  tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1153 
1154  if (old_tx_mode != tp->tx_mode)
1155  tw32_f(MAC_TX_MODE, tp->tx_mode);
1156 }
1157 
1158 static void tg3_phy_copper_begin(struct tg3 *tp)
1159 { DBGP("%s\n", __func__);
1160 
1161  u32 new_adv;
1162 
1163  if (tp->link_config.speed == SPEED_INVALID) {
1164  if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1165  tp->link_config.advertising &=
1166  ~(ADVERTISED_1000baseT_Half |
1167  ADVERTISED_1000baseT_Full);
1168 
1169  tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
1170  tp->link_config.flowctrl);
1171  } else {
1172  /* Asking for a specific link mode. */
1173  if (tp->link_config.speed == SPEED_1000) {
1174  if (tp->link_config.duplex == DUPLEX_FULL)
1175  new_adv = ADVERTISED_1000baseT_Full;
1176  else
1177  new_adv = ADVERTISED_1000baseT_Half;
1178  } else if (tp->link_config.speed == SPEED_100) {
1179  if (tp->link_config.duplex == DUPLEX_FULL)
1180  new_adv = ADVERTISED_100baseT_Full;
1181  else
1182  new_adv = ADVERTISED_100baseT_Half;
1183  } else {
1184  if (tp->link_config.duplex == DUPLEX_FULL)
1185  new_adv = ADVERTISED_10baseT_Full;
1186  else
1187  new_adv = ADVERTISED_10baseT_Half;
1188  }
1189 
1190  tg3_phy_autoneg_cfg(tp, new_adv,
1191  tp->link_config.flowctrl);
1192  }
1193 
1194  tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1195 }
1196 
1197 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1198 { DBGP("%s\n", __func__);
1199 
1200  if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1201  return 1;
1202  else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
1203  if (speed != SPEED_10)
1204  return 1;
1205  } else if (speed == SPEED_10)
1206  return 1;
1207 
1208  return 0;
1209 }
1210 
1211 #if 1
1212 
1213 static void tg3_ump_link_report(struct tg3 *tp)
1214 { DBGP("%s\n", __func__);
1215 
1216  u32 reg;
1217  u32 val;
1218 
1219  if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1220  return;
1221 
1222  tg3_wait_for_event_ack(tp);
1223 
1224  tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1225 
1226  tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1227 
1228  val = 0;
1229  if (!tg3_readphy(tp, MII_BMCR, &reg))
1230  val = reg << 16;
1231  if (!tg3_readphy(tp, MII_BMSR, &reg))
1232  val |= (reg & 0xffff);
1233  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1234 
1235  val = 0;
1236  if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1237  val = reg << 16;
1238  if (!tg3_readphy(tp, MII_LPA, &reg))
1239  val |= (reg & 0xffff);
1240  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1241 
1242  val = 0;
1243  if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1244  if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1245  val = reg << 16;
1246  if (!tg3_readphy(tp, MII_STAT1000, &reg))
1247  val |= (reg & 0xffff);
1248  }
1249  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1250 
1251  if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1252  val = reg << 16;
1253  else
1254  val = 0;
1255  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1256 
1257  tg3_generate_fw_event(tp);
1258 }
1259 
1260 /* NOTE: Debugging only code */
1261 static void tg3_link_report(struct tg3 *tp)
1262 { DBGP("%s\n", __func__);
1263 
1264  if (!netdev_link_ok(tp->dev)) {
1265  DBGC(tp->dev, "Link is down\n");
1266  tg3_ump_link_report(tp);
1267  } else {
1268  DBGC(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1269  (tp->link_config.active_speed == SPEED_1000 ?
1270  1000 :
1271  (tp->link_config.active_speed == SPEED_100 ?
1272  100 : 10)),
1273  (tp->link_config.active_duplex == DUPLEX_FULL ?
1274  "full" : "half"));
1275 
1276  DBGC(tp->dev, "Flow control is %s for TX and %s for RX\n",
1277  (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1278  "on" : "off",
1279  (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1280  "on" : "off");
1281 
1282  if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1283  DBGC(tp->dev, "EEE is %s\n",
1284  tp->setlpicnt ? "enabled" : "disabled");
1285 
1286  tg3_ump_link_report(tp);
1287  }
1288 }
1289 #endif
1290 
1291 struct tg3_fiber_aneginfo {
1292  int state;
1293 #define ANEG_STATE_UNKNOWN 0
1294 #define ANEG_STATE_AN_ENABLE 1
1295 #define ANEG_STATE_RESTART_INIT 2
1296 #define ANEG_STATE_RESTART 3
1297 #define ANEG_STATE_DISABLE_LINK_OK 4
1298 #define ANEG_STATE_ABILITY_DETECT_INIT 5
1299 #define ANEG_STATE_ABILITY_DETECT 6
1300 #define ANEG_STATE_ACK_DETECT_INIT 7
1301 #define ANEG_STATE_ACK_DETECT 8
1302 #define ANEG_STATE_COMPLETE_ACK_INIT 9
1303 #define ANEG_STATE_COMPLETE_ACK 10
1304 #define ANEG_STATE_IDLE_DETECT_INIT 11
1305 #define ANEG_STATE_IDLE_DETECT 12
1306 #define ANEG_STATE_LINK_OK 13
1307 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
1308 #define ANEG_STATE_NEXT_PAGE_WAIT 15
1309 
1310  u32 flags;
1311 #define MR_AN_ENABLE 0x00000001
1312 #define MR_RESTART_AN 0x00000002
1313 #define MR_AN_COMPLETE 0x00000004
1314 #define MR_PAGE_RX 0x00000008
1315 #define MR_NP_LOADED 0x00000010
1316 #define MR_TOGGLE_TX 0x00000020
1317 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
1318 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
1319 #define MR_LP_ADV_SYM_PAUSE 0x00000100
1320 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
1321 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1322 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1323 #define MR_LP_ADV_NEXT_PAGE 0x00001000
1324 #define MR_TOGGLE_RX 0x00002000
1325 #define MR_NP_RX 0x00004000
1326 
1327 #define MR_LINK_OK 0x80000000
1328 
1329  unsigned long link_time, cur_time;
1330 
1331  u32 ability_match_cfg;
1332  int ability_match_count;
1333 
1334  char ability_match, idle_match, ack_match;
1335 
1336  u32 txconfig, rxconfig;
1337 #define ANEG_CFG_NP 0x00000080
1338 #define ANEG_CFG_ACK 0x00000040
1339 #define ANEG_CFG_RF2 0x00000020
1340 #define ANEG_CFG_RF1 0x00000010
1341 #define ANEG_CFG_PS2 0x00000001
1342 #define ANEG_CFG_PS1 0x00008000
1343 #define ANEG_CFG_HD 0x00004000
1344 #define ANEG_CFG_FD 0x00002000
1345 #define ANEG_CFG_INVAL 0x00001f06
1346 
1347 };
1348 #define ANEG_OK 0
1349 #define ANEG_DONE 1
1350 #define ANEG_TIMER_ENAB 2
1351 #define ANEG_FAILED -1
1352 
1353 #define ANEG_STATE_SETTLE_TIME 10000
1354 
1355 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1356 {
1357  u16 miireg;
1358 
1359  if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1360  miireg = ADVERTISE_1000XPAUSE;
1361  else if (flow_ctrl & FLOW_CTRL_TX)
1362  miireg = ADVERTISE_1000XPSE_ASYM;
1363  else if (flow_ctrl & FLOW_CTRL_RX)
1364  miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1365  else
1366  miireg = 0;
1367 
1368  return miireg;
1369 }
1370 
1371 static void tg3_init_bcm8002(struct tg3 *tp)
1372 {
1373  u32 mac_status = tr32(MAC_STATUS);
1374  int i;
1375 
1376  /* Reset when initting first time or we have a link. */
1377  if (tg3_flag(tp, INIT_COMPLETE) &&
1378  !(mac_status & MAC_STATUS_PCS_SYNCED))
1379  return;
1380 
1381  /* Set PLL lock range. */
1382  tg3_writephy(tp, 0x16, 0x8007);
1383 
1384  /* SW reset */
1385  tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1386 
1387  /* Wait for reset to complete. */
1388  /* XXX schedule_timeout() ... */
1389  for (i = 0; i < 500; i++)
1390  udelay(10);
1391 
1392  /* Config mode; select PMA/Ch 1 regs. */
1393  tg3_writephy(tp, 0x10, 0x8411);
1394 
1395  /* Enable auto-lock and comdet, select txclk for tx. */
1396  tg3_writephy(tp, 0x11, 0x0a10);
1397 
1398  tg3_writephy(tp, 0x18, 0x00a0);
1399  tg3_writephy(tp, 0x16, 0x41ff);
1400 
1401  /* Assert and deassert POR. */
1402  tg3_writephy(tp, 0x13, 0x0400);
1403  udelay(40);
1404  tg3_writephy(tp, 0x13, 0x0000);
1405 
1406  tg3_writephy(tp, 0x11, 0x0a50);
1407  udelay(40);
1408  tg3_writephy(tp, 0x11, 0x0a10);
1409 
1410  /* Wait for signal to stabilize */
1411  /* XXX schedule_timeout() ... */
1412  for (i = 0; i < 15000; i++)
1413  udelay(10);
1414 
1415  /* Deselect the channel register so we can read the PHYID
1416  * later.
1417  */
1418  tg3_writephy(tp, 0x10, 0x8011);
1419 }
1420 
1421 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
1422 {
1423  u16 flowctrl;
1424  int current_link_up;
1425  u32 sg_dig_ctrl, sg_dig_status;
1426  u32 serdes_cfg, expected_sg_dig_ctrl;
1427  int workaround, port_a;
1428 
1429  serdes_cfg = 0;
1430  expected_sg_dig_ctrl = 0;
1431  workaround = 0;
1432  port_a = 1;
1433  current_link_up = 0;
1434 
1435  if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
1436  tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
1437  workaround = 1;
1438  if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
1439  port_a = 0;
1440 
1441  /* preserve bits 0-11,13,14 for signal pre-emphasis */
1442  /* preserve bits 20-23 for voltage regulator */
1443  serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
1444  }
1445 
1446  sg_dig_ctrl = tr32(SG_DIG_CTRL);
1447 
1448  if (tp->link_config.autoneg != AUTONEG_ENABLE) {
1449  if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
1450  if (workaround) {
1451  u32 val = serdes_cfg;
1452 
1453  if (port_a)
1454  val |= 0xc010000;
1455  else
1456  val |= 0x4010000;
1457  tw32_f(MAC_SERDES_CFG, val);
1458  }
1459 
1460  tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1461  }
1462  if (mac_status & MAC_STATUS_PCS_SYNCED) {
1463  tg3_setup_flow_control(tp, 0, 0);
1464  current_link_up = 1;
1465  }
1466  goto out;
1467  }
1468 
1469  /* Want auto-negotiation. */
1470  expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
1471 
1472  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
1473  if (flowctrl & ADVERTISE_1000XPAUSE)
1474  expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
1475  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
1476  expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
1477 
1478  if (sg_dig_ctrl != expected_sg_dig_ctrl) {
1479  if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
1480  tp->serdes_counter &&
1481  ((mac_status & (MAC_STATUS_PCS_SYNCED |
1482  MAC_STATUS_RCVD_CFG)) ==
1483  MAC_STATUS_PCS_SYNCED)) {
1484  tp->serdes_counter--;
1485  current_link_up = 1;
1486  goto out;
1487  }
1488 restart_autoneg:
1489  if (workaround)
1490  tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
1491  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
1492  udelay(5);
1493  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
1494 
1495  tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
1496  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1497  } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
1498  MAC_STATUS_SIGNAL_DET)) {
1499  sg_dig_status = tr32(SG_DIG_STATUS);
1500  mac_status = tr32(MAC_STATUS);
1501 
1502  if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
1503  (mac_status & MAC_STATUS_PCS_SYNCED)) {
1504  u32 local_adv = 0, remote_adv = 0;
1505 
1506  if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
1507  local_adv |= ADVERTISE_1000XPAUSE;
1508  if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
1509  local_adv |= ADVERTISE_1000XPSE_ASYM;
1510 
1511  if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
1512  remote_adv |= LPA_1000XPAUSE;
1513  if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
1514  remote_adv |= LPA_1000XPAUSE_ASYM;
1515 
1516  tp->link_config.rmt_adv =
1517  mii_adv_to_ethtool_adv_x(remote_adv);
1518 
1519  tg3_setup_flow_control(tp, local_adv, remote_adv);
1520  current_link_up = 1;
1521  tp->serdes_counter = 0;
1522  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1523  } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
1524  if (tp->serdes_counter)
1525  tp->serdes_counter--;
1526  else {
1527  if (workaround) {
1528  u32 val = serdes_cfg;
1529 
1530  if (port_a)
1531  val |= 0xc010000;
1532  else
1533  val |= 0x4010000;
1534 
1535  tw32_f(MAC_SERDES_CFG, val);
1536  }
1537 
1538  tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
1539  udelay(40);
1540 
1541  /* Link parallel detection - link is up */
1542  /* only if we have PCS_SYNC and not */
1543  /* receiving config code words */
1544  mac_status = tr32(MAC_STATUS);
1545  if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
1546  !(mac_status & MAC_STATUS_RCVD_CFG)) {
1547  tg3_setup_flow_control(tp, 0, 0);
1548  current_link_up = 1;
1549  tp->phy_flags |=
1550  TG3_PHYFLG_PARALLEL_DETECT;
1551  tp->serdes_counter =
1552  SERDES_PARALLEL_DET_TIMEOUT;
1553  } else
1554  goto restart_autoneg;
1555  }
1556  }
1557  } else {
1558  tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
1559  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1560  }
1561 
1562 out:
1563  return current_link_up;
1564 }
1565 
1566 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
1567  struct tg3_fiber_aneginfo *ap)
1568 {
1569  u16 flowctrl;
1570  unsigned long delta;
1571  u32 rx_cfg_reg;
1572  int ret;
1573 
1574  if (ap->state == ANEG_STATE_UNKNOWN) {
1575  ap->rxconfig = 0;
1576  ap->link_time = 0;
1577  ap->cur_time = 0;
1578  ap->ability_match_cfg = 0;
1579  ap->ability_match_count = 0;
1580  ap->ability_match = 0;
1581  ap->idle_match = 0;
1582  ap->ack_match = 0;
1583  }
1584  ap->cur_time++;
1585 
1586  if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
1587  rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
1588 
1589  if (rx_cfg_reg != ap->ability_match_cfg) {
1590  ap->ability_match_cfg = rx_cfg_reg;
1591  ap->ability_match = 0;
1592  ap->ability_match_count = 0;
1593  } else {
1594  if (++ap->ability_match_count > 1) {
1595  ap->ability_match = 1;
1596  ap->ability_match_cfg = rx_cfg_reg;
1597  }
1598  }
1599  if (rx_cfg_reg & ANEG_CFG_ACK)
1600  ap->ack_match = 1;
1601  else
1602  ap->ack_match = 0;
1603 
1604  ap->idle_match = 0;
1605  } else {
1606  ap->idle_match = 1;
1607  ap->ability_match_cfg = 0;
1608  ap->ability_match_count = 0;
1609  ap->ability_match = 0;
1610  ap->ack_match = 0;
1611 
1612  rx_cfg_reg = 0;
1613  }
1614 
1615  ap->rxconfig = rx_cfg_reg;
1616  ret = ANEG_OK;
1617 
1618  switch (ap->state) {
1619  case ANEG_STATE_UNKNOWN:
1620  if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1621  ap->state = ANEG_STATE_AN_ENABLE;
1622 
1623  /* fallthru */
1624  case ANEG_STATE_AN_ENABLE:
1625  ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1626  if (ap->flags & MR_AN_ENABLE) {
1627  ap->link_time = 0;
1628  ap->cur_time = 0;
1629  ap->ability_match_cfg = 0;
1630  ap->ability_match_count = 0;
1631  ap->ability_match = 0;
1632  ap->idle_match = 0;
1633  ap->ack_match = 0;
1634 
1635  ap->state = ANEG_STATE_RESTART_INIT;
1636  } else {
1637  ap->state = ANEG_STATE_DISABLE_LINK_OK;
1638  }
1639  break;
1640 
1641  case ANEG_STATE_RESTART_INIT:
1642  ap->link_time = ap->cur_time;
1643  ap->flags &= ~(MR_NP_LOADED);
1644  ap->txconfig = 0;
1645  tw32(MAC_TX_AUTO_NEG, 0);
1646  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1647  tw32_f(MAC_MODE, tp->mac_mode);
1648  udelay(40);
1649 
1650  ret = ANEG_TIMER_ENAB;
1651  ap->state = ANEG_STATE_RESTART;
1652 
1653  /* fallthru */
1654  case ANEG_STATE_RESTART:
1655  delta = ap->cur_time - ap->link_time;
1656  if (delta > ANEG_STATE_SETTLE_TIME)
1657  ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1658  else
1659  ret = ANEG_TIMER_ENAB;
1660  break;
1661 
1662  case ANEG_STATE_DISABLE_LINK_OK:
1663  ret = ANEG_DONE;
1664  break;
1665 
1666  case ANEG_STATE_ABILITY_DETECT_INIT:
1667  ap->flags &= ~(MR_TOGGLE_TX);
1668  ap->txconfig = ANEG_CFG_FD;
1669  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
1670  if (flowctrl & ADVERTISE_1000XPAUSE)
1671  ap->txconfig |= ANEG_CFG_PS1;
1672  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
1673  ap->txconfig |= ANEG_CFG_PS2;
1674  tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1675  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1676  tw32_f(MAC_MODE, tp->mac_mode);
1677  udelay(40);
1678 
1679  ap->state = ANEG_STATE_ABILITY_DETECT;
1680  break;
1681 
1682  case ANEG_STATE_ABILITY_DETECT:
1683  if (ap->ability_match != 0 && ap->rxconfig != 0)
1684  ap->state = ANEG_STATE_ACK_DETECT_INIT;
1685  break;
1686 
1687  case ANEG_STATE_ACK_DETECT_INIT:
1688  ap->txconfig |= ANEG_CFG_ACK;
1689  tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1690  tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1691  tw32_f(MAC_MODE, tp->mac_mode);
1692  udelay(40);
1693 
1694  ap->state = ANEG_STATE_ACK_DETECT;
1695 
1696  /* fallthru */
1697  case ANEG_STATE_ACK_DETECT:
1698  if (ap->ack_match != 0) {
1699  if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1700  (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1701  ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1702  } else {
1703  ap->state = ANEG_STATE_AN_ENABLE;
1704  }
1705  } else if (ap->ability_match != 0 &&
1706  ap->rxconfig == 0) {
1707  ap->state = ANEG_STATE_AN_ENABLE;
1708  }
1709  break;
1710 
1711  case ANEG_STATE_COMPLETE_ACK_INIT:
1712  if (ap->rxconfig & ANEG_CFG_INVAL) {
1713  ret = ANEG_FAILED;
1714  break;
1715  }
1716  ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1717  MR_LP_ADV_HALF_DUPLEX |
1718  MR_LP_ADV_SYM_PAUSE |
1719  MR_LP_ADV_ASYM_PAUSE |
1720  MR_LP_ADV_REMOTE_FAULT1 |
1721  MR_LP_ADV_REMOTE_FAULT2 |
1722  MR_LP_ADV_NEXT_PAGE |
1723  MR_TOGGLE_RX |
1724  MR_NP_RX);
1725  if (ap->rxconfig & ANEG_CFG_FD)
1726  ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1727  if (ap->rxconfig & ANEG_CFG_HD)
1728  ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1729  if (ap->rxconfig & ANEG_CFG_PS1)
1730  ap->flags |= MR_LP_ADV_SYM_PAUSE;
1731  if (ap->rxconfig & ANEG_CFG_PS2)
1732  ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1733  if (ap->rxconfig & ANEG_CFG_RF1)
1734  ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1735  if (ap->rxconfig & ANEG_CFG_RF2)
1736  ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1737  if (ap->rxconfig & ANEG_CFG_NP)
1738  ap->flags |= MR_LP_ADV_NEXT_PAGE;
1739 
1740  ap->link_time = ap->cur_time;
1741 
1742  ap->flags ^= (MR_TOGGLE_TX);
1743  if (ap->rxconfig & 0x0008)
1744  ap->flags |= MR_TOGGLE_RX;
1745  if (ap->rxconfig & ANEG_CFG_NP)
1746  ap->flags |= MR_NP_RX;
1747  ap->flags |= MR_PAGE_RX;
1748 
1749  ap->state = ANEG_STATE_COMPLETE_ACK;
1750  ret = ANEG_TIMER_ENAB;
1751  break;
1752 
1753  case ANEG_STATE_COMPLETE_ACK:
1754  if (ap->ability_match != 0 &&
1755  ap->rxconfig == 0) {
1756  ap->state = ANEG_STATE_AN_ENABLE;
1757  break;
1758  }
1759  delta = ap->cur_time - ap->link_time;
1760  if (delta > ANEG_STATE_SETTLE_TIME) {
1761  if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1762  ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1763  } else {
1764  if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1765  !(ap->flags & MR_NP_RX)) {
1766  ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1767  } else {
1768  ret = ANEG_FAILED;
1769  }
1770  }
1771  }
1772  break;
1773 
1774  case ANEG_STATE_IDLE_DETECT_INIT:
1775  ap->link_time = ap->cur_time;
1776  tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1777  tw32_f(MAC_MODE, tp->mac_mode);
1778  udelay(40);
1779 
1780  ap->state = ANEG_STATE_IDLE_DETECT;
1781  ret = ANEG_TIMER_ENAB;
1782  break;
1783 
1784  case ANEG_STATE_IDLE_DETECT:
1785  if (ap->ability_match != 0 &&
1786  ap->rxconfig == 0) {
1787  ap->state = ANEG_STATE_AN_ENABLE;
1788  break;
1789  }
1790  delta = ap->cur_time - ap->link_time;
1791  if (delta > ANEG_STATE_SETTLE_TIME) {
1792  /* XXX another gem from the Broadcom driver :( */
1793  ap->state = ANEG_STATE_LINK_OK;
1794  }
1795  break;
1796 
1797  case ANEG_STATE_LINK_OK:
1798  ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1799  ret = ANEG_DONE;
1800  break;
1801 
1802  case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1803  /* ??? unimplemented */
1804  break;
1805 
1806  case ANEG_STATE_NEXT_PAGE_WAIT:
1807  /* ??? unimplemented */
1808  break;
1809 
1810  default:
1811  ret = ANEG_FAILED;
1812  break;
1813  }
1814 
1815  return ret;
1816 }
1817 
1818 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
1819 {
1820  int res = 0;
1821  struct tg3_fiber_aneginfo aninfo;
1822  int status = ANEG_FAILED;
1823  unsigned int tick;
1824  u32 tmp;
1825 
1826  tw32_f(MAC_TX_AUTO_NEG, 0);
1827 
1828  tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1829  tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1830  udelay(40);
1831 
1832  tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1833  udelay(40);
1834 
1835  memset(&aninfo, 0, sizeof(aninfo));
1836  aninfo.flags |= MR_AN_ENABLE;
1837  aninfo.state = ANEG_STATE_UNKNOWN;
1838  aninfo.cur_time = 0;
1839  tick = 0;
1840  while (++tick < 195000) {
1841  status = tg3_fiber_aneg_smachine(tp, &aninfo);
1842  if (status == ANEG_DONE || status == ANEG_FAILED)
1843  break;
1844 
1845  udelay(1);
1846  }
1847 
1848  tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1849  tw32_f(MAC_MODE, tp->mac_mode);
1850  udelay(40);
1851 
1852  *txflags = aninfo.txconfig;
1853  *rxflags = aninfo.flags;
1854 
1855  if (status == ANEG_DONE &&
1856  (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
1857  MR_LP_ADV_FULL_DUPLEX)))
1858  res = 1;
1859 
1860  return res;
1861 }
1862 
1863 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
1864 {
1865  int current_link_up = 0;
1866 
1867  if (!(mac_status & MAC_STATUS_PCS_SYNCED))
1868  goto out;
1869 
1870  if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1871  u32 txflags, rxflags;
1872  int i;
1873 
1874  if (fiber_autoneg(tp, &txflags, &rxflags)) {
1875  u32 local_adv = 0, remote_adv = 0;
1876 
1877  if (txflags & ANEG_CFG_PS1)
1878  local_adv |= ADVERTISE_1000XPAUSE;
1879  if (txflags & ANEG_CFG_PS2)
1880  local_adv |= ADVERTISE_1000XPSE_ASYM;
1881 
1882  if (rxflags & MR_LP_ADV_SYM_PAUSE)
1883  remote_adv |= LPA_1000XPAUSE;
1884  if (rxflags & MR_LP_ADV_ASYM_PAUSE)
1885  remote_adv |= LPA_1000XPAUSE_ASYM;
1886 
1887  tp->link_config.rmt_adv =
1888  mii_adv_to_ethtool_adv_x(remote_adv);
1889 
1890  tg3_setup_flow_control(tp, local_adv, remote_adv);
1891 
1892  current_link_up = 1;
1893  }
1894  for (i = 0; i < 30; i++) {
1895  udelay(20);
1896  tw32_f(MAC_STATUS,
1897  (MAC_STATUS_SYNC_CHANGED |
1898  MAC_STATUS_CFG_CHANGED));
1899  udelay(40);
1900  if ((tr32(MAC_STATUS) &
1901  (MAC_STATUS_SYNC_CHANGED |
1902  MAC_STATUS_CFG_CHANGED)) == 0)
1903  break;
1904  }
1905 
1906  mac_status = tr32(MAC_STATUS);
1907  if (!current_link_up &&
1908  (mac_status & MAC_STATUS_PCS_SYNCED) &&
1909  !(mac_status & MAC_STATUS_RCVD_CFG))
1910  current_link_up = 1;
1911  } else {
1912  tg3_setup_flow_control(tp, 0, 0);
1913 
1914  /* Forcing 1000FD link up. */
1915  current_link_up = 1;
1916 
1917  tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
1918  udelay(40);
1919 
1920  tw32_f(MAC_MODE, tp->mac_mode);
1921  udelay(40);
1922  }
1923 
1924 out:
1925  return current_link_up;
1926 }
1927 
1928 static int tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
1929 {
1930  if (curr_link_up != tp->link_up) {
1931  if (curr_link_up) {
1932  netdev_link_up(tp->dev);
1933  } else {
1934  netdev_link_down(tp->dev);
1935  if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
1936  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
1937  }
1938 
1939  tg3_link_report(tp);
1940  return 1;
1941  }
1942 
1943  return 0;
1944 }
1945 
1946 static void tg3_clear_mac_status(struct tg3 *tp)
1947 {
1948  tw32(MAC_EVENT, 0);
1949 
1950  tw32_f(MAC_STATUS,
1951  MAC_STATUS_SYNC_CHANGED |
1952  MAC_STATUS_CFG_CHANGED |
1953  MAC_STATUS_MI_COMPLETION |
1954  MAC_STATUS_LNKSTATE_CHANGED);
1955  udelay(40);
1956 }
1957 
1958 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
1959 {
1960  u32 orig_pause_cfg;
1961  u16 orig_active_speed;
1962  u8 orig_active_duplex;
1963  u32 mac_status;
1964  int current_link_up = force_reset;
1965  int i;
1966 
1967  orig_pause_cfg = tp->link_config.active_flowctrl;
1968  orig_active_speed = tp->link_config.active_speed;
1969  orig_active_duplex = tp->link_config.active_duplex;
1970 
1971  if (!tg3_flag(tp, HW_AUTONEG) &&
1972  tp->link_up &&
1973  tg3_flag(tp, INIT_COMPLETE)) {
1974  mac_status = tr32(MAC_STATUS);
1975  mac_status &= (MAC_STATUS_PCS_SYNCED |
1976  MAC_STATUS_SIGNAL_DET |
1977  MAC_STATUS_CFG_CHANGED |
1978  MAC_STATUS_RCVD_CFG);
1979  if (mac_status == (MAC_STATUS_PCS_SYNCED |
1980  MAC_STATUS_SIGNAL_DET)) {
1981  tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
1982  MAC_STATUS_CFG_CHANGED));
1983  return 0;
1984  }
1985  }
1986 
1987  tw32_f(MAC_TX_AUTO_NEG, 0);
1988 
1989  tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1990  tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1991  tw32_f(MAC_MODE, tp->mac_mode);
1992  udelay(40);
1993 
1994  if (tp->phy_id == TG3_PHY_ID_BCM8002)
1995  tg3_init_bcm8002(tp);
1996 
1997  /* Enable link change event even when serdes polling. */
1998  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1999  udelay(40);
2000 
2001  current_link_up = 0;
2002  tp->link_config.rmt_adv = 0;
2003  mac_status = tr32(MAC_STATUS);
2004 
2005  if (tg3_flag(tp, HW_AUTONEG))
2006  current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2007  else
2008  current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2009 
2010  tp->hw_status->status =
2011  (SD_STATUS_UPDATED |
2012  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2013 
2014  for (i = 0; i < 100; i++) {
2015  tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2016  MAC_STATUS_CFG_CHANGED));
2017  udelay(5);
2018  if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2019  MAC_STATUS_CFG_CHANGED |
2020  MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2021  break;
2022  }
2023 
2024  mac_status = tr32(MAC_STATUS);
2025  if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2026  current_link_up = 0;
2027  if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2028  tp->serdes_counter == 0) {
2029  tw32_f(MAC_MODE, (tp->mac_mode |
2030  MAC_MODE_SEND_CONFIGS));
2031  udelay(1);
2032  tw32_f(MAC_MODE, tp->mac_mode);
2033  }
2034  }
2035 
2036  if (current_link_up) {
2037  tp->link_config.active_speed = SPEED_1000;
2038  tp->link_config.active_duplex = DUPLEX_FULL;
2039  tw32(MAC_LED_CTRL, (tp->led_ctrl |
2040  LED_CTRL_LNKLED_OVERRIDE |
2041  LED_CTRL_1000MBPS_ON));
2042  } else {
2043  tp->link_config.active_speed = SPEED_UNKNOWN;
2044  tp->link_config.active_duplex = DUPLEX_UNKNOWN;
2045  tw32(MAC_LED_CTRL, (tp->led_ctrl |
2046  LED_CTRL_LNKLED_OVERRIDE |
2047  LED_CTRL_TRAFFIC_OVERRIDE));
2048  }
2049 
2050  if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
2051  u32 now_pause_cfg = tp->link_config.active_flowctrl;
2052  if (orig_pause_cfg != now_pause_cfg ||
2053  orig_active_speed != tp->link_config.active_speed ||
2054  orig_active_duplex != tp->link_config.active_duplex)
2055  tg3_link_report(tp);
2056  }
2057 
2058  return 0;
2059 }
2060 
2061 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2062 {
2063  int err = 0;
2064  u32 bmsr, bmcr;
2065  u16 current_speed = SPEED_UNKNOWN;
2066  u8 current_duplex = DUPLEX_UNKNOWN;
2067  int current_link_up = 0;
2068  u32 local_adv, remote_adv, sgsr;
2069 
2070  if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2071  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) &&
2072  !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
2073  (sgsr & SERDES_TG3_SGMII_MODE)) {
2074 
2075  if (force_reset)
2076  tg3_phy_reset(tp);
2077 
2078  tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2079 
2080  if (!(sgsr & SERDES_TG3_LINK_UP)) {
2081  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2082  } else {
2083  current_link_up = 1;
2084  if (sgsr & SERDES_TG3_SPEED_1000) {
2085  current_speed = SPEED_1000;
2086  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2087  } else if (sgsr & SERDES_TG3_SPEED_100) {
2088  current_speed = SPEED_100;
2089  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2090  } else {
2091  current_speed = SPEED_10;
2092  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2093  }
2094 
2095  if (sgsr & SERDES_TG3_FULL_DUPLEX)
2096  current_duplex = DUPLEX_FULL;
2097  else
2098  current_duplex = DUPLEX_HALF;
2099  }
2100 
2101  tw32_f(MAC_MODE, tp->mac_mode);
2102  udelay(40);
2103 
2104  tg3_clear_mac_status(tp);
2105 
2106  goto fiber_setup_done;
2107  }
2108 
2109  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2110  tw32_f(MAC_MODE, tp->mac_mode);
2111  udelay(40);
2112 
2113  tg3_clear_mac_status(tp);
2114 
2115  if (force_reset)
2116  tg3_phy_reset(tp);
2117 
2118  tp->link_config.rmt_adv = 0;
2119 
2120  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2121  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2122  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2123  if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2124  bmsr |= BMSR_LSTATUS;
2125  else
2126  bmsr &= ~BMSR_LSTATUS;
2127  }
2128 
2129  err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2130 
2131  if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2132  (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
2133  /* do nothing, just check for link up at the end */
2134  } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2135  u32 adv, newadv;
2136 
2137  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2138  newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2139  ADVERTISE_1000XPAUSE |
2140  ADVERTISE_1000XPSE_ASYM |
2141  ADVERTISE_SLCT);
2142 
2143  newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2144  newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
2145 
2146  if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
2147  tg3_writephy(tp, MII_ADVERTISE, newadv);
2148  bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2149  tg3_writephy(tp, MII_BMCR, bmcr);
2150 
2151  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2152  tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2153  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
2154 
2155  return err;
2156  }
2157  } else {
2158  u32 new_bmcr;
2159 
2160  bmcr &= ~BMCR_SPEED1000;
2161  new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2162 
2163  if (tp->link_config.duplex == DUPLEX_FULL)
2164  new_bmcr |= BMCR_FULLDPLX;
2165 
2166  if (new_bmcr != bmcr) {
2167  /* BMCR_SPEED1000 is a reserved bit that needs
2168  * to be set on write.
2169  */
2170  new_bmcr |= BMCR_SPEED1000;
2171 
2172  /* Force a linkdown */
2173  if (tp->link_up) {
2174  u32 adv;
2175 
2176  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2177  adv &= ~(ADVERTISE_1000XFULL |
2178  ADVERTISE_1000XHALF |
2179  ADVERTISE_SLCT);
2180  tg3_writephy(tp, MII_ADVERTISE, adv);
2181  tg3_writephy(tp, MII_BMCR, bmcr |
2182  BMCR_ANRESTART |
2183  BMCR_ANENABLE);
2184  udelay(10);
2185  netdev_link_down(tp->dev);
2186  }
2187  tg3_writephy(tp, MII_BMCR, new_bmcr);
2188  bmcr = new_bmcr;
2189  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2190  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2191  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2192  if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2193  bmsr |= BMSR_LSTATUS;
2194  else
2195  bmsr &= ~BMSR_LSTATUS;
2196  }
2197  tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
2198  }
2199  }
2200 
2201  if (bmsr & BMSR_LSTATUS) {
2202  current_speed = SPEED_1000;
2203  current_link_up = 1;
2204  if (bmcr & BMCR_FULLDPLX)
2205  current_duplex = DUPLEX_FULL;
2206  else
2207  current_duplex = DUPLEX_HALF;
2208 
2209  local_adv = 0;
2210  remote_adv = 0;
2211 
2212  if (bmcr & BMCR_ANENABLE) {
2213  u32 common;
2214 
2215  err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2216  err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2217  common = local_adv & remote_adv;
2218  if (common & (ADVERTISE_1000XHALF |
2219  ADVERTISE_1000XFULL)) {
2220  if (common & ADVERTISE_1000XFULL)
2221  current_duplex = DUPLEX_FULL;
2222  else
2223  current_duplex = DUPLEX_HALF;
2224 
2225  tp->link_config.rmt_adv =
2226  mii_adv_to_ethtool_adv_x(remote_adv);
2227  } else if (!tg3_flag(tp, 5780_CLASS)) {
2228  /* Link is up via parallel detect */
2229  } else {
2230  current_link_up = 0;
2231  }
2232  }
2233  }
2234 
2235 fiber_setup_done:
2236  if (current_link_up && current_duplex == DUPLEX_FULL)
2237  tg3_setup_flow_control(tp, local_adv, remote_adv);
2238 
2239  tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2240  if (tp->link_config.active_duplex == DUPLEX_HALF)
2241  tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2242 
2243  tw32_f(MAC_MODE, tp->mac_mode);
2244  udelay(40);
2245 
2246  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2247 
2248  tp->link_config.active_speed = current_speed;
2249  tp->link_config.active_duplex = current_duplex;
2250 
2251  tg3_test_and_report_link_chg(tp, current_link_up);
2252  return err;
2253 }
2254 
2255 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2256 { DBGP("%s\n", __func__);
2257 
2258  int current_link_up;
2259  u32 bmsr, val;
2260  u32 lcl_adv, rmt_adv;
2261  u16 current_speed;
2262  u8 current_duplex;
2263  int i, err;
2264 
2265  tw32(MAC_EVENT, 0);
2266 
2267  tw32_f(MAC_STATUS,
2268  (MAC_STATUS_SYNC_CHANGED |
2269  MAC_STATUS_CFG_CHANGED |
2270  MAC_STATUS_MI_COMPLETION |
2271  MAC_STATUS_LNKSTATE_CHANGED));
2272  udelay(40);
2273 
2274  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2275  tw32_f(MAC_MI_MODE,
2276  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2277  udelay(80);
2278  }
2279 
2280  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
2281 
2282  /* Some third-party PHYs need to be reset on link going
2283  * down.
2284  */
2285  if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2286  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2287  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2288  netdev_link_ok(tp->dev)) {
2289  tg3_readphy(tp, MII_BMSR, &bmsr);
2290  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2291  !(bmsr & BMSR_LSTATUS))
2292  force_reset = 1;
2293  }
2294  if (force_reset)
2295  tg3_phy_reset(tp);
2296 
2297  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2298  tg3_readphy(tp, MII_BMSR, &bmsr);
2299  if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2300  !tg3_flag(tp, INIT_COMPLETE))
2301  bmsr = 0;
2302 
2303  if (!(bmsr & BMSR_LSTATUS)) {
2304  err = tg3_init_5401phy_dsp(tp);
2305  if (err)
2306  return err;
2307 
2308  tg3_readphy(tp, MII_BMSR, &bmsr);
2309  for (i = 0; i < 1000; i++) {
2310  udelay(10);
2311  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2312  (bmsr & BMSR_LSTATUS)) {
2313  udelay(40);
2314  break;
2315  }
2316  }
2317 
2318  if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
2319  TG3_PHY_REV_BCM5401_B0 &&
2320  !(bmsr & BMSR_LSTATUS) &&
2321  tp->link_config.active_speed == SPEED_1000) {
2322  err = tg3_phy_reset(tp);
2323  if (!err)
2324  err = tg3_init_5401phy_dsp(tp);
2325  if (err)
2326  return err;
2327  }
2328  }
2329  } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2330  tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2331  /* 5701 {A0,B0} CRC bug workaround */
2332  tg3_writephy(tp, 0x15, 0x0a75);
2333  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
2334  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2335  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
2336  }
2337 
2338  /* Clear pending interrupts... */
2339  tg3_readphy(tp, MII_TG3_ISTAT, &val);
2340  tg3_readphy(tp, MII_TG3_ISTAT, &val);
2341 
2342  if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
2343  tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2344  else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
2345  tg3_writephy(tp, MII_TG3_IMASK, ~0);
2346 
2347  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2348  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2349  if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2350  tg3_writephy(tp, MII_TG3_EXT_CTRL,
2351  MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2352  else
2353  tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2354  }
2355 
2356  current_link_up = 0;
2357  current_speed = SPEED_INVALID;
2358  current_duplex = DUPLEX_INVALID;
2359 
2360  if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
2361  err = tg3_phy_auxctl_read(tp,
2362  MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
2363  &val);
2364  if (!err && !(val & (1 << 10))) {
2365  tg3_phy_auxctl_write(tp,
2366  MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
2367  val | (1 << 10));
2368  goto relink;
2369  }
2370  }
2371 
2372  bmsr = 0;
2373  for (i = 0; i < 100; i++) {
2374  tg3_readphy(tp, MII_BMSR, &bmsr);
2375  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2376  (bmsr & BMSR_LSTATUS))
2377  break;
2378  udelay(40);
2379  }
2380 
2381  if (bmsr & BMSR_LSTATUS) {
2382  u32 aux_stat, bmcr;
2383 
2384  tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2385  for (i = 0; i < 2000; i++) {
2386  udelay(10);
2387  if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2388  aux_stat)
2389  break;
2390  }
2391 
2392  tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2393  &current_speed,
2394  &current_duplex);
2395 
2396  bmcr = 0;
2397  for (i = 0; i < 200; i++) {
2398  tg3_readphy(tp, MII_BMCR, &bmcr);
2399  if (tg3_readphy(tp, MII_BMCR, &bmcr))
2400  continue;
2401  if (bmcr && bmcr != 0x7fff)
2402  break;
2403  udelay(10);
2404  }
2405 
2406  lcl_adv = 0;
2407  rmt_adv = 0;
2408 
2409  tp->link_config.active_speed = current_speed;
2410  tp->link_config.active_duplex = current_duplex;
2411 
2412  if ((bmcr & BMCR_ANENABLE) &&
2413  tg3_copper_is_advertising_all(tp,
2414  tp->link_config.advertising)) {
2415  if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2416  &rmt_adv)) {
2417  current_link_up = 1;
2418  }
2419  }
2420 
2421  if (current_link_up == 1 &&
2422  tp->link_config.active_duplex == DUPLEX_FULL)
2423  tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2424  }
2425 
2426 relink:
2427  if (current_link_up == 0) {
2428  tg3_phy_copper_begin(tp);
2429 
2430  tg3_readphy(tp, MII_BMSR, &bmsr);
2431  if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
2432  (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
2433  current_link_up = 1;
2434  }
2435 
2436  tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2437  if (current_link_up == 1) {
2438  if (tp->link_config.active_speed == SPEED_100 ||
2439  tp->link_config.active_speed == SPEED_10)
2440  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2441  else
2442  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2443  } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2444  tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2445  else
2446  tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2447 
2448  tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2449  if (tp->link_config.active_duplex == DUPLEX_HALF)
2450  tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2451 
2452  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2453  if (current_link_up == 1 &&
2454  tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2455  tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2456  else
2457  tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2458  }
2459 
2460  /* ??? Without this setting Netgear GA302T PHY does not
2461  * ??? send/receive packets...
2462  */
2463  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
2464  tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2465  tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2466  tw32_f(MAC_MI_MODE, tp->mi_mode);
2467  udelay(80);
2468  }
2469 
2470  tw32_f(MAC_MODE, tp->mac_mode);
2471  udelay(40);
2472 
2473  /* Enabled attention when the link has changed state. */
2474  tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2475  udelay(40);
2476 
2477  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2478  current_link_up == 1 &&
2479  tp->link_config.active_speed == SPEED_1000 &&
2480  (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
2481  udelay(120);
2482  /* NOTE: this freezes for mdc? */
2483  tw32_f(MAC_STATUS,
2484  (MAC_STATUS_SYNC_CHANGED |
2485  MAC_STATUS_CFG_CHANGED));
2486  udelay(40);
2487  tg3_write_mem(tp,
2488  NIC_SRAM_FIRMWARE_MBOX,
2489  NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2490  }
2491 
2492  /* Prevent send BD corruption. */
2493  if (tg3_flag(tp, CLKREQ_BUG)) {
2494  u16 oldlnkctl, newlnkctl;
2495 
2496  pci_read_config_word(tp->pdev,
2497  tp->pcie_cap + PCI_EXP_LNKCTL,
2498  &oldlnkctl);
2499  if (tp->link_config.active_speed == SPEED_100 ||
2500  tp->link_config.active_speed == SPEED_10)
2501  newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
2502  else
2503  newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
2504  if (newlnkctl != oldlnkctl)
2505  pci_write_config_word(tp->pdev,
2506  tp->pcie_cap + PCI_EXP_LNKCTL,
2507  newlnkctl);
2508  }
2509 
2510  if (current_link_up != netdev_link_ok(tp->dev)) {
2511  if (current_link_up)
2512  netdev_link_up(tp->dev);
2513  else
2514  netdev_link_down(tp->dev);
2515  tg3_link_report(tp);
2516  }
2517 
2518  return 0;
2519 }
2520 
2521 int tg3_setup_phy(struct tg3 *tp, int force_reset)
2522 { DBGP("%s\n", __func__);
2523 
2524  u32 val;
2525  int err;
2526 
2527  if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
2528  err = tg3_setup_fiber_phy(tp, force_reset);
2529  else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2530  err = tg3_setup_fiber_mii_phy(tp, force_reset);
2531  else
2532  err = tg3_setup_copper_phy(tp, force_reset);
2533 
2534  val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2535  (6 << TX_LENGTHS_IPG_SHIFT);
2536  if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
2537  val |= tr32(MAC_TX_LENGTHS) &
2538  (TX_LENGTHS_JMB_FRM_LEN_MSK |
2539  TX_LENGTHS_CNT_DWN_VAL_MSK);
2540 
2541  if (tp->link_config.active_speed == SPEED_1000 &&
2542  tp->link_config.active_duplex == DUPLEX_HALF)
2543  tw32(MAC_TX_LENGTHS, val |
2544  (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
2545  else
2546  tw32(MAC_TX_LENGTHS, val |
2547  (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
2548 
2549  if (!tg3_flag(tp, 5705_PLUS)) {
2550  if (netdev_link_ok(tp->dev)) {
2551  tw32(HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS);
2552  } else {
2553  tw32(HOSTCC_STAT_COAL_TICKS, 0);
2554  }
2555  }
2556 
2557  val = tr32(PCIE_PWR_MGMT_THRESH);
2558  if (!netdev_link_ok(tp->dev))
2559  val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK);
2560  else
2561  val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
2562  tw32(PCIE_PWR_MGMT_THRESH, val);
2563 
2564  return err;
2565 }
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Definition: tg3_phy.c:859
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Definition: tg3_phy.c:138
TG3PCI_SUBDEVICE_ID_DELL_MERLOT
#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT
Definition: tg3.h:231
ANEG_DONE
#define ANEG_DONE
Definition: tg3_phy.c:1349
CHIPREV_ID_5701_B0
#define CHIPREV_ID_5701_B0
Definition: tg3.h:268
MAC_MODE_PORT_MODE_MASK
#define MAC_MODE_PORT_MODE_MASK
Definition: tg3.h:504
ASIC_REV_5700
#define ASIC_REV_5700
Definition: tg3.h:299
tg3_phy_auxctl_write
static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
Definition: tg3_phy.c:423
NIC_SRAM_FW_CMD_MBOX
#define NIC_SRAM_FW_CMD_MBOX
Definition: tg3.h:2234
ASIC_REV_5906
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Definition: tg3.h:310
TG3_PHY_ID_REV_MASK
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Definition: tg3.h:3214
ANEG_CFG_PS1
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Definition: tg3_phy.c:1342
PHY_BUSY_LOOPS
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Definition: tg3_phy.c:84
BMCR_ANRESTART
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Definition: mii.h:46
MR_AN_ENABLE
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Definition: tg3_phy.c:1311
MI_COM_PHY_ADDR_SHIFT
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Definition: tg3.h:611
MAC_STATUS_MI_COMPLETION
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Definition: tg3.h:538
LPA_1000XPAUSE
#define LPA_1000XPAUSE
Definition: mii.h:102
tg3_fiber_aneginfo::idle_match
char idle_match
Definition: tg3_phy.c:1334
MII_TG3_AUXCTL_MISC_WIRESPD_EN
#define MII_TG3_AUXCTL_MISC_WIRESPD_EN
Definition: tg3.h:2372
tg3_poll_link
void tg3_poll_link(struct tg3 *tp)
Definition: tg3_phy.c:1009
ADVERTISE_100FULL
#define ADVERTISE_100FULL
Definition: mii.h:80
MII_TG3_DSP_RW_PORT
#define MII_TG3_DSP_RW_PORT
Definition: tg3.h:2332
SERDES_TG3_SGMII_MODE
#define SERDES_TG3_SGMII_MODE
Definition: tg3.h:2443
MII_TG3_AUXCTL_SHDWSEL_MISC
#define MII_TG3_AUXCTL_SHDWSEL_MISC
Definition: tg3.h:2371
MII_TG3_IMASK
#define MII_TG3_IMASK
Definition: tg3.h:2392
TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
Definition: tg3.h:235
TG3_CPMU_PHY_STRAP_IS_SERDES
#define TG3_CPMU_PHY_STRAP_IS_SERDES
Definition: tg3.h:1263
SERDES_TG3_SPEED_1000
#define SERDES_TG3_SPEED_1000
Definition: tg3.h:2447
OTP_MODE
#define OTP_MODE
Definition: tg3.h:2065
MII_TG3_AUXCTL_MISC_FORCE_AMDIX
#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX
Definition: tg3.h:2373
pci_read_config_word
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
OTP_CTRL_OTP_CMD_INIT
#define OTP_CTRL_OTP_CMD_INIT
Definition: tg3.h:2070
netdev_link_down
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:230
SERDES_AN_TIMEOUT_5714S
#define SERDES_AN_TIMEOUT_5714S
Definition: tg3.h:3152
SG_DIG_AUTONEG_COMPLETE
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Definition: tg3.h:909
ASIC_REV_5720
#define ASIC_REV_5720
Definition: tg3.h:320
MAC_MODE_LINK_POLARITY
#define MAC_MODE_LINK_POLARITY
Definition: tg3.h:513
tulip_private::advertising
u16 advertising[4]
Definition: tulip.c:418
tg3_advert_flowctrl_1000X
static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
Definition: tg3_phy.c:1355
TG3PCI_DEVICE_TIGON3_5718
#define TG3PCI_DEVICE_TIGON3_5718
Definition: tg3.h:198
tg3_adv_1000T_flowctrl_ok
static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
Definition: tg3_phy.c:1067
MII_TG3_AUX_STAT_10FULL
#define MII_TG3_AUX_STAT_10FULL
Definition: tg3.h:2382
SG_DIG_STATUS
#define SG_DIG_STATUS
Definition: tg3.h:897
ADVERTISED_FIBRE
#define ADVERTISED_FIBRE
Definition: tg3_phy.c:862
MAC_STATUS_CFG_CHANGED
#define MAC_STATUS_CFG_CHANGED
Definition: tg3.h:534
flowctrl
static int flowctrl
Definition: sundance.c:75
TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
Definition: tg3.h:236
MR_RESTART_AN
#define MR_RESTART_AN
Definition: tg3_phy.c:1312
MR_NP_RX
#define MR_NP_RX
Definition: tg3_phy.c:1325
TX_LENGTHS_JMB_FRM_LEN_MSK
#define TX_LENGTHS_JMB_FRM_LEN_MSK
Definition: tg3.h:649
TG3_OTP_HPFFLTR_MASK
#define TG3_OTP_HPFFLTR_MASK
Definition: tg3.h:2123
SG_DIG_SOFT_RESET
#define SG_DIG_SOFT_RESET
Definition: tg3.h:865
SPEED_10
#define SPEED_10
Definition: atl1e.h:50
TG3PCI_DUAL_MAC_CTRL
#define TG3PCI_DUAL_MAC_CTRL
Definition: tg3.h:415
ADVERTISED_TP
#define ADVERTISED_TP
Definition: tg3_phy.c:861
LED_CTRL_TRAFFIC_OVERRIDE
#define LED_CTRL_TRAFFIC_OVERRIDE
Definition: tg3.h:558
tg3_phy_reset_chanpat
static int tg3_phy_reset_chanpat(struct tg3 *tp)
Definition: tg3_phy.c:390
TG3PCI_SUBDEVICE_ID_3COM_3C996T
#define TG3PCI_SUBDEVICE_ID_3COM_3C996T
Definition: tg3.h:223
MII_TG3_FET_SHADOW_EN
#define MII_TG3_FET_SHADOW_EN
Definition: tg3.h:2430
SG_DIG_PARTNER_PAUSE_CAPABLE
#define SG_DIG_PARTNER_PAUSE_CAPABLE
Definition: tg3.h:901
MAC_MODE_PORT_MODE_TBI
#define MAC_MODE_PORT_MODE_TBI
Definition: tg3.h:505
ANEG_CFG_RF2
#define ANEG_CFG_RF2
Definition: tg3_phy.c:1339
CHIPREV_ID_5704_A1
#define CHIPREV_ID_5704_A1
Definition: tg3.h:276
TG3_OTP_ROFF_MASK
#define TG3_OTP_ROFF_MASK
Definition: tg3.h:2133
MII_TG3_DSP_EXP75
#define MII_TG3_DSP_EXP75
Definition: tg3.h:2351
out
__be32 out[4]
Definition: CIB_PRM.h:36
GET_ASIC_REV
#define GET_ASIC_REV(CHIP_REV_ID)
Definition: tg3.h:298
tg3_setup_fiber_mii_phy
static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2061
CHIPREV_ID_57765_A0
#define CHIPREV_ID_57765_A0
Definition: tg3.h:295
MII_TG3_AUX_STAT_SPDMASK
#define MII_TG3_AUX_STAT_SPDMASK
Definition: tg3.h:2380
ANEG_STATE_NEXT_PAGE_WAIT
#define ANEG_STATE_NEXT_PAGE_WAIT
Definition: tg3_phy.c:1308
tg3_phydsp_write
static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
Definition: tg3_phy.c:411
CPMU_CTRL_GPHY_10MB_RXONLY
#define CPMU_CTRL_GPHY_10MB_RXONLY
Definition: tg3.h:1223
MAC_STATUS_SIGNAL_DET
#define MAC_STATUS_SIGNAL_DET
Definition: tg3.h:532
tg3_setup_phy
int tg3_setup_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2521
TX_LENGTHS_CNT_DWN_VAL_MSK
#define TX_LENGTHS_CNT_DWN_VAL_MSK
Definition: tg3.h:650
TX_STATUS_LINK_UP
#define TX_STATUS_LINK_UP
Definition: tg3.h:639
FLOW_CTRL_TX
#define FLOW_CTRL_TX
Definition: bnx2.h:4152
TG3_PHYFLG_PHY_SERDES
#define TG3_PHYFLG_PHY_SERDES
Definition: tg3.h:3237
ANEG_STATE_IDLE_DETECT_INIT
#define ANEG_STATE_IDLE_DETECT_INIT
Definition: tg3_phy.c:1304
ADVERTISED_1000baseT_Half
#define ADVERTISED_1000baseT_Half
Definition: bnx2.h:46
tg3_fiber_aneg_smachine
static int tg3_fiber_aneg_smachine(struct tg3 *tp, struct tg3_fiber_aneginfo *ap)
Definition: tg3_phy.c:1566
TG3_PHYFLG_MII_SERDES
#define TG3_PHYFLG_MII_SERDES
Definition: tg3.h:3238
TG3_PHY_REV_BCM5401_B0
#define TG3_PHY_REV_BCM5401_B0
Definition: tg3.h:3215
MII_TG3_INT_LINKCHG
#define MII_TG3_INT_LINKCHG
Definition: tg3.h:2395
subsys_tbl_ent::subsys_devid
u16 subsys_devid
Definition: tg3_phy.c:137
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
Definition: tg3.h:218
tmp
unsigned long tmp
Definition: linux_pci.h:64
BMCR_SPEED1000
#define BMCR_SPEED1000
Definition: mii.h:43
TG3_PHY_AUXCTL_SMDSP_ENABLE
#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)
Definition: tg3_phy.c:432
SPEED_100
#define SPEED_100
Definition: atl1e.h:51
MII_TG3_AUX_STAT
#define MII_TG3_AUX_STAT
Definition: tg3.h:2378
TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
Definition: tg3.h:238
TG3_PHY_MII_ADDR
#define TG3_PHY_MII_ADDR
Definition: tg3.h:2306
MII_TG3_TEST1_TRIM_EN
#define MII_TG3_TEST1_TRIM_EN
Definition: tg3.h:2415
TX_MODE_FLOW_CTRL_ENABLE
#define TX_MODE_FLOW_CTRL_ENABLE
Definition: tg3.h:629
MII_TG3_FET_SHDW_MISCCTRL_MDIX
#define MII_TG3_FET_SHDW_MISCCTRL_MDIX
Definition: tg3.h:2433
tg3_setup_flow_control
static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Definition: tg3_phy.c:1124
TG3_PHYFLG_CAPACITIVE_COUPLING
#define TG3_PHYFLG_CAPACITIVE_COUPLING
Definition: tg3.h:3244
MR_AN_COMPLETE
#define MR_AN_COMPLETE
Definition: tg3_phy.c:1313
ADVERTISE_1000XHALF
#define ADVERTISE_1000XHALF
Definition: mii.h:77
TG3_PHYFLG_ANY_SERDES
#define TG3_PHYFLG_ANY_SERDES
Definition: tg3.h:3239
fiber_autoneg
static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Definition: tg3_phy.c:1818
DUAL_MAC_CTRL_ID
#define DUAL_MAC_CTRL_ID
Definition: tg3.h:417
OTP_CTRL
#define OTP_CTRL
Definition: tg3.h:2067
TG3_OTP_LPFDIS_SHIFT
#define TG3_OTP_LPFDIS_SHIFT
Definition: tg3.h:2128
tg3_fiber_aneginfo::link_time
unsigned long link_time
Definition: tg3_phy.c:1329
tg3_phy_reset
int tg3_phy_reset(struct tg3 *tp)
Definition: tg3_phy.c:622
MII_TG3_AUX_STAT_100HALF
#define MII_TG3_AUX_STAT_100HALF
Definition: tg3.h:2383
tg3_phy_init_link_config
static void tg3_phy_init_link_config(struct tg3 *tp)
Definition: tg3_phy.c:866
mii_adv_to_ethtool_adv_x
static u32 mii_adv_to_ethtool_adv_x(u32 adv)
Definition: tg3.h:3436
TG3_PHY_ID_BCM5701
#define TG3_PHY_ID_BCM5701
Definition: tg3.h:3189
TG3_PHYFLG_IS_FET
#define TG3_PHYFLG_IS_FET
Definition: tg3.h:3241
TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
Definition: tg3.h:234
LPA_1000XPAUSE_ASYM
#define LPA_1000XPAUSE_ASYM
Definition: mii.h:104
TG3PCI_SUBDEVICE_ID_3COM_3C1000T
#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T
Definition: tg3.h:226
TG3_PHY_ID_BCM8002
#define TG3_PHY_ID_BCM8002
Definition: tg3.h:3208
TG3_OTP_VDAC_MASK
#define TG3_OTP_VDAC_MASK
Definition: tg3.h:2129
DBGP
#define DBGP(...)
Definition: compiler.h:532
MII_TG3_CTRL_ENABLE_AS_MASTER
#define MII_TG3_CTRL_ENABLE_AS_MASTER
Definition: tg3.h:2316
MAC_TX_LENGTHS
#define MAC_TX_LENGTHS
Definition: tg3.h:642
ADVERTISE_SLCT
#define ADVERTISE_SLCT
Definition: mii.h:72
TG3_OTP_VDAC_SHIFT
#define TG3_OTP_VDAC_SHIFT
Definition: tg3.h:2130
TG3_OTP_HPFOVER_SHIFT
#define TG3_OTP_HPFOVER_SHIFT
Definition: tg3.h:2126
ANEG_FAILED
#define ANEG_FAILED
Definition: tg3_phy.c:1351
MII_TG3_ISTAT
#define MII_TG3_ISTAT
Definition: tg3.h:2391
ANEG_CFG_RF1
#define ANEG_CFG_RF1
Definition: tg3_phy.c:1340
tg3_flag_set
#define tg3_flag_set(tp, flag)
Definition: tg3.h:3367
MII_TG3_FET_TEST
#define MII_TG3_FET_TEST
Definition: tg3.h:2429
MAC_STATUS_SYNC_CHANGED
#define MAC_STATUS_SYNC_CHANGED
Definition: tg3.h:535
DUPLEX_INVALID
#define DUPLEX_INVALID
Definition: bnx2.h:112
TX_LENGTHS_SLOT_TIME_SHIFT
#define TX_LENGTHS_SLOT_TIME_SHIFT
Definition: tg3.h:644
TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
Definition: tg3.h:237
MR_LP_ADV_REMOTE_FAULT1
#define MR_LP_ADV_REMOTE_FAULT1
Definition: tg3_phy.c:1321
NIC_SRAM_FW_CMD_DATA_MBOX
#define NIC_SRAM_FW_CMD_DATA_MBOX
Definition: tg3.h:2245
tg3_advert_flowctrl_1000T
static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
Definition: tg3_phy.c:775
__unused
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
netdev_link_up
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:788
SERDES_AN_TIMEOUT_5704S
#define SERDES_AN_TIMEOUT_5704S
Definition: tg3.h:3150
tg3_fiber_aneginfo::state
int state
Definition: tg3_phy.c:1292
NIC_SRAM_FW_CMD_LEN_MBOX
#define NIC_SRAM_FW_CMD_LEN_MBOX
Definition: tg3.h:2244
RX_MODE_FLOW_CTRL_ENABLE
#define RX_MODE_FLOW_CTRL_ENABLE
Definition: tg3.h:654
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
netdev_link_ok
static int netdev_link_ok(struct net_device *netdev)
Check link state of network device.
Definition: netdevice.h:639
TG3PCI_SUBDEVICE_ID_DELL_VIPER
#define TG3PCI_SUBDEVICE_ID_DELL_VIPER
Definition: tg3.h:229
ANEG_CFG_PS2
#define ANEG_CFG_PS2
Definition: tg3_phy.c:1341
TG3_PHYFLG_ADC_BUG
#define TG3_PHYFLG_ADC_BUG
Definition: tg3.h:3248
tg3_phy_autoneg_cfg
static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
Definition: tg3_phy.c:792
DUPLEX_FULL
#define DUPLEX_FULL
Definition: bnx2.h:111
DUPLEX_UNKNOWN
#define DUPLEX_UNKNOWN
Definition: tg3.h:156
LED_CTRL_MODE_PHY_1
#define LED_CTRL_MODE_PHY_1
Definition: tg3.h:566
MII_TG3_AUX_STAT_1000HALF
#define MII_TG3_AUX_STAT_1000HALF
Definition: tg3.h:2386
tg3_init_5401phy_dsp
static int tg3_init_5401phy_dsp(struct tg3 *tp)
Definition: tg3_phy.c:839
ethtool_adv_to_mii_adv_x
static u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
Definition: tg3.h:3452
TG3PCI_SUBDEVICE_ID_3COM_3C996BT
#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT
Definition: tg3.h:224
tp
static struct tulip_private * tp
Definition: tulip.c:442
MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
Definition: tg3.h:2374
SPEED_UNKNOWN
#define SPEED_UNKNOWN
Definition: tg3.h:150
MII_TG3_DSP_EXP8_REJ2MHz
#define MII_TG3_DSP_EXP8_REJ2MHz
Definition: tg3.h:2349
TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
Definition: tg3.h:227
TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
Definition: tg3.h:230
ASIC_REV_5704
#define ASIC_REV_5704
Definition: tg3.h:302
MII_CTRL1000
#define MII_CTRL1000
Definition: mii.h:24
tg3_bmcr_reset
static int tg3_bmcr_reset(struct tg3 *tp)
Definition: tg3_phy.c:272
MII_TG3_DSP_AADJ1CH0
#define MII_TG3_DSP_AADJ1CH0
Definition: tg3.h:2342
MII_TG3_DSP_EXP8_AEDW
#define MII_TG3_DSP_EXP8_AEDW
Definition: tg3.h:2350
tg3_fiber_aneginfo::flags
u32 flags
Definition: tg3_phy.c:1310
ASIC_REV_5705
#define ASIC_REV_5705
Definition: tg3.h:303
TG3_PHYFLG_ADJUST_TRIM
#define TG3_PHYFLG_ADJUST_TRIM
Definition: tg3.h:3247
MR_LINK_OK
#define MR_LINK_OK
Definition: tg3_phy.c:1327
ASIC_REV_5719
#define ASIC_REV_5719
Definition: tg3.h:319
ADVERTISE_1000XPSE_ASYM
#define ADVERTISE_1000XPSE_ASYM
Definition: mii.h:81
ASIC_REV_5703
#define ASIC_REV_5703
Definition: tg3.h:301
SD_STATUS_LINK_CHG
#define SD_STATUS_LINK_CHG
Definition: tg3.h:2673
tg3_setup_fiber_hw_autoneg
static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
Definition: tg3_phy.c:1421
high
uint32_t high
High 32 bits of address.
Definition: myson.h:20
tg3_init_bcm8002
static void tg3_init_bcm8002(struct tg3 *tp)
Definition: tg3_phy.c:1371
FWCMD_NICDRV_LINK_UPDATE
#define FWCMD_NICDRV_LINK_UPDATE
Definition: tg3.h:2241
MAC_MODE_PORT_INT_LPBACK
#define MAC_MODE_PORT_INT_LPBACK
Definition: tg3.h:509
OTP_ADDRESS_MAGIC1
#define OTP_ADDRESS_MAGIC1
Definition: tg3.h:2075
ANEG_STATE_ABILITY_DETECT_INIT
#define ANEG_STATE_ABILITY_DETECT_INIT
Definition: tg3_phy.c:1298
MII_TG3_MISC_SHDW
#define MII_TG3_MISC_SHDW
Definition: tg3.h:2400
MAC_MODE_PORT_MODE_MII
#define MAC_MODE_PORT_MODE_MII
Definition: tg3.h:507
MII_TG3_DSP_EXP8
#define MII_TG3_DSP_EXP8
Definition: tg3.h:2348
TG3_CPMU_CTRL
#define TG3_CPMU_CTRL
Definition: tg3.h:1219
SG_DIG_ASYM_PAUSE
#define SG_DIG_ASYM_PAUSE
Definition: tg3.h:880
ADVERTISE_PAUSE_ASYM
#define ADVERTISE_PAUSE_ASYM
Definition: mii.h:84
TG3_OTP_HPFOVER_MASK
#define TG3_OTP_HPFOVER_MASK
Definition: tg3.h:2125
limit
uint16_t limit
Limit.
Definition: librm.h:136
BMSR_LSTATUS
#define BMSR_LSTATUS
Definition: mii.h:57
MR_TOGGLE_RX
#define MR_TOGGLE_RX
Definition: tg3_phy.c:1324
ANEG_STATE_IDLE_DETECT
#define ANEG_STATE_IDLE_DETECT
Definition: tg3_phy.c:1305
tg3_flag
#define tg3_flag(tp, flag)
Definition: tg3.h:3365
SG_DIG_IS_SERDES
#define SG_DIG_IS_SERDES
Definition: tg3.h:906
MI_COM_CMD_READ
#define MI_COM_CMD_READ
Definition: tg3.h:606
MII_TG3_DSP_EXP96
#define MII_TG3_DSP_EXP96
Definition: tg3.h:2352
LED_CTRL_LNKLED_OVERRIDE
#define LED_CTRL_LNKLED_OVERRIDE
Definition: tg3.h:554
tg3_fiber_aneginfo::ability_match
char ability_match
Definition: tg3_phy.c:1334
TG3_PHY_ID_INVALID
#define TG3_PHY_ID_INVALID
Definition: tg3.h:3209
AUTONEG_ENABLE
#define AUTONEG_ENABLE
Definition: tg3_phy.c:864
GRC_MISC_CFG_EPHY_IDDQ
#define GRC_MISC_CFG_EPHY_IDDQ
Definition: tg3.h:1835
MII_TG3_FET_PTEST
#define MII_TG3_FET_PTEST
Definition: tg3.h:2425
tg3_test_and_report_link_chg
static int tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
Definition: tg3_phy.c:1928
pci.h
PCI bus.
LED_CTRL_1000MBPS_ON
#define LED_CTRL_1000MBPS_ON
Definition: tg3.h:555
MII_TG3_AUX_STAT_FULL
#define MII_TG3_AUX_STAT_FULL
Definition: tg3.h:2389
MII_TG3_AUXCTL_SHDWSEL_MISCTEST
#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST
Definition: tg3.h:2369
CHIPREV_ID_5700_ALTIMA
#define CHIPREV_ID_5700_ALTIMA
Definition: tg3.h:265
TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
Definition: tg3.h:216
ANEG_OK
#define ANEG_OK
Definition: tg3_phy.c:1348
MAC_MODE_PORT_MODE_GMII
#define MAC_MODE_PORT_MODE_GMII
Definition: tg3.h:506
SG_DIG_CTRL
#define SG_DIG_CTRL
Definition: tg3.h:863
MAC_EVENT_LNKSTATE_CHANGED
#define MAC_EVENT_LNKSTATE_CHANGED
Definition: tg3.h:546
TG3_OTP_AGCTGT_MASK
#define TG3_OTP_AGCTGT_MASK
Definition: tg3.h:2121
TG3_PHY_AUXCTL_SMDSP_DISABLE
#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp)
Definition: tg3_phy.c:437
MII_TG3_DSP_AADJ1CH3
#define MII_TG3_DSP_AADJ1CH3
Definition: tg3.h:2345
ENODEV
#define ENODEV
No such device.
Definition: errno.h:509
MI_COM_REG_ADDR_SHIFT
#define MI_COM_REG_ADDR_SHIFT
Definition: tg3.h:613
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
CHIPREV_5761_AX
#define CHIPREV_5761_AX
Definition: tg3.h:332
SERDES_PARALLEL_DET_TIMEOUT
#define SERDES_PARALLEL_DET_TIMEOUT
Definition: tg3.h:3151
MAC_MODE_HALF_DUPLEX
#define MAC_MODE_HALF_DUPLEX
Definition: tg3.h:503
SERDES_TG3_1000X_STATUS
#define SERDES_TG3_1000X_STATUS
Definition: tg3.h:2442
tg3_fiber_aneginfo::ability_match_count
int ability_match_count
Definition: tg3_phy.c:1332
MAC_EVENT
#define MAC_EVENT
Definition: tg3.h:544
SG_DIG_USING_HW_AUTONEG
#define SG_DIG_USING_HW_AUTONEG
Definition: tg3.h:864
tg3_fiber_aneginfo::ability_match_cfg
u32 ability_match_cfg
Definition: tg3_phy.c:1331
MII_BMCR
#define MII_BMCR
Definition: atl1e.h:871
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
Definition: tg3.h:217
TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
Definition: tg3.h:211
tw32_f
#define tw32_f(reg, val)
Definition: tg3.h:3333
MII_TG3_DSP_TAP1_AGCTGT_DFLT
#define MII_TG3_DSP_TAP1_AGCTGT_DFLT
Definition: tg3.h:2337
FLOW_CTRL_RX
#define FLOW_CTRL_RX
Definition: bnx2.h:4153
SERDES_TG3_FULL_DUPLEX
#define SERDES_TG3_FULL_DUPLEX
Definition: tg3.h:2445
ADVERTISE_1000HALF
#define ADVERTISE_1000HALF
Definition: mii.h:134
OTP_MODE_OTP_THRU_GRC
#define OTP_MODE_OTP_THRU_GRC
Definition: tg3.h:2066
TG3_OTP_10BTAMP_MASK
#define TG3_OTP_10BTAMP_MASK
Definition: tg3.h:2131
common
struct ib_cm_common common
Definition: ib_mad.h:11
ADVERTISE_CSMA
#define ADVERTISE_CSMA
Definition: mii.h:73
SG_DIG_PAUSE_CAP
#define SG_DIG_PAUSE_CAP
Definition: tg3.h:879
MII_TG3_EXT_CTRL
#define MII_TG3_EXT_CTRL
Definition: tg3.h:2322
MII_TG3_EXT_CTRL_LNK3_LED_MODE
#define MII_TG3_EXT_CTRL_LNK3_LED_MODE
Definition: tg3.h:2324
tg3_fiber_aneginfo::rxconfig
u32 rxconfig
Definition: tg3_phy.c:1336
MAC_LED_CTRL
#define MAC_LED_CTRL
Definition: tg3.h:553
tg3_5700_link_polarity
static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
Definition: tg3_phy.c:1197
status
uint8_t status
Status.
Definition: ena.h:16
tg3_phy_apply_otp
static void tg3_phy_apply_otp(struct tg3 *tp)
Definition: tg3_phy.c:510
LED_CTRL_MODE_PHY_2
#define LED_CTRL_MODE_PHY_2
Definition: tg3.h:567
tg3_fiber_aneginfo::cur_time
unsigned long cur_time
Definition: tg3_phy.c:1329
MR_LP_ADV_ASYM_PAUSE
#define MR_LP_ADV_ASYM_PAUSE
Definition: tg3_phy.c:1320
tg3_phy_auxctl_read
static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
Definition: tg3_phy.c:548
MAC_STATUS_PCS_SYNCED
#define MAC_STATUS_PCS_SYNCED
Definition: tg3.h:531
MII_TG3_AUX_STAT_10HALF
#define MII_TG3_AUX_STAT_10HALF
Definition: tg3.h:2381
tg3_fiber_aneginfo::ack_match
char ack_match
Definition: tg3_phy.c:1334
ANEG_STATE_SETTLE_TIME
#define ANEG_STATE_SETTLE_TIME
Definition: tg3_phy.c:1353
TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
Definition: tg3.h:213
TG3_OTP_RCOFF_MASK
#define TG3_OTP_RCOFF_MASK
Definition: tg3.h:2135
MAC_MI_MODE_AUTO_POLL
#define MAC_MI_MODE_AUTO_POLL
Definition: tg3.h:621
MII_TG3_CTRL_ADV_1000_HALF
#define MII_TG3_CTRL_ADV_1000_HALF
Definition: tg3.h:2313
HOSTCC_STAT_COAL_TICKS
#define HOSTCC_STAT_COAL_TICKS
Definition: tg3.h:1350
TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
Definition: tg3.h:219
tg3_writephy
int tg3_writephy(struct tg3 *tp, int reg, u32 val)
Definition: tg3_phy.c:222
OTP_CTRL_OTP_CMD_START
#define OTP_CTRL_OTP_CMD_START
Definition: tg3.h:2071
duplex
duplex
Definition: nic.h:40
MAC_RX_AUTO_NEG
#define MAC_RX_AUTO_NEG
Definition: tg3.h:600
ANEG_STATE_NEXT_PAGE_WAIT_INIT
#define ANEG_STATE_NEXT_PAGE_WAIT_INIT
Definition: tg3_phy.c:1307
MI_COM_PHY_ADDR_MASK
#define MI_COM_PHY_ADDR_MASK
Definition: tg3.h:610
CPMU_LSPD_1000MB_MACCLK_MASK
#define CPMU_LSPD_1000MB_MACCLK_MASK
Definition: tg3.h:1232
MAC_STATUS
#define MAC_STATUS
Definition: tg3.h:530
CHIPREV_ID_5701_A0
#define CHIPREV_ID_5701_A0
Definition: tg3.h:267
SD_STATUS_UPDATED
#define SD_STATUS_UPDATED
Definition: tg3.h:2672
MII_TG3_DSP_ADDRESS
#define MII_TG3_DSP_ADDRESS
Definition: tg3.h:2334
TG3_CPMU_LSPD_1000MB_CLK
#define TG3_CPMU_LSPD_1000MB_CLK
Definition: tg3.h:1229
OTP_ADDRESS_MAGIC2
#define OTP_ADDRESS_MAGIC2
Definition: tg3.h:2076
tg3_write_mem
void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
Definition: tg3_hw.c:922
tg3_phy_set_wirespeed
static void tg3_phy_set_wirespeed(struct tg3 *tp)
Definition: tg3_phy.c:604
MII_TG3_AUXCTL_SHDWSEL_PWRCTL
#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL
Definition: tg3.h:2362
tg3_phy_probe
int tg3_phy_probe(struct tg3 *tp)
Definition: tg3_phy.c:896
mii.h
Media Independent Interface constants.
MR_LP_ADV_HALF_DUPLEX
#define MR_LP_ADV_HALF_DUPLEX
Definition: tg3_phy.c:1318
MII_PHYSID2
#define MII_PHYSID2
Definition: atl1e.h:874
TG3_PHYFLG_EEE_CAP
#define TG3_PHYFLG_EEE_CAP
Definition: tg3.h:3253
TG3_PHYFLG_JITTER_BUG
#define TG3_PHYFLG_JITTER_BUG
Definition: tg3.h:3246
ADVERTISE_10HALF
#define ADVERTISE_10HALF
Definition: mii.h:74
NIC_SRAM_FIRMWARE_MBOX_MAGIC2
#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2
Definition: tg3.h:2205
SG_DIG_PARTNER_ASYM_PAUSE
#define SG_DIG_PARTNER_ASYM_PAUSE
Definition: tg3.h:900
OTP_READ_DATA
#define OTP_READ_DATA
Definition: tg3.h:2079
tg3_setup_fiber_phy
static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:1958
MI_COM_START
#define MI_COM_START
Definition: tg3.h:608
MR_PAGE_RX
#define MR_PAGE_RX
Definition: tg3_phy.c:1314
ANEG_STATE_COMPLETE_ACK
#define ANEG_STATE_COMPLETE_ACK
Definition: tg3_phy.c:1303
BMCR_RESET
#define BMCR_RESET
Definition: mii.h:52
ANEG_STATE_RESTART_INIT
#define ANEG_STATE_RESTART_INIT
Definition: tg3_phy.c:1295
ADVERTISED_10baseT_Full
#define ADVERTISED_10baseT_Full
Definition: bnx2.h:43
SG_DIG_COMMON_SETUP
#define SG_DIG_COMMON_SETUP
Definition: tg3.h:892
ANEG_STATE_RESTART
#define ANEG_STATE_RESTART
Definition: tg3_phy.c:1296
tw32
#define tw32(reg, val)
Definition: tg3.h:3329
TG3_OTP_AGCTGT_SHIFT
#define TG3_OTP_AGCTGT_SHIFT
Definition: tg3.h:2122
TG3_PHY_ID_BCM5703
#define TG3_PHY_ID_BCM5703
Definition: tg3.h:3190
TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
Definition: tg3.h:214
tg3_phy_write_and_check_testpat
static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
Definition: tg3_phy.c:323
DBGCP
#define DBGCP(...)
Definition: compiler.h:539
MI_COM_DATA_MASK
#define MI_COM_DATA_MASK
Definition: tg3.h:614
MII_TG3_AUX_STAT_1000FULL
#define MII_TG3_AUX_STAT_1000FULL
Definition: tg3.h:2387
MAC_MI_MODE
#define MAC_MI_MODE
Definition: tg3.h:618
MII_TG3_DSP_CONTROL
#define MII_TG3_DSP_CONTROL
Definition: tg3.h:2333
TG3_OTP_ROFF_SHIFT
#define TG3_OTP_ROFF_SHIFT
Definition: tg3.h:2134
MII_TG3_DSP_AADJ1CH3_ADCCKADJ
#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ
Definition: tg3.h:2346
GRC_MISC_CFG
#define GRC_MISC_CFG
Definition: tg3.h:1819
MR_TOGGLE_TX
#define MR_TOGGLE_TX
Definition: tg3_phy.c:1316
ANEG_STATE_COMPLETE_ACK_INIT
#define ANEG_STATE_COMPLETE_ACK_INIT
Definition: tg3_phy.c:1302
ANEG_STATE_ACK_DETECT
#define ANEG_STATE_ACK_DETECT
Definition: tg3_phy.c:1301
ASIC_REV_5714
#define ASIC_REV_5714
Definition: tg3.h:307
ADVERTISE_PAUSE_CAP
#define ADVERTISE_PAUSE_CAP
Definition: mii.h:83
TG3PCI_SUBVENDOR_ID_DELL
#define TG3PCI_SUBVENDOR_ID_DELL
Definition: tg3.h:228
tg3_setup_copper_phy
static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2255
MII_TG3_AUX_STAT_100
#define MII_TG3_AUX_STAT_100
Definition: tg3.h:2388
ADVERTISE_100HALF
#define ADVERTISE_100HALF
Definition: mii.h:78
GET_CHIP_REV
#define GET_CHIP_REV(CHIP_REV_ID)
Definition: tg3.h:321
TG3_BMCR_SPEED1000
#define TG3_BMCR_SPEED1000
Definition: tg3.h:2310
CHIPREV_ID_5704_A0
#define CHIPREV_ID_5704_A0
Definition: tg3.h:275
tg3_phy_toggle_automdix
static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
Definition: tg3_phy.c:562
tg3_aux_stat_to_speed_duplex
static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
Definition: tg3_phy.c:1019
ANEG_TIMER_ENAB
#define ANEG_TIMER_ENAB
Definition: tg3_phy.c:1350
CHIPREV_ID_5717_A0
#define CHIPREV_ID_5717_A0
Definition: tg3.h:294
MR_LP_ADV_NEXT_PAGE
#define MR_LP_ADV_NEXT_PAGE
Definition: tg3_phy.c:1323
ANEG_CFG_FD
#define ANEG_CFG_FD
Definition: tg3_phy.c:1344
PCIE_PWR_MGMT_THRESH
#define PCIE_PWR_MGMT_THRESH
Definition: tg3.h:2087
BMCR_ANENABLE
#define BMCR_ANENABLE
Definition: mii.h:49
ANEG_STATE_DISABLE_LINK_OK
#define ANEG_STATE_DISABLE_LINK_OK
Definition: tg3_phy.c:1297
tg3_copper_is_advertising_all
static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
Definition: tg3_phy.c:738
MII_BMSR
#define MII_BMSR
Definition: atl1e.h:872
MII_PHYSID1
#define MII_PHYSID1
Definition: atl1e.h:873
ANEG_CFG_ACK
#define ANEG_CFG_ACK
Definition: tg3_phy.c:1338
MR_LP_ADV_FULL_DUPLEX
#define MR_LP_ADV_FULL_DUPLEX
Definition: tg3_phy.c:1317
MII_TG3_TEST1
#define MII_TG3_TEST1
Definition: tg3.h:2414
MAC_MODE
#define MAC_MODE
Definition: tg3.h:501
TX_LENGTHS_IPG_CRS_SHIFT
#define TX_LENGTHS_IPG_CRS_SHIFT
Definition: tg3.h:648
MI_COM_BUSY
#define MI_COM_BUSY
Definition: tg3.h:609
ANEG_STATE_ACK_DETECT_INIT
#define ANEG_STATE_ACK_DETECT_INIT
Definition: tg3_phy.c:1300
MAC_STATUS_LNKSTATE_CHANGED
#define MAC_STATUS_LNKSTATE_CHANGED
Definition: tg3.h:537
DEFAULT_STAT_COAL_TICKS
#define DEFAULT_STAT_COAL_TICKS
Definition: tg3.h:1351
TG3PCI_SUBVENDOR_ID_3COM
#define TG3PCI_SUBVENDOR_ID_3COM
Definition: tg3.h:222
ADVERTISED_1000baseT_Full
#define ADVERTISED_1000baseT_Full
Definition: bnx2.h:47
tg3_mdio_init
void tg3_mdio_init(struct tg3 *tp)
Definition: tg3_phy.c:14
MII_TG3_CTRL
#define MII_TG3_CTRL
Definition: tg3.h:2312
ANEG_STATE_ABILITY_DETECT
#define ANEG_STATE_ABILITY_DETECT
Definition: tg3_phy.c:1299
TG3_PHYFLG_PARALLEL_DETECT
#define TG3_PHYFLG_PARALLEL_DETECT
Definition: tg3.h:3252
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
cmd
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
tg3_read_otp_phycfg
u32 tg3_read_otp_phycfg(struct tg3 *tp)
int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
Definition: tg3_phy.c:57
ADVERTISED_100baseT_Full
#define ADVERTISED_100baseT_Full
Definition: bnx2.h:45
string.h
String functions.
tg3_wait_macro_done
static int tg3_wait_macro_done(struct tg3 *tp)
Definition: tg3_phy.c:304
PCI_EXP_LNKCTL_CLKREQ_EN
#define PCI_EXP_LNKCTL_CLKREQ_EN
Definition: tg3.h:18
TG3PCI_SUBVENDOR_ID_BROADCOM
#define TG3PCI_SUBVENDOR_ID_BROADCOM
Definition: tg3.h:210
MII_TG3_CTRL_AS_MASTER
#define MII_TG3_CTRL_AS_MASTER
Definition: tg3.h:2315
done
struct bofm_section_header done
Definition: bofm_test.c:46
ADVERTISED_10baseT_Half
#define ADVERTISED_10baseT_Half
Definition: bnx2.h:42
u8
uint8_t u8
Definition: stdint.h:19
u32
uint32_t u32
Definition: stdint.h:23
OTP_STATUS_CMD_DONE
#define OTP_STATUS_CMD_DONE
Definition: tg3.h:2073
TG3_PHY_ID_MASK
#define TG3_PHY_ID_MASK
Definition: tg3.h:3185
MII_TG3_AUXCTL_SHDWSEL_AUXCTL
#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL
Definition: tg3.h:2357
TG3_PHY_ID_BCM5401
#define TG3_PHY_ID_BCM5401
Definition: tg3.h:3187
BMCR_FULLDPLX
#define BMCR_FULLDPLX
Definition: mii.h:45
MAC_SERDES_CFG
#define MAC_SERDES_CFG
Definition: tg3.h:743
TG3_PHYFLG_NO_ETH_WIRE_SPEED
#define TG3_PHYFLG_NO_ETH_WIRE_SPEED
Definition: tg3.h:3245
MAC_TX_STATUS
#define MAC_TX_STATUS
Definition: tg3.h:635
NIC_SRAM_FIRMWARE_MBOX
#define NIC_SRAM_FIRMWARE_MBOX
Definition: tg3.h:2203
TG3PCI_SUBVENDOR_ID_IBM
#define TG3PCI_SUBVENDOR_ID_IBM
Definition: tg3.h:239
MAC_RX_MODE
#define MAC_RX_MODE
Definition: tg3.h:651
ADVERTISE_1000XFULL
#define ADVERTISE_1000XFULL
Definition: mii.h:75
DUPLEX_HALF
#define DUPLEX_HALF
Definition: bnx2.h:110
MR_LP_ADV_REMOTE_FAULT2
#define MR_LP_ADV_REMOTE_FAULT2
Definition: tg3_phy.c:1322
MII_STAT1000
#define MII_STAT1000
Definition: mii.h:25
tg3_wait_for_event_ack
void tg3_wait_for_event_ack(struct tg3 *tp)
Definition: tg3_hw.c:909
memset
void * memset(void *dest, int character, size_t len) __nonnull
tg3_setup_fiber_by_hand
static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
Definition: tg3_phy.c:1863
ASIC_REV_5701
#define ASIC_REV_5701
Definition: tg3.h:300
ANEG_STATE_LINK_OK
#define ANEG_STATE_LINK_OK
Definition: tg3_phy.c:1306
TG3_KNOWN_PHY_ID
#define TG3_KNOWN_PHY_ID(X)
Definition: tg3.h:3220
ASIC_REV_57765
#define ASIC_REV_57765
Definition: tg3.h:317
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