iPXE
tg3.h
Go to the documentation of this file.
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2007-2011 Broadcom Corporation.
8  */
9 
10 #ifndef _T3_H
11 #define _T3_H
12 
13 #undef ERRFILE
14 #define ERRFILE ERRFILE_tg3
15 
16 /* From linux/include/linux/pci_regs.h: */
17 #define PCI_EXP_LNKCTL 16 /* Link Control */
18 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
19 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
20 
21 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
22 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
23 
24 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
25 /* </pci_regs.h> */
26 
27 /* ethtool.h: */
28 #define ADVERTISED_10baseT_Half (1 << 0)
29 #define ADVERTISED_10baseT_Full (1 << 1)
30 #define ADVERTISED_100baseT_Half (1 << 2)
31 #define ADVERTISED_100baseT_Full (1 << 3)
32 #define ADVERTISED_1000baseT_Half (1 << 4)
33 #define ADVERTISED_1000baseT_Full (1 << 5)
34 #define ADVERTISED_Autoneg (1 << 6)
35 /* </ethtool.h> */
36 
37 #ifndef ADVERTISED_Pause
38 #define ADVERTISED_Pause (1 << 13)
39 #endif
40 #ifndef ADVERTISED_Asym_Pause
41 #define ADVERTISED_Asym_Pause (1 << 14)
42 #endif
43 
44 /* mdio.h: */
45 #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
46 
47 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
48 
49 #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
50 #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
51 /* </mdio.h> */
52 
53 /* mii.h */
54 #define FLOW_CTRL_TX 0x01
55 #define FLOW_CTRL_RX 0x02
56 /* </mii.h> */
57 
58 /* pci_regs.h */
59 #define PCI_X_CMD 2 /* Modes & Features */
60 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
61 
62 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
63 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
64 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
65 #define PCI_EXP_DEVSTA 10 /* Device Status */
66 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
67 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
68 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
69 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
70 /* </pci_regs.h> */
71 
72 /* pci_ids.h: */
73 #define PCI_VENDOR_ID_BROADCOM 0x14e4
74 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
75 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
76 #define PCI_DEVICE_ID_NX2_5709 0x1639
77 #define PCI_DEVICE_ID_NX2_5709S 0x163a
78 #define PCI_DEVICE_ID_TIGON3_5700 0x1644
79 #define PCI_DEVICE_ID_TIGON3_5701 0x1645
80 #define PCI_DEVICE_ID_TIGON3_5702 0x1646
81 #define PCI_DEVICE_ID_TIGON3_5703 0x1647
82 #define PCI_DEVICE_ID_TIGON3_5704 0x1648
83 #define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
84 #define PCI_DEVICE_ID_NX2_5706 0x164a
85 #define PCI_DEVICE_ID_NX2_5708 0x164c
86 #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
87 #define PCI_DEVICE_ID_NX2_57710 0x164e
88 #define PCI_DEVICE_ID_NX2_57711 0x164f
89 #define PCI_DEVICE_ID_NX2_57711E 0x1650
90 #define PCI_DEVICE_ID_TIGON3_5705 0x1653
91 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
92 #define PCI_DEVICE_ID_TIGON3_5721 0x1659
93 #define PCI_DEVICE_ID_TIGON3_5722 0x165a
94 #define PCI_DEVICE_ID_TIGON3_5723 0x165b
95 #define PCI_DEVICE_ID_TIGON3_5705M 0x165d
96 #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
97 #define PCI_DEVICE_ID_NX2_57712 0x1662
98 #define PCI_DEVICE_ID_NX2_57712E 0x1663
99 #define PCI_DEVICE_ID_TIGON3_5714 0x1668
100 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669
101 #define PCI_DEVICE_ID_TIGON3_5780 0x166a
102 #define PCI_DEVICE_ID_TIGON3_5780S 0x166b
103 #define PCI_DEVICE_ID_TIGON3_5705F 0x166e
104 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
105 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
106 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
107 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
108 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
109 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
110 #define PCI_DEVICE_ID_TIGON3_5754 0x167a
111 #define PCI_DEVICE_ID_TIGON3_5755 0x167b
112 #define PCI_DEVICE_ID_TIGON3_5751M 0x167d
113 #define PCI_DEVICE_ID_TIGON3_5751F 0x167e
114 #define PCI_DEVICE_ID_TIGON3_5787F 0x167f
115 #define PCI_DEVICE_ID_TIGON3_5761E 0x1680
116 #define PCI_DEVICE_ID_TIGON3_5761 0x1681
117 #define PCI_DEVICE_ID_TIGON3_5764 0x1684
118 #define PCI_DEVICE_ID_TIGON3_5787M 0x1693
119 #define PCI_DEVICE_ID_TIGON3_5782 0x1696
120 #define PCI_DEVICE_ID_TIGON3_5784 0x1698
121 #define PCI_DEVICE_ID_TIGON3_5786 0x169a
122 #define PCI_DEVICE_ID_TIGON3_5787 0x169b
123 #define PCI_DEVICE_ID_TIGON3_5788 0x169c
124 #define PCI_DEVICE_ID_TIGON3_5789 0x169d
125 #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
126 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
127 #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
128 #define PCI_DEVICE_ID_NX2_5706S 0x16aa
129 #define PCI_DEVICE_ID_NX2_5708S 0x16ac
130 #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
131 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
132 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd
133 #define PCI_DEVICE_ID_TIGON3_5753 0x16f7
134 #define PCI_DEVICE_ID_TIGON3_5753M 0x16fd
135 #define PCI_DEVICE_ID_TIGON3_5753F 0x16fe
136 #define PCI_DEVICE_ID_TIGON3_5901 0x170d
137 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
138 #define PCI_DEVICE_ID_TIGON3_5906 0x1712
139 #define PCI_DEVICE_ID_TIGON3_5906M 0x1713
140 #define PCI_VENDOR_ID_COMPAQ 0x0e11
141 #define PCI_VENDOR_ID_IBM 0x1014
142 #define PCI_VENDOR_ID_DELL 0x1028
143 #define PCI_VENDOR_ID_3COM 0x10b7
144 /* </pci_ids.h> */
145 
146 #define SPEED_10 10
147 #define SPEED_100 100
148 #define SPEED_1000 1000
149 #ifndef SPEED_UNKNOWN
150 #define SPEED_UNKNOWN -1
151 #endif
152 
153 #define DUPLEX_HALF 0x00
154 #define DUPLEX_FULL 0x01
155 #ifndef DUPLEX_UNKNOWN
156 #define DUPLEX_UNKNOWN 0xff
157 #endif
158 
159 #define TG3_64BIT_REG_HIGH 0x00UL
160 #define TG3_64BIT_REG_LOW 0x04UL
161 
162 /* Descriptor block info. */
163 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
164 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
165 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
166 #define BDINFO_FLAGS_DISABLED 0x00000002
167 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
168 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
169 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
170 #define TG3_BDINFO_SIZE 0x10UL
171 
172 #define RX_STD_MAX_SIZE 1536
173 #define TG3_RX_STD_MAX_SIZE_5700 512
174 #define TG3_RX_STD_MAX_SIZE_5717 2048
175 #define TG3_RX_JMB_MAX_SIZE_5700 256
176 #define TG3_RX_JMB_MAX_SIZE_5717 1024
177 #define TG3_RX_RET_MAX_SIZE_5700 1024
178 #define TG3_RX_RET_MAX_SIZE_5705 512
179 #define TG3_RX_RET_MAX_SIZE_5717 4096
180 
181 /* First 256 bytes are a mirror of PCI config space. */
182 #define TG3PCI_VENDOR 0x00000000
183 #define TG3PCI_VENDOR_BROADCOM 0x14e4
184 #define TG3PCI_DEVICE 0x00000002
185 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
186 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
187 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
188 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
189 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688
190 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
191 #define TG3PCI_DEVICE_TIGON3_57780 0x1692
192 #define TG3PCI_DEVICE_TIGON3_57760 0x1690
193 #define TG3PCI_DEVICE_TIGON3_57790 0x1694
194 #define TG3PCI_DEVICE_TIGON3_57788 0x1691
195 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
196 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
197 #define TG3PCI_DEVICE_TIGON3_5717 0x1655
198 #define TG3PCI_DEVICE_TIGON3_5718 0x1656
199 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
200 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
201 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
202 #define TG3PCI_DEVICE_TIGON3_57762 0x1682
203 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4
204 #define TG3PCI_DEVICE_TIGON3_57766 0x1686
205 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
206 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
207 #define TG3PCI_DEVICE_TIGON3_5719 0x1657
208 #define TG3PCI_DEVICE_TIGON3_5720 0x165f
209 /* 0x04 --> 0x2c unused */
210 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
211 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
212 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
213 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
214 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
215 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
216 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
217 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
218 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
219 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
220 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
221 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
222 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
223 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
224 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
225 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
226 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
227 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
228 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
229 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
230 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
231 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
232 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
233 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
234 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
235 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
236 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
237 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
238 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
239 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
240 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
241 /* 0x30 --> 0x64 unused */
242 #define TG3PCI_MSI_DATA 0x00000064
243 /* 0x66 --> 0x68 unused */
244 #define TG3PCI_MISC_HOST_CTRL 0x00000068
245 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
246 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
247 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
248 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
249 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
250 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
251 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
252 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
253 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
254 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
255 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
256 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
257 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
258  (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
259  MISC_HOST_CTRL_CHIPREV_SHIFT)
260 #define CHIPREV_ID_5700_A0 0x7000
261 #define CHIPREV_ID_5700_A1 0x7001
262 #define CHIPREV_ID_5700_B0 0x7100
263 #define CHIPREV_ID_5700_B1 0x7101
264 #define CHIPREV_ID_5700_B3 0x7102
265 #define CHIPREV_ID_5700_ALTIMA 0x7104
266 #define CHIPREV_ID_5700_C0 0x7200
267 #define CHIPREV_ID_5701_A0 0x0000
268 #define CHIPREV_ID_5701_B0 0x0100
269 #define CHIPREV_ID_5701_B2 0x0102
270 #define CHIPREV_ID_5701_B5 0x0105
271 #define CHIPREV_ID_5703_A0 0x1000
272 #define CHIPREV_ID_5703_A1 0x1001
273 #define CHIPREV_ID_5703_A2 0x1002
274 #define CHIPREV_ID_5703_A3 0x1003
275 #define CHIPREV_ID_5704_A0 0x2000
276 #define CHIPREV_ID_5704_A1 0x2001
277 #define CHIPREV_ID_5704_A2 0x2002
278 #define CHIPREV_ID_5704_A3 0x2003
279 #define CHIPREV_ID_5705_A0 0x3000
280 #define CHIPREV_ID_5705_A1 0x3001
281 #define CHIPREV_ID_5705_A2 0x3002
282 #define CHIPREV_ID_5705_A3 0x3003
283 #define CHIPREV_ID_5750_A0 0x4000
284 #define CHIPREV_ID_5750_A1 0x4001
285 #define CHIPREV_ID_5750_A3 0x4003
286 #define CHIPREV_ID_5750_C2 0x4202
287 #define CHIPREV_ID_5752_A0_HW 0x5000
288 #define CHIPREV_ID_5752_A0 0x6000
289 #define CHIPREV_ID_5752_A1 0x6001
290 #define CHIPREV_ID_5714_A2 0x9002
291 #define CHIPREV_ID_5906_A1 0xc001
292 #define CHIPREV_ID_57780_A0 0x57780000
293 #define CHIPREV_ID_57780_A1 0x57780001
294 #define CHIPREV_ID_5717_A0 0x05717000
295 #define CHIPREV_ID_57765_A0 0x57785000
296 #define CHIPREV_ID_5719_A0 0x05719000
297 #define CHIPREV_ID_5720_A0 0x05720000
298 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
299 #define ASIC_REV_5700 0x07
300 #define ASIC_REV_5701 0x00
301 #define ASIC_REV_5703 0x01
302 #define ASIC_REV_5704 0x02
303 #define ASIC_REV_5705 0x03
304 #define ASIC_REV_5750 0x04
305 #define ASIC_REV_5752 0x06
306 #define ASIC_REV_5780 0x08
307 #define ASIC_REV_5714 0x09
308 #define ASIC_REV_5755 0x0a
309 #define ASIC_REV_5787 0x0b
310 #define ASIC_REV_5906 0x0c
311 #define ASIC_REV_USE_PROD_ID_REG 0x0f
312 #define ASIC_REV_5784 0x5784
313 #define ASIC_REV_5761 0x5761
314 #define ASIC_REV_5785 0x5785
315 #define ASIC_REV_57780 0x57780
316 #define ASIC_REV_5717 0x5717
317 #define ASIC_REV_57765 0x57785
318 #define ASIC_REV_57766 0x57766
319 #define ASIC_REV_5719 0x5719
320 #define ASIC_REV_5720 0x5720
321 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
322 #define CHIPREV_5700_AX 0x70
323 #define CHIPREV_5700_BX 0x71
324 #define CHIPREV_5700_CX 0x72
325 #define CHIPREV_5701_AX 0x00
326 #define CHIPREV_5703_AX 0x10
327 #define CHIPREV_5704_AX 0x20
328 #define CHIPREV_5704_BX 0x21
329 #define CHIPREV_5750_AX 0x40
330 #define CHIPREV_5750_BX 0x41
331 #define CHIPREV_5784_AX 0x57840
332 #define CHIPREV_5761_AX 0x57610
333 #define CHIPREV_57765_AX 0x577650
334 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
335 #define METAL_REV_A0 0x00
336 #define METAL_REV_A1 0x01
337 #define METAL_REV_B0 0x00
338 #define METAL_REV_B1 0x01
339 #define METAL_REV_B2 0x02
340 #define TG3PCI_DMA_RW_CTRL 0x0000006c
341 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
342 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
343 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
344 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
345 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
346 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
347 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
348 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
349 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
350 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
351 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
352 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
353 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
354 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
355 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
356 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
357 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
358 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
359 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
360 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
361 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
362 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
363 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
364 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
365 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
366 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
367 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
368 #define DMA_RWCTRL_ONE_DMA 0x00004000
369 #define DMA_RWCTRL_READ_WATER 0x00070000
370 #define DMA_RWCTRL_READ_WATER_SHIFT 16
371 #define DMA_RWCTRL_WRITE_WATER 0x00380000
372 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
373 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
374 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
375 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
376 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
377 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
378 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
379 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
380 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
381 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
382 #define TG3PCI_PCISTATE 0x00000070
383 #define PCISTATE_FORCE_RESET 0x00000001
384 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
385 #define PCISTATE_CONV_PCI_MODE 0x00000004
386 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
387 #define PCISTATE_BUS_32BIT 0x00000010
388 #define PCISTATE_ROM_ENABLE 0x00000020
389 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
390 #define PCISTATE_FLAT_VIEW 0x00000100
391 #define PCISTATE_RETRY_SAME_DMA 0x00002000
392 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
393 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
394 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
395 #define TG3PCI_CLOCK_CTRL 0x00000074
396 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
397 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
398 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
399 #define CLOCK_CTRL_ALTCLK 0x00001000
400 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
401 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
402 #define CLOCK_CTRL_625_CORE 0x00100000
403 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
404 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
405 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
406 #define TG3PCI_REG_BASE_ADDR 0x00000078
407 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
408 #define TG3PCI_REG_DATA 0x00000080
409 #define TG3PCI_MEM_WIN_DATA 0x00000084
410 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
411 /* 0x94 --> 0x98 unused */
412 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
413 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
414 /* 0xa8 --> 0xb8 unused */
415 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
416 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
417 #define DUAL_MAC_CTRL_ID 0x00000004
418 #define TG3PCI_PRODID_ASICREV 0x000000bc
419 #define PROD_ID_ASIC_REV_MASK 0x0fffffff
420 /* 0xc0 --> 0xf4 unused */
421 
422 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
423 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
424 /* 0xf8 --> 0x200 unused */
425 
426 #define TG3_CORR_ERR_STAT 0x00000110
427 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
428 /* 0x114 --> 0x200 unused */
429 
430 /* Mailbox registers */
431 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
432 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
433 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
434 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
435 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
436 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
437 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
438 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
439 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
440 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
441 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
442 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
443 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
444 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
445 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
446  TG3_64BIT_REG_LOW)
447 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
448 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
449  TG3_64BIT_REG_LOW)
450 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
451 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
452 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
453 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
454 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
455 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
456 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
457 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
458 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
459 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
460 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
461 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
462 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
463 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
464 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
465 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
466 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
467 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
468 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
469 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
470 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
471 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
472 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
473 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
474 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
475 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
476 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
477 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
478 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
479 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
480 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
481 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
482 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
483 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
484 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
485 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
486 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
487 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
488 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
489 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
490 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
491 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
492 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
493 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
494 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
495 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
496 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
497 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
498 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
499 
500 /* MAC control registers */
501 #define MAC_MODE 0x00000400
502 #define MAC_MODE_RESET 0x00000001
503 #define MAC_MODE_HALF_DUPLEX 0x00000002
504 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
505 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
506 #define MAC_MODE_PORT_MODE_GMII 0x00000008
507 #define MAC_MODE_PORT_MODE_MII 0x00000004
508 #define MAC_MODE_PORT_MODE_NONE 0x00000000
509 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
510 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
511 #define MAC_MODE_TX_BURSTING 0x00000100
512 #define MAC_MODE_MAX_DEFER 0x00000200
513 #define MAC_MODE_LINK_POLARITY 0x00000400
514 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
515 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
516 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
517 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
518 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
519 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
520 #define MAC_MODE_SEND_CONFIGS 0x00020000
521 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
522 #define MAC_MODE_ACPI_ENABLE 0x00080000
523 #define MAC_MODE_MIP_ENABLE 0x00100000
524 #define MAC_MODE_TDE_ENABLE 0x00200000
525 #define MAC_MODE_RDE_ENABLE 0x00400000
526 #define MAC_MODE_FHDE_ENABLE 0x00800000
527 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
528 #define MAC_MODE_APE_RX_EN 0x08000000
529 #define MAC_MODE_APE_TX_EN 0x10000000
530 #define MAC_STATUS 0x00000404
531 #define MAC_STATUS_PCS_SYNCED 0x00000001
532 #define MAC_STATUS_SIGNAL_DET 0x00000002
533 #define MAC_STATUS_RCVD_CFG 0x00000004
534 #define MAC_STATUS_CFG_CHANGED 0x00000008
535 #define MAC_STATUS_SYNC_CHANGED 0x00000010
536 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
537 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
538 #define MAC_STATUS_MI_COMPLETION 0x00400000
539 #define MAC_STATUS_MI_INTERRUPT 0x00800000
540 #define MAC_STATUS_AP_ERROR 0x01000000
541 #define MAC_STATUS_ODI_ERROR 0x02000000
542 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
543 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
544 #define MAC_EVENT 0x00000408
545 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
546 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
547 #define MAC_EVENT_MI_COMPLETION 0x00400000
548 #define MAC_EVENT_MI_INTERRUPT 0x00800000
549 #define MAC_EVENT_AP_ERROR 0x01000000
550 #define MAC_EVENT_ODI_ERROR 0x02000000
551 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
552 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
553 #define MAC_LED_CTRL 0x0000040c
554 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
555 #define LED_CTRL_1000MBPS_ON 0x00000002
556 #define LED_CTRL_100MBPS_ON 0x00000004
557 #define LED_CTRL_10MBPS_ON 0x00000008
558 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
559 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
560 #define LED_CTRL_TRAFFIC_LED 0x00000040
561 #define LED_CTRL_1000MBPS_STATUS 0x00000080
562 #define LED_CTRL_100MBPS_STATUS 0x00000100
563 #define LED_CTRL_10MBPS_STATUS 0x00000200
564 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
565 #define LED_CTRL_MODE_MAC 0x00000000
566 #define LED_CTRL_MODE_PHY_1 0x00000800
567 #define LED_CTRL_MODE_PHY_2 0x00001000
568 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
569 #define LED_CTRL_MODE_SHARED 0x00004000
570 #define LED_CTRL_MODE_COMBO 0x00008000
571 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
572 #define LED_CTRL_BLINK_RATE_SHIFT 19
573 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
574 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
575 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
576 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
577 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
578 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
579 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
580 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
581 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
582 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
583 #define MAC_ACPI_MBUF_PTR 0x00000430
584 #define MAC_ACPI_LEN_OFFSET 0x00000434
585 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
586 #define ACPI_LENOFF_LEN_SHIFT 0
587 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
588 #define ACPI_LENOFF_OFF_SHIFT 16
589 #define MAC_TX_BACKOFF_SEED 0x00000438
590 #define TX_BACKOFF_SEED_MASK 0x000003ff
591 #define MAC_RX_MTU_SIZE 0x0000043c
592 #define RX_MTU_SIZE_MASK 0x0000ffff
593 #define MAC_PCS_TEST 0x00000440
594 #define PCS_TEST_PATTERN_MASK 0x000fffff
595 #define PCS_TEST_PATTERN_SHIFT 0
596 #define PCS_TEST_ENABLE 0x00100000
597 #define MAC_TX_AUTO_NEG 0x00000444
598 #define TX_AUTO_NEG_MASK 0x0000ffff
599 #define TX_AUTO_NEG_SHIFT 0
600 #define MAC_RX_AUTO_NEG 0x00000448
601 #define RX_AUTO_NEG_MASK 0x0000ffff
602 #define RX_AUTO_NEG_SHIFT 0
603 #define MAC_MI_COM 0x0000044c
604 #define MI_COM_CMD_MASK 0x0c000000
605 #define MI_COM_CMD_WRITE 0x04000000
606 #define MI_COM_CMD_READ 0x08000000
607 #define MI_COM_READ_FAILED 0x10000000
608 #define MI_COM_START 0x20000000
609 #define MI_COM_BUSY 0x20000000
610 #define MI_COM_PHY_ADDR_MASK 0x03e00000
611 #define MI_COM_PHY_ADDR_SHIFT 21
612 #define MI_COM_REG_ADDR_MASK 0x001f0000
613 #define MI_COM_REG_ADDR_SHIFT 16
614 #define MI_COM_DATA_MASK 0x0000ffff
615 #define MAC_MI_STAT 0x00000450
616 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
617 #define MAC_MI_STAT_10MBPS_MODE 0x00000002
618 #define MAC_MI_MODE 0x00000454
619 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
620 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
621 #define MAC_MI_MODE_AUTO_POLL 0x00000010
622 #define MAC_MI_MODE_500KHZ_CONST 0x00008000
623 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
624 #define MAC_AUTO_POLL_STATUS 0x00000458
625 #define MAC_AUTO_POLL_ERROR 0x00000001
626 #define MAC_TX_MODE 0x0000045c
627 #define TX_MODE_RESET 0x00000001
628 #define TX_MODE_ENABLE 0x00000002
629 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
630 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
631 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
632 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
633 #define TX_MODE_JMB_FRM_LEN 0x00400000
634 #define TX_MODE_CNT_DN_MODE 0x00800000
635 #define MAC_TX_STATUS 0x00000460
636 #define TX_STATUS_XOFFED 0x00000001
637 #define TX_STATUS_SENT_XOFF 0x00000002
638 #define TX_STATUS_SENT_XON 0x00000004
639 #define TX_STATUS_LINK_UP 0x00000008
640 #define TX_STATUS_ODI_UNDERRUN 0x00000010
641 #define TX_STATUS_ODI_OVERRUN 0x00000020
642 #define MAC_TX_LENGTHS 0x00000464
643 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
644 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
645 #define TX_LENGTHS_IPG_MASK 0x00000f00
646 #define TX_LENGTHS_IPG_SHIFT 8
647 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
648 #define TX_LENGTHS_IPG_CRS_SHIFT 12
649 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
650 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
651 #define MAC_RX_MODE 0x00000468
652 #define RX_MODE_RESET 0x00000001
653 #define RX_MODE_ENABLE 0x00000002
654 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
655 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
656 #define RX_MODE_KEEP_PAUSE 0x00000010
657 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
658 #define RX_MODE_ACCEPT_RUNTS 0x00000040
659 #define RX_MODE_LEN_CHECK 0x00000080
660 #define RX_MODE_PROMISC 0x00000100
661 #define RX_MODE_NO_CRC_CHECK 0x00000200
662 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
663 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
664 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
665 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
666 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
667 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
668 #define RX_MODE_RSS_ENABLE 0x00800000
669 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
670 #define MAC_RX_STATUS 0x0000046c
671 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
672 #define RX_STATUS_XOFF_RCVD 0x00000002
673 #define RX_STATUS_XON_RCVD 0x00000004
674 #define MAC_HASH_REG_0 0x00000470
675 #define MAC_HASH_REG_1 0x00000474
676 #define MAC_HASH_REG_2 0x00000478
677 #define MAC_HASH_REG_3 0x0000047c
678 #define MAC_RCV_RULE_0 0x00000480
679 #define MAC_RCV_VALUE_0 0x00000484
680 #define MAC_RCV_RULE_1 0x00000488
681 #define MAC_RCV_VALUE_1 0x0000048c
682 #define MAC_RCV_RULE_2 0x00000490
683 #define MAC_RCV_VALUE_2 0x00000494
684 #define MAC_RCV_RULE_3 0x00000498
685 #define MAC_RCV_VALUE_3 0x0000049c
686 #define MAC_RCV_RULE_4 0x000004a0
687 #define MAC_RCV_VALUE_4 0x000004a4
688 #define MAC_RCV_RULE_5 0x000004a8
689 #define MAC_RCV_VALUE_5 0x000004ac
690 #define MAC_RCV_RULE_6 0x000004b0
691 #define MAC_RCV_VALUE_6 0x000004b4
692 #define MAC_RCV_RULE_7 0x000004b8
693 #define MAC_RCV_VALUE_7 0x000004bc
694 #define MAC_RCV_RULE_8 0x000004c0
695 #define MAC_RCV_VALUE_8 0x000004c4
696 #define MAC_RCV_RULE_9 0x000004c8
697 #define MAC_RCV_VALUE_9 0x000004cc
698 #define MAC_RCV_RULE_10 0x000004d0
699 #define MAC_RCV_VALUE_10 0x000004d4
700 #define MAC_RCV_RULE_11 0x000004d8
701 #define MAC_RCV_VALUE_11 0x000004dc
702 #define MAC_RCV_RULE_12 0x000004e0
703 #define MAC_RCV_VALUE_12 0x000004e4
704 #define MAC_RCV_RULE_13 0x000004e8
705 #define MAC_RCV_VALUE_13 0x000004ec
706 #define MAC_RCV_RULE_14 0x000004f0
707 #define MAC_RCV_VALUE_14 0x000004f4
708 #define MAC_RCV_RULE_15 0x000004f8
709 #define MAC_RCV_VALUE_15 0x000004fc
710 #define RCV_RULE_DISABLE_MASK 0x7fffffff
711 #define MAC_RCV_RULE_CFG 0x00000500
712 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
713 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
714 /* 0x508 --> 0x520 unused */
715 #define MAC_HASHREGU_0 0x00000520
716 #define MAC_HASHREGU_1 0x00000524
717 #define MAC_HASHREGU_2 0x00000528
718 #define MAC_HASHREGU_3 0x0000052c
719 #define MAC_EXTADDR_0_HIGH 0x00000530
720 #define MAC_EXTADDR_0_LOW 0x00000534
721 #define MAC_EXTADDR_1_HIGH 0x00000538
722 #define MAC_EXTADDR_1_LOW 0x0000053c
723 #define MAC_EXTADDR_2_HIGH 0x00000540
724 #define MAC_EXTADDR_2_LOW 0x00000544
725 #define MAC_EXTADDR_3_HIGH 0x00000548
726 #define MAC_EXTADDR_3_LOW 0x0000054c
727 #define MAC_EXTADDR_4_HIGH 0x00000550
728 #define MAC_EXTADDR_4_LOW 0x00000554
729 #define MAC_EXTADDR_5_HIGH 0x00000558
730 #define MAC_EXTADDR_5_LOW 0x0000055c
731 #define MAC_EXTADDR_6_HIGH 0x00000560
732 #define MAC_EXTADDR_6_LOW 0x00000564
733 #define MAC_EXTADDR_7_HIGH 0x00000568
734 #define MAC_EXTADDR_7_LOW 0x0000056c
735 #define MAC_EXTADDR_8_HIGH 0x00000570
736 #define MAC_EXTADDR_8_LOW 0x00000574
737 #define MAC_EXTADDR_9_HIGH 0x00000578
738 #define MAC_EXTADDR_9_LOW 0x0000057c
739 #define MAC_EXTADDR_10_HIGH 0x00000580
740 #define MAC_EXTADDR_10_LOW 0x00000584
741 #define MAC_EXTADDR_11_HIGH 0x00000588
742 #define MAC_EXTADDR_11_LOW 0x0000058c
743 #define MAC_SERDES_CFG 0x00000590
744 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
745 #define MAC_SERDES_STAT 0x00000594
746 /* 0x598 --> 0x5a0 unused */
747 #define MAC_PHYCFG1 0x000005a0
748 #define MAC_PHYCFG1_RGMII_INT 0x00000001
749 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
750 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
751 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
752 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
753 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
754 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
755 #define MAC_PHYCFG1_TXC_DRV 0x20000000
756 #define MAC_PHYCFG2 0x000005a4
757 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
758 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
759 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
760 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
761 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
762 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
763 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
764 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
765 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
766 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
767 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
768 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
769 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
770 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
771 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
772 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
773 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
774 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
775 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
776 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
777 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
778 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
779 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
780 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
781 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
782 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
783 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
784 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
785 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
786 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
787 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
788 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
789 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
790 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
791 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
792 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
793 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
794 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
795 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
796 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
797 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
798 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
799 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
800 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
801 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
802 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
803 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
804 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
805 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
806 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
807 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
808 #define MAC_PHYCFG2_50610_LED_MODES \
809  (MAC_PHYCFG2_EMODE_MASK_50610 | \
810  MAC_PHYCFG2_EMODE_COMP_50610 | \
811  MAC_PHYCFG2_FMODE_MASK_50610 | \
812  MAC_PHYCFG2_FMODE_COMP_50610 | \
813  MAC_PHYCFG2_GMODE_MASK_50610 | \
814  MAC_PHYCFG2_GMODE_COMP_50610 | \
815  MAC_PHYCFG2_ACT_MASK_50610 | \
816  MAC_PHYCFG2_ACT_COMP_50610 | \
817  MAC_PHYCFG2_QUAL_MASK_50610 | \
818  MAC_PHYCFG2_QUAL_COMP_50610)
819 #define MAC_PHYCFG2_AC131_LED_MODES \
820  (MAC_PHYCFG2_EMODE_MASK_AC131 | \
821  MAC_PHYCFG2_EMODE_COMP_AC131 | \
822  MAC_PHYCFG2_FMODE_MASK_AC131 | \
823  MAC_PHYCFG2_FMODE_COMP_AC131 | \
824  MAC_PHYCFG2_GMODE_MASK_AC131 | \
825  MAC_PHYCFG2_GMODE_COMP_AC131 | \
826  MAC_PHYCFG2_ACT_MASK_AC131 | \
827  MAC_PHYCFG2_ACT_COMP_AC131 | \
828  MAC_PHYCFG2_QUAL_MASK_AC131 | \
829  MAC_PHYCFG2_QUAL_COMP_AC131)
830 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
831  (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
832  MAC_PHYCFG2_EMODE_COMP_RT8211 | \
833  MAC_PHYCFG2_FMODE_MASK_RT8211 | \
834  MAC_PHYCFG2_FMODE_COMP_RT8211 | \
835  MAC_PHYCFG2_GMODE_MASK_RT8211 | \
836  MAC_PHYCFG2_GMODE_COMP_RT8211 | \
837  MAC_PHYCFG2_ACT_MASK_RT8211 | \
838  MAC_PHYCFG2_ACT_COMP_RT8211 | \
839  MAC_PHYCFG2_QUAL_MASK_RT8211 | \
840  MAC_PHYCFG2_QUAL_COMP_RT8211)
841 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
842  (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
843  MAC_PHYCFG2_EMODE_COMP_RT8201 | \
844  MAC_PHYCFG2_FMODE_MASK_RT8201 | \
845  MAC_PHYCFG2_FMODE_COMP_RT8201 | \
846  MAC_PHYCFG2_GMODE_MASK_RT8201 | \
847  MAC_PHYCFG2_GMODE_COMP_RT8201 | \
848  MAC_PHYCFG2_ACT_MASK_RT8201 | \
849  MAC_PHYCFG2_ACT_COMP_RT8201 | \
850  MAC_PHYCFG2_QUAL_MASK_RT8201 | \
851  MAC_PHYCFG2_QUAL_COMP_RT8201)
852 #define MAC_EXT_RGMII_MODE 0x000005a8
853 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001
854 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
855 #define MAC_RGMII_MODE_TX_RESET 0x00000004
856 #define MAC_RGMII_MODE_RX_INT_B 0x00000100
857 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200
858 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
859 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
860 /* 0x5ac --> 0x5b0 unused */
861 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
862 #define SERDES_RX_SIG_DETECT 0x00000400
863 #define SG_DIG_CTRL 0x000005b0
864 #define SG_DIG_USING_HW_AUTONEG 0x80000000
865 #define SG_DIG_SOFT_RESET 0x40000000
866 #define SG_DIG_DISABLE_LINKRDY 0x20000000
867 #define SG_DIG_CRC16_CLEAR_N 0x01000000
868 #define SG_DIG_EN10B 0x00800000
869 #define SG_DIG_CLEAR_STATUS 0x00400000
870 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
871 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
872 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
873 #define SG_DIG_SPEED_STATUS_SHIFT 18
874 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
875 #define SG_DIG_RESTART_AUTONEG 0x00010000
876 #define SG_DIG_FIBER_MODE 0x00008000
877 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
878 #define SG_DIG_PAUSE_MASK 0x00001800
879 #define SG_DIG_PAUSE_CAP 0x00000800
880 #define SG_DIG_ASYM_PAUSE 0x00001000
881 #define SG_DIG_GBIC_ENABLE 0x00000400
882 #define SG_DIG_CHECK_END_ENABLE 0x00000200
883 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
884 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
885 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
886 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
887 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
888 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
889 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
890 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
891 #define SG_DIG_LOOPBACK 0x00000001
892 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
893  SG_DIG_LOCAL_DUPLEX_STATUS | \
894  SG_DIG_LOCAL_LINK_STATUS | \
895  (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
896  SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
897 #define SG_DIG_STATUS 0x000005b4
898 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
899 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
900 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
901 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
902 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
903 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
904 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
905 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
906 #define SG_DIG_IS_SERDES 0x00000100
907 #define SG_DIG_COMMA_DETECTOR 0x00000008
908 #define SG_DIG_MAC_ACK_STATUS 0x00000004
909 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
910 #define SG_DIG_AUTONEG_ERROR 0x00000001
911 /* 0x5b8 --> 0x600 unused */
912 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
913 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
914 /* 0x624 --> 0x670 unused */
915 
916 #define MAC_RSS_INDIR_TBL_0 0x00000630
917 
918 #define MAC_RSS_HASH_KEY_0 0x00000670
919 #define MAC_RSS_HASH_KEY_1 0x00000674
920 #define MAC_RSS_HASH_KEY_2 0x00000678
921 #define MAC_RSS_HASH_KEY_3 0x0000067c
922 #define MAC_RSS_HASH_KEY_4 0x00000680
923 #define MAC_RSS_HASH_KEY_5 0x00000684
924 #define MAC_RSS_HASH_KEY_6 0x00000688
925 #define MAC_RSS_HASH_KEY_7 0x0000068c
926 #define MAC_RSS_HASH_KEY_8 0x00000690
927 #define MAC_RSS_HASH_KEY_9 0x00000694
928 /* 0x698 --> 0x800 unused */
929 
930 #define MAC_TX_STATS_OCTETS 0x00000800
931 #define MAC_TX_STATS_RESV1 0x00000804
932 #define MAC_TX_STATS_COLLISIONS 0x00000808
933 #define MAC_TX_STATS_XON_SENT 0x0000080c
934 #define MAC_TX_STATS_XOFF_SENT 0x00000810
935 #define MAC_TX_STATS_RESV2 0x00000814
936 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
937 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
938 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
939 #define MAC_TX_STATS_DEFERRED 0x00000824
940 #define MAC_TX_STATS_RESV3 0x00000828
941 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
942 #define MAC_TX_STATS_LATE_COL 0x00000830
943 #define MAC_TX_STATS_RESV4_1 0x00000834
944 #define MAC_TX_STATS_RESV4_2 0x00000838
945 #define MAC_TX_STATS_RESV4_3 0x0000083c
946 #define MAC_TX_STATS_RESV4_4 0x00000840
947 #define MAC_TX_STATS_RESV4_5 0x00000844
948 #define MAC_TX_STATS_RESV4_6 0x00000848
949 #define MAC_TX_STATS_RESV4_7 0x0000084c
950 #define MAC_TX_STATS_RESV4_8 0x00000850
951 #define MAC_TX_STATS_RESV4_9 0x00000854
952 #define MAC_TX_STATS_RESV4_10 0x00000858
953 #define MAC_TX_STATS_RESV4_11 0x0000085c
954 #define MAC_TX_STATS_RESV4_12 0x00000860
955 #define MAC_TX_STATS_RESV4_13 0x00000864
956 #define MAC_TX_STATS_RESV4_14 0x00000868
957 #define MAC_TX_STATS_UCAST 0x0000086c
958 #define MAC_TX_STATS_MCAST 0x00000870
959 #define MAC_TX_STATS_BCAST 0x00000874
960 #define MAC_TX_STATS_RESV5_1 0x00000878
961 #define MAC_TX_STATS_RESV5_2 0x0000087c
962 #define MAC_RX_STATS_OCTETS 0x00000880
963 #define MAC_RX_STATS_RESV1 0x00000884
964 #define MAC_RX_STATS_FRAGMENTS 0x00000888
965 #define MAC_RX_STATS_UCAST 0x0000088c
966 #define MAC_RX_STATS_MCAST 0x00000890
967 #define MAC_RX_STATS_BCAST 0x00000894
968 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
969 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
970 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
971 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
972 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
973 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
974 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
975 #define MAC_RX_STATS_JABBERS 0x000008b4
976 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
977 /* 0x8bc --> 0xc00 unused */
978 
979 /* Send data initiator control registers */
980 #define SNDDATAI_MODE 0x00000c00
981 #define SNDDATAI_MODE_RESET 0x00000001
982 #define SNDDATAI_MODE_ENABLE 0x00000002
983 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
984 #define SNDDATAI_STATUS 0x00000c04
985 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
986 #define SNDDATAI_STATSCTRL 0x00000c08
987 #define SNDDATAI_SCTRL_ENABLE 0x00000001
988 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
989 #define SNDDATAI_SCTRL_CLEAR 0x00000004
990 #define SNDDATAI_SCTRL_FLUSH 0x00000008
991 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
992 #define SNDDATAI_STATSENAB 0x00000c0c
993 #define SNDDATAI_STATSINCMASK 0x00000c10
994 #define ISO_PKT_TX 0x00000c20
995 /* 0xc24 --> 0xc80 unused */
996 #define SNDDATAI_COS_CNT_0 0x00000c80
997 #define SNDDATAI_COS_CNT_1 0x00000c84
998 #define SNDDATAI_COS_CNT_2 0x00000c88
999 #define SNDDATAI_COS_CNT_3 0x00000c8c
1000 #define SNDDATAI_COS_CNT_4 0x00000c90
1001 #define SNDDATAI_COS_CNT_5 0x00000c94
1002 #define SNDDATAI_COS_CNT_6 0x00000c98
1003 #define SNDDATAI_COS_CNT_7 0x00000c9c
1004 #define SNDDATAI_COS_CNT_8 0x00000ca0
1005 #define SNDDATAI_COS_CNT_9 0x00000ca4
1006 #define SNDDATAI_COS_CNT_10 0x00000ca8
1007 #define SNDDATAI_COS_CNT_11 0x00000cac
1008 #define SNDDATAI_COS_CNT_12 0x00000cb0
1009 #define SNDDATAI_COS_CNT_13 0x00000cb4
1010 #define SNDDATAI_COS_CNT_14 0x00000cb8
1011 #define SNDDATAI_COS_CNT_15 0x00000cbc
1012 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
1013 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
1014 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
1015 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
1016 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
1017 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
1018 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
1019 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
1020 /* 0xce0 --> 0x1000 unused */
1021 
1022 /* Send data completion control registers */
1023 #define SNDDATAC_MODE 0x00001000
1024 #define SNDDATAC_MODE_RESET 0x00000001
1025 #define SNDDATAC_MODE_ENABLE 0x00000002
1026 #define SNDDATAC_MODE_CDELAY 0x00000010
1027 /* 0x1004 --> 0x1400 unused */
1028 
1029 /* Send BD ring selector */
1030 #define SNDBDS_MODE 0x00001400
1031 #define SNDBDS_MODE_RESET 0x00000001
1032 #define SNDBDS_MODE_ENABLE 0x00000002
1033 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
1034 #define SNDBDS_STATUS 0x00001404
1035 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
1036 #define SNDBDS_HWDIAG 0x00001408
1037 /* 0x140c --> 0x1440 */
1038 #define SNDBDS_SEL_CON_IDX_0 0x00001440
1039 #define SNDBDS_SEL_CON_IDX_1 0x00001444
1040 #define SNDBDS_SEL_CON_IDX_2 0x00001448
1041 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
1042 #define SNDBDS_SEL_CON_IDX_4 0x00001450
1043 #define SNDBDS_SEL_CON_IDX_5 0x00001454
1044 #define SNDBDS_SEL_CON_IDX_6 0x00001458
1045 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
1046 #define SNDBDS_SEL_CON_IDX_8 0x00001460
1047 #define SNDBDS_SEL_CON_IDX_9 0x00001464
1048 #define SNDBDS_SEL_CON_IDX_10 0x00001468
1049 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
1050 #define SNDBDS_SEL_CON_IDX_12 0x00001470
1051 #define SNDBDS_SEL_CON_IDX_13 0x00001474
1052 #define SNDBDS_SEL_CON_IDX_14 0x00001478
1053 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
1054 /* 0x1480 --> 0x1800 unused */
1055 
1056 /* Send BD initiator control registers */
1057 #define SNDBDI_MODE 0x00001800
1058 #define SNDBDI_MODE_RESET 0x00000001
1059 #define SNDBDI_MODE_ENABLE 0x00000002
1060 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
1061 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
1062 #define SNDBDI_STATUS 0x00001804
1063 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
1064 #define SNDBDI_IN_PROD_IDX_0 0x00001808
1065 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
1066 #define SNDBDI_IN_PROD_IDX_2 0x00001810
1067 #define SNDBDI_IN_PROD_IDX_3 0x00001814
1068 #define SNDBDI_IN_PROD_IDX_4 0x00001818
1069 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
1070 #define SNDBDI_IN_PROD_IDX_6 0x00001820
1071 #define SNDBDI_IN_PROD_IDX_7 0x00001824
1072 #define SNDBDI_IN_PROD_IDX_8 0x00001828
1073 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
1074 #define SNDBDI_IN_PROD_IDX_10 0x00001830
1075 #define SNDBDI_IN_PROD_IDX_11 0x00001834
1076 #define SNDBDI_IN_PROD_IDX_12 0x00001838
1077 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
1078 #define SNDBDI_IN_PROD_IDX_14 0x00001840
1079 #define SNDBDI_IN_PROD_IDX_15 0x00001844
1080 /* 0x1848 --> 0x1c00 unused */
1081 
1082 /* Send BD completion control registers */
1083 #define SNDBDC_MODE 0x00001c00
1084 #define SNDBDC_MODE_RESET 0x00000001
1085 #define SNDBDC_MODE_ENABLE 0x00000002
1086 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
1087 /* 0x1c04 --> 0x2000 unused */
1088 
1089 /* Receive list placement control registers */
1090 #define RCVLPC_MODE 0x00002000
1091 #define RCVLPC_MODE_RESET 0x00000001
1092 #define RCVLPC_MODE_ENABLE 0x00000002
1093 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
1094 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
1095 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
1096 #define RCVLPC_STATUS 0x00002004
1097 #define RCVLPC_STATUS_CLASS0 0x00000004
1098 #define RCVLPC_STATUS_MAPOOR 0x00000008
1099 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1100 #define RCVLPC_LOCK 0x00002008
1101 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1102 #define RCVLPC_LOCK_REQ_SHIFT 0
1103 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1104 #define RCVLPC_LOCK_GRANT_SHIFT 16
1105 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
1106 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1107 #define RCVLPC_CONFIG 0x00002010
1108 #define RCVLPC_STATSCTRL 0x00002014
1109 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
1110 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1111 #define RCVLPC_STATS_ENABLE 0x00002018
1112 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1113 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1114 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1115 #define RCVLPC_STATS_INCMASK 0x0000201c
1116 /* 0x2020 --> 0x2100 unused */
1117 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1118 #define SELLST_TAIL 0x00000004
1119 #define SELLST_CONT 0x00000008
1120 #define SELLST_UNUSED 0x0000000c
1121 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1122 #define RCVLPC_DROP_FILTER_CNT 0x00002240
1123 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1124 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1125 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1126 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
1127 #define RCVLPC_IN_ERRORS_CNT 0x00002254
1128 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1129 /* 0x225c --> 0x2400 unused */
1130 
1131 /* Receive Data and Receive BD Initiator Control */
1132 #define RCVDBDI_MODE 0x00002400
1133 #define RCVDBDI_MODE_RESET 0x00000001
1134 #define RCVDBDI_MODE_ENABLE 0x00000002
1135 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1136 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1137 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1138 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1139 #define RCVDBDI_STATUS 0x00002404
1140 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1141 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1142 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1143 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1144 /* 0x240c --> 0x2440 unused */
1145 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1146 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1147 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1148 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
1149 #define RCVDBDI_STD_CON_IDX 0x00002474
1150 #define RCVDBDI_MINI_CON_IDX 0x00002478
1151 /* 0x247c --> 0x2480 unused */
1152 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
1153 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
1154 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
1155 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1156 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
1157 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
1158 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
1159 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1160 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1161 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1162 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1163 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1164 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1165 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1166 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1167 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1168 #define RCVDBDI_HWDIAG 0x000024c0
1169 /* 0x24c4 --> 0x2800 unused */
1170 
1171 /* Receive Data Completion Control */
1172 #define RCVDCC_MODE 0x00002800
1173 #define RCVDCC_MODE_RESET 0x00000001
1174 #define RCVDCC_MODE_ENABLE 0x00000002
1175 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1176 /* 0x2804 --> 0x2c00 unused */
1177 
1178 /* Receive BD Initiator Control Registers */
1179 #define RCVBDI_MODE 0x00002c00
1180 #define RCVBDI_MODE_RESET 0x00000001
1181 #define RCVBDI_MODE_ENABLE 0x00000002
1182 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1183 #define RCVBDI_STATUS 0x00002c04
1184 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
1185 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1186 #define RCVBDI_STD_PROD_IDX 0x00002c0c
1187 #define RCVBDI_MINI_PROD_IDX 0x00002c10
1188 #define RCVBDI_MINI_THRESH 0x00002c14
1189 #define RCVBDI_STD_THRESH 0x00002c18
1190 #define RCVBDI_JUMBO_THRESH 0x00002c1c
1191 /* 0x2c20 --> 0x2d00 unused */
1192 
1193 #define STD_REPLENISH_LWM 0x00002d00
1194 #define JMB_REPLENISH_LWM 0x00002d04
1195 /* 0x2d08 --> 0x3000 unused */
1196 
1197 /* Receive BD Completion Control Registers */
1198 #define RCVCC_MODE 0x00003000
1199 #define RCVCC_MODE_RESET 0x00000001
1200 #define RCVCC_MODE_ENABLE 0x00000002
1201 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
1202 #define RCVCC_STATUS 0x00003004
1203 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
1204 #define RCVCC_JUMP_PROD_IDX 0x00003008
1205 #define RCVCC_STD_PROD_IDX 0x0000300c
1206 #define RCVCC_MINI_PROD_IDX 0x00003010
1207 /* 0x3014 --> 0x3400 unused */
1208 
1209 /* Receive list selector control registers */
1210 #define RCVLSC_MODE 0x00003400
1211 #define RCVLSC_MODE_RESET 0x00000001
1212 #define RCVLSC_MODE_ENABLE 0x00000002
1213 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1214 #define RCVLSC_STATUS 0x00003404
1215 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1216 /* 0x3408 --> 0x3600 unused */
1217 
1218 /* CPMU registers */
1219 #define TG3_CPMU_CTRL 0x00003600
1220 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1221 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1222 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1223 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1224 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1225 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1226 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1227 /* 0x3608 --> 0x360c unused */
1228 
1229 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1230 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1231 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1232 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1233 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1234 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1235 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1236 
1237 #define TG3_CPMU_D0_CLCK_POLICY 0x00003614
1238 /* 0x3614 --> 0x361c unused */
1239 
1240 #define TG3_CPMU_HST_ACC 0x0000361c
1241 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1242 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1243 /* 0x3620 --> 0x3630 unused */
1244 
1245 #define TG3_CPMU_CLCK_ORIDE 0x00003624
1246 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1247 
1248 #define TG3_CPMU_CLCK_ORIDE_EN 0x00003628
1249 #define CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN 0x00002000
1250 
1251 #define TG3_CPMU_CLCK_STAT 0x00003630
1252 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1253 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1254 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1255 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1256 /* 0x3634 --> 0x365c unused */
1257 
1258 #define TG3_CPMU_MUTEX_REQ 0x0000365c
1259 #define CPMU_MUTEX_REQ_DRIVER 0x00001000
1260 #define TG3_CPMU_MUTEX_GNT 0x00003660
1261 #define CPMU_MUTEX_GNT_DRIVER 0x00001000
1262 #define TG3_CPMU_PHY_STRAP 0x00003664
1263 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1264 /* 0x3664 --> 0x36b0 unused */
1265 
1266 #define TG3_CPMU_EEE_MODE 0x000036b0
1267 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1268 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1269 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1270 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1271 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1272 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1273 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1274 #define TG3_CPMU_EEE_DBTMR1 0x000036b4
1275 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1276 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000070ff
1277 #define TG3_CPMU_EEE_DBTMR2 0x000036b8
1278 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1279 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000070ff
1280 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1281 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1282 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1283 /* 0x36c0 --> 0x36d0 unused */
1284 
1285 #define TG3_CPMU_EEE_CTRL 0x000036d0
1286 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1287 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1288 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1289 /* 0x36d4 --> 0x3800 unused */
1290 
1291 /* Mbuf cluster free registers */
1292 #define MBFREE_MODE 0x00003800
1293 #define MBFREE_MODE_RESET 0x00000001
1294 #define MBFREE_MODE_ENABLE 0x00000002
1295 #define MBFREE_STATUS 0x00003804
1296 /* 0x3808 --> 0x3c00 unused */
1297 
1298 /* Host coalescing control registers */
1299 #define HOSTCC_MODE 0x00003c00
1300 #define HOSTCC_MODE_RESET 0x00000001
1301 #define HOSTCC_MODE_ENABLE 0x00000002
1302 #define HOSTCC_MODE_ATTN 0x00000004
1303 #define HOSTCC_MODE_NOW 0x00000008
1304 #define HOSTCC_MODE_FULL_STATUS 0x00000000
1305 #define HOSTCC_MODE_64BYTE 0x00000080
1306 #define HOSTCC_MODE_32BYTE 0x00000100
1307 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1308 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1309 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1310 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1311 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1312 #define HOSTCC_STATUS 0x00003c04
1313 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1314 #define HOSTCC_RXCOL_TICKS 0x00003c08
1315 #define LOW_RXCOL_TICKS 0x00000032
1316 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1317 #define DEFAULT_RXCOL_TICKS 0x00000048
1318 #define HIGH_RXCOL_TICKS 0x00000096
1319 #define MAX_RXCOL_TICKS 0x000003ff
1320 #define HOSTCC_TXCOL_TICKS 0x00003c0c
1321 #define LOW_TXCOL_TICKS 0x00000096
1322 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1323 #define DEFAULT_TXCOL_TICKS 0x0000012c
1324 #define HIGH_TXCOL_TICKS 0x00000145
1325 #define MAX_TXCOL_TICKS 0x000003ff
1326 #define HOSTCC_RXMAX_FRAMES 0x00003c10
1327 #define LOW_RXMAX_FRAMES 0x00000005
1328 #define DEFAULT_RXMAX_FRAMES 0x00000008
1329 #define HIGH_RXMAX_FRAMES 0x00000012
1330 #define MAX_RXMAX_FRAMES 0x000000ff
1331 #define HOSTCC_TXMAX_FRAMES 0x00003c14
1332 #define LOW_TXMAX_FRAMES 0x00000035
1333 #define DEFAULT_TXMAX_FRAMES 0x0000004b
1334 #define HIGH_TXMAX_FRAMES 0x00000052
1335 #define MAX_TXMAX_FRAMES 0x000000ff
1336 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1337 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
1338 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1339 #define MAX_RXCOAL_TICK_INT 0x000003ff
1340 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1341 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
1342 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1343 #define MAX_TXCOAL_TICK_INT 0x000003ff
1344 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1345 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1346 #define MAX_RXCOAL_MAXF_INT 0x000000ff
1347 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1348 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1349 #define MAX_TXCOAL_MAXF_INT 0x000000ff
1350 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
1351 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
1352 #define MAX_STAT_COAL_TICKS 0xd693d400
1353 #define MIN_STAT_COAL_TICKS 0x00000064
1354 /* 0x3c2c --> 0x3c30 unused */
1355 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1356 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1357 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1358 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1359 #define HOSTCC_FLOW_ATTN 0x00003c48
1360 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1361 /* 0x3c4c --> 0x3c50 unused */
1362 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
1363 #define HOSTCC_STD_CON_IDX 0x00003c54
1364 #define HOSTCC_MINI_CON_IDX 0x00003c58
1365 /* 0x3c5c --> 0x3c80 unused */
1366 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
1367 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
1368 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
1369 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1370 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
1371 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
1372 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
1373 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1374 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1375 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1376 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1377 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
1378 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1379 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1380 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1381 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1382 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
1383 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
1384 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
1385 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
1386 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
1387 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
1388 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
1389 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
1390 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
1391 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
1392 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
1393 #define HOSTCC_SND_CON_IDX_11 0x00003cec
1394 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
1395 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
1396 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
1397 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
1398 #define HOSTCC_STATBLCK_RING1 0x00003d00
1399 /* 0x3d00 --> 0x3d80 unused */
1400 
1401 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1402 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1403 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1404 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1405 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1406 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1407 /* 0x3d98 --> 0x4000 unused */
1408 
1409 /* Memory arbiter control registers */
1410 #define MEMARB_MODE 0x00004000
1411 #define MEMARB_MODE_RESET 0x00000001
1412 #define MEMARB_MODE_ENABLE 0x00000002
1413 #define MEMARB_STATUS 0x00004004
1414 #define MEMARB_TRAP_ADDR_LOW 0x00004008
1415 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1416 /* 0x4010 --> 0x4400 unused */
1417 
1418 /* Buffer manager control registers */
1419 #define BUFMGR_MODE 0x00004400
1420 #define BUFMGR_MODE_RESET 0x00000001
1421 #define BUFMGR_MODE_ENABLE 0x00000002
1422 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1423 #define BUFMGR_MODE_BM_TEST 0x00000008
1424 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1425 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1426 #define BUFMGR_STATUS 0x00004404
1427 #define BUFMGR_STATUS_ERROR 0x00000004
1428 #define BUFMGR_STATUS_MBLOW 0x00000010
1429 #define BUFMGR_MB_POOL_ADDR 0x00004408
1430 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1431 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1432 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1433 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1434 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1435 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1436 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1437 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1438 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1439 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1440 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1441 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1442 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1443 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1444 #define BUFMGR_MB_HIGH_WATER 0x00004418
1445 #define DEFAULT_MB_HIGH_WATER 0x00000060
1446 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1447 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1448 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1449 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1450 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1451 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1452 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1453 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1454 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1455 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1456 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1457 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1458 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1459 #define BUFMGR_DMA_LOW_WATER 0x00004434
1460 #define DEFAULT_DMA_LOW_WATER 0x00000005
1461 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1462 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1463 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1464 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1465 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1466 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1467 #define BUFMGR_HWDIAG_0 0x0000444c
1468 #define BUFMGR_HWDIAG_1 0x00004450
1469 #define BUFMGR_HWDIAG_2 0x00004454
1470 /* 0x4458 --> 0x4800 unused */
1471 
1472 /* Read DMA control registers */
1473 #define RDMAC_MODE 0x00004800
1474 #define RDMAC_MODE_RESET 0x00000001
1475 #define RDMAC_MODE_ENABLE 0x00000002
1476 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1477 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1478 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1479 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1480 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1481 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1482 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1483 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1484 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1485 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1486 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1487 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1488 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1489 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1490 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1491 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1492 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1493 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1494 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1495 #define RDMAC_STATUS 0x00004804
1496 #define RDMAC_STATUS_TGTABORT 0x00000004
1497 #define RDMAC_STATUS_MSTABORT 0x00000008
1498 #define RDMAC_STATUS_PARITYERR 0x00000010
1499 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1500 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1501 #define RDMAC_STATUS_FIFOURUN 0x00000080
1502 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1503 #define RDMAC_STATUS_LNGREAD 0x00000200
1504 /* 0x4808 --> 0x4900 unused */
1505 
1506 #define TG3_RDMA_RSRVCTRL_REG 0x00004900
1507 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1508 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1509 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1510 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1511 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1512 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1513 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1514 /* 0x4904 --> 0x4910 unused */
1515 
1516 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1517 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1518 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1519 /* 0x4914 --> 0x4c00 unused */
1520 
1521 /* Write DMA control registers */
1522 #define WDMAC_MODE 0x00004c00
1523 #define WDMAC_MODE_RESET 0x00000001
1524 #define WDMAC_MODE_ENABLE 0x00000002
1525 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1526 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1527 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1528 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1529 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1530 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1531 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1532 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1533 #define WDMAC_MODE_RX_ACCEL 0x00000400
1534 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1535 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1536 #define WDMAC_STATUS 0x00004c04
1537 #define WDMAC_STATUS_TGTABORT 0x00000004
1538 #define WDMAC_STATUS_MSTABORT 0x00000008
1539 #define WDMAC_STATUS_PARITYERR 0x00000010
1540 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1541 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1542 #define WDMAC_STATUS_FIFOURUN 0x00000080
1543 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1544 #define WDMAC_STATUS_LNGREAD 0x00000200
1545 /* 0x4c08 --> 0x5000 unused */
1546 
1547 /* Per-cpu register offsets (arm9) */
1548 #define CPU_MODE 0x00000000
1549 #define CPU_MODE_RESET 0x00000001
1550 #define CPU_MODE_HALT 0x00000400
1551 #define CPU_STATE 0x00000004
1552 #define CPU_EVTMASK 0x00000008
1553 /* 0xc --> 0x1c reserved */
1554 #define CPU_PC 0x0000001c
1555 #define CPU_INSN 0x00000020
1556 #define CPU_SPAD_UFLOW 0x00000024
1557 #define CPU_WDOG_CLEAR 0x00000028
1558 #define CPU_WDOG_VECTOR 0x0000002c
1559 #define CPU_WDOG_PC 0x00000030
1560 #define CPU_HW_BP 0x00000034
1561 /* 0x38 --> 0x44 unused */
1562 #define CPU_WDOG_SAVED_STATE 0x00000044
1563 #define CPU_LAST_BRANCH_ADDR 0x00000048
1564 #define CPU_SPAD_UFLOW_SET 0x0000004c
1565 /* 0x50 --> 0x200 unused */
1566 #define CPU_R0 0x00000200
1567 #define CPU_R1 0x00000204
1568 #define CPU_R2 0x00000208
1569 #define CPU_R3 0x0000020c
1570 #define CPU_R4 0x00000210
1571 #define CPU_R5 0x00000214
1572 #define CPU_R6 0x00000218
1573 #define CPU_R7 0x0000021c
1574 #define CPU_R8 0x00000220
1575 #define CPU_R9 0x00000224
1576 #define CPU_R10 0x00000228
1577 #define CPU_R11 0x0000022c
1578 #define CPU_R12 0x00000230
1579 #define CPU_R13 0x00000234
1580 #define CPU_R14 0x00000238
1581 #define CPU_R15 0x0000023c
1582 #define CPU_R16 0x00000240
1583 #define CPU_R17 0x00000244
1584 #define CPU_R18 0x00000248
1585 #define CPU_R19 0x0000024c
1586 #define CPU_R20 0x00000250
1587 #define CPU_R21 0x00000254
1588 #define CPU_R22 0x00000258
1589 #define CPU_R23 0x0000025c
1590 #define CPU_R24 0x00000260
1591 #define CPU_R25 0x00000264
1592 #define CPU_R26 0x00000268
1593 #define CPU_R27 0x0000026c
1594 #define CPU_R28 0x00000270
1595 #define CPU_R29 0x00000274
1596 #define CPU_R30 0x00000278
1597 #define CPU_R31 0x0000027c
1598 /* 0x280 --> 0x400 unused */
1599 
1600 #define RX_CPU_BASE 0x00005000
1601 #define RX_CPU_MODE 0x00005000
1602 #define RX_CPU_STATE 0x00005004
1603 #define RX_CPU_PGMCTR 0x0000501c
1604 #define RX_CPU_HWBKPT 0x00005034
1605 #define TX_CPU_BASE 0x00005400
1606 #define TX_CPU_MODE 0x00005400
1607 #define TX_CPU_STATE 0x00005404
1608 #define TX_CPU_PGMCTR 0x0000541c
1609 
1610 #define VCPU_STATUS 0x00005100
1611 #define VCPU_STATUS_INIT_DONE 0x04000000
1612 #define VCPU_STATUS_DRV_RESET 0x08000000
1613 
1614 #define VCPU_CFGSHDW 0x00005104
1615 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1616 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1617 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1618 
1619 /* Mailboxes */
1620 #define GRCMBOX_BASE 0x00005600
1621 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1622 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1623 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1624 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1625 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1626 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1627 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1628 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1629 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1630 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1631 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1632 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1633 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1634 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1635 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1636 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1637 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1638 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1639 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1640 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1641 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1642 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1643 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1644 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1645 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1646 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1647 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1648 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1649 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1650 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1651 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1652 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1653 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1654 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1655 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1656 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1657 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1658 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1659 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1660 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1661 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1662 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1663 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1664 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1665 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1666 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1667 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1668 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1669 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1670 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1671 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1672 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1673 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1674 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1675 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1676 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1677 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1678 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1679 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1680 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1681 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1682 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1683 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1684 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1685 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1686 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1687 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1688 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1689 /* 0x5a10 --> 0x5c00 */
1690 
1691 /* Flow Through queues */
1692 #define FTQ_RESET 0x00005c00
1693 /* 0x5c04 --> 0x5c10 unused */
1694 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1695 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1696 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1697 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1698 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1699 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1700 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1701 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1702 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1703 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1704 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1705 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1706 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1707 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1708 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1709 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1710 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1711 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1712 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1713 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1714 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1715 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1716 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1717 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1718 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1719 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1720 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1721 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1722 #define FTQ_SWTYPE1_CTL 0x00005c80
1723 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1724 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1725 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1726 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1727 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1728 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1729 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1730 #define FTQ_HOST_COAL_CTL 0x00005ca0
1731 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1732 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1733 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1734 #define FTQ_MAC_TX_CTL 0x00005cb0
1735 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1736 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1737 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1738 #define FTQ_MB_FREE_CTL 0x00005cc0
1739 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1740 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1741 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1742 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1743 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1744 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1745 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1746 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1747 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1748 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1749 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1750 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1751 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1752 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1753 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1754 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1755 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1756 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1757 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1758 #define FTQ_SWTYPE2_CTL 0x00005d10
1759 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1760 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1761 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1762 /* 0x5d20 --> 0x6000 unused */
1763 
1764 /* Message signaled interrupt registers */
1765 #define MSGINT_MODE 0x00006000
1766 #define MSGINT_MODE_RESET 0x00000001
1767 #define MSGINT_MODE_ENABLE 0x00000002
1768 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1769 #define MSGINT_MODE_MULTIVEC_EN 0x00000080
1770 #define MSGINT_STATUS 0x00006004
1771 #define MSGINT_STATUS_MSI_REQ 0x00000001
1772 #define MSGINT_FIFO 0x00006008
1773 /* 0x600c --> 0x6400 unused */
1774 
1775 /* DMA completion registers */
1776 #define DMAC_MODE 0x00006400
1777 #define DMAC_MODE_RESET 0x00000001
1778 #define DMAC_MODE_ENABLE 0x00000002
1779 /* 0x6404 --> 0x6800 unused */
1780 
1781 /* GRC registers */
1782 #define GRC_MODE 0x00006800
1783 #define GRC_MODE_UPD_ON_COAL 0x00000001
1784 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1785 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1786 #define GRC_MODE_BSWAP_DATA 0x00000010
1787 #define GRC_MODE_WSWAP_DATA 0x00000020
1788 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1789 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1790 #define GRC_MODE_SPLITHDR 0x00000100
1791 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1792 #define GRC_MODE_INCL_CRC 0x00000400
1793 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1794 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1795 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1796 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1797 #define GRC_MODE_B2HRX_ENABLE 0x00008000
1798 #define GRC_MODE_HOST_STACKUP 0x00010000
1799 #define GRC_MODE_HOST_SENDBDS 0x00020000
1800 #define GRC_MODE_HTX2B_ENABLE 0x00040000
1801 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1802 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1803 #define GRC_MODE_PCIE_TL_SEL 0x00000000
1804 #define GRC_MODE_PCIE_PL_SEL 0x00400000
1805 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1806 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1807 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1808 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1809 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1810 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1811 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1812 #define GRC_MODE_PCIE_DL_SEL 0x20000000
1813 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1814 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1815 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1816  GRC_MODE_PCIE_PL_SEL | \
1817  GRC_MODE_PCIE_DL_SEL | \
1818  GRC_MODE_PCIE_HI_1K_EN)
1819 #define GRC_MISC_CFG 0x00006804
1820 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1821 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1822 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1823 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1824 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1825 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1826 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1827 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1828 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1829 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1830 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1831 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1832 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1833 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1834 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1835 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1836 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1837 #define GRC_LOCAL_CTRL 0x00006808
1838 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1839 #define GRC_LCLCTRL_CLEARINT 0x00000002
1840 #define GRC_LCLCTRL_SETINT 0x00000004
1841 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1842 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1843 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1844 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1845 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1846 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1847 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1848 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1849 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1850 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1851 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1852 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1853 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1854 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1855 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1856 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1857 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1858 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1859 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1860 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1861 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1862 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1863 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1864 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1865 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1866 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1867 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1868 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1869 #define GRC_TIMER 0x0000680c
1870 #define GRC_RX_CPU_EVENT 0x00006810
1871 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1872 #define GRC_RX_TIMER_REF 0x00006814
1873 #define GRC_RX_CPU_SEM 0x00006818
1874 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1875 #define GRC_TX_CPU_EVENT 0x00006820
1876 #define GRC_TX_TIMER_REF 0x00006824
1877 #define GRC_TX_CPU_SEM 0x00006828
1878 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1879 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1880 #define GRC_EEPROM_ADDR 0x00006838
1881 #define EEPROM_ADDR_WRITE 0x00000000
1882 #define EEPROM_ADDR_READ 0x80000000
1883 #define EEPROM_ADDR_COMPLETE 0x40000000
1884 #define EEPROM_ADDR_FSM_RESET 0x20000000
1885 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1886 #define EEPROM_ADDR_DEVID_SHIFT 26
1887 #define EEPROM_ADDR_START 0x02000000
1888 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1889 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1890 #define EEPROM_ADDR_ADDR_SHIFT 0
1891 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1892 #define EEPROM_CHIP_SIZE (64 * 1024)
1893 #define GRC_EEPROM_DATA 0x0000683c
1894 #define GRC_EEPROM_CTRL 0x00006840
1895 #define GRC_MDI_CTRL 0x00006844
1896 #define GRC_SEEPROM_DELAY 0x00006848
1897 /* 0x684c --> 0x6890 unused */
1898 #define GRC_VCPU_EXT_CTRL 0x00006890
1899 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1900 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1901 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1902 
1903 /* 0x6c00 --> 0x7000 unused */
1904 
1905 /* NVRAM Control registers */
1906 #define NVRAM_CMD 0x00007000
1907 #define NVRAM_CMD_RESET 0x00000001
1908 #define NVRAM_CMD_DONE 0x00000008
1909 #define NVRAM_CMD_GO 0x00000010
1910 #define NVRAM_CMD_WR 0x00000020
1911 #define NVRAM_CMD_RD 0x00000000
1912 #define NVRAM_CMD_ERASE 0x00000040
1913 #define NVRAM_CMD_FIRST 0x00000080
1914 #define NVRAM_CMD_LAST 0x00000100
1915 #define NVRAM_CMD_WREN 0x00010000
1916 #define NVRAM_CMD_WRDI 0x00020000
1917 #define NVRAM_STAT 0x00007004
1918 #define NVRAM_WRDATA 0x00007008
1919 #define NVRAM_ADDR 0x0000700c
1920 #define NVRAM_ADDR_MSK 0x00ffffff
1921 #define NVRAM_RDDATA 0x00007010
1922 #define NVRAM_CFG1 0x00007014
1923 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1924 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1925 #define NVRAM_CFG1_PASS_THRU 0x00000004
1926 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1927 #define NVRAM_CFG1_BIT_BANG 0x00000008
1928 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1929 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1930 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1931 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1932 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1933 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1934 #define FLASH_VENDOR_ST 0x03000001
1935 #define FLASH_VENDOR_SAIFUN 0x01000003
1936 #define FLASH_VENDOR_SST_SMALL 0x00000001
1937 #define FLASH_VENDOR_SST_LARGE 0x02000001
1938 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1939 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1940 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1941 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1942 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1943 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1944 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1945 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1946 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1947 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1948 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1949 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1950 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1951 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1952 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1953 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1954 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1955 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1956 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1957 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1958 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1959 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1960 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1961 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1962 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1963 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1964 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1965 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1966 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1967 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1968 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1969 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1970 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1971 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1972 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1973 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1974 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1975 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1976 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1977 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1978 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1979 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1980 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1981 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1982 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1983 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1984 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1985 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1986 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1987 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1988 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1989 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1990 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1991 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1992 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1993 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1994 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1995 #define FLASH_5717VENDOR_ST_25USPT 0x03400002
1996 #define FLASH_5717VENDOR_ST_45USPT 0x03400001
1997 #define FLASH_5720_EEPROM_HD 0x00000001
1998 #define FLASH_5720_EEPROM_LD 0x00000003
1999 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
2000 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
2001 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
2002 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
2003 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
2004 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
2005 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
2006 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
2007 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
2008 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
2009 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
2010 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
2011 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
2012 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
2013 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
2014 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
2015 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
2016 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
2017 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
2018 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
2019 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
2020 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
2021 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
2022 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
2023 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
2024 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
2025 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
2026 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
2027 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002
2028 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001
2029 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
2030 #define FLASH_5752PAGE_SIZE_256 0x00000000
2031 #define FLASH_5752PAGE_SIZE_512 0x10000000
2032 #define FLASH_5752PAGE_SIZE_1K 0x20000000
2033 #define FLASH_5752PAGE_SIZE_2K 0x30000000
2034 #define FLASH_5752PAGE_SIZE_4K 0x40000000
2035 #define FLASH_5752PAGE_SIZE_264 0x50000000
2036 #define FLASH_5752PAGE_SIZE_528 0x60000000
2037 #define NVRAM_CFG2 0x00007018
2038 #define NVRAM_CFG3 0x0000701c
2039 #define NVRAM_SWARB 0x00007020
2040 #define SWARB_REQ_SET0 0x00000001
2041 #define SWARB_REQ_SET1 0x00000002
2042 #define SWARB_REQ_SET2 0x00000004
2043 #define SWARB_REQ_SET3 0x00000008
2044 #define SWARB_REQ_CLR0 0x00000010
2045 #define SWARB_REQ_CLR1 0x00000020
2046 #define SWARB_REQ_CLR2 0x00000040
2047 #define SWARB_REQ_CLR3 0x00000080
2048 #define SWARB_GNT0 0x00000100
2049 #define SWARB_GNT1 0x00000200
2050 #define SWARB_GNT2 0x00000400
2051 #define SWARB_GNT3 0x00000800
2052 #define SWARB_REQ0 0x00001000
2053 #define SWARB_REQ1 0x00002000
2054 #define SWARB_REQ2 0x00004000
2055 #define SWARB_REQ3 0x00008000
2056 #define NVRAM_ACCESS 0x00007024
2057 #define ACCESS_ENABLE 0x00000001
2058 #define ACCESS_WR_ENABLE 0x00000002
2059 #define NVRAM_WRITE1 0x00007028
2060 /* 0x702c unused */
2061 
2062 #define NVRAM_ADDR_LOCKOUT 0x00007030
2063 /* 0x7034 --> 0x7500 unused */
2064 
2065 #define OTP_MODE 0x00007500
2066 #define OTP_MODE_OTP_THRU_GRC 0x00000001
2067 #define OTP_CTRL 0x00007504
2068 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
2069 #define OTP_CTRL_OTP_CMD_READ 0x00000000
2070 #define OTP_CTRL_OTP_CMD_INIT 0x00000008
2071 #define OTP_CTRL_OTP_CMD_START 0x00000001
2072 #define OTP_STATUS 0x00007508
2073 #define OTP_STATUS_CMD_DONE 0x00000001
2074 #define OTP_ADDRESS 0x0000750c
2075 #define OTP_ADDRESS_MAGIC1 0x000000a0
2076 #define OTP_ADDRESS_MAGIC2 0x00000080
2077 /* 0x7510 unused */
2078 
2079 #define OTP_READ_DATA 0x00007514
2080 /* 0x7518 --> 0x7c04 unused */
2081 
2082 #define PCIE_TRANSACTION_CFG 0x00007c04
2083 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
2084 #define PCIE_TRANS_CFG_LOM 0x00000020
2085 /* 0x7c08 --> 0x7d28 unused */
2086 
2087 #define PCIE_PWR_MGMT_THRESH 0x00007d28
2088 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2089 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2090 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2091 /* 0x7d2c --> 0x7d54 unused */
2092 
2093 #define TG3_PCIE_LNKCTL 0x00007d54
2094 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2095 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2096 /* 0x7d58 --> 0x7e70 unused */
2097 
2098 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2099 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2100 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2101 
2102 #define TG3_PCIE_EIDLE_DELAY 0x00007e70
2103 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2104 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2105 /* 0x7e74 --> 0x8000 unused */
2106 
2107 
2108 /* Alternate PCIE definitions */
2109 #define TG3_PCIE_TLDLPL_PORT 0x00007c00
2110 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2111 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2112 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2113 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2114 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2115 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2116 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2117 
2118 #define TG3_REG_BLK_SIZE 0x00008000
2119 
2120 /* OTP bit definitions */
2121 #define TG3_OTP_AGCTGT_MASK 0x000000e0
2122 #define TG3_OTP_AGCTGT_SHIFT 1
2123 #define TG3_OTP_HPFFLTR_MASK 0x00000300
2124 #define TG3_OTP_HPFFLTR_SHIFT 1
2125 #define TG3_OTP_HPFOVER_MASK 0x00000400
2126 #define TG3_OTP_HPFOVER_SHIFT 1
2127 #define TG3_OTP_LPFDIS_MASK 0x00000800
2128 #define TG3_OTP_LPFDIS_SHIFT 11
2129 #define TG3_OTP_VDAC_MASK 0xff000000
2130 #define TG3_OTP_VDAC_SHIFT 24
2131 #define TG3_OTP_10BTAMP_MASK 0x0000f000
2132 #define TG3_OTP_10BTAMP_SHIFT 8
2133 #define TG3_OTP_ROFF_MASK 0x00e00000
2134 #define TG3_OTP_ROFF_SHIFT 11
2135 #define TG3_OTP_RCOFF_MASK 0x001c0000
2136 #define TG3_OTP_RCOFF_SHIFT 16
2137 
2138 #define TG3_OTP_DEFAULT 0x286c1640
2139 
2140 
2141 /* Hardware Legacy NVRAM layout */
2142 #define TG3_NVM_VPD_OFF 0x100
2143 #define TG3_NVM_VPD_LEN 256
2144 
2145 /* Hardware Selfboot NVRAM layout */
2146 #define TG3_NVM_HWSB_CFG1 0x00000004
2147 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2148 #define TG3_NVM_HWSB_CFG1_MAJSFT 27
2149 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2150 #define TG3_NVM_HWSB_CFG1_MINSFT 22
2151 
2152 #define TG3_EEPROM_MAGIC 0x669955aa
2153 #define TG3_EEPROM_MAGIC_FW 0xa5000000
2154 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2155 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2156 #define TG3_EEPROM_SB_FORMAT_1 0x00200000
2157 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2158 #define TG3_EEPROM_SB_REVISION_0 0x00000000
2159 #define TG3_EEPROM_SB_REVISION_2 0x00020000
2160 #define TG3_EEPROM_SB_REVISION_3 0x00030000
2161 #define TG3_EEPROM_SB_REVISION_4 0x00040000
2162 #define TG3_EEPROM_SB_REVISION_5 0x00050000
2163 #define TG3_EEPROM_SB_REVISION_6 0x00060000
2164 #define TG3_EEPROM_MAGIC_HW 0xabcd
2165 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2166 
2167 #define TG3_NVM_DIR_START 0x18
2168 #define TG3_NVM_DIR_END 0x78
2169 #define TG3_NVM_DIRENT_SIZE 0xc
2170 #define TG3_NVM_DIRTYPE_SHIFT 24
2171 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2172 #define TG3_NVM_DIRTYPE_ASFINI 1
2173 #define TG3_NVM_DIRTYPE_EXTVPD 20
2174 #define TG3_NVM_PTREV_BCVER 0x94
2175 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2176 #define TG3_NVM_BCVER_MAJSFT 8
2177 #define TG3_NVM_BCVER_MINMSK 0x000000ff
2178 
2179 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2180 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2181 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2182 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2183 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2184 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2185 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2186 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2187 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2188 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2189 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2190 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2191 
2192 
2193 /* 32K Window into NIC internal memory */
2194 #define NIC_SRAM_WIN_BASE 0x00008000
2195 
2196 /* Offsets into first 32k of NIC internal memory. */
2197 #define NIC_SRAM_PAGE_ZERO 0x00000000
2198 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
2199 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
2200 #define NIC_SRAM_STATS_BLK 0x00000300
2201 #define NIC_SRAM_STATUS_BLK 0x00000b00
2202 
2203 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2204 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2205 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
2206 
2207 #define NIC_SRAM_DATA_SIG 0x00000b54
2208 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
2209 
2210 #define NIC_SRAM_DATA_CFG 0x00000b58
2211 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2212 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2213 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2214 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2215 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2216 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2217 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2218 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2219 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2220 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2221 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2222 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2223 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2224 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2225 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2226 
2227 #define NIC_SRAM_DATA_VER 0x00000b5c
2228 #define NIC_SRAM_DATA_VER_SHIFT 16
2229 
2230 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
2231 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2232 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2233 
2234 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2235 #define FWCMD_NICDRV_ALIVE 0x00000001
2236 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
2237 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2238 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2239 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
2240 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
2241 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2242 #define FWCMD_NICDRV_ALIVE2 0x0000000d
2243 #define FWCMD_NICDRV_ALIVE3 0x0000000e
2244 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2245 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2246 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2247 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2248 #define DRV_STATE_START 0x00000001
2249 #define DRV_STATE_START_DONE 0x80000001
2250 #define DRV_STATE_UNLOAD 0x00000002
2251 #define DRV_STATE_UNLOAD_DONE 0x80000002
2252 #define DRV_STATE_WOL 0x00000003
2253 #define DRV_STATE_SUSPEND 0x00000004
2254 
2255 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2256 
2257 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2258 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2259 
2260 #define NIC_SRAM_WOL_MBOX 0x00000d30
2261 #define WOL_SIGNATURE 0x474c0000
2262 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
2263 #define WOL_DRV_WOL 0x00000002
2264 #define WOL_SET_MAGIC_PKT 0x00000004
2265 
2266 #define NIC_SRAM_DATA_CFG_2 0x00000d38
2267 
2268 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
2269 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
2270 #define SHASTA_EXT_LED_LEGACY 0x00000000
2271 #define SHASTA_EXT_LED_SHARED 0x00008000
2272 #define SHASTA_EXT_LED_MAC 0x00010000
2273 #define SHASTA_EXT_LED_COMBO 0x00018000
2274 
2275 #define NIC_SRAM_DATA_CFG_3 0x00000d3c
2276 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2277 
2278 #define NIC_SRAM_DATA_CFG_4 0x00000d60
2279 #define NIC_SRAM_GMII_MODE 0x00000002
2280 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2281 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2282 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2283 
2284 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2285 
2286 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2287 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2288 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2289 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2290 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2291 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2292 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2293 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2294 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2295 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2296 
2297 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2298 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2299 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2300 
2301 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2302 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2303 
2304 
2305 /* Currently this is fixed. */
2306 #define TG3_PHY_MII_ADDR 0x01
2307 
2308 
2309 /*** Tigon3 specific PHY MII registers. ***/
2310 #define TG3_BMCR_SPEED1000 0x0040
2311 
2312 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
2313 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
2314 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
2315 #define MII_TG3_CTRL_AS_MASTER 0x0800
2316 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
2317 
2318 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2319 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2320 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2321 
2322 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2323 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2324 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2325 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2326 #define MII_TG3_EXT_CTRL_TBI 0x8000
2327 
2328 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2329 #define MII_TG3_EXT_STAT_LPASS 0x0100
2330 
2331 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2332 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2333 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2334 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2335 
2336 #define MII_TG3_DSP_TAP1 0x0001
2337 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2338 #define MII_TG3_DSP_TAP26 0x001a
2339 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2340 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2341 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2342 #define MII_TG3_DSP_AADJ1CH0 0x001f
2343 #define MII_TG3_DSP_CH34TP2 0x4022
2344 #define MII_TG3_DSP_CH34TP2_HIBW01 0x017b
2345 #define MII_TG3_DSP_AADJ1CH3 0x601f
2346 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2347 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2348 #define MII_TG3_DSP_EXP8 0x0f08
2349 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2350 #define MII_TG3_DSP_EXP8_AEDW 0x0200
2351 #define MII_TG3_DSP_EXP75 0x0f75
2352 #define MII_TG3_DSP_EXP96 0x0f96
2353 #define MII_TG3_DSP_EXP97 0x0f97
2354 
2355 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
2356 
2357 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2358 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2359 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2360 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2361 
2362 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2363 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2364 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2365 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2366 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2367 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2368 
2369 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2370 
2371 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2372 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2373 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2374 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2375 #define MII_TG3_AUXCTL_MISC_WREN 0x8000
2376 
2377 
2378 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
2379 #define MII_TG3_AUX_STAT_LPASS 0x0004
2380 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
2381 #define MII_TG3_AUX_STAT_10HALF 0x0100
2382 #define MII_TG3_AUX_STAT_10FULL 0x0200
2383 #define MII_TG3_AUX_STAT_100HALF 0x0300
2384 #define MII_TG3_AUX_STAT_100_4 0x0400
2385 #define MII_TG3_AUX_STAT_100FULL 0x0500
2386 #define MII_TG3_AUX_STAT_1000HALF 0x0600
2387 #define MII_TG3_AUX_STAT_1000FULL 0x0700
2388 #define MII_TG3_AUX_STAT_100 0x0008
2389 #define MII_TG3_AUX_STAT_FULL 0x0001
2390 
2391 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
2392 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
2393 
2394 /* ISTAT/IMASK event bits */
2395 #define MII_TG3_INT_LINKCHG 0x0002
2396 #define MII_TG3_INT_SPEEDCHG 0x0004
2397 #define MII_TG3_INT_DUPLEXCHG 0x0008
2398 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2399 
2400 #define MII_TG3_MISC_SHDW 0x1c
2401 #define MII_TG3_MISC_SHDW_WREN 0x8000
2402 
2403 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2404 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2405 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2406 
2407 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2408 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2409 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2410 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2411 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2412 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2413 
2414 #define MII_TG3_TEST1 0x1e
2415 #define MII_TG3_TEST1_TRIM_EN 0x0010
2416 #define MII_TG3_TEST1_CRC_EN 0x8000
2417 
2418 /* Clause 45 expansion registers */
2419 #define TG3_CL45_D7_EEERES_STAT 0x803e
2420 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2421 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2422 
2423 
2424 /* Fast Ethernet Tranceiver definitions */
2425 #define MII_TG3_FET_PTEST 0x17
2426 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2427 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2428 
2429 #define MII_TG3_FET_TEST 0x1f
2430 #define MII_TG3_FET_SHADOW_EN 0x0080
2431 
2432 #define MII_TG3_FET_SHDW_MISCCTRL 0x10
2433 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2434 
2435 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2436 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2437 
2438 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2439 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2440 
2441 /* Serdes PHY Register Definitions */
2442 #define SERDES_TG3_1000X_STATUS 0x14
2443 #define SERDES_TG3_SGMII_MODE 0x0001
2444 #define SERDES_TG3_LINK_UP 0x0002
2445 #define SERDES_TG3_FULL_DUPLEX 0x0004
2446 #define SERDES_TG3_SPEED_100 0x0008
2447 #define SERDES_TG3_SPEED_1000 0x0010
2448 
2449 
2450 /* APE registers. Accessible through BAR1 */
2451 #define TG3_APE_EVENT 0x000c
2452 #define APE_EVENT_1 0x00000001
2453 #define TG3_APE_LOCK_REQ 0x002c
2454 #define APE_LOCK_REQ_DRIVER 0x00001000
2455 #define TG3_APE_LOCK_GRANT 0x004c
2456 #define APE_LOCK_GRANT_DRIVER 0x00001000
2457 #define TG3_APE_SEG_SIG 0x4000
2458 #define APE_SEG_SIG_MAGIC 0x41504521
2459 
2460 /* APE shared memory. Accessible through BAR1 */
2461 #define TG3_APE_FW_STATUS 0x400c
2462 #define APE_FW_STATUS_READY 0x00000100
2463 #define TG3_APE_FW_FEATURES 0x4010
2464 #define TG3_APE_FW_FEATURE_NCSI 0x00000002
2465 #define TG3_APE_FW_VERSION 0x4018
2466 #define APE_FW_VERSION_MAJMSK 0xff000000
2467 #define APE_FW_VERSION_MAJSFT 24
2468 #define APE_FW_VERSION_MINMSK 0x00ff0000
2469 #define APE_FW_VERSION_MINSFT 16
2470 #define APE_FW_VERSION_REVMSK 0x0000ff00
2471 #define APE_FW_VERSION_REVSFT 8
2472 #define APE_FW_VERSION_BLDMSK 0x000000ff
2473 #define TG3_APE_HOST_SEG_SIG 0x4200
2474 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2475 #define TG3_APE_HOST_SEG_LEN 0x4204
2476 #define APE_HOST_SEG_LEN_MAGIC 0x00000020
2477 #define TG3_APE_HOST_INIT_COUNT 0x4208
2478 #define TG3_APE_HOST_DRIVER_ID 0x420c
2479 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2480 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2481  (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2482 #define TG3_APE_HOST_BEHAVIOR 0x4210
2483 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2484 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2485 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
2486 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
2487 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2488 #define TG3_APE_HOST_DRVR_STATE 0x421c
2489 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2490 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2491 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2492 #define TG3_APE_HOST_WOL_SPEED 0x4224
2493 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2494 
2495 #define TG3_APE_EVENT_STATUS 0x4300
2496 
2497 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2498 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2499 #define APE_EVENT_STATUS_STATE_START 0x00010000
2500 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2501 #define APE_EVENT_STATUS_STATE_WOL 0x00030000
2502 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2503 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2504 
2505 #define TG3_APE_PER_LOCK_REQ 0x8400
2506 #define APE_LOCK_PER_REQ_DRIVER 0x00001000
2507 #define TG3_APE_PER_LOCK_GRANT 0x8420
2508 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2509 
2510 /* APE convenience enumerations. */
2511 #define TG3_APE_LOCK_GRC 1
2512 #define TG3_APE_LOCK_MEM 4
2513 
2514 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2515 
2516 
2517 /* There are two ways to manage the TX descriptors on the tigon3.
2518  * Either the descriptors are in host DMA'able memory, or they
2519  * exist only in the cards on-chip SRAM. All 16 send bds are under
2520  * the same mode, they may not be configured individually.
2521  *
2522  * This driver always uses host memory TX descriptors.
2523  *
2524  * To use host memory TX descriptors:
2525  * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2526  * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2527  * 2) Allocate DMA'able memory.
2528  * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2529  * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2530  * obtained in step 2
2531  * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2532  * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2533  * of TX descriptors. Leave flags field clear.
2534  * 4) Access TX descriptors via host memory. The chip
2535  * will refetch into local SRAM as needed when producer
2536  * index mailboxes are updated.
2537  *
2538  * To use on-chip TX descriptors:
2539  * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2540  * Make sure GRC_MODE_HOST_SENDBDS is clear.
2541  * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2542  * a) Set TG3_BDINFO_HOST_ADDR to zero.
2543  * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2544  * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2545  * 3) Access TX descriptors directly in on-chip SRAM
2546  * using normal {read,write}l(). (and not using
2547  * pointer dereferencing of ioremap()'d memory like
2548  * the broken Broadcom driver does)
2549  *
2550  * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2551  * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2552  */
2556 
2558 #define TXD_FLAG_TCPUDP_CSUM 0x0001
2559 #define TXD_FLAG_IP_CSUM 0x0002
2560 #define TXD_FLAG_END 0x0004
2561 #define TXD_FLAG_IP_FRAG 0x0008
2562 #define TXD_FLAG_JMB_PKT 0x0008
2563 #define TXD_FLAG_IP_FRAG_END 0x0010
2564 #define TXD_FLAG_VLAN 0x0040
2565 #define TXD_FLAG_COAL_NOW 0x0080
2566 #define TXD_FLAG_CPU_PRE_DMA 0x0100
2567 #define TXD_FLAG_CPU_POST_DMA 0x0200
2568 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
2569 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2570 #define TXD_FLAG_NO_CRC 0x8000
2571 #define TXD_LEN_SHIFT 16
2572 
2574 #define TXD_VLAN_TAG_SHIFT 0
2575 #define TXD_MSS_SHIFT 16
2576 };
2577 
2578 #define TXD_ADDR 0x00UL /* 64-bit */
2579 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2580 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2581 #define TXD_SIZE 0x10UL
2582 
2586 
2588 #define RXD_IDX_MASK 0xffff0000
2589 #define RXD_IDX_SHIFT 16
2590 #define RXD_LEN_MASK 0x0000ffff
2591 #define RXD_LEN_SHIFT 0
2592 
2594 #define RXD_TYPE_SHIFT 16
2595 #define RXD_FLAGS_SHIFT 0
2596 
2597 #define RXD_FLAG_END 0x0004
2598 #define RXD_FLAG_MINI 0x0800
2599 #define RXD_FLAG_JUMBO 0x0020
2600 #define RXD_FLAG_VLAN 0x0040
2601 #define RXD_FLAG_ERROR 0x0400
2602 #define RXD_FLAG_IP_CSUM 0x1000
2603 #define RXD_FLAG_TCPUDP_CSUM 0x2000
2604 #define RXD_FLAG_IS_TCP 0x4000
2605 
2607 #define RXD_IPCSUM_MASK 0xffff0000
2608 #define RXD_IPCSUM_SHIFT 16
2609 #define RXD_TCPCSUM_MASK 0x0000ffff
2610 #define RXD_TCPCSUM_SHIFT 0
2611 
2613 
2614 #define RXD_VLAN_MASK 0x0000ffff
2615 
2616 #define RXD_ERR_BAD_CRC 0x00010000
2617 #define RXD_ERR_COLLISION 0x00020000
2618 #define RXD_ERR_LINK_LOST 0x00040000
2619 #define RXD_ERR_PHY_DECODE 0x00080000
2620 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2621 #define RXD_ERR_MAC_ABRT 0x00200000
2622 #define RXD_ERR_TOO_SMALL 0x00400000
2623 #define RXD_ERR_NO_RESOURCES 0x00800000
2624 #define RXD_ERR_HUGE_FRAME 0x01000000
2625 #define RXD_ERR_MASK 0xffff0000
2626 
2629 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2630 #define RXD_OPAQUE_INDEX_SHIFT 0
2631 #define RXD_OPAQUE_RING_STD 0x00010000
2632 #define RXD_OPAQUE_RING_JUMBO 0x00020000
2633 #define RXD_OPAQUE_RING_MINI 0x00040000
2634 #define RXD_OPAQUE_RING_MASK 0x00070000
2635 };
2636 
2638  struct {
2641  } addrlist[3];
2645 };
2646 
2647 /* We only use this when testing out the DMA engine
2648  * at probe time. This is the internal format of buffer
2649  * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2650  */
2655  /* XXX FIX THIS */
2656 #if __BYTE_ORDER == __BIG_ENDIAN
2659 #else
2660  u16 len;
2661  u16 cqid_sqid;
2662 #endif
2667 };
2668 
2669 #define TG3_HW_STATUS_SIZE 0x50
2672 #define SD_STATUS_UPDATED 0x00000001
2673 #define SD_STATUS_LINK_CHG 0x00000002
2674 #define SD_STATUS_ERROR 0x00000004
2675 
2677 
2678 #if __BYTE_ORDER == __BIG_ENDIAN
2681 #else
2683  u16 rx_consumer;
2684 #endif
2685 
2686 #if __BYTE_ORDER == __BIG_ENDIAN
2689 #else
2691  u16 reserved;
2692 #endif
2693  struct {
2694 #if __BYTE_ORDER == __BIG_ENDIAN
2697 #else
2698  u16 rx_producer;
2699  u16 tx_consumer;
2700 #endif
2701  } idx[16];
2702 };
2703 
2704 typedef struct {
2706 } tg3_stat64_t;
2707 
2709  u8 __reserved0[0x400-0x300];
2710 
2711  /* Statistics maintained by Receive MAC. */
2739 
2741 
2742  /* Statistics maintained by Transmit MAC. */
2776 
2778 
2779  /* Statistics maintained by Receive List Placement. */
2788 
2790 
2791  /* Statistics maintained by Send Data Initiator. */
2796 
2797  /* Statistics maintained by Host Coalescing. */
2803 
2804  /* NOT a part of the hardware statistics block format.
2805  * These stats are here as storage for tg3_periodic_fetch_stats().
2806  */
2808 
2809  u8 __reserved4[0xb00-0x9c8];
2810 };
2811 
2812 typedef unsigned long dma_addr_t;
2813 
2814 /* 'mapping' is superfluous as the chip does not write into
2815  * the tx/rx post rings so we could just fetch it from there.
2816  * But the cache behavior is better how we are doing it now.
2817  */
2818 struct ring_info {
2819  struct io_buffer *iob;
2820 /// dma_addr_t mapping;
2821 };
2822 
2824  /* Describes what we're trying to get. */
2830 
2831  /* Describes what we actually have. */
2833 
2835 #define SPEED_INVALID 0xffff
2836 #define DUPLEX_INVALID 0xff
2837 #define AUTONEG_INVALID 0xff
2840 
2841  /* When we go in and out of low power mode we need
2842  * to swap with this state.
2843  */
2848 };
2849 
2854 
2858 
2861 };
2862 
2864  /* Statistics maintained by Receive MAC. */
2891 
2892  /* Statistics maintained by Transmit MAC. */
2924 
2925  /* Statistics maintained by Receive List Placement. */
2932 
2933  /* Statistics maintained by Send Data Initiator. */
2937 
2938  /* Statistics maintained by Host Coalescing. */
2944 
2946 };
2947 
2948 /* number of io_buffers to allocate */
2949 #define TG3_DEF_RX_RING_PENDING 8
2950 
2958 };
2959 
2960 #define TG3_IRQ_MAX_VECS_RSS 5
2961 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2962 
3033 
3034  /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3035  TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
3036 };
3037 
3038 /* Following definition is copied from linux-3.0rc1/include/linux/kernel.h */
3039 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
3040 /* bitops.h */
3041 #define BITS_PER_BYTE 8
3042 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
3043 /* types.h: */
3044 #define DECLARE_BITMAP(name,bits) \
3045  unsigned long name[BITS_TO_LONGS(bits)]
3046 
3047 struct tg3 {
3048  /* begin "general, frequently-used members" cacheline section */
3049 
3050  /* If the IRQ handler (which runs lockless) needs to be
3051  * quiesced, the following bitmask state is used. The
3052  * SYNC flag is set by non-IRQ context code to initiate
3053  * the quiescence.
3054  *
3055  * When the IRQ handler notices that SYNC is set, it
3056  * disables interrupts and returns.
3057  *
3058  * When all outstanding IRQ handlers have returned after
3059  * the SYNC flag has been set, the setter can be assured
3060  * that interrupts will no longer get run.
3061  *
3062  * In this way all SMP driver locks are never acquired
3063  * in hw IRQ context, only sw IRQ context or lower.
3064  */
3065  unsigned int irq_sync;
3066 
3067  /* SMP locking strategy:
3068  *
3069  * lock: Held during reset, PHY access, timer, and when
3070  * updating tg3_flags.
3071  *
3072  * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3073  * netif_tx_lock when it needs to call
3074  * netif_wake_queue.
3075  *
3076  * Both of these locks are to be held with BH safety.
3077  *
3078  * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3079  * are running lockless, it is necessary to completely
3080  * quiesce the chip with tg3_netif_stop and tg3_full_lock
3081  * before reconfiguring the device.
3082  *
3083  * indirect_lock: Held when accessing registers indirectly
3084  * with IRQ disabling.
3085  */
3086 
3087  u32 (*read32_mbox) (struct tg3 *, u32);
3088  void (*write32_mbox) (struct tg3 *, u32,
3089  u32);
3090  void *regs;
3091  struct net_device *dev;
3092  struct pci_device *pdev;
3093 
3095 
3096  /* begin "tx thread" cacheline section */
3097  void (*write32_tx_mbox) (struct tg3 *, u32,
3098  u32);
3099 
3100  /* begin "rx thread" cacheline section */
3101  void (*write32_rx_mbox) (struct tg3 *, u32,
3102  u32);
3105 
3106  /* was struct tg3_napi: */
3108 
3112  /* NOTE: there was a coal_now in struct tg3_napi and struct tg3. We
3113  * didn't use coal_now in struct tg3, so it was removed */
3115 
3121 
3127 
3131  /* end tg3_napi */
3132 
3133  /* begin "everything else" cacheline(s) section */
3134  unsigned long rx_dropped;
3135 
3137 
3138  union {
3139  unsigned long phy_crc_errors;
3140  };
3141 
3147 
3148  /* 1 second counter for transient serdes link events */
3150 #define SERDES_AN_TIMEOUT_5704S 2
3151 #define SERDES_PARALLEL_DET_TIMEOUT 1
3152 #define SERDES_AN_TIMEOUT_5714S 1
3153 
3156 
3157  /* cache h/w values, often passed straight to h/w */
3167 
3168  /* PCI block */
3173 
3174  int pm_cap;
3175  union {
3178  };
3180 
3182 
3183  /* PHY info */
3185 #define TG3_PHY_ID_MASK 0xfffffff0
3186 #define TG3_PHY_ID_BCM5400 0x60008040
3187 #define TG3_PHY_ID_BCM5401 0x60008050
3188 #define TG3_PHY_ID_BCM5411 0x60008070
3189 #define TG3_PHY_ID_BCM5701 0x60008110
3190 #define TG3_PHY_ID_BCM5703 0x60008160
3191 #define TG3_PHY_ID_BCM5704 0x60008190
3192 #define TG3_PHY_ID_BCM5705 0x600081a0
3193 #define TG3_PHY_ID_BCM5750 0x60008180
3194 #define TG3_PHY_ID_BCM5752 0x60008100
3195 #define TG3_PHY_ID_BCM5714 0x60008340
3196 #define TG3_PHY_ID_BCM5780 0x60008350
3197 #define TG3_PHY_ID_BCM5755 0xbc050cc0
3198 #define TG3_PHY_ID_BCM5787 0xbc050ce0
3199 #define TG3_PHY_ID_BCM5756 0xbc050ed0
3200 #define TG3_PHY_ID_BCM5784 0xbc050fa0
3201 #define TG3_PHY_ID_BCM5761 0xbc050fd0
3202 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3203 #define TG3_PHY_ID_BCM5718S 0xbc050ff0
3204 #define TG3_PHY_ID_BCM57765 0x5c0d8a40
3205 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3206 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3207 #define TG3_PHY_ID_BCM5906 0xdc00ac40
3208 #define TG3_PHY_ID_BCM8002 0x60010140
3209 #define TG3_PHY_ID_INVALID 0xffffffff
3210 
3211 #define PHY_ID_RTL8211C 0x001cc910
3212 #define PHY_ID_RTL8201E 0x00008200
3213 
3214 #define TG3_PHY_ID_REV_MASK 0x0000000f
3215 #define TG3_PHY_REV_BCM5401_B0 0x1
3216 
3217  /* This macro assumes the passed PHY ID is
3218  * already masked with TG3_PHY_ID_MASK.
3219  */
3220 #define TG3_KNOWN_PHY_ID(X) \
3221  ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3222  (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3223  (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3224  (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3225  (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3226  (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3227  (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3228  (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3229  (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3230  (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3231  (X) == TG3_PHY_ID_BCM8002)
3232 
3234 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3235 #define TG3_PHYFLG_IS_CONNECTED 0x00000002
3236 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3237 #define TG3_PHYFLG_PHY_SERDES 0x00000010
3238 #define TG3_PHYFLG_MII_SERDES 0x00000020
3239 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3240  TG3_PHYFLG_MII_SERDES)
3241 #define TG3_PHYFLG_IS_FET 0x00000040
3242 #define TG3_PHYFLG_10_100_ONLY 0x00000080
3243 #define TG3_PHYFLG_ENABLE_APD 0x00000100
3244 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3245 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3246 #define TG3_PHYFLG_JITTER_BUG 0x00000800
3247 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3248 #define TG3_PHYFLG_ADC_BUG 0x00002000
3249 #define TG3_PHYFLG_5704_A0_BUG 0x00004000
3250 #define TG3_PHYFLG_BER_BUG 0x00008000
3251 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3252 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3253 #define TG3_PHYFLG_EEE_CAP 0x00040000
3254 
3258 
3259 #define TG3_BPN_SIZE 24
3261 #define TG3_VER_SIZE 32
3266 
3269 #define TG3_NVRAM_SIZE_2KB 0x00000800
3270 #define TG3_NVRAM_SIZE_64KB 0x00010000
3271 #define TG3_NVRAM_SIZE_128KB 0x00020000
3272 #define TG3_NVRAM_SIZE_256KB 0x00040000
3273 #define TG3_NVRAM_SIZE_512KB 0x00080000
3274 #define TG3_NVRAM_SIZE_1MB 0x00100000
3275 #define TG3_NVRAM_SIZE_2MB 0x00200000
3276 
3279 
3280 #define JEDEC_ATMEL 0x1f
3281 #define JEDEC_ST 0x20
3282 #define JEDEC_SAIFUN 0x4f
3283 #define JEDEC_SST 0xbf
3284 
3285 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3286 #define ATMEL_AT24C02_PAGE_SIZE (8)
3287 
3288 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3289 #define ATMEL_AT24C64_PAGE_SIZE (32)
3290 
3291 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3292 #define ATMEL_AT24C512_PAGE_SIZE (128)
3293 
3294 #define ATMEL_AT45DB0X1B_PAGE_POS 9
3295 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3296 
3297 #define ATMEL_AT25F512_PAGE_SIZE 256
3298 
3299 #define ST_M45PEX0_PAGE_SIZE 256
3300 
3301 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
3302 
3303 #define SST_25VF0X0_PAGE_SIZE 4098
3304 
3307  int link_up;
3308 };
3309 
3310 #define TG3_TX_RING_SIZE 512
3311 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
3312 
3313 #define TG3_DMA_ALIGNMENT 16
3314 
3315 #define TG3_RX_STD_DMA_SZ (1536 + 64 + 2)
3316 
3317 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
3318 {
3319  tp->write32_mbox(tp, off, val);
3320 /// if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
3321 /// tp->read32_mbox(tp, off);
3322 }
3323 
3324 u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off);
3325 void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val);
3326 u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off);
3327 void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val);
3328 
3329 #define tw32(reg, val) tg3_write_indirect_reg32(tp, reg, val)
3330 ///#define tw32_mailbox(reg, val) tg3_write_indirect_mbox(((val) & 0xffffffff), tp->regs + (reg))
3331 #define tw32_mailbox(reg, val) tg3_write_indirect_mbox(tp, (reg), (val))
3332 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
3333 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
3334 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
3335 
3336 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
3337 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
3338 
3339 #define tr32(reg) tg3_read_indirect_reg32(tp, reg)
3340 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
3341 
3342 /* Functions & macros to verify TG3_FLAGS types */
3343 
3344 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
3345 {
3346  unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
3347  unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
3348  return ( !! ( bits[index] & ( 1UL << bit ) ) );
3349 }
3350 
3351 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
3352 {
3353  unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
3354  unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
3355  bits[index] |= ( 1UL << bit );
3356 }
3357 
3358 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
3359 {
3360  unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
3361  unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
3362  bits[index] &= ~( 1UL << bit );
3363 }
3364 
3365 #define tg3_flag(tp, flag) \
3366  _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
3367 #define tg3_flag_set(tp, flag) \
3368  _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
3369 #define tg3_flag_clear(tp, flag) \
3370  _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
3371 
3372 /* tg3_main.c forward declarations */
3373 int tg3_init_rings(struct tg3 *tp);
3374 void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr);
3375 ///int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
3376 
3377 /* tg3_phy.c forward declarations */
3378 u32 tg3_read_otp_phycfg(struct tg3 *tp);
3379 void tg3_mdio_init(struct tg3 *tp);
3380 int tg3_phy_probe(struct tg3 *tp);
3381 int tg3_phy_reset(struct tg3 *tp);
3382 int tg3_setup_phy(struct tg3 *tp, int force_reset);
3383 int tg3_readphy(struct tg3 *tp, int reg, u32 *val);
3384 int tg3_writephy(struct tg3 *tp, int reg, u32 val);
3385 
3386 /* tg3_hw.c forward declarations */
3387 void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait);
3388 void tg3_write_mem(struct tg3 *tp, u32 off, u32 val);
3389 int tg3_get_invariants(struct tg3 *tp);
3390 void tg3_init_bufmgr_config(struct tg3 *tp);
3391 int tg3_get_device_address(struct tg3 *tp);
3392 int tg3_halt(struct tg3 *tp);
3393 void tg3_set_txd(struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags);
3394 void tg3_set_power_state_0(struct tg3 *tp);
3395 int tg3_alloc_consistent(struct tg3 *tp);
3396 int tg3_init_hw(struct tg3 *tp, int reset_phy);
3397 void tg3_poll_link(struct tg3 *tp);
3398 void tg3_wait_for_event_ack(struct tg3 *tp);
3399 void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1);
3400 void tg3_disable_ints(struct tg3 *tp);
3401 void tg3_enable_ints(struct tg3 *tp);
3402 
3403 static inline void tg3_generate_fw_event(struct tg3 *tp)
3404 {
3405  u32 val;
3406 
3410 }
3411 
3412 /* linux-2.6.39, include/linux/mii.h: */
3413 /**
3414  * mii_resolve_flowctrl_fdx
3415  * @lcladv: value of MII ADVERTISE register
3416  * @rmtadv: value of MII LPA register
3417  *
3418  * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
3419  */
3420 static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
3421 {
3422  u8 cap = 0;
3423 
3424  if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
3425  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
3426  } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
3427  if (lcladv & ADVERTISE_PAUSE_CAP)
3428  cap = FLOW_CTRL_RX;
3429  else if (rmtadv & ADVERTISE_PAUSE_CAP)
3430  cap = FLOW_CTRL_TX;
3431  }
3432 
3433  return cap;
3434 }
3435 
3437 {
3438  u32 result = 0;
3439 
3440  if (adv & ADVERTISE_1000XHALF)
3442  if (adv & ADVERTISE_1000XFULL)
3444  if (adv & ADVERTISE_1000XPAUSE)
3446  if (adv & ADVERTISE_1000XPSE_ASYM)
3448 
3449  return result;
3450 }
3451 
3452 static inline u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
3453 {
3454  u32 result = 0;
3455 
3456  if (ethadv & ADVERTISED_1000baseT_Half)
3458  if (ethadv & ADVERTISED_1000baseT_Full)
3460  if (ethadv & ADVERTISED_Pause)
3462  if (ethadv & ADVERTISED_Asym_Pause)
3464 
3465  return result;
3466 }
3467 
3468 
3469 #define ETH_FCS_LEN 4
3470 
3471 #endif /* !(_T3_H) */
uint16_t u16
Definition: stdint.h:21
#define ADVERTISED_Pause
Definition: tg3.h:38
tg3_stat64_t rx_512_to_1023_octet_packets
Definition: tg3.h:2733
u64 tx_collide_12times
Definition: tg3.h:2914
tg3_stat64_t rx_jabbers
Definition: tg3.h:2725
unsigned long rx_dropped
Definition: tg3.h:3134
int tg3_writephy(struct tg3 *tp, int reg, u32 val)
Definition: tg3_phy.c:221
u32 status_tag
Definition: tg3.h:2676
static void tg3_generate_fw_event(struct tg3 *tp)
Definition: tg3.h:3403
u64 __reserved2
Definition: tg3.h:2744
u64 rx_1024_to_1522_octet_packets
Definition: tg3.h:2886
tg3_stat64_t rx_mcast_packets
Definition: tg3.h:2716
tg3_stat64_t rx_undersize_packets
Definition: tg3.h:2726
#define tr32(reg)
Definition: tg3.h:3339
Definition: tg3.h:3047
static u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
mii_resolve_flowctrl_fdx @lcladv: value of MII ADVERTISE register @rmtadv: value of MII LPA register
Definition: tg3.h:3420
tg3_stat64_t tx_mcast_packets
Definition: tg3.h:2771
#define ADVERTISED_Asym_Pause
Definition: tg3.h:41
int pcie_readrq
Definition: tg3.h:3179
void(* write32_rx_mbox)(struct tg3 *, u32, u32)
Definition: tg3.h:3101
tg3_stat64_t rx_align_errors
Definition: tg3.h:2719
tg3_stat64_t tx_collide_9times
Definition: tg3.h:2763
u64 tx_collide_4times
Definition: tg3.h:2906
#define ADVERTISE_1000XPAUSE
Definition: mii.h:77
struct net_device * dev
Definition: tg3.h:3091
void tg3_init_bufmgr_config(struct tg3 *tp)
Definition: tg3_hw.c:849
static unsigned int unsigned int bit
Definition: bigint.h:196
int tg3_phy_probe(struct tg3 *tp)
Definition: tg3_phy.c:895
u32 tg3_read_otp_phycfg(struct tg3 *tp)
int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
Definition: tg3_phy.c:56
u16 timer_counter
Definition: tg3.h:3142
tg3_stat64_t tx_collide_8times
Definition: tg3.h:2762
u32 rx_std_max_post
Definition: tg3.h:3103
dma_addr_t rx_rcb_mapping
Definition: tg3.h:3129
u32 dma_low_water
Definition: tg3.h:2859
tg3_stat64_t rx_64_or_less_octet_packets
Definition: tg3.h:2729
tg3_stat64_t tx_carrier_sense_errors
Definition: tg3.h:2773
u64 tx_mcast_packets
Definition: tg3.h:2919
tg3_stat64_t rx_out_length_errors
Definition: tg3.h:2728
void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
Definition: tg3_hw.c:41
tg3_stat64_t rx_fcs_errors
Definition: tg3.h:2718
u32 rx_std_iob_cnt
Definition: tg3.h:2954
tg3_stat64_t tx_collide_4times
Definition: tg3.h:2758
u32 grc_local_ctrl
Definition: tg3.h:3164
struct tg3_bufmgr_config bufmgr_config
Definition: tg3.h:3155
u64 rx_undersize_packets
Definition: tg3.h:2878
u32 last_irq_tag
Definition: tg3.h:3110
u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
Definition: tg3_hw.c:48
u16 asf_multiplier
Definition: tg3.h:3146
u64 rx_2048_to_4095_octet_packets
Definition: tg3.h:2888
int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
Definition: tg3_phy.c:85
u64 tx_collide_9times
Definition: tg3.h:2911
u64 rx_128_to_255_octet_packets
Definition: tg3.h:2883
u64 nic_tx_threshold_hit
Definition: tg3.h:2943
u32 nvram_jedecnum
Definition: tg3.h:3278
struct ring_info * tx_buffers
Definition: tg3.h:3126
u64 rx_fcs_errors
Definition: tg3.h:2870
tg3_stat64_t rx_1523_to_2047_octet_packets
Definition: tg3.h:2735
u32 nic_sram_data_cfg
Definition: tg3.h:3263
u32 tx_prod
Definition: tg3.h:3122
u8 phy_addr
Definition: tg3.h:3181
void * regs
Definition: tg3.h:3090
unsigned long dma_addr_t
Definition: bnx2.h:20
u64 tx_comp_queue_full
Definition: tg3.h:2936
u64 dma_writeq_full
Definition: tg3.h:2926
int tg3_setup_phy(struct tg3 *tp, int force_reset)
Definition: tg3_phy.c:2520
tg3_stat64_t tx_octets
Definition: tg3.h:2743
int link_up
Definition: tg3.h:3307
u64 tx_collide_8times
Definition: tg3.h:2910
u64 rx_512_to_1023_octet_packets
Definition: tg3.h:2885
tg3_stat64_t rx_bcast_packets
Definition: tg3.h:2717
u32 prodmbox
Definition: tg3.h:3124
u64 tx_carrier_sense_errors
Definition: tg3.h:2921
u32 mac_mode
Definition: tg3.h:3160
tg3_stat64_t rx_frame_too_long_errors
Definition: tg3.h:2724
u16 pci_cmd
Definition: tg3.h:3170
u32 dma_rwctrl
Definition: tg3.h:3165
void(* write32_tx_mbox)(struct tg3 *, u32, u32)
Definition: tg3.h:3097
u64 rx_xoff_entered
Definition: tg3.h:2875
tg3_stat64_t tx_collide_6times
Definition: tg3.h:2760
u64 rx_in_length_errors
Definition: tg3.h:2879
u32 serdes_counter
Definition: tg3.h:3149
void tg3_poll_link(struct tg3 *tp)
Definition: tg3_phy.c:1008
u64 dma_readq_full
Definition: tg3.h:2934
int tg3_init_rings(struct tg3 *tp)
Definition: tg3.c:203
u64 rx_8192_to_9022_octet_packets
Definition: tg3.h:2890
u32 mbuf_read_dma_low_water_jumbo
Definition: tg3.h:2855
#define TG3_VER_SIZE
Definition: tg3.h:3261
tg3_stat64_t tx_collide_11times
Definition: tg3.h:2765
unsigned long phy_crc_errors
Definition: tg3.h:3139
u64 ring_set_send_prod_index
Definition: tg3.h:2939
tg3_stat64_t tx_collide_13times
Definition: tg3.h:2767
u64 rx_xoff_pause_rcvd
Definition: tg3.h:2873
u64 tx_xon_sent
Definition: tg3.h:2895
u64 __reserved3
Definition: tg3.h:2753
u32 misc_host_ctrl
Definition: tg3.h:3162
u32 rx_mode
Definition: tg3.h:3158
u16 asf_counter
Definition: tg3.h:3145
u64 tx_deferred
Definition: tg3.h:2901
u32 status
Definition: tg3.h:2671
struct tg3_hw_status::@337 idx[16]
u32 int_mbox
Definition: tg3.h:3111
u64 rx_frame_too_long_errors
Definition: tg3.h:2876
struct pci_device * pdev_peer
Definition: tg3.h:3265
u16 rx_mini_consumer
Definition: tg3.h:2688
tg3_stat64_t tx_xon_sent
Definition: tg3.h:2746
#define ADVERTISE_1000XHALF
Definition: mii.h:75
tg3_stat64_t rxbds_empty
Definition: tg3.h:2784
u64 tx_collide_11times
Definition: tg3.h:2913
static u32 mii_adv_to_ethtool_adv_x(u32 adv)
Definition: tg3.h:3436
int result
Definition: bigint.h:148
u64 tx_discards
Definition: tg3.h:2922
u16 reserved
Definition: tg3.h:2687
u64 tx_single_collisions
Definition: tg3.h:2899
tg3_stat64_t rx_128_to_255_octet_packets
Definition: tg3.h:2731
int tg3_phy_reset(struct tg3 *tp)
Definition: tg3_phy.c:621
u64 rx_mcast_packets
Definition: tg3.h:2868
u64 dma_write_prioq_full
Definition: tg3.h:2927
u64 tx_xoff_sent
Definition: tg3.h:2896
int tg3_halt(struct tg3 *tp)
Definition: tg3_hw.c:1480
#define FLOW_CTRL_TX
Definition: tg3.h:54
tg3_stat64_t tx_collide_12times
Definition: tg3.h:2766
#define TG3_BPN_SIZE
Definition: tg3.h:3259
unsigned int irq_sync
Definition: tg3.h:3065
void tg3_set_power_state_0(struct tg3 *tp)
Definition: tg3_hw.c:129
u64 rx_bcast_packets
Definition: tg3.h:2869
tg3_stat64_t nic_tx_threshold_hit
Definition: tg3.h:2802
#define ADVERTISED_1000baseT_Half
Definition: tg3.h:32
u16 rx_producer
Definition: tg3.h:2696
u8 __reserved0[0x400-0x300]
Definition: tg3.h:2709
#define u32
Definition: vga.h:21
u64 dma_read_prioq_full
Definition: tg3.h:2935
u32 phy_id
Definition: tg3.h:3184
u32 led_ctrl
Definition: tg3.h:3255
uint64_t u64
Definition: stdint.h:25
#define ADVERTISED_1000baseT_Full
Definition: tg3.h:33
static u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
Definition: tg3.h:3452
tg3_stat64_t tx_collide_5times
Definition: tg3.h:2759
static struct tulip_private * tp
Definition: tulip.c:441
u64 rx_1523_to_2047_octet_packets
Definition: tg3.h:2887
u32 setlpicnt
Definition: tg3.h:3257
u32 last_tag
Definition: tg3.h:3109
static int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
Definition: tg3.h:3344
u64 rx_64_or_less_octet_packets
Definition: tg3.h:2881
tg3_stat64_t rx_fragments
Definition: tg3.h:2714
tg3_stat64_t ring_set_send_prod_index
Definition: tg3.h:2798
tg3_stat64_t rx_in_length_errors
Definition: tg3.h:2727
int pcie_cap
Definition: tg3.h:3177
tg3_stat64_t dma_read_prioq_full
Definition: tg3.h:2794
u64 rx_4096_to_8191_octet_packets
Definition: tg3.h:2889
#define ADVERTISE_1000XPSE_ASYM
Definition: mii.h:79
u64 tx_bcast_packets
Definition: tg3.h:2920
tg3_stat64_t tx_mac_errors
Definition: tg3.h:2749
u64 tx_collide_14times
Definition: tg3.h:2916
tg3_stat64_t tx_late_collisions
Definition: tg3.h:2755
u32 mbuf_mac_rx_low_water
Definition: tg3.h:2852
u64 tx_collide_6times
Definition: tg3.h:2908
tg3_stat64_t tx_collide_15times
Definition: tg3.h:2769
#define ADVERTISE_PAUSE_ASYM
Definition: mii.h:82
struct tg3_tx_buffer_desc * tx_ring
Definition: tg3.h:3125
u64 rx_fragments
Definition: tg3.h:2866
u32 consmbox
Definition: tg3.h:3116
u64 tx_collide_5times
Definition: tg3.h:2907
struct tg3_link_config link_config
Definition: tg3.h:3154
u32 nvram_size
Definition: tg3.h:3268
union aes_table_entry entry[256]
Table entries, indexed by S(N)
Definition: aes.c:26
tg3_stat64_t rx_xoff_entered
Definition: tg3.h:2723
u32 pci_chip_rev_id
Definition: tg3.h:3169
struct tg3_rx_buffer_desc * rx_rcb
Definition: tg3.h:3120
tg3_stat64_t dma_write_prioq_full
Definition: tg3.h:2783
u64 tx_collide_2times
Definition: tg3.h:2904
static unsigned int unsigned int reg
Definition: intel.h:245
u64 tx_collide_13times
Definition: tg3.h:2915
tg3_stat64_t rx_2048_to_4095_octet_packets
Definition: tg3.h:2736
tg3_stat64_t rx_threshold_hit
Definition: tg3.h:2787
A PCI device.
Definition: pci.h:187
u64 rx_65_to_127_octet_packets
Definition: tg3.h:2882
#define TG3_DEF_RX_RING_PENDING
Definition: tg3.h:2949
tg3_stat64_t tx_single_collisions
Definition: tg3.h:2750
u64 rx_256_to_511_octet_packets
Definition: tg3.h:2884
A network device.
Definition: netdevice.h:348
u64 tx_late_collisions
Definition: tg3.h:2903
dma_addr_t tx_desc_mapping
Definition: tg3.h:3130
void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr)
Definition: tg3.c:41
u32 rx_std_cons_idx
Definition: tg3.h:2953
u64 tx_ucast_packets
Definition: tg3.h:2918
tg3_stat64_t tx_collide_2times
Definition: tg3.h:2756
tg3_stat64_t tx_mult_collisions
Definition: tg3.h:2751
u32 nvram_pagesize
Definition: tg3.h:3277
u32 pci_clock_ctrl
Definition: tg3.h:3264
u64 rx_ucast_packets
Definition: tg3.h:2867
u32 rx_rcb_ptr
Definition: tg3.h:3117
u32 phy_otp
Definition: tg3.h:3256
u32 grc_mode
Definition: tg3.h:3163
u32 dma_high_water
Definition: tg3.h:2860
#define tw32_f(reg, val)
Definition: tg3.h:3333
u64 __reserved1
Definition: tg3.h:2713
u32 coal_now
Definition: tg3.h:3114
u32 coalesce_mode
Definition: tg3.h:3166
u64 tx_flow_control
Definition: tg3.h:2897
struct tg3_rx_prodring_set prodring
Definition: tg3.h:3119
#define FLOW_CTRL_RX
Definition: tg3.h:55
tg3_stat64_t rx_256_to_511_octet_packets
Definition: tg3.h:2732
tg3_stat64_t tx_collide_10times
Definition: tg3.h:2764
u32(* read32_mbox)(struct tg3 *, u32)
Definition: tg3.h:3087
#define GRC_RX_CPU_DRIVER_EVENT
Definition: tg3.h:1871
void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
Definition: tg3_hw.c:1093
#define GRC_RX_CPU_EVENT
Definition: tg3.h:1870
void tg3_set_txd(struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags)
Definition: tg3_hw.c:2582
void __asmcall int val
Definition: setjmp.h:28
u8 pci_lat_timer
Definition: tg3.h:3172
tg3_stat64_t rx_errors
Definition: tg3.h:2786
u16 tx_consumer
Definition: tg3.h:2695
u64 tx_excessive_collisions
Definition: tg3.h:2902
char board_part_number[TG3_BPN_SIZE]
Definition: tg3.h:3260
tg3_stat64_t rx_65_to_127_octet_packets
Definition: tg3.h:2730
void(* write32_mbox)(struct tg3 *, u32, u32)
Definition: tg3.h:3088
dma_addr_t status_mapping
Definition: tg3.h:3128
tg3_stat64_t rx_1024_to_1522_octet_packets
Definition: tg3.h:2734
tg3_stat64_t tx_collide_3times
Definition: tg3.h:2757
u32 phy_flags
Definition: tg3.h:3233
tg3_stat64_t nic_irqs
Definition: tg3.h:2800
dma_addr_t rx_std_mapping
Definition: tg3.h:2957
tg3_stat64_t rx_4096_to_8191_octet_packets
Definition: tg3.h:2737
u64 rx_out_length_errors
Definition: tg3.h:2880
u32 mi_mode
Definition: tg3.h:3161
u64 mbuf_lwm_thresh_hit
Definition: tg3.h:2945
u64 tx_collisions
Definition: tg3.h:2894
int tg3_get_device_address(struct tg3 *tp)
Definition: tg3_hw.c:1649
tg3_stat64_t rx_xoff_pause_rcvd
Definition: tg3.h:2721
void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
Definition: tg3_hw.c:921
static volatile void * bits
Definition: bitops.h:27
uint32_t len
Length.
Definition: ena.h:14
u64 rx_mac_ctrl_rcvd
Definition: tg3.h:2874
u32 mbuf_read_dma_low_water
Definition: tg3.h:2851
u64 rx_xon_pause_rcvd
Definition: tg3.h:2872
tg3_stat64_t rx_mac_ctrl_rcvd
Definition: tg3.h:2722
tg3_stat64_t tx_comp_queue_full
Definition: tg3.h:2795
u64 tx_collide_7times
Definition: tg3.h:2909
u16 timer_multiplier
Definition: tg3.h:3143
u64 nic_avoided_irqs
Definition: tg3.h:2942
u64 tx_mac_errors
Definition: tg3.h:2898
void tg3_mdio_init(struct tg3 *tp)
Definition: tg3_phy.c:13
int pm_cap
Definition: tg3.h:3174
void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
Definition: tg3_hw.c:70
tg3_stat64_t tx_deferred
Definition: tg3.h:2752
DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS)
tg3_stat64_t tx_flow_control
Definition: tg3.h:2748
u32 rx_pkt_map_sz
Definition: tg3.h:3104
u32 timer_offset
Definition: tg3.h:3144
tg3_stat64_t rx_discards
Definition: tg3.h:2785
int tg3_alloc_consistent(struct tg3 *tp)
Definition: tg3.c:84
tg3_stat64_t tx_collide_7times
Definition: tg3.h:2761
u64 tx_mult_collisions
Definition: tg3.h:2900
u32 rx_std_prod_idx
Definition: tg3.h:2952
tg3_stat64_t tx_excessive_collisions
Definition: tg3.h:2754
tg3_stat64_t dma_writeq_full
Definition: tg3.h:2782
tg3_stat64_t dma_readq_full
Definition: tg3.h:2793
struct io_buffer * rx_iobufs[TG3_DEF_RX_RING_PENDING]
Definition: tg3.h:2956
u32 mbuf_high_water
Definition: tg3.h:2853
tg3_stat64_t rx_ucast_packets
Definition: tg3.h:2715
tg3_stat64_t nic_avoided_irqs
Definition: tg3.h:2801
struct tg3_rx_buffer_desc * rx_std
Definition: tg3.h:2955
struct pci_device * pdev
Definition: tg3.h:3092
tg3_stat64_t tx_ucast_packets
Definition: tg3.h:2770
u16 rx_consumer
Definition: tg3.h:2679
u64 tx_collide_10times
Definition: tg3.h:2912
u8 __reserved4[0xb00-0x9c8]
Definition: tg3.h:2809
u64 tx_collide_3times
Definition: tg3.h:2905
#define ADVERTISE_PAUSE_CAP
Definition: mii.h:81
struct tg3_hw_status * hw_status
Definition: tg3.h:3107
u32 tx_mode
Definition: tg3.h:3159
u64 ring_status_update
Definition: tg3.h:2940
u64 rxbds_empty
Definition: tg3.h:2928
uint32_t high
High 32 bits of address.
Definition: intel.h:22
u32 low
Definition: tg3.h:2705
u32 msg_enable
Definition: tg3.h:3094
u32 mbuf_high_water_jumbo
Definition: tg3.h:2857
tg3_stat64_t COS_out_packets[16]
Definition: tg3.h:2792
tg3_stat64_t ring_status_update
Definition: tg3.h:2799
static void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
Definition: tg3.h:3351
u64 tx_collide_15times
Definition: tg3.h:2917
tg3_stat64_t mbuf_lwm_thresh_hit
Definition: tg3.h:2807
tg3_stat64_t rx_octets
Definition: tg3.h:2712
int pcix_cap
Definition: tg3.h:3176
u16 rx_jumbo_consumer
Definition: tg3.h:2680
u32 mbuf_mac_rx_low_water_jumbo
Definition: tg3.h:2856
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
u64 __unused1[31]
Definition: tg3.h:2777
u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
Definition: tg3_hw.c:97
struct tg3_ext_rx_buffer_desc::@336 addrlist[3]
tg3_stat64_t tx_collide_14times
Definition: tg3.h:2768
u64 __unused2[9]
Definition: tg3.h:2789
tg3_stat64_t tx_collisions
Definition: tg3.h:2745
void tg3_enable_ints(struct tg3 *tp)
Definition: tg3_hw.c:967
tg3_stat64_t rx_8192_to_9022_octet_packets
Definition: tg3.h:2738
u16 * rx_rcb_prod_idx
Definition: tg3.h:3118
static void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
Definition: tg3.h:3317
u64 rx_discards
Definition: tg3.h:2929
tg3_stat64_t tx_errors
Definition: tg3.h:2775
int nvram_lock_cnt
Definition: tg3.h:3267
tg3_stat64_t tx_bcast_packets
Definition: tg3.h:2772
tg3_stat64_t tx_discards
Definition: tg3.h:2774
void tg3_disable_ints(struct tg3 *tp)
Definition: tg3_hw.c:958
u64 rx_align_errors
Definition: tg3.h:2871
int tg3_init_hw(struct tg3 *tp, int reset_phy)
Definition: tg3_hw.c:2572
TG3_FLAGS
Definition: tg3.h:2963
static void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
Definition: tg3.h:3358
void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
Definition: tg3_hw.c:113
u32 tx_cons
Definition: tg3.h:3123
unsigned long dma_addr_t
Definition: tg3.h:2812
struct io_buffer * iob
Definition: tg3.h:2819
u16 subsystem_vendor
Definition: tg3.h:3305
char fw_ver[TG3_VER_SIZE]
Definition: tg3.h:3262
uint8_t u8
Definition: stdint.h:19
tg3_stat64_t COS_rx_packets[16]
Definition: tg3.h:2780
struct tg3_rx_buffer_desc std
Definition: tg3.h:2644
u64 rx_threshold_hit
Definition: tg3.h:2931
uint32_t u32
Definition: stdint.h:23
u16 subsystem_device
Definition: tg3.h:3306
u64 __unused0[37]
Definition: tg3.h:2740
tg3_stat64_t COS_rx_filter_dropped
Definition: tg3.h:2781
uint16_t flag
Flag number.
Definition: hyperv.h:14
tg3_stat64_t tx_xoff_sent
Definition: tg3.h:2747
u64 rx_jabbers
Definition: tg3.h:2877
#define ADVERTISE_1000XFULL
Definition: mii.h:73
int tg3_get_invariants(struct tg3 *tp)
Definition: tg3_hw.c:393
u8 pci_cacheline_sz
Definition: tg3.h:3171
tg3_stat64_t rx_xon_pause_rcvd
Definition: tg3.h:2720
void tg3_wait_for_event_ack(struct tg3 *tp)
Definition: tg3_hw.c:908
A persistent I/O buffer.
Definition: iobuf.h:32
uint8_t flags
Flags.
Definition: ena.h:18