tg3.h File Reference

Go to the source code of this file.

Data Structures
struct	tg3_tx_buffer_desc
struct	tg3_rx_buffer_desc
struct	tg3_ext_rx_buffer_desc
struct	tg3_internal_buffer_desc
struct	tg3_hw_status
struct	tg3_stat64_t
struct	tg3_hw_stats
struct	ring_info
struct	tg3_link_config
struct	tg3_bufmgr_config
struct	tg3_ethtool_stats
struct	tg3_rx_prodring_set
struct	tg3

Macros
#define	ERRFILE   ERRFILE_tg3
#define	PCI_EXP_LNKCTL   16 /* Link Control */
#define	PCI_EXP_LNKCTL_CLKREQ_EN   0x100 /* Enable clkreq */
#define	PCI_CAP_ID_PCIX   0x07 /* PCI-X */
#define	PCI_X_CMD_READ_2K   0x0008 /* 2Kbyte maximum read byte count */
#define	PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */
#define	PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */
#define	ADVERTISED_10baseT_Half   (1 << 0)
#define	ADVERTISED_10baseT_Full   (1 << 1)
#define	ADVERTISED_100baseT_Half   (1 << 2)
#define	ADVERTISED_100baseT_Full   (1 << 3)
#define	ADVERTISED_1000baseT_Half   (1 << 4)
#define	ADVERTISED_1000baseT_Full   (1 << 5)
#define	ADVERTISED_Autoneg   (1 << 6)
#define	ADVERTISED_Pause   (1 << 13)
#define	ADVERTISED_Asym_Pause   (1 << 14)
#define	MDIO_AN_EEE_ADV   60 /* EEE advertisement */
#define	MDIO_MMD_AN   7 /* Auto-Negotiation */
#define	MDIO_AN_EEE_ADV_100TX   0x0002 /* Advertise 100TX EEE cap */
#define	MDIO_AN_EEE_ADV_1000T   0x0004 /* Advertise 1000T EEE cap */
#define	FLOW_CTRL_TX   0x01
#define	FLOW_CTRL_RX   0x02
#define	PCI_X_CMD   2 /* Modes & Features */
#define	PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */
#define	PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */
#define	PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */
#define	PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */
#define	PCI_EXP_DEVSTA   10 /* Device Status */
#define	PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */
#define	PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */
#define	PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */
#define	PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */
#define	PCI_VENDOR_ID_BROADCOM   0x14e4
#define	PCI_DEVICE_ID_TIGON3_5752   0x1600
#define	PCI_DEVICE_ID_TIGON3_5752M   0x1601
#define	PCI_DEVICE_ID_NX2_5709   0x1639
#define	PCI_DEVICE_ID_NX2_5709S   0x163a
#define	PCI_DEVICE_ID_TIGON3_5700   0x1644
#define	PCI_DEVICE_ID_TIGON3_5701   0x1645
#define	PCI_DEVICE_ID_TIGON3_5702   0x1646
#define	PCI_DEVICE_ID_TIGON3_5703   0x1647
#define	PCI_DEVICE_ID_TIGON3_5704   0x1648
#define	PCI_DEVICE_ID_TIGON3_5704S_2   0x1649
#define	PCI_DEVICE_ID_NX2_5706   0x164a
#define	PCI_DEVICE_ID_NX2_5708   0x164c
#define	PCI_DEVICE_ID_TIGON3_5702FE   0x164d
#define	PCI_DEVICE_ID_NX2_57710   0x164e
#define	PCI_DEVICE_ID_NX2_57711   0x164f
#define	PCI_DEVICE_ID_NX2_57711E   0x1650
#define	PCI_DEVICE_ID_TIGON3_5705   0x1653
#define	PCI_DEVICE_ID_TIGON3_5705_2   0x1654
#define	PCI_DEVICE_ID_TIGON3_5721   0x1659
#define	PCI_DEVICE_ID_TIGON3_5722   0x165a
#define	PCI_DEVICE_ID_TIGON3_5723   0x165b
#define	PCI_DEVICE_ID_TIGON3_5705M   0x165d
#define	PCI_DEVICE_ID_TIGON3_5705M_2   0x165e
#define	PCI_DEVICE_ID_NX2_57712   0x1662
#define	PCI_DEVICE_ID_NX2_57712E   0x1663
#define	PCI_DEVICE_ID_TIGON3_5714   0x1668
#define	PCI_DEVICE_ID_TIGON3_5714S   0x1669
#define	PCI_DEVICE_ID_TIGON3_5780   0x166a
#define	PCI_DEVICE_ID_TIGON3_5780S   0x166b
#define	PCI_DEVICE_ID_TIGON3_5705F   0x166e
#define	PCI_DEVICE_ID_TIGON3_5754M   0x1672
#define	PCI_DEVICE_ID_TIGON3_5755M   0x1673
#define	PCI_DEVICE_ID_TIGON3_5756   0x1674
#define	PCI_DEVICE_ID_TIGON3_5751   0x1677
#define	PCI_DEVICE_ID_TIGON3_5715   0x1678
#define	PCI_DEVICE_ID_TIGON3_5715S   0x1679
#define	PCI_DEVICE_ID_TIGON3_5754   0x167a
#define	PCI_DEVICE_ID_TIGON3_5755   0x167b
#define	PCI_DEVICE_ID_TIGON3_5751M   0x167d
#define	PCI_DEVICE_ID_TIGON3_5751F   0x167e
#define	PCI_DEVICE_ID_TIGON3_5787F   0x167f
#define	PCI_DEVICE_ID_TIGON3_5761E   0x1680
#define	PCI_DEVICE_ID_TIGON3_5761   0x1681
#define	PCI_DEVICE_ID_TIGON3_5764   0x1684
#define	PCI_DEVICE_ID_TIGON3_5787M   0x1693
#define	PCI_DEVICE_ID_TIGON3_5782   0x1696
#define	PCI_DEVICE_ID_TIGON3_5784   0x1698
#define	PCI_DEVICE_ID_TIGON3_5786   0x169a
#define	PCI_DEVICE_ID_TIGON3_5787   0x169b
#define	PCI_DEVICE_ID_TIGON3_5788   0x169c
#define	PCI_DEVICE_ID_TIGON3_5789   0x169d
#define	PCI_DEVICE_ID_TIGON3_5702X   0x16a6
#define	PCI_DEVICE_ID_TIGON3_5703X   0x16a7
#define	PCI_DEVICE_ID_TIGON3_5704S   0x16a8
#define	PCI_DEVICE_ID_NX2_5706S   0x16aa
#define	PCI_DEVICE_ID_NX2_5708S   0x16ac
#define	PCI_DEVICE_ID_TIGON3_5702A3   0x16c6
#define	PCI_DEVICE_ID_TIGON3_5703A3   0x16c7
#define	PCI_DEVICE_ID_TIGON3_5781   0x16dd
#define	PCI_DEVICE_ID_TIGON3_5753   0x16f7
#define	PCI_DEVICE_ID_TIGON3_5753M   0x16fd
#define	PCI_DEVICE_ID_TIGON3_5753F   0x16fe
#define	PCI_DEVICE_ID_TIGON3_5901   0x170d
#define	PCI_DEVICE_ID_TIGON3_5901_2   0x170e
#define	PCI_DEVICE_ID_TIGON3_5906   0x1712
#define	PCI_DEVICE_ID_TIGON3_5906M   0x1713
#define	PCI_VENDOR_ID_COMPAQ   0x0e11
#define	PCI_VENDOR_ID_IBM   0x1014
#define	PCI_VENDOR_ID_DELL   0x1028
#define	PCI_VENDOR_ID_3COM   0x10b7
#define	SPEED_10   10
#define	SPEED_100   100
#define	SPEED_1000   1000
#define	SPEED_UNKNOWN   -1
#define	DUPLEX_HALF   0x00
#define	DUPLEX_FULL   0x01
#define	DUPLEX_UNKNOWN   0xff
#define	TG3_64BIT_REG_HIGH   0x00UL
#define	TG3_64BIT_REG_LOW   0x04UL
#define	TG3_BDINFO_HOST_ADDR   0x0UL /* 64-bit */
#define	TG3_BDINFO_MAXLEN_FLAGS   0x8UL /* 32-bit */
#define	BDINFO_FLAGS_USE_EXT_RECV   0x00000001 /* ext rx_buffer_desc */
#define	BDINFO_FLAGS_DISABLED   0x00000002
#define	BDINFO_FLAGS_MAXLEN_MASK   0xffff0000
#define	BDINFO_FLAGS_MAXLEN_SHIFT   16
#define	TG3_BDINFO_NIC_ADDR   0xcUL /* 32-bit */
#define	TG3_BDINFO_SIZE   0x10UL
#define	RX_STD_MAX_SIZE   1536
#define	TG3_RX_STD_MAX_SIZE_5700   512
#define	TG3_RX_STD_MAX_SIZE_5717   2048
#define	TG3_RX_JMB_MAX_SIZE_5700   256
#define	TG3_RX_JMB_MAX_SIZE_5717   1024
#define	TG3_RX_RET_MAX_SIZE_5700   1024
#define	TG3_RX_RET_MAX_SIZE_5705   512
#define	TG3_RX_RET_MAX_SIZE_5717   4096
#define	TG3PCI_VENDOR   0x00000000
#define	TG3PCI_VENDOR_BROADCOM   0x14e4
#define	TG3PCI_DEVICE   0x00000002
#define	TG3PCI_DEVICE_TIGON3_1   0x1644 /* BCM5700 */
#define	TG3PCI_DEVICE_TIGON3_2   0x1645 /* BCM5701 */
#define	TG3PCI_DEVICE_TIGON3_3   0x1646 /* BCM5702 */
#define	TG3PCI_DEVICE_TIGON3_4   0x1647 /* BCM5703 */
#define	TG3PCI_DEVICE_TIGON3_5761S   0x1688
#define	TG3PCI_DEVICE_TIGON3_5761SE   0x1689
#define	TG3PCI_DEVICE_TIGON3_57780   0x1692
#define	TG3PCI_DEVICE_TIGON3_57760   0x1690
#define	TG3PCI_DEVICE_TIGON3_57790   0x1694
#define	TG3PCI_DEVICE_TIGON3_57788   0x1691
#define	TG3PCI_DEVICE_TIGON3_5785_G   0x1699 /* GPHY */
#define	TG3PCI_DEVICE_TIGON3_5785_F   0x16a0 /* 10/100 only */
#define	TG3PCI_DEVICE_TIGON3_5717   0x1655
#define	TG3PCI_DEVICE_TIGON3_5718   0x1656
#define	TG3PCI_DEVICE_TIGON3_57781   0x16b1
#define	TG3PCI_DEVICE_TIGON3_57785   0x16b5
#define	TG3PCI_DEVICE_TIGON3_57761   0x16b0
#define	TG3PCI_DEVICE_TIGON3_57762   0x1682
#define	TG3PCI_DEVICE_TIGON3_57765   0x16b4
#define	TG3PCI_DEVICE_TIGON3_57766   0x1686
#define	TG3PCI_DEVICE_TIGON3_57791   0x16b2
#define	TG3PCI_DEVICE_TIGON3_57795   0x16b6
#define	TG3PCI_DEVICE_TIGON3_5719   0x1657
#define	TG3PCI_DEVICE_TIGON3_5720   0x165f
#define	TG3PCI_SUBVENDOR_ID_BROADCOM   PCI_VENDOR_ID_BROADCOM
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5   0x0001
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6   0x0002
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9   0x0003
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1   0x0005
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8   0x0006
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7   0x0007
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10   0x0008
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12   0x8008
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1   0x0009
#define	TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2   0x8009
#define	TG3PCI_SUBVENDOR_ID_3COM   PCI_VENDOR_ID_3COM
#define	TG3PCI_SUBDEVICE_ID_3COM_3C996T   0x1000
#define	TG3PCI_SUBDEVICE_ID_3COM_3C996BT   0x1006
#define	TG3PCI_SUBDEVICE_ID_3COM_3C996SX   0x1004
#define	TG3PCI_SUBDEVICE_ID_3COM_3C1000T   0x1007
#define	TG3PCI_SUBDEVICE_ID_3COM_3C940BR01   0x1008
#define	TG3PCI_SUBVENDOR_ID_DELL   PCI_VENDOR_ID_DELL
#define	TG3PCI_SUBDEVICE_ID_DELL_VIPER   0x00d1
#define	TG3PCI_SUBDEVICE_ID_DELL_JAGUAR   0x0106
#define	TG3PCI_SUBDEVICE_ID_DELL_MERLOT   0x0109
#define	TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT   0x010a
#define	TG3PCI_SUBVENDOR_ID_COMPAQ   PCI_VENDOR_ID_COMPAQ
#define	TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE   0x007c
#define	TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2   0x009a
#define	TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING   0x007d
#define	TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780   0x0085
#define	TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2   0x0099
#define	TG3PCI_SUBVENDOR_ID_IBM   PCI_VENDOR_ID_IBM
#define	TG3PCI_SUBDEVICE_ID_IBM_5703SAX2   0x0281
#define	TG3PCI_MSI_DATA   0x00000064
#define	TG3PCI_MISC_HOST_CTRL   0x00000068
#define	MISC_HOST_CTRL_CLEAR_INT   0x00000001
#define	MISC_HOST_CTRL_MASK_PCI_INT   0x00000002
#define	MISC_HOST_CTRL_BYTE_SWAP   0x00000004
#define	MISC_HOST_CTRL_WORD_SWAP   0x00000008
#define	MISC_HOST_CTRL_PCISTATE_RW   0x00000010
#define	MISC_HOST_CTRL_CLKREG_RW   0x00000020
#define	MISC_HOST_CTRL_REGWORD_SWAP   0x00000040
#define	MISC_HOST_CTRL_INDIR_ACCESS   0x00000080
#define	MISC_HOST_CTRL_IRQ_MASK_MODE   0x00000100
#define	MISC_HOST_CTRL_TAGGED_STATUS   0x00000200
#define	MISC_HOST_CTRL_CHIPREV   0xffff0000
#define	MISC_HOST_CTRL_CHIPREV_SHIFT   16
#define	GET_CHIP_REV_ID(MISC_HOST_CTRL)
#define	CHIPREV_ID_5700_A0   0x7000
#define	CHIPREV_ID_5700_A1   0x7001
#define	CHIPREV_ID_5700_B0   0x7100
#define	CHIPREV_ID_5700_B1   0x7101
#define	CHIPREV_ID_5700_B3   0x7102
#define	CHIPREV_ID_5700_ALTIMA   0x7104
#define	CHIPREV_ID_5700_C0   0x7200
#define	CHIPREV_ID_5701_A0   0x0000
#define	CHIPREV_ID_5701_B0   0x0100
#define	CHIPREV_ID_5701_B2   0x0102
#define	CHIPREV_ID_5701_B5   0x0105
#define	CHIPREV_ID_5703_A0   0x1000
#define	CHIPREV_ID_5703_A1   0x1001
#define	CHIPREV_ID_5703_A2   0x1002
#define	CHIPREV_ID_5703_A3   0x1003
#define	CHIPREV_ID_5704_A0   0x2000
#define	CHIPREV_ID_5704_A1   0x2001
#define	CHIPREV_ID_5704_A2   0x2002
#define	CHIPREV_ID_5704_A3   0x2003
#define	CHIPREV_ID_5705_A0   0x3000
#define	CHIPREV_ID_5705_A1   0x3001
#define	CHIPREV_ID_5705_A2   0x3002
#define	CHIPREV_ID_5705_A3   0x3003
#define	CHIPREV_ID_5750_A0   0x4000
#define	CHIPREV_ID_5750_A1   0x4001
#define	CHIPREV_ID_5750_A3   0x4003
#define	CHIPREV_ID_5750_C2   0x4202
#define	CHIPREV_ID_5752_A0_HW   0x5000
#define	CHIPREV_ID_5752_A0   0x6000
#define	CHIPREV_ID_5752_A1   0x6001
#define	CHIPREV_ID_5714_A2   0x9002
#define	CHIPREV_ID_5906_A1   0xc001
#define	CHIPREV_ID_57780_A0   0x57780000
#define	CHIPREV_ID_57780_A1   0x57780001
#define	CHIPREV_ID_5717_A0   0x05717000
#define	CHIPREV_ID_57765_A0   0x57785000
#define	CHIPREV_ID_5719_A0   0x05719000
#define	CHIPREV_ID_5720_A0   0x05720000
#define	GET_ASIC_REV(CHIP_REV_ID)
#define	ASIC_REV_5700   0x07
#define	ASIC_REV_5701   0x00
#define	ASIC_REV_5703   0x01
#define	ASIC_REV_5704   0x02
#define	ASIC_REV_5705   0x03
#define	ASIC_REV_5750   0x04
#define	ASIC_REV_5752   0x06
#define	ASIC_REV_5780   0x08
#define	ASIC_REV_5714   0x09
#define	ASIC_REV_5755   0x0a
#define	ASIC_REV_5787   0x0b
#define	ASIC_REV_5906   0x0c
#define	ASIC_REV_USE_PROD_ID_REG   0x0f
#define	ASIC_REV_5784   0x5784
#define	ASIC_REV_5761   0x5761
#define	ASIC_REV_5785   0x5785
#define	ASIC_REV_57780   0x57780
#define	ASIC_REV_5717   0x5717
#define	ASIC_REV_57765   0x57785
#define	ASIC_REV_57766   0x57766
#define	ASIC_REV_5719   0x5719
#define	ASIC_REV_5720   0x5720
#define	GET_CHIP_REV(CHIP_REV_ID)
#define	CHIPREV_5700_AX   0x70
#define	CHIPREV_5700_BX   0x71
#define	CHIPREV_5700_CX   0x72
#define	CHIPREV_5701_AX   0x00
#define	CHIPREV_5703_AX   0x10
#define	CHIPREV_5704_AX   0x20
#define	CHIPREV_5704_BX   0x21
#define	CHIPREV_5750_AX   0x40
#define	CHIPREV_5750_BX   0x41
#define	CHIPREV_5784_AX   0x57840
#define	CHIPREV_5761_AX   0x57610
#define	CHIPREV_57765_AX   0x577650
#define	GET_METAL_REV(CHIP_REV_ID)
#define	METAL_REV_A0   0x00
#define	METAL_REV_A1   0x01
#define	METAL_REV_B0   0x00
#define	METAL_REV_B1   0x01
#define	METAL_REV_B2   0x02
#define	TG3PCI_DMA_RW_CTRL   0x0000006c
#define	DMA_RWCTRL_DIS_CACHE_ALIGNMENT   0x00000001
#define	DMA_RWCTRL_TAGGED_STAT_WA   0x00000080
#define	DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK   0x00000380
#define	DMA_RWCTRL_READ_BNDRY_MASK   0x00000700
#define	DMA_RWCTRL_READ_BNDRY_DISAB   0x00000000
#define	DMA_RWCTRL_READ_BNDRY_16   0x00000100
#define	DMA_RWCTRL_READ_BNDRY_128_PCIX   0x00000100
#define	DMA_RWCTRL_READ_BNDRY_32   0x00000200
#define	DMA_RWCTRL_READ_BNDRY_256_PCIX   0x00000200
#define	DMA_RWCTRL_READ_BNDRY_64   0x00000300
#define	DMA_RWCTRL_READ_BNDRY_384_PCIX   0x00000300
#define	DMA_RWCTRL_READ_BNDRY_128   0x00000400
#define	DMA_RWCTRL_READ_BNDRY_256   0x00000500
#define	DMA_RWCTRL_READ_BNDRY_512   0x00000600
#define	DMA_RWCTRL_READ_BNDRY_1024   0x00000700
#define	DMA_RWCTRL_WRITE_BNDRY_MASK   0x00003800
#define	DMA_RWCTRL_WRITE_BNDRY_DISAB   0x00000000
#define	DMA_RWCTRL_WRITE_BNDRY_16   0x00000800
#define	DMA_RWCTRL_WRITE_BNDRY_128_PCIX   0x00000800
#define	DMA_RWCTRL_WRITE_BNDRY_32   0x00001000
#define	DMA_RWCTRL_WRITE_BNDRY_256_PCIX   0x00001000
#define	DMA_RWCTRL_WRITE_BNDRY_64   0x00001800
#define	DMA_RWCTRL_WRITE_BNDRY_384_PCIX   0x00001800
#define	DMA_RWCTRL_WRITE_BNDRY_128   0x00002000
#define	DMA_RWCTRL_WRITE_BNDRY_256   0x00002800
#define	DMA_RWCTRL_WRITE_BNDRY_512   0x00003000
#define	DMA_RWCTRL_WRITE_BNDRY_1024   0x00003800
#define	DMA_RWCTRL_ONE_DMA   0x00004000
#define	DMA_RWCTRL_READ_WATER   0x00070000
#define	DMA_RWCTRL_READ_WATER_SHIFT   16
#define	DMA_RWCTRL_WRITE_WATER   0x00380000
#define	DMA_RWCTRL_WRITE_WATER_SHIFT   19
#define	DMA_RWCTRL_USE_MEM_READ_MULT   0x00400000
#define	DMA_RWCTRL_ASSERT_ALL_BE   0x00800000
#define	DMA_RWCTRL_PCI_READ_CMD   0x0f000000
#define	DMA_RWCTRL_PCI_READ_CMD_SHIFT   24
#define	DMA_RWCTRL_PCI_WRITE_CMD   0xf0000000
#define	DMA_RWCTRL_PCI_WRITE_CMD_SHIFT   28
#define	DMA_RWCTRL_WRITE_BNDRY_64_PCIE   0x10000000
#define	DMA_RWCTRL_WRITE_BNDRY_128_PCIE   0x30000000
#define	DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE   0x70000000
#define	TG3PCI_PCISTATE   0x00000070
#define	PCISTATE_FORCE_RESET   0x00000001
#define	PCISTATE_INT_NOT_ACTIVE   0x00000002
#define	PCISTATE_CONV_PCI_MODE   0x00000004
#define	PCISTATE_BUS_SPEED_HIGH   0x00000008
#define	PCISTATE_BUS_32BIT   0x00000010
#define	PCISTATE_ROM_ENABLE   0x00000020
#define	PCISTATE_ROM_RETRY_ENABLE   0x00000040
#define	PCISTATE_FLAT_VIEW   0x00000100
#define	PCISTATE_RETRY_SAME_DMA   0x00002000
#define	PCISTATE_ALLOW_APE_CTLSPC_WR   0x00010000
#define	PCISTATE_ALLOW_APE_SHMEM_WR   0x00020000
#define	PCISTATE_ALLOW_APE_PSPACE_WR   0x00040000
#define	TG3PCI_CLOCK_CTRL   0x00000074
#define	CLOCK_CTRL_CORECLK_DISABLE   0x00000200
#define	CLOCK_CTRL_RXCLK_DISABLE   0x00000400
#define	CLOCK_CTRL_TXCLK_DISABLE   0x00000800
#define	CLOCK_CTRL_ALTCLK   0x00001000
#define	CLOCK_CTRL_PWRDOWN_PLL133   0x00008000
#define	CLOCK_CTRL_44MHZ_CORE   0x00040000
#define	CLOCK_CTRL_625_CORE   0x00100000
#define	CLOCK_CTRL_FORCE_CLKRUN   0x00200000
#define	CLOCK_CTRL_CLKRUN_OENABLE   0x00400000
#define	CLOCK_CTRL_DELAY_PCI_GRANT   0x80000000
#define	TG3PCI_REG_BASE_ADDR   0x00000078
#define	TG3PCI_MEM_WIN_BASE_ADDR   0x0000007c
#define	TG3PCI_REG_DATA   0x00000080
#define	TG3PCI_MEM_WIN_DATA   0x00000084
#define	TG3PCI_MISC_LOCAL_CTRL   0x00000090
#define	TG3PCI_STD_RING_PROD_IDX   0x00000098 /* 64-bit */
#define	TG3PCI_RCV_RET_RING_CON_IDX   0x000000a0 /* 64-bit */
#define	TG3PCI_DUAL_MAC_CTRL   0x000000b8
#define	DUAL_MAC_CTRL_CH_MASK   0x00000003
#define	DUAL_MAC_CTRL_ID   0x00000004
#define	TG3PCI_PRODID_ASICREV   0x000000bc
#define	PROD_ID_ASIC_REV_MASK   0x0fffffff
#define	TG3PCI_GEN2_PRODID_ASICREV   0x000000f4
#define	TG3PCI_GEN15_PRODID_ASICREV   0x000000fc
#define	TG3_CORR_ERR_STAT   0x00000110
#define	TG3_CORR_ERR_STAT_CLEAR   0xffffffff
#define	MAILBOX_INTERRUPT_0   0x00000200 /* 64-bit */
#define	MAILBOX_INTERRUPT_1   0x00000208 /* 64-bit */
#define	MAILBOX_INTERRUPT_2   0x00000210 /* 64-bit */
#define	MAILBOX_INTERRUPT_3   0x00000218 /* 64-bit */
#define	MAILBOX_GENERAL_0   0x00000220 /* 64-bit */
#define	MAILBOX_GENERAL_1   0x00000228 /* 64-bit */
#define	MAILBOX_GENERAL_2   0x00000230 /* 64-bit */
#define	MAILBOX_GENERAL_3   0x00000238 /* 64-bit */
#define	MAILBOX_GENERAL_4   0x00000240 /* 64-bit */
#define	MAILBOX_GENERAL_5   0x00000248 /* 64-bit */
#define	MAILBOX_GENERAL_6   0x00000250 /* 64-bit */
#define	MAILBOX_GENERAL_7   0x00000258 /* 64-bit */
#define	MAILBOX_RELOAD_STAT   0x00000260 /* 64-bit */
#define	MAILBOX_RCV_STD_PROD_IDX   0x00000268 /* 64-bit */
#define	TG3_RX_STD_PROD_IDX_REG
#define	MAILBOX_RCV_JUMBO_PROD_IDX   0x00000270 /* 64-bit */
#define	TG3_RX_JMB_PROD_IDX_REG
#define	MAILBOX_RCV_MINI_PROD_IDX   0x00000278 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_0   0x00000280 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_1   0x00000288 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_2   0x00000290 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_3   0x00000298 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_4   0x000002a0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_5   0x000002a8 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_6   0x000002b0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_7   0x000002b8 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_8   0x000002c0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_9   0x000002c8 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_10   0x000002d0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_11   0x000002d8 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_12   0x000002e0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_13   0x000002e8 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_14   0x000002f0 /* 64-bit */
#define	MAILBOX_RCVRET_CON_IDX_15   0x000002f8 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_0   0x00000300 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_1   0x00000308 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_2   0x00000310 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_3   0x00000318 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_4   0x00000320 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_5   0x00000328 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_6   0x00000330 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_7   0x00000338 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_8   0x00000340 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_9   0x00000348 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_10   0x00000350 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_11   0x00000358 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_12   0x00000360 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_13   0x00000368 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_14   0x00000370 /* 64-bit */
#define	MAILBOX_SNDHOST_PROD_IDX_15   0x00000378 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_0   0x00000380 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_1   0x00000388 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_2   0x00000390 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_3   0x00000398 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_4   0x000003a0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_5   0x000003a8 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_6   0x000003b0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_7   0x000003b8 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_8   0x000003c0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_9   0x000003c8 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_10   0x000003d0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_11   0x000003d8 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_12   0x000003e0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_13   0x000003e8 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_14   0x000003f0 /* 64-bit */
#define	MAILBOX_SNDNIC_PROD_IDX_15   0x000003f8 /* 64-bit */
#define	MAC_MODE   0x00000400
#define	MAC_MODE_RESET   0x00000001
#define	MAC_MODE_HALF_DUPLEX   0x00000002
#define	MAC_MODE_PORT_MODE_MASK   0x0000000c
#define	MAC_MODE_PORT_MODE_TBI   0x0000000c
#define	MAC_MODE_PORT_MODE_GMII   0x00000008
#define	MAC_MODE_PORT_MODE_MII   0x00000004
#define	MAC_MODE_PORT_MODE_NONE   0x00000000
#define	MAC_MODE_PORT_INT_LPBACK   0x00000010
#define	MAC_MODE_TAGGED_MAC_CTRL   0x00000080
#define	MAC_MODE_TX_BURSTING   0x00000100
#define	MAC_MODE_MAX_DEFER   0x00000200
#define	MAC_MODE_LINK_POLARITY   0x00000400
#define	MAC_MODE_RXSTAT_ENABLE   0x00000800
#define	MAC_MODE_RXSTAT_CLEAR   0x00001000
#define	MAC_MODE_RXSTAT_FLUSH   0x00002000
#define	MAC_MODE_TXSTAT_ENABLE   0x00004000
#define	MAC_MODE_TXSTAT_CLEAR   0x00008000
#define	MAC_MODE_TXSTAT_FLUSH   0x00010000
#define	MAC_MODE_SEND_CONFIGS   0x00020000
#define	MAC_MODE_MAGIC_PKT_ENABLE   0x00040000
#define	MAC_MODE_ACPI_ENABLE   0x00080000
#define	MAC_MODE_MIP_ENABLE   0x00100000
#define	MAC_MODE_TDE_ENABLE   0x00200000
#define	MAC_MODE_RDE_ENABLE   0x00400000
#define	MAC_MODE_FHDE_ENABLE   0x00800000
#define	MAC_MODE_KEEP_FRAME_IN_WOL   0x01000000
#define	MAC_MODE_APE_RX_EN   0x08000000
#define	MAC_MODE_APE_TX_EN   0x10000000
#define	MAC_STATUS   0x00000404
#define	MAC_STATUS_PCS_SYNCED   0x00000001
#define	MAC_STATUS_SIGNAL_DET   0x00000002
#define	MAC_STATUS_RCVD_CFG   0x00000004
#define	MAC_STATUS_CFG_CHANGED   0x00000008
#define	MAC_STATUS_SYNC_CHANGED   0x00000010
#define	MAC_STATUS_PORT_DEC_ERR   0x00000400
#define	MAC_STATUS_LNKSTATE_CHANGED   0x00001000
#define	MAC_STATUS_MI_COMPLETION   0x00400000
#define	MAC_STATUS_MI_INTERRUPT   0x00800000
#define	MAC_STATUS_AP_ERROR   0x01000000
#define	MAC_STATUS_ODI_ERROR   0x02000000
#define	MAC_STATUS_RXSTAT_OVERRUN   0x04000000
#define	MAC_STATUS_TXSTAT_OVERRUN   0x08000000
#define	MAC_EVENT   0x00000408
#define	MAC_EVENT_PORT_DECODE_ERR   0x00000400
#define	MAC_EVENT_LNKSTATE_CHANGED   0x00001000
#define	MAC_EVENT_MI_COMPLETION   0x00400000
#define	MAC_EVENT_MI_INTERRUPT   0x00800000
#define	MAC_EVENT_AP_ERROR   0x01000000
#define	MAC_EVENT_ODI_ERROR   0x02000000
#define	MAC_EVENT_RXSTAT_OVERRUN   0x04000000
#define	MAC_EVENT_TXSTAT_OVERRUN   0x08000000
#define	MAC_LED_CTRL   0x0000040c
#define	LED_CTRL_LNKLED_OVERRIDE   0x00000001
#define	LED_CTRL_1000MBPS_ON   0x00000002
#define	LED_CTRL_100MBPS_ON   0x00000004
#define	LED_CTRL_10MBPS_ON   0x00000008
#define	LED_CTRL_TRAFFIC_OVERRIDE   0x00000010
#define	LED_CTRL_TRAFFIC_BLINK   0x00000020
#define	LED_CTRL_TRAFFIC_LED   0x00000040
#define	LED_CTRL_1000MBPS_STATUS   0x00000080
#define	LED_CTRL_100MBPS_STATUS   0x00000100
#define	LED_CTRL_10MBPS_STATUS   0x00000200
#define	LED_CTRL_TRAFFIC_STATUS   0x00000400
#define	LED_CTRL_MODE_MAC   0x00000000
#define	LED_CTRL_MODE_PHY_1   0x00000800
#define	LED_CTRL_MODE_PHY_2   0x00001000
#define	LED_CTRL_MODE_SHASTA_MAC   0x00002000
#define	LED_CTRL_MODE_SHARED   0x00004000
#define	LED_CTRL_MODE_COMBO   0x00008000
#define	LED_CTRL_BLINK_RATE_MASK   0x7ff80000
#define	LED_CTRL_BLINK_RATE_SHIFT   19
#define	LED_CTRL_BLINK_PER_OVERRIDE   0x00080000
#define	LED_CTRL_BLINK_RATE_OVERRIDE   0x80000000
#define	MAC_ADDR_0_HIGH   0x00000410 /* upper 2 bytes */
#define	MAC_ADDR_0_LOW   0x00000414 /* lower 4 bytes */
#define	MAC_ADDR_1_HIGH   0x00000418 /* upper 2 bytes */
#define	MAC_ADDR_1_LOW   0x0000041c /* lower 4 bytes */
#define	MAC_ADDR_2_HIGH   0x00000420 /* upper 2 bytes */
#define	MAC_ADDR_2_LOW   0x00000424 /* lower 4 bytes */
#define	MAC_ADDR_3_HIGH   0x00000428 /* upper 2 bytes */
#define	MAC_ADDR_3_LOW   0x0000042c /* lower 4 bytes */
#define	MAC_ACPI_MBUF_PTR   0x00000430
#define	MAC_ACPI_LEN_OFFSET   0x00000434
#define	ACPI_LENOFF_LEN_MASK   0x0000ffff
#define	ACPI_LENOFF_LEN_SHIFT   0
#define	ACPI_LENOFF_OFF_MASK   0x0fff0000
#define	ACPI_LENOFF_OFF_SHIFT   16
#define	MAC_TX_BACKOFF_SEED   0x00000438
#define	TX_BACKOFF_SEED_MASK   0x000003ff
#define	MAC_RX_MTU_SIZE   0x0000043c
#define	RX_MTU_SIZE_MASK   0x0000ffff
#define	MAC_PCS_TEST   0x00000440
#define	PCS_TEST_PATTERN_MASK   0x000fffff
#define	PCS_TEST_PATTERN_SHIFT   0
#define	PCS_TEST_ENABLE   0x00100000
#define	MAC_TX_AUTO_NEG   0x00000444
#define	TX_AUTO_NEG_MASK   0x0000ffff
#define	TX_AUTO_NEG_SHIFT   0
#define	MAC_RX_AUTO_NEG   0x00000448
#define	RX_AUTO_NEG_MASK   0x0000ffff
#define	RX_AUTO_NEG_SHIFT   0
#define	MAC_MI_COM   0x0000044c
#define	MI_COM_CMD_MASK   0x0c000000
#define	MI_COM_CMD_WRITE   0x04000000
#define	MI_COM_CMD_READ   0x08000000
#define	MI_COM_READ_FAILED   0x10000000
#define	MI_COM_START   0x20000000
#define	MI_COM_BUSY   0x20000000
#define	MI_COM_PHY_ADDR_MASK   0x03e00000
#define	MI_COM_PHY_ADDR_SHIFT   21
#define	MI_COM_REG_ADDR_MASK   0x001f0000
#define	MI_COM_REG_ADDR_SHIFT   16
#define	MI_COM_DATA_MASK   0x0000ffff
#define	MAC_MI_STAT   0x00000450
#define	MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001
#define	MAC_MI_STAT_10MBPS_MODE   0x00000002
#define	MAC_MI_MODE   0x00000454
#define	MAC_MI_MODE_CLK_10MHZ   0x00000001
#define	MAC_MI_MODE_SHORT_PREAMBLE   0x00000002
#define	MAC_MI_MODE_AUTO_POLL   0x00000010
#define	MAC_MI_MODE_500KHZ_CONST   0x00008000
#define	MAC_MI_MODE_BASE   0x000c0000 /* XXX magic values XXX */
#define	MAC_AUTO_POLL_STATUS   0x00000458
#define	MAC_AUTO_POLL_ERROR   0x00000001
#define	MAC_TX_MODE   0x0000045c
#define	TX_MODE_RESET   0x00000001
#define	TX_MODE_ENABLE   0x00000002
#define	TX_MODE_FLOW_CTRL_ENABLE   0x00000010
#define	TX_MODE_BIG_BCKOFF_ENABLE   0x00000020
#define	TX_MODE_LONG_PAUSE_ENABLE   0x00000040
#define	TX_MODE_MBUF_LOCKUP_FIX   0x00000100
#define	TX_MODE_JMB_FRM_LEN   0x00400000
#define	TX_MODE_CNT_DN_MODE   0x00800000
#define	MAC_TX_STATUS   0x00000460
#define	TX_STATUS_XOFFED   0x00000001
#define	TX_STATUS_SENT_XOFF   0x00000002
#define	TX_STATUS_SENT_XON   0x00000004
#define	TX_STATUS_LINK_UP   0x00000008
#define	TX_STATUS_ODI_UNDERRUN   0x00000010
#define	TX_STATUS_ODI_OVERRUN   0x00000020
#define	MAC_TX_LENGTHS   0x00000464
#define	TX_LENGTHS_SLOT_TIME_MASK   0x000000ff
#define	TX_LENGTHS_SLOT_TIME_SHIFT   0
#define	TX_LENGTHS_IPG_MASK   0x00000f00
#define	TX_LENGTHS_IPG_SHIFT   8
#define	TX_LENGTHS_IPG_CRS_MASK   0x00003000
#define	TX_LENGTHS_IPG_CRS_SHIFT   12
#define	TX_LENGTHS_JMB_FRM_LEN_MSK   0x00ff0000
#define	TX_LENGTHS_CNT_DWN_VAL_MSK   0xff000000
#define	MAC_RX_MODE   0x00000468
#define	RX_MODE_RESET   0x00000001
#define	RX_MODE_ENABLE   0x00000002
#define	RX_MODE_FLOW_CTRL_ENABLE   0x00000004
#define	RX_MODE_KEEP_MAC_CTRL   0x00000008
#define	RX_MODE_KEEP_PAUSE   0x00000010
#define	RX_MODE_ACCEPT_OVERSIZED   0x00000020
#define	RX_MODE_ACCEPT_RUNTS   0x00000040
#define	RX_MODE_LEN_CHECK   0x00000080
#define	RX_MODE_PROMISC   0x00000100
#define	RX_MODE_NO_CRC_CHECK   0x00000200
#define	RX_MODE_KEEP_VLAN_TAG   0x00000400
#define	RX_MODE_RSS_IPV4_HASH_EN   0x00010000
#define	RX_MODE_RSS_TCP_IPV4_HASH_EN   0x00020000
#define	RX_MODE_RSS_IPV6_HASH_EN   0x00040000
#define	RX_MODE_RSS_TCP_IPV6_HASH_EN   0x00080000
#define	RX_MODE_RSS_ITBL_HASH_BITS_7   0x00700000
#define	RX_MODE_RSS_ENABLE   0x00800000
#define	RX_MODE_IPV6_CSUM_ENABLE   0x01000000
#define	MAC_RX_STATUS   0x0000046c
#define	RX_STATUS_REMOTE_TX_XOFFED   0x00000001
#define	RX_STATUS_XOFF_RCVD   0x00000002
#define	RX_STATUS_XON_RCVD   0x00000004
#define	MAC_HASH_REG_0   0x00000470
#define	MAC_HASH_REG_1   0x00000474
#define	MAC_HASH_REG_2   0x00000478
#define	MAC_HASH_REG_3   0x0000047c
#define	MAC_RCV_RULE_0   0x00000480
#define	MAC_RCV_VALUE_0   0x00000484
#define	MAC_RCV_RULE_1   0x00000488
#define	MAC_RCV_VALUE_1   0x0000048c
#define	MAC_RCV_RULE_2   0x00000490
#define	MAC_RCV_VALUE_2   0x00000494
#define	MAC_RCV_RULE_3   0x00000498
#define	MAC_RCV_VALUE_3   0x0000049c
#define	MAC_RCV_RULE_4   0x000004a0
#define	MAC_RCV_VALUE_4   0x000004a4
#define	MAC_RCV_RULE_5   0x000004a8
#define	MAC_RCV_VALUE_5   0x000004ac
#define	MAC_RCV_RULE_6   0x000004b0
#define	MAC_RCV_VALUE_6   0x000004b4
#define	MAC_RCV_RULE_7   0x000004b8
#define	MAC_RCV_VALUE_7   0x000004bc
#define	MAC_RCV_RULE_8   0x000004c0
#define	MAC_RCV_VALUE_8   0x000004c4
#define	MAC_RCV_RULE_9   0x000004c8
#define	MAC_RCV_VALUE_9   0x000004cc
#define	MAC_RCV_RULE_10   0x000004d0
#define	MAC_RCV_VALUE_10   0x000004d4
#define	MAC_RCV_RULE_11   0x000004d8
#define	MAC_RCV_VALUE_11   0x000004dc
#define	MAC_RCV_RULE_12   0x000004e0
#define	MAC_RCV_VALUE_12   0x000004e4
#define	MAC_RCV_RULE_13   0x000004e8
#define	MAC_RCV_VALUE_13   0x000004ec
#define	MAC_RCV_RULE_14   0x000004f0
#define	MAC_RCV_VALUE_14   0x000004f4
#define	MAC_RCV_RULE_15   0x000004f8
#define	MAC_RCV_VALUE_15   0x000004fc
#define	RCV_RULE_DISABLE_MASK   0x7fffffff
#define	MAC_RCV_RULE_CFG   0x00000500
#define	RCV_RULE_CFG_DEFAULT_CLASS   0x00000008
#define	MAC_LOW_WMARK_MAX_RX_FRAME   0x00000504
#define	MAC_HASHREGU_0   0x00000520
#define	MAC_HASHREGU_1   0x00000524
#define	MAC_HASHREGU_2   0x00000528
#define	MAC_HASHREGU_3   0x0000052c
#define	MAC_EXTADDR_0_HIGH   0x00000530
#define	MAC_EXTADDR_0_LOW   0x00000534
#define	MAC_EXTADDR_1_HIGH   0x00000538
#define	MAC_EXTADDR_1_LOW   0x0000053c
#define	MAC_EXTADDR_2_HIGH   0x00000540
#define	MAC_EXTADDR_2_LOW   0x00000544
#define	MAC_EXTADDR_3_HIGH   0x00000548
#define	MAC_EXTADDR_3_LOW   0x0000054c
#define	MAC_EXTADDR_4_HIGH   0x00000550
#define	MAC_EXTADDR_4_LOW   0x00000554
#define	MAC_EXTADDR_5_HIGH   0x00000558
#define	MAC_EXTADDR_5_LOW   0x0000055c
#define	MAC_EXTADDR_6_HIGH   0x00000560
#define	MAC_EXTADDR_6_LOW   0x00000564
#define	MAC_EXTADDR_7_HIGH   0x00000568
#define	MAC_EXTADDR_7_LOW   0x0000056c
#define	MAC_EXTADDR_8_HIGH   0x00000570
#define	MAC_EXTADDR_8_LOW   0x00000574
#define	MAC_EXTADDR_9_HIGH   0x00000578
#define	MAC_EXTADDR_9_LOW   0x0000057c
#define	MAC_EXTADDR_10_HIGH   0x00000580
#define	MAC_EXTADDR_10_LOW   0x00000584
#define	MAC_EXTADDR_11_HIGH   0x00000588
#define	MAC_EXTADDR_11_LOW   0x0000058c
#define	MAC_SERDES_CFG   0x00000590
#define	MAC_SERDES_CFG_EDGE_SELECT   0x00001000
#define	MAC_SERDES_STAT   0x00000594
#define	MAC_PHYCFG1   0x000005a0
#define	MAC_PHYCFG1_RGMII_INT   0x00000001
#define	MAC_PHYCFG1_RXCLK_TO_MASK   0x00001ff0
#define	MAC_PHYCFG1_RXCLK_TIMEOUT   0x00001000
#define	MAC_PHYCFG1_TXCLK_TO_MASK   0x01ff0000
#define	MAC_PHYCFG1_TXCLK_TIMEOUT   0x01000000
#define	MAC_PHYCFG1_RGMII_EXT_RX_DEC   0x02000000
#define	MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000
#define	MAC_PHYCFG1_TXC_DRV   0x20000000
#define	MAC_PHYCFG2   0x000005a4
#define	MAC_PHYCFG2_INBAND_ENABLE   0x00000001
#define	MAC_PHYCFG2_EMODE_MASK_MASK   0x000001c0
#define	MAC_PHYCFG2_EMODE_MASK_AC131   0x000000c0
#define	MAC_PHYCFG2_EMODE_MASK_50610   0x00000100
#define	MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000
#define	MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0
#define	MAC_PHYCFG2_EMODE_COMP_MASK   0x00000e00
#define	MAC_PHYCFG2_EMODE_COMP_AC131   0x00000600
#define	MAC_PHYCFG2_EMODE_COMP_50610   0x00000400
#define	MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800
#define	MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000
#define	MAC_PHYCFG2_FMODE_MASK_MASK   0x00007000
#define	MAC_PHYCFG2_FMODE_MASK_AC131   0x00006000
#define	MAC_PHYCFG2_FMODE_MASK_50610   0x00004000
#define	MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000
#define	MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000
#define	MAC_PHYCFG2_FMODE_COMP_MASK   0x00038000
#define	MAC_PHYCFG2_FMODE_COMP_AC131   0x00030000
#define	MAC_PHYCFG2_FMODE_COMP_50610   0x00008000
#define	MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000
#define	MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000
#define	MAC_PHYCFG2_GMODE_MASK_MASK   0x001c0000
#define	MAC_PHYCFG2_GMODE_MASK_AC131   0x001c0000
#define	MAC_PHYCFG2_GMODE_MASK_50610   0x00100000
#define	MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000
#define	MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000
#define	MAC_PHYCFG2_GMODE_COMP_MASK   0x00e00000
#define	MAC_PHYCFG2_GMODE_COMP_AC131   0x00e00000
#define	MAC_PHYCFG2_GMODE_COMP_50610   0x00000000
#define	MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000
#define	MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000
#define	MAC_PHYCFG2_ACT_MASK_MASK   0x03000000
#define	MAC_PHYCFG2_ACT_MASK_AC131   0x03000000
#define	MAC_PHYCFG2_ACT_MASK_50610   0x01000000
#define	MAC_PHYCFG2_ACT_MASK_RT8211   0x03000000
#define	MAC_PHYCFG2_ACT_MASK_RT8201   0x01000000
#define	MAC_PHYCFG2_ACT_COMP_MASK   0x0c000000
#define	MAC_PHYCFG2_ACT_COMP_AC131   0x00000000
#define	MAC_PHYCFG2_ACT_COMP_50610   0x00000000
#define	MAC_PHYCFG2_ACT_COMP_RT8211   0x00000000
#define	MAC_PHYCFG2_ACT_COMP_RT8201   0x08000000
#define	MAC_PHYCFG2_QUAL_MASK_MASK   0x30000000
#define	MAC_PHYCFG2_QUAL_MASK_AC131   0x30000000
#define	MAC_PHYCFG2_QUAL_MASK_50610   0x30000000
#define	MAC_PHYCFG2_QUAL_MASK_RT8211   0x30000000
#define	MAC_PHYCFG2_QUAL_MASK_RT8201   0x30000000
#define	MAC_PHYCFG2_QUAL_COMP_MASK   0xc0000000
#define	MAC_PHYCFG2_QUAL_COMP_AC131   0x00000000
#define	MAC_PHYCFG2_QUAL_COMP_50610   0x00000000
#define	MAC_PHYCFG2_QUAL_COMP_RT8211   0x00000000
#define	MAC_PHYCFG2_QUAL_COMP_RT8201   0x00000000
#define	MAC_PHYCFG2_50610_LED_MODES
#define	MAC_PHYCFG2_AC131_LED_MODES
#define	MAC_PHYCFG2_RTL8211C_LED_MODES
#define	MAC_PHYCFG2_RTL8201E_LED_MODES
#define	MAC_EXT_RGMII_MODE   0x000005a8
#define	MAC_RGMII_MODE_TX_ENABLE   0x00000001
#define	MAC_RGMII_MODE_TX_LOWPWR   0x00000002
#define	MAC_RGMII_MODE_TX_RESET   0x00000004
#define	MAC_RGMII_MODE_RX_INT_B   0x00000100
#define	MAC_RGMII_MODE_RX_QUALITY   0x00000200
#define	MAC_RGMII_MODE_RX_ACTIVITY   0x00000400
#define	MAC_RGMII_MODE_RX_ENG_DET   0x00000800
#define	SERDES_RX_CTRL   0x000005b0 /* 5780/5714 only */
#define	SERDES_RX_SIG_DETECT   0x00000400
#define	SG_DIG_CTRL   0x000005b0
#define	SG_DIG_USING_HW_AUTONEG   0x80000000
#define	SG_DIG_SOFT_RESET   0x40000000
#define	SG_DIG_DISABLE_LINKRDY   0x20000000
#define	SG_DIG_CRC16_CLEAR_N   0x01000000
#define	SG_DIG_EN10B   0x00800000
#define	SG_DIG_CLEAR_STATUS   0x00400000
#define	SG_DIG_LOCAL_DUPLEX_STATUS   0x00200000
#define	SG_DIG_LOCAL_LINK_STATUS   0x00100000
#define	SG_DIG_SPEED_STATUS_MASK   0x000c0000
#define	SG_DIG_SPEED_STATUS_SHIFT   18
#define	SG_DIG_JUMBO_PACKET_DISABLE   0x00020000
#define	SG_DIG_RESTART_AUTONEG   0x00010000
#define	SG_DIG_FIBER_MODE   0x00008000
#define	SG_DIG_REMOTE_FAULT_MASK   0x00006000
#define	SG_DIG_PAUSE_MASK   0x00001800
#define	SG_DIG_PAUSE_CAP   0x00000800
#define	SG_DIG_ASYM_PAUSE   0x00001000
#define	SG_DIG_GBIC_ENABLE   0x00000400
#define	SG_DIG_CHECK_END_ENABLE   0x00000200
#define	SG_DIG_SGMII_AUTONEG_TIMER   0x00000100
#define	SG_DIG_CLOCK_PHASE_SELECT   0x00000080
#define	SG_DIG_GMII_INPUT_SELECT   0x00000040
#define	SG_DIG_MRADV_CRC16_SELECT   0x00000020
#define	SG_DIG_COMMA_DETECT_ENABLE   0x00000010
#define	SG_DIG_AUTONEG_TIMER_REDUCE   0x00000008
#define	SG_DIG_AUTONEG_LOW_ENABLE   0x00000004
#define	SG_DIG_REMOTE_LOOPBACK   0x00000002
#define	SG_DIG_LOOPBACK   0x00000001
#define	SG_DIG_COMMON_SETUP
#define	SG_DIG_STATUS   0x000005b4
#define	SG_DIG_CRC16_BUS_MASK   0xffff0000
#define	SG_DIG_PARTNER_FAULT_MASK   0x00600000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_PARTNER_ASYM_PAUSE   0x00100000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_PARTNER_PAUSE_CAPABLE   0x00080000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_PARTNER_HALF_DUPLEX   0x00040000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_PARTNER_FULL_DUPLEX   0x00020000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_PARTNER_NEXT_PAGE   0x00010000 /* If !MRADV_CRC16_SELECT */
#define	SG_DIG_AUTONEG_STATE_MASK   0x00000ff0
#define	SG_DIG_IS_SERDES   0x00000100
#define	SG_DIG_COMMA_DETECTOR   0x00000008
#define	SG_DIG_MAC_ACK_STATUS   0x00000004
#define	SG_DIG_AUTONEG_COMPLETE   0x00000002
#define	SG_DIG_AUTONEG_ERROR   0x00000001
#define	MAC_TX_MAC_STATE_BASE   0x00000600 /* 16 bytes */
#define	MAC_RX_MAC_STATE_BASE   0x00000610 /* 20 bytes */
#define	MAC_RSS_INDIR_TBL_0   0x00000630
#define	MAC_RSS_HASH_KEY_0   0x00000670
#define	MAC_RSS_HASH_KEY_1   0x00000674
#define	MAC_RSS_HASH_KEY_2   0x00000678
#define	MAC_RSS_HASH_KEY_3   0x0000067c
#define	MAC_RSS_HASH_KEY_4   0x00000680
#define	MAC_RSS_HASH_KEY_5   0x00000684
#define	MAC_RSS_HASH_KEY_6   0x00000688
#define	MAC_RSS_HASH_KEY_7   0x0000068c
#define	MAC_RSS_HASH_KEY_8   0x00000690
#define	MAC_RSS_HASH_KEY_9   0x00000694
#define	MAC_TX_STATS_OCTETS   0x00000800
#define	MAC_TX_STATS_RESV1   0x00000804
#define	MAC_TX_STATS_COLLISIONS   0x00000808
#define	MAC_TX_STATS_XON_SENT   0x0000080c
#define	MAC_TX_STATS_XOFF_SENT   0x00000810
#define	MAC_TX_STATS_RESV2   0x00000814
#define	MAC_TX_STATS_MAC_ERRORS   0x00000818
#define	MAC_TX_STATS_SINGLE_COLLISIONS   0x0000081c
#define	MAC_TX_STATS_MULT_COLLISIONS   0x00000820
#define	MAC_TX_STATS_DEFERRED   0x00000824
#define	MAC_TX_STATS_RESV3   0x00000828
#define	MAC_TX_STATS_EXCESSIVE_COL   0x0000082c
#define	MAC_TX_STATS_LATE_COL   0x00000830
#define	MAC_TX_STATS_RESV4_1   0x00000834
#define	MAC_TX_STATS_RESV4_2   0x00000838
#define	MAC_TX_STATS_RESV4_3   0x0000083c
#define	MAC_TX_STATS_RESV4_4   0x00000840
#define	MAC_TX_STATS_RESV4_5   0x00000844
#define	MAC_TX_STATS_RESV4_6   0x00000848
#define	MAC_TX_STATS_RESV4_7   0x0000084c
#define	MAC_TX_STATS_RESV4_8   0x00000850
#define	MAC_TX_STATS_RESV4_9   0x00000854
#define	MAC_TX_STATS_RESV4_10   0x00000858
#define	MAC_TX_STATS_RESV4_11   0x0000085c
#define	MAC_TX_STATS_RESV4_12   0x00000860
#define	MAC_TX_STATS_RESV4_13   0x00000864
#define	MAC_TX_STATS_RESV4_14   0x00000868
#define	MAC_TX_STATS_UCAST   0x0000086c
#define	MAC_TX_STATS_MCAST   0x00000870
#define	MAC_TX_STATS_BCAST   0x00000874
#define	MAC_TX_STATS_RESV5_1   0x00000878
#define	MAC_TX_STATS_RESV5_2   0x0000087c
#define	MAC_RX_STATS_OCTETS   0x00000880
#define	MAC_RX_STATS_RESV1   0x00000884
#define	MAC_RX_STATS_FRAGMENTS   0x00000888
#define	MAC_RX_STATS_UCAST   0x0000088c
#define	MAC_RX_STATS_MCAST   0x00000890
#define	MAC_RX_STATS_BCAST   0x00000894
#define	MAC_RX_STATS_FCS_ERRORS   0x00000898
#define	MAC_RX_STATS_ALIGN_ERRORS   0x0000089c
#define	MAC_RX_STATS_XON_PAUSE_RECVD   0x000008a0
#define	MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4
#define	MAC_RX_STATS_MAC_CTRL_RECVD   0x000008a8
#define	MAC_RX_STATS_XOFF_ENTERED   0x000008ac
#define	MAC_RX_STATS_FRAME_TOO_LONG   0x000008b0
#define	MAC_RX_STATS_JABBERS   0x000008b4
#define	MAC_RX_STATS_UNDERSIZE   0x000008b8
#define	SNDDATAI_MODE   0x00000c00
#define	SNDDATAI_MODE_RESET   0x00000001
#define	SNDDATAI_MODE_ENABLE   0x00000002
#define	SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004
#define	SNDDATAI_STATUS   0x00000c04
#define	SNDDATAI_STATUS_STAT_OFLOW   0x00000004
#define	SNDDATAI_STATSCTRL   0x00000c08
#define	SNDDATAI_SCTRL_ENABLE   0x00000001
#define	SNDDATAI_SCTRL_FASTUPD   0x00000002
#define	SNDDATAI_SCTRL_CLEAR   0x00000004
#define	SNDDATAI_SCTRL_FLUSH   0x00000008
#define	SNDDATAI_SCTRL_FORCE_ZERO   0x00000010
#define	SNDDATAI_STATSENAB   0x00000c0c
#define	SNDDATAI_STATSINCMASK   0x00000c10
#define	ISO_PKT_TX   0x00000c20
#define	SNDDATAI_COS_CNT_0   0x00000c80
#define	SNDDATAI_COS_CNT_1   0x00000c84
#define	SNDDATAI_COS_CNT_2   0x00000c88
#define	SNDDATAI_COS_CNT_3   0x00000c8c
#define	SNDDATAI_COS_CNT_4   0x00000c90
#define	SNDDATAI_COS_CNT_5   0x00000c94
#define	SNDDATAI_COS_CNT_6   0x00000c98
#define	SNDDATAI_COS_CNT_7   0x00000c9c
#define	SNDDATAI_COS_CNT_8   0x00000ca0
#define	SNDDATAI_COS_CNT_9   0x00000ca4
#define	SNDDATAI_COS_CNT_10   0x00000ca8
#define	SNDDATAI_COS_CNT_11   0x00000cac
#define	SNDDATAI_COS_CNT_12   0x00000cb0
#define	SNDDATAI_COS_CNT_13   0x00000cb4
#define	SNDDATAI_COS_CNT_14   0x00000cb8
#define	SNDDATAI_COS_CNT_15   0x00000cbc
#define	SNDDATAI_DMA_RDQ_FULL_CNT   0x00000cc0
#define	SNDDATAI_DMA_PRIO_RDQ_FULL_CNT   0x00000cc4
#define	SNDDATAI_SDCQ_FULL_CNT   0x00000cc8
#define	SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc
#define	SNDDATAI_STATS_UPDATED_CNT   0x00000cd0
#define	SNDDATAI_INTERRUPTS_CNT   0x00000cd4
#define	SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8
#define	SNDDATAI_SND_THRESH_HIT_CNT   0x00000cdc
#define	SNDDATAC_MODE   0x00001000
#define	SNDDATAC_MODE_RESET   0x00000001
#define	SNDDATAC_MODE_ENABLE   0x00000002
#define	SNDDATAC_MODE_CDELAY   0x00000010
#define	SNDBDS_MODE   0x00001400
#define	SNDBDS_MODE_RESET   0x00000001
#define	SNDBDS_MODE_ENABLE   0x00000002
#define	SNDBDS_MODE_ATTN_ENABLE   0x00000004
#define	SNDBDS_STATUS   0x00001404
#define	SNDBDS_STATUS_ERROR_ATTN   0x00000004
#define	SNDBDS_HWDIAG   0x00001408
#define	SNDBDS_SEL_CON_IDX_0   0x00001440
#define	SNDBDS_SEL_CON_IDX_1   0x00001444
#define	SNDBDS_SEL_CON_IDX_2   0x00001448
#define	SNDBDS_SEL_CON_IDX_3   0x0000144c
#define	SNDBDS_SEL_CON_IDX_4   0x00001450
#define	SNDBDS_SEL_CON_IDX_5   0x00001454
#define	SNDBDS_SEL_CON_IDX_6   0x00001458
#define	SNDBDS_SEL_CON_IDX_7   0x0000145c
#define	SNDBDS_SEL_CON_IDX_8   0x00001460
#define	SNDBDS_SEL_CON_IDX_9   0x00001464
#define	SNDBDS_SEL_CON_IDX_10   0x00001468
#define	SNDBDS_SEL_CON_IDX_11   0x0000146c
#define	SNDBDS_SEL_CON_IDX_12   0x00001470
#define	SNDBDS_SEL_CON_IDX_13   0x00001474
#define	SNDBDS_SEL_CON_IDX_14   0x00001478
#define	SNDBDS_SEL_CON_IDX_15   0x0000147c
#define	SNDBDI_MODE   0x00001800
#define	SNDBDI_MODE_RESET   0x00000001
#define	SNDBDI_MODE_ENABLE   0x00000002
#define	SNDBDI_MODE_ATTN_ENABLE   0x00000004
#define	SNDBDI_MODE_MULTI_TXQ_EN   0x00000020
#define	SNDBDI_STATUS   0x00001804
#define	SNDBDI_STATUS_ERROR_ATTN   0x00000004
#define	SNDBDI_IN_PROD_IDX_0   0x00001808
#define	SNDBDI_IN_PROD_IDX_1   0x0000180c
#define	SNDBDI_IN_PROD_IDX_2   0x00001810
#define	SNDBDI_IN_PROD_IDX_3   0x00001814
#define	SNDBDI_IN_PROD_IDX_4   0x00001818
#define	SNDBDI_IN_PROD_IDX_5   0x0000181c
#define	SNDBDI_IN_PROD_IDX_6   0x00001820
#define	SNDBDI_IN_PROD_IDX_7   0x00001824
#define	SNDBDI_IN_PROD_IDX_8   0x00001828
#define	SNDBDI_IN_PROD_IDX_9   0x0000182c
#define	SNDBDI_IN_PROD_IDX_10   0x00001830
#define	SNDBDI_IN_PROD_IDX_11   0x00001834
#define	SNDBDI_IN_PROD_IDX_12   0x00001838
#define	SNDBDI_IN_PROD_IDX_13   0x0000183c
#define	SNDBDI_IN_PROD_IDX_14   0x00001840
#define	SNDBDI_IN_PROD_IDX_15   0x00001844
#define	SNDBDC_MODE   0x00001c00
#define	SNDBDC_MODE_RESET   0x00000001
#define	SNDBDC_MODE_ENABLE   0x00000002
#define	SNDBDC_MODE_ATTN_ENABLE   0x00000004
#define	RCVLPC_MODE   0x00002000
#define	RCVLPC_MODE_RESET   0x00000001
#define	RCVLPC_MODE_ENABLE   0x00000002
#define	RCVLPC_MODE_CLASS0_ATTN_ENAB   0x00000004
#define	RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008
#define	RCVLPC_MODE_STAT_OFLOW_ENAB   0x00000010
#define	RCVLPC_STATUS   0x00002004
#define	RCVLPC_STATUS_CLASS0   0x00000004
#define	RCVLPC_STATUS_MAPOOR   0x00000008
#define	RCVLPC_STATUS_STAT_OFLOW   0x00000010
#define	RCVLPC_LOCK   0x00002008
#define	RCVLPC_LOCK_REQ_MASK   0x0000ffff
#define	RCVLPC_LOCK_REQ_SHIFT   0
#define	RCVLPC_LOCK_GRANT_MASK   0xffff0000
#define	RCVLPC_LOCK_GRANT_SHIFT   16
#define	RCVLPC_NON_EMPTY_BITS   0x0000200c
#define	RCVLPC_NON_EMPTY_BITS_MASK   0x0000ffff
#define	RCVLPC_CONFIG   0x00002010
#define	RCVLPC_STATSCTRL   0x00002014
#define	RCVLPC_STATSCTRL_ENABLE   0x00000001
#define	RCVLPC_STATSCTRL_FASTUPD   0x00000002
#define	RCVLPC_STATS_ENABLE   0x00002018
#define	RCVLPC_STATSENAB_ASF_FIX   0x00000002
#define	RCVLPC_STATSENAB_DACK_FIX   0x00040000
#define	RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000
#define	RCVLPC_STATS_INCMASK   0x0000201c
#define	RCVLPC_SELLST_BASE   0x00002100 /* 16 16-byte entries */
#define	SELLST_TAIL   0x00000004
#define	SELLST_CONT   0x00000008
#define	SELLST_UNUSED   0x0000000c
#define	RCVLPC_COS_CNTL_BASE   0x00002200 /* 16 4-byte entries */
#define	RCVLPC_DROP_FILTER_CNT   0x00002240
#define	RCVLPC_DMA_WQ_FULL_CNT   0x00002244
#define	RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248
#define	RCVLPC_NO_RCV_BD_CNT   0x0000224c
#define	RCVLPC_IN_DISCARDS_CNT   0x00002250
#define	RCVLPC_IN_ERRORS_CNT   0x00002254
#define	RCVLPC_RCV_THRESH_HIT_CNT   0x00002258
#define	RCVDBDI_MODE   0x00002400
#define	RCVDBDI_MODE_RESET   0x00000001
#define	RCVDBDI_MODE_ENABLE   0x00000002
#define	RCVDBDI_MODE_JUMBOBD_NEEDED   0x00000004
#define	RCVDBDI_MODE_FRM_TOO_BIG   0x00000008
#define	RCVDBDI_MODE_INV_RING_SZ   0x00000010
#define	RCVDBDI_MODE_LRG_RING_SZ   0x00010000
#define	RCVDBDI_STATUS   0x00002404
#define	RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004
#define	RCVDBDI_STATUS_FRM_TOO_BIG   0x00000008
#define	RCVDBDI_STATUS_INV_RING_SZ   0x00000010
#define	RCVDBDI_SPLIT_FRAME_MINSZ   0x00002408
#define	RCVDBDI_JUMBO_BD   0x00002440 /* TG3_BDINFO_... */
#define	RCVDBDI_STD_BD   0x00002450 /* TG3_BDINFO_... */
#define	RCVDBDI_MINI_BD   0x00002460 /* TG3_BDINFO_... */
#define	RCVDBDI_JUMBO_CON_IDX   0x00002470
#define	RCVDBDI_STD_CON_IDX   0x00002474
#define	RCVDBDI_MINI_CON_IDX   0x00002478
#define	RCVDBDI_BD_PROD_IDX_0   0x00002480
#define	RCVDBDI_BD_PROD_IDX_1   0x00002484
#define	RCVDBDI_BD_PROD_IDX_2   0x00002488
#define	RCVDBDI_BD_PROD_IDX_3   0x0000248c
#define	RCVDBDI_BD_PROD_IDX_4   0x00002490
#define	RCVDBDI_BD_PROD_IDX_5   0x00002494
#define	RCVDBDI_BD_PROD_IDX_6   0x00002498
#define	RCVDBDI_BD_PROD_IDX_7   0x0000249c
#define	RCVDBDI_BD_PROD_IDX_8   0x000024a0
#define	RCVDBDI_BD_PROD_IDX_9   0x000024a4
#define	RCVDBDI_BD_PROD_IDX_10   0x000024a8
#define	RCVDBDI_BD_PROD_IDX_11   0x000024ac
#define	RCVDBDI_BD_PROD_IDX_12   0x000024b0
#define	RCVDBDI_BD_PROD_IDX_13   0x000024b4
#define	RCVDBDI_BD_PROD_IDX_14   0x000024b8
#define	RCVDBDI_BD_PROD_IDX_15   0x000024bc
#define	RCVDBDI_HWDIAG   0x000024c0
#define	RCVDCC_MODE   0x00002800
#define	RCVDCC_MODE_RESET   0x00000001
#define	RCVDCC_MODE_ENABLE   0x00000002
#define	RCVDCC_MODE_ATTN_ENABLE   0x00000004
#define	RCVBDI_MODE   0x00002c00
#define	RCVBDI_MODE_RESET   0x00000001
#define	RCVBDI_MODE_ENABLE   0x00000002
#define	RCVBDI_MODE_RCB_ATTN_ENAB   0x00000004
#define	RCVBDI_STATUS   0x00002c04
#define	RCVBDI_STATUS_RCB_ATTN   0x00000004
#define	RCVBDI_JUMBO_PROD_IDX   0x00002c08
#define	RCVBDI_STD_PROD_IDX   0x00002c0c
#define	RCVBDI_MINI_PROD_IDX   0x00002c10
#define	RCVBDI_MINI_THRESH   0x00002c14
#define	RCVBDI_STD_THRESH   0x00002c18
#define	RCVBDI_JUMBO_THRESH   0x00002c1c
#define	STD_REPLENISH_LWM   0x00002d00
#define	JMB_REPLENISH_LWM   0x00002d04
#define	RCVCC_MODE   0x00003000
#define	RCVCC_MODE_RESET   0x00000001
#define	RCVCC_MODE_ENABLE   0x00000002
#define	RCVCC_MODE_ATTN_ENABLE   0x00000004
#define	RCVCC_STATUS   0x00003004
#define	RCVCC_STATUS_ERROR_ATTN   0x00000004
#define	RCVCC_JUMP_PROD_IDX   0x00003008
#define	RCVCC_STD_PROD_IDX   0x0000300c
#define	RCVCC_MINI_PROD_IDX   0x00003010
#define	RCVLSC_MODE   0x00003400
#define	RCVLSC_MODE_RESET   0x00000001
#define	RCVLSC_MODE_ENABLE   0x00000002
#define	RCVLSC_MODE_ATTN_ENABLE   0x00000004
#define	RCVLSC_STATUS   0x00003404
#define	RCVLSC_STATUS_ERROR_ATTN   0x00000004
#define	TG3_CPMU_CTRL   0x00003600
#define	CPMU_CTRL_LINK_IDLE_MODE   0x00000200
#define	CPMU_CTRL_LINK_AWARE_MODE   0x00000400
#define	CPMU_CTRL_LINK_SPEED_MODE   0x00004000
#define	CPMU_CTRL_GPHY_10MB_RXONLY   0x00010000
#define	TG3_CPMU_LSPD_10MB_CLK   0x00003604
#define	CPMU_LSPD_10MB_MACCLK_MASK   0x001f0000
#define	CPMU_LSPD_10MB_MACCLK_6_25   0x00130000
#define	TG3_CPMU_LSPD_1000MB_CLK   0x0000360c
#define	CPMU_LSPD_1000MB_MACCLK_62_5   0x00000000
#define	CPMU_LSPD_1000MB_MACCLK_12_5   0x00110000
#define	CPMU_LSPD_1000MB_MACCLK_MASK   0x001f0000
#define	TG3_CPMU_LNK_AWARE_PWRMD   0x00003610
#define	CPMU_LNK_AWARE_MACCLK_MASK   0x001f0000
#define	CPMU_LNK_AWARE_MACCLK_6_25   0x00130000
#define	TG3_CPMU_D0_CLCK_POLICY   0x00003614
#define	TG3_CPMU_HST_ACC   0x0000361c
#define	CPMU_HST_ACC_MACCLK_MASK   0x001f0000
#define	CPMU_HST_ACC_MACCLK_6_25   0x00130000
#define	TG3_CPMU_CLCK_ORIDE   0x00003624
#define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000
#define	TG3_CPMU_CLCK_ORIDE_EN   0x00003628
#define	CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN   0x00002000
#define	TG3_CPMU_CLCK_STAT   0x00003630
#define	CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
#define	CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
#define	CPMU_CLCK_STAT_MAC_CLCK_12_5   0x00110000
#define	CPMU_CLCK_STAT_MAC_CLCK_6_25   0x00130000
#define	TG3_CPMU_MUTEX_REQ   0x0000365c
#define	CPMU_MUTEX_REQ_DRIVER   0x00001000
#define	TG3_CPMU_MUTEX_GNT   0x00003660
#define	CPMU_MUTEX_GNT_DRIVER   0x00001000
#define	TG3_CPMU_PHY_STRAP   0x00003664
#define	TG3_CPMU_PHY_STRAP_IS_SERDES   0x00000020
#define	TG3_CPMU_EEE_MODE   0x000036b0
#define	TG3_CPMU_EEEMD_APE_TX_DET_EN   0x00000004
#define	TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008
#define	TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
#define	TG3_CPMU_EEEMD_LPI_ENABLE   0x00000080
#define	TG3_CPMU_EEEMD_LPI_IN_TX   0x00000100
#define	TG3_CPMU_EEEMD_LPI_IN_RX   0x00000200
#define	TG3_CPMU_EEEMD_EEE_ENABLE   0x00100000
#define	TG3_CPMU_EEE_DBTMR1   0x000036b4
#define	TG3_CPMU_DBTMR1_PCIEXIT_2047US   0x07ff0000
#define	TG3_CPMU_DBTMR1_LNKIDLE_2047US   0x000070ff
#define	TG3_CPMU_EEE_DBTMR2   0x000036b8
#define	TG3_CPMU_DBTMR2_APE_TX_2047US   0x07ff0000
#define	TG3_CPMU_DBTMR2_TXIDXEQ_2047US   0x000070ff
#define	TG3_CPMU_EEE_LNKIDL_CTRL   0x000036bc
#define	TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000
#define	TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004
#define	TG3_CPMU_EEE_CTRL   0x000036d0
#define	TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
#define	TG3_CPMU_EEE_CTRL_EXIT_36_US   0x00000384
#define	TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
#define	MBFREE_MODE   0x00003800
#define	MBFREE_MODE_RESET   0x00000001
#define	MBFREE_MODE_ENABLE   0x00000002
#define	MBFREE_STATUS   0x00003804
#define	HOSTCC_MODE   0x00003c00
#define	HOSTCC_MODE_RESET   0x00000001
#define	HOSTCC_MODE_ENABLE   0x00000002
#define	HOSTCC_MODE_ATTN   0x00000004
#define	HOSTCC_MODE_NOW   0x00000008
#define	HOSTCC_MODE_FULL_STATUS   0x00000000
#define	HOSTCC_MODE_64BYTE   0x00000080
#define	HOSTCC_MODE_32BYTE   0x00000100
#define	HOSTCC_MODE_CLRTICK_RXBD   0x00000200
#define	HOSTCC_MODE_CLRTICK_TXBD   0x00000400
#define	HOSTCC_MODE_NOINT_ON_NOW   0x00000800
#define	HOSTCC_MODE_NOINT_ON_FORCE   0x00001000
#define	HOSTCC_MODE_COAL_VEC1_NOW   0x00002000
#define	HOSTCC_STATUS   0x00003c04
#define	HOSTCC_STATUS_ERROR_ATTN   0x00000004
#define	HOSTCC_RXCOL_TICKS   0x00003c08
#define	LOW_RXCOL_TICKS   0x00000032
#define	LOW_RXCOL_TICKS_CLRTCKS   0x00000014
#define	DEFAULT_RXCOL_TICKS   0x00000048
#define	HIGH_RXCOL_TICKS   0x00000096
#define	MAX_RXCOL_TICKS   0x000003ff
#define	HOSTCC_TXCOL_TICKS   0x00003c0c
#define	LOW_TXCOL_TICKS   0x00000096
#define	LOW_TXCOL_TICKS_CLRTCKS   0x00000048
#define	DEFAULT_TXCOL_TICKS   0x0000012c
#define	HIGH_TXCOL_TICKS   0x00000145
#define	MAX_TXCOL_TICKS   0x000003ff
#define	HOSTCC_RXMAX_FRAMES   0x00003c10
#define	LOW_RXMAX_FRAMES   0x00000005
#define	DEFAULT_RXMAX_FRAMES   0x00000008
#define	HIGH_RXMAX_FRAMES   0x00000012
#define	MAX_RXMAX_FRAMES   0x000000ff
#define	HOSTCC_TXMAX_FRAMES   0x00003c14
#define	LOW_TXMAX_FRAMES   0x00000035
#define	DEFAULT_TXMAX_FRAMES   0x0000004b
#define	HIGH_TXMAX_FRAMES   0x00000052
#define	MAX_TXMAX_FRAMES   0x000000ff
#define	HOSTCC_RXCOAL_TICK_INT   0x00003c18
#define	DEFAULT_RXCOAL_TICK_INT   0x00000019
#define	DEFAULT_RXCOAL_TICK_INT_CLRTCKS   0x00000014
#define	MAX_RXCOAL_TICK_INT   0x000003ff
#define	HOSTCC_TXCOAL_TICK_INT   0x00003c1c
#define	DEFAULT_TXCOAL_TICK_INT   0x00000019
#define	DEFAULT_TXCOAL_TICK_INT_CLRTCKS   0x00000014
#define	MAX_TXCOAL_TICK_INT   0x000003ff
#define	HOSTCC_RXCOAL_MAXF_INT   0x00003c20
#define	DEFAULT_RXCOAL_MAXF_INT   0x00000005
#define	MAX_RXCOAL_MAXF_INT   0x000000ff
#define	HOSTCC_TXCOAL_MAXF_INT   0x00003c24
#define	DEFAULT_TXCOAL_MAXF_INT   0x00000005
#define	MAX_TXCOAL_MAXF_INT   0x000000ff
#define	HOSTCC_STAT_COAL_TICKS   0x00003c28
#define	DEFAULT_STAT_COAL_TICKS   0x000f4240
#define	MAX_STAT_COAL_TICKS   0xd693d400
#define	MIN_STAT_COAL_TICKS   0x00000064
#define	HOSTCC_STATS_BLK_HOST_ADDR   0x00003c30 /* 64-bit */
#define	HOSTCC_STATUS_BLK_HOST_ADDR   0x00003c38 /* 64-bit */
#define	HOSTCC_STATS_BLK_NIC_ADDR   0x00003c40
#define	HOSTCC_STATUS_BLK_NIC_ADDR   0x00003c44
#define	HOSTCC_FLOW_ATTN   0x00003c48
#define	HOSTCC_FLOW_ATTN_MBUF_LWM   0x00000040
#define	HOSTCC_JUMBO_CON_IDX   0x00003c50
#define	HOSTCC_STD_CON_IDX   0x00003c54
#define	HOSTCC_MINI_CON_IDX   0x00003c58
#define	HOSTCC_RET_PROD_IDX_0   0x00003c80
#define	HOSTCC_RET_PROD_IDX_1   0x00003c84
#define	HOSTCC_RET_PROD_IDX_2   0x00003c88
#define	HOSTCC_RET_PROD_IDX_3   0x00003c8c
#define	HOSTCC_RET_PROD_IDX_4   0x00003c90
#define	HOSTCC_RET_PROD_IDX_5   0x00003c94
#define	HOSTCC_RET_PROD_IDX_6   0x00003c98
#define	HOSTCC_RET_PROD_IDX_7   0x00003c9c
#define	HOSTCC_RET_PROD_IDX_8   0x00003ca0
#define	HOSTCC_RET_PROD_IDX_9   0x00003ca4
#define	HOSTCC_RET_PROD_IDX_10   0x00003ca8
#define	HOSTCC_RET_PROD_IDX_11   0x00003cac
#define	HOSTCC_RET_PROD_IDX_12   0x00003cb0
#define	HOSTCC_RET_PROD_IDX_13   0x00003cb4
#define	HOSTCC_RET_PROD_IDX_14   0x00003cb8
#define	HOSTCC_RET_PROD_IDX_15   0x00003cbc
#define	HOSTCC_SND_CON_IDX_0   0x00003cc0
#define	HOSTCC_SND_CON_IDX_1   0x00003cc4
#define	HOSTCC_SND_CON_IDX_2   0x00003cc8
#define	HOSTCC_SND_CON_IDX_3   0x00003ccc
#define	HOSTCC_SND_CON_IDX_4   0x00003cd0
#define	HOSTCC_SND_CON_IDX_5   0x00003cd4
#define	HOSTCC_SND_CON_IDX_6   0x00003cd8
#define	HOSTCC_SND_CON_IDX_7   0x00003cdc
#define	HOSTCC_SND_CON_IDX_8   0x00003ce0
#define	HOSTCC_SND_CON_IDX_9   0x00003ce4
#define	HOSTCC_SND_CON_IDX_10   0x00003ce8
#define	HOSTCC_SND_CON_IDX_11   0x00003cec
#define	HOSTCC_SND_CON_IDX_12   0x00003cf0
#define	HOSTCC_SND_CON_IDX_13   0x00003cf4
#define	HOSTCC_SND_CON_IDX_14   0x00003cf8
#define	HOSTCC_SND_CON_IDX_15   0x00003cfc
#define	HOSTCC_STATBLCK_RING1   0x00003d00
#define	HOSTCC_RXCOL_TICKS_VEC1   0x00003d80
#define	HOSTCC_TXCOL_TICKS_VEC1   0x00003d84
#define	HOSTCC_RXMAX_FRAMES_VEC1   0x00003d88
#define	HOSTCC_TXMAX_FRAMES_VEC1   0x00003d8c
#define	HOSTCC_RXCOAL_MAXF_INT_VEC1   0x00003d90
#define	HOSTCC_TXCOAL_MAXF_INT_VEC1   0x00003d94
#define	MEMARB_MODE   0x00004000
#define	MEMARB_MODE_RESET   0x00000001
#define	MEMARB_MODE_ENABLE   0x00000002
#define	MEMARB_STATUS   0x00004004
#define	MEMARB_TRAP_ADDR_LOW   0x00004008
#define	MEMARB_TRAP_ADDR_HIGH   0x0000400c
#define	BUFMGR_MODE   0x00004400
#define	BUFMGR_MODE_RESET   0x00000001
#define	BUFMGR_MODE_ENABLE   0x00000002
#define	BUFMGR_MODE_ATTN_ENABLE   0x00000004
#define	BUFMGR_MODE_BM_TEST   0x00000008
#define	BUFMGR_MODE_MBLOW_ATTN_ENAB   0x00000010
#define	BUFMGR_MODE_NO_TX_UNDERRUN   0x80000000
#define	BUFMGR_STATUS   0x00004404
#define	BUFMGR_STATUS_ERROR   0x00000004
#define	BUFMGR_STATUS_MBLOW   0x00000010
#define	BUFMGR_MB_POOL_ADDR   0x00004408
#define	BUFMGR_MB_POOL_SIZE   0x0000440c
#define	BUFMGR_MB_RDMA_LOW_WATER   0x00004410
#define	DEFAULT_MB_RDMA_LOW_WATER   0x00000050
#define	DEFAULT_MB_RDMA_LOW_WATER_5705   0x00000000
#define	DEFAULT_MB_RDMA_LOW_WATER_JUMBO   0x00000130
#define	DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780   0x00000000
#define	BUFMGR_MB_MACRX_LOW_WATER   0x00004414
#define	DEFAULT_MB_MACRX_LOW_WATER   0x00000020
#define	DEFAULT_MB_MACRX_LOW_WATER_5705   0x00000010
#define	DEFAULT_MB_MACRX_LOW_WATER_5906   0x00000004
#define	DEFAULT_MB_MACRX_LOW_WATER_57765   0x0000002a
#define	DEFAULT_MB_MACRX_LOW_WATER_JUMBO   0x00000098
#define	DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780   0x0000004b
#define	DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765   0x0000007e
#define	BUFMGR_MB_HIGH_WATER   0x00004418
#define	DEFAULT_MB_HIGH_WATER   0x00000060
#define	DEFAULT_MB_HIGH_WATER_5705   0x00000060
#define	DEFAULT_MB_HIGH_WATER_5906   0x00000010
#define	DEFAULT_MB_HIGH_WATER_57765   0x000000a0
#define	DEFAULT_MB_HIGH_WATER_JUMBO   0x0000017c
#define	DEFAULT_MB_HIGH_WATER_JUMBO_5780   0x00000096
#define	DEFAULT_MB_HIGH_WATER_JUMBO_57765   0x000000ea
#define	BUFMGR_RX_MB_ALLOC_REQ   0x0000441c
#define	BUFMGR_MB_ALLOC_BIT   0x10000000
#define	BUFMGR_RX_MB_ALLOC_RESP   0x00004420
#define	BUFMGR_TX_MB_ALLOC_REQ   0x00004424
#define	BUFMGR_TX_MB_ALLOC_RESP   0x00004428
#define	BUFMGR_DMA_DESC_POOL_ADDR   0x0000442c
#define	BUFMGR_DMA_DESC_POOL_SIZE   0x00004430
#define	BUFMGR_DMA_LOW_WATER   0x00004434
#define	DEFAULT_DMA_LOW_WATER   0x00000005
#define	BUFMGR_DMA_HIGH_WATER   0x00004438
#define	DEFAULT_DMA_HIGH_WATER   0x0000000a
#define	BUFMGR_RX_DMA_ALLOC_REQ   0x0000443c
#define	BUFMGR_RX_DMA_ALLOC_RESP   0x00004440
#define	BUFMGR_TX_DMA_ALLOC_REQ   0x00004444
#define	BUFMGR_TX_DMA_ALLOC_RESP   0x00004448
#define	BUFMGR_HWDIAG_0   0x0000444c
#define	BUFMGR_HWDIAG_1   0x00004450
#define	BUFMGR_HWDIAG_2   0x00004454
#define	RDMAC_MODE   0x00004800
#define	RDMAC_MODE_RESET   0x00000001
#define	RDMAC_MODE_ENABLE   0x00000002
#define	RDMAC_MODE_TGTABORT_ENAB   0x00000004
#define	RDMAC_MODE_MSTABORT_ENAB   0x00000008
#define	RDMAC_MODE_PARITYERR_ENAB   0x00000010
#define	RDMAC_MODE_ADDROFLOW_ENAB   0x00000020
#define	RDMAC_MODE_FIFOOFLOW_ENAB   0x00000040
#define	RDMAC_MODE_FIFOURUN_ENAB   0x00000080
#define	RDMAC_MODE_FIFOOREAD_ENAB   0x00000100
#define	RDMAC_MODE_LNGREAD_ENAB   0x00000200
#define	RDMAC_MODE_SPLIT_ENABLE   0x00000800
#define	RDMAC_MODE_BD_SBD_CRPT_ENAB   0x00000800
#define	RDMAC_MODE_SPLIT_RESET   0x00001000
#define	RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000
#define	RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000
#define	RDMAC_MODE_FIFO_SIZE_128   0x00020000
#define	RDMAC_MODE_FIFO_LONG_BURST   0x00030000
#define	RDMAC_MODE_MULT_DMA_RD_DIS   0x01000000
#define	RDMAC_MODE_IPV4_LSO_EN   0x08000000
#define	RDMAC_MODE_IPV6_LSO_EN   0x10000000
#define	RDMAC_MODE_H2BNC_VLAN_DET   0x20000000
#define	RDMAC_STATUS   0x00004804
#define	RDMAC_STATUS_TGTABORT   0x00000004
#define	RDMAC_STATUS_MSTABORT   0x00000008
#define	RDMAC_STATUS_PARITYERR   0x00000010
#define	RDMAC_STATUS_ADDROFLOW   0x00000020
#define	RDMAC_STATUS_FIFOOFLOW   0x00000040
#define	RDMAC_STATUS_FIFOURUN   0x00000080
#define	RDMAC_STATUS_FIFOOREAD   0x00000100
#define	RDMAC_STATUS_LNGREAD   0x00000200
#define	TG3_RDMA_RSRVCTRL_REG   0x00004900
#define	TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX   0x00000004
#define	TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K   0x00000c00
#define	TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK   0x00000ff0
#define	TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K   0x000c0000
#define	TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK   0x000ff000
#define	TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000
#define	TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000
#define	TG3_LSO_RD_DMA_CRPTEN_CTRL   0x00004910
#define	TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K   0x00030000
#define	TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
#define	WDMAC_MODE   0x00004c00
#define	WDMAC_MODE_RESET   0x00000001
#define	WDMAC_MODE_ENABLE   0x00000002
#define	WDMAC_MODE_TGTABORT_ENAB   0x00000004
#define	WDMAC_MODE_MSTABORT_ENAB   0x00000008
#define	WDMAC_MODE_PARITYERR_ENAB   0x00000010
#define	WDMAC_MODE_ADDROFLOW_ENAB   0x00000020
#define	WDMAC_MODE_FIFOOFLOW_ENAB   0x00000040
#define	WDMAC_MODE_FIFOURUN_ENAB   0x00000080
#define	WDMAC_MODE_FIFOOREAD_ENAB   0x00000100
#define	WDMAC_MODE_LNGREAD_ENAB   0x00000200
#define	WDMAC_MODE_RX_ACCEL   0x00000400
#define	WDMAC_MODE_STATUS_TAG_FIX   0x20000000
#define	WDMAC_MODE_BURST_ALL_DATA   0xc0000000
#define	WDMAC_STATUS   0x00004c04
#define	WDMAC_STATUS_TGTABORT   0x00000004
#define	WDMAC_STATUS_MSTABORT   0x00000008
#define	WDMAC_STATUS_PARITYERR   0x00000010
#define	WDMAC_STATUS_ADDROFLOW   0x00000020
#define	WDMAC_STATUS_FIFOOFLOW   0x00000040
#define	WDMAC_STATUS_FIFOURUN   0x00000080
#define	WDMAC_STATUS_FIFOOREAD   0x00000100
#define	WDMAC_STATUS_LNGREAD   0x00000200
#define	CPU_MODE   0x00000000
#define	CPU_MODE_RESET   0x00000001
#define	CPU_MODE_HALT   0x00000400
#define	CPU_STATE   0x00000004
#define	CPU_EVTMASK   0x00000008
#define	CPU_PC   0x0000001c
#define	CPU_INSN   0x00000020
#define	CPU_SPAD_UFLOW   0x00000024
#define	CPU_WDOG_CLEAR   0x00000028
#define	CPU_WDOG_VECTOR   0x0000002c
#define	CPU_WDOG_PC   0x00000030
#define	CPU_HW_BP   0x00000034
#define	CPU_WDOG_SAVED_STATE   0x00000044
#define	CPU_LAST_BRANCH_ADDR   0x00000048
#define	CPU_SPAD_UFLOW_SET   0x0000004c
#define	CPU_R0   0x00000200
#define	CPU_R1   0x00000204
#define	CPU_R2   0x00000208
#define	CPU_R3   0x0000020c
#define	CPU_R4   0x00000210
#define	CPU_R5   0x00000214
#define	CPU_R6   0x00000218
#define	CPU_R7   0x0000021c
#define	CPU_R8   0x00000220
#define	CPU_R9   0x00000224
#define	CPU_R10   0x00000228
#define	CPU_R11   0x0000022c
#define	CPU_R12   0x00000230
#define	CPU_R13   0x00000234
#define	CPU_R14   0x00000238
#define	CPU_R15   0x0000023c
#define	CPU_R16   0x00000240
#define	CPU_R17   0x00000244
#define	CPU_R18   0x00000248
#define	CPU_R19   0x0000024c
#define	CPU_R20   0x00000250
#define	CPU_R21   0x00000254
#define	CPU_R22   0x00000258
#define	CPU_R23   0x0000025c
#define	CPU_R24   0x00000260
#define	CPU_R25   0x00000264
#define	CPU_R26   0x00000268
#define	CPU_R27   0x0000026c
#define	CPU_R28   0x00000270
#define	CPU_R29   0x00000274
#define	CPU_R30   0x00000278
#define	CPU_R31   0x0000027c
#define	RX_CPU_BASE   0x00005000
#define	RX_CPU_MODE   0x00005000
#define	RX_CPU_STATE   0x00005004
#define	RX_CPU_PGMCTR   0x0000501c
#define	RX_CPU_HWBKPT   0x00005034
#define	TX_CPU_BASE   0x00005400
#define	TX_CPU_MODE   0x00005400
#define	TX_CPU_STATE   0x00005404
#define	TX_CPU_PGMCTR   0x0000541c
#define	VCPU_STATUS   0x00005100
#define	VCPU_STATUS_INIT_DONE   0x04000000
#define	VCPU_STATUS_DRV_RESET   0x08000000
#define	VCPU_CFGSHDW   0x00005104
#define	VCPU_CFGSHDW_WOL_ENABLE   0x00000001
#define	VCPU_CFGSHDW_WOL_MAGPKT   0x00000004
#define	VCPU_CFGSHDW_ASPM_DBNC   0x00001000
#define	GRCMBOX_BASE   0x00005600
#define	GRCMBOX_INTERRUPT_0   0x00005800 /* 64-bit */
#define	GRCMBOX_INTERRUPT_1   0x00005808 /* 64-bit */
#define	GRCMBOX_INTERRUPT_2   0x00005810 /* 64-bit */
#define	GRCMBOX_INTERRUPT_3   0x00005818 /* 64-bit */
#define	GRCMBOX_GENERAL_0   0x00005820 /* 64-bit */
#define	GRCMBOX_GENERAL_1   0x00005828 /* 64-bit */
#define	GRCMBOX_GENERAL_2   0x00005830 /* 64-bit */
#define	GRCMBOX_GENERAL_3   0x00005838 /* 64-bit */
#define	GRCMBOX_GENERAL_4   0x00005840 /* 64-bit */
#define	GRCMBOX_GENERAL_5   0x00005848 /* 64-bit */
#define	GRCMBOX_GENERAL_6   0x00005850 /* 64-bit */
#define	GRCMBOX_GENERAL_7   0x00005858 /* 64-bit */
#define	GRCMBOX_RELOAD_STAT   0x00005860 /* 64-bit */
#define	GRCMBOX_RCVSTD_PROD_IDX   0x00005868 /* 64-bit */
#define	GRCMBOX_RCVJUMBO_PROD_IDX   0x00005870 /* 64-bit */
#define	GRCMBOX_RCVMINI_PROD_IDX   0x00005878 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_0   0x00005880 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_1   0x00005888 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_2   0x00005890 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_3   0x00005898 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_4   0x000058a0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_5   0x000058a8 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_6   0x000058b0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_7   0x000058b8 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_8   0x000058c0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_9   0x000058c8 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_10   0x000058d0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_11   0x000058d8 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_12   0x000058e0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_13   0x000058e8 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_14   0x000058f0 /* 64-bit */
#define	GRCMBOX_RCVRET_CON_IDX_15   0x000058f8 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_0   0x00005900 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_1   0x00005908 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_2   0x00005910 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_3   0x00005918 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_4   0x00005920 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_5   0x00005928 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_6   0x00005930 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_7   0x00005938 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_8   0x00005940 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_9   0x00005948 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_10   0x00005950 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_11   0x00005958 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_12   0x00005960 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_13   0x00005968 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_14   0x00005970 /* 64-bit */
#define	GRCMBOX_SNDHOST_PROD_IDX_15   0x00005978 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_0   0x00005980 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_1   0x00005988 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_2   0x00005990 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_3   0x00005998 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_4   0x000059a0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_5   0x000059a8 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_6   0x000059b0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_7   0x000059b8 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_8   0x000059c0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_9   0x000059c8 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_10   0x000059d0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_11   0x000059d8 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_12   0x000059e0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_13   0x000059e8 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_14   0x000059f0 /* 64-bit */
#define	GRCMBOX_SNDNIC_PROD_IDX_15   0x000059f8 /* 64-bit */
#define	GRCMBOX_HIGH_PRIO_EV_VECTOR   0x00005a00
#define	GRCMBOX_HIGH_PRIO_EV_MASK   0x00005a04
#define	GRCMBOX_LOW_PRIO_EV_VEC   0x00005a08
#define	GRCMBOX_LOW_PRIO_EV_MASK   0x00005a0c
#define	FTQ_RESET   0x00005c00
#define	FTQ_DMA_NORM_READ_CTL   0x00005c10
#define	FTQ_DMA_NORM_READ_FULL_CNT   0x00005c14
#define	FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18
#define	FTQ_DMA_NORM_READ_WRITE_PEEK   0x00005c1c
#define	FTQ_DMA_HIGH_READ_CTL   0x00005c20
#define	FTQ_DMA_HIGH_READ_FULL_CNT   0x00005c24
#define	FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28
#define	FTQ_DMA_HIGH_READ_WRITE_PEEK   0x00005c2c
#define	FTQ_DMA_COMP_DISC_CTL   0x00005c30
#define	FTQ_DMA_COMP_DISC_FULL_CNT   0x00005c34
#define	FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38
#define	FTQ_DMA_COMP_DISC_WRITE_PEEK   0x00005c3c
#define	FTQ_SEND_BD_COMP_CTL   0x00005c40
#define	FTQ_SEND_BD_COMP_FULL_CNT   0x00005c44
#define	FTQ_SEND_BD_COMP_FIFO_ENQDEQ   0x00005c48
#define	FTQ_SEND_BD_COMP_WRITE_PEEK   0x00005c4c
#define	FTQ_SEND_DATA_INIT_CTL   0x00005c50
#define	FTQ_SEND_DATA_INIT_FULL_CNT   0x00005c54
#define	FTQ_SEND_DATA_INIT_FIFO_ENQDEQ   0x00005c58
#define	FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c
#define	FTQ_DMA_NORM_WRITE_CTL   0x00005c60
#define	FTQ_DMA_NORM_WRITE_FULL_CNT   0x00005c64
#define	FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ   0x00005c68
#define	FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c
#define	FTQ_DMA_HIGH_WRITE_CTL   0x00005c70
#define	FTQ_DMA_HIGH_WRITE_FULL_CNT   0x00005c74
#define	FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ   0x00005c78
#define	FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c
#define	FTQ_SWTYPE1_CTL   0x00005c80
#define	FTQ_SWTYPE1_FULL_CNT   0x00005c84
#define	FTQ_SWTYPE1_FIFO_ENQDEQ   0x00005c88
#define	FTQ_SWTYPE1_WRITE_PEEK   0x00005c8c
#define	FTQ_SEND_DATA_COMP_CTL   0x00005c90
#define	FTQ_SEND_DATA_COMP_FULL_CNT   0x00005c94
#define	FTQ_SEND_DATA_COMP_FIFO_ENQDEQ   0x00005c98
#define	FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c
#define	FTQ_HOST_COAL_CTL   0x00005ca0
#define	FTQ_HOST_COAL_FULL_CNT   0x00005ca4
#define	FTQ_HOST_COAL_FIFO_ENQDEQ   0x00005ca8
#define	FTQ_HOST_COAL_WRITE_PEEK   0x00005cac
#define	FTQ_MAC_TX_CTL   0x00005cb0
#define	FTQ_MAC_TX_FULL_CNT   0x00005cb4
#define	FTQ_MAC_TX_FIFO_ENQDEQ   0x00005cb8
#define	FTQ_MAC_TX_WRITE_PEEK   0x00005cbc
#define	FTQ_MB_FREE_CTL   0x00005cc0
#define	FTQ_MB_FREE_FULL_CNT   0x00005cc4
#define	FTQ_MB_FREE_FIFO_ENQDEQ   0x00005cc8
#define	FTQ_MB_FREE_WRITE_PEEK   0x00005ccc
#define	FTQ_RCVBD_COMP_CTL   0x00005cd0
#define	FTQ_RCVBD_COMP_FULL_CNT   0x00005cd4
#define	FTQ_RCVBD_COMP_FIFO_ENQDEQ   0x00005cd8
#define	FTQ_RCVBD_COMP_WRITE_PEEK   0x00005cdc
#define	FTQ_RCVLST_PLMT_CTL   0x00005ce0
#define	FTQ_RCVLST_PLMT_FULL_CNT   0x00005ce4
#define	FTQ_RCVLST_PLMT_FIFO_ENQDEQ   0x00005ce8
#define	FTQ_RCVLST_PLMT_WRITE_PEEK   0x00005cec
#define	FTQ_RCVDATA_INI_CTL   0x00005cf0
#define	FTQ_RCVDATA_INI_FULL_CNT   0x00005cf4
#define	FTQ_RCVDATA_INI_FIFO_ENQDEQ   0x00005cf8
#define	FTQ_RCVDATA_INI_WRITE_PEEK   0x00005cfc
#define	FTQ_RCVDATA_COMP_CTL   0x00005d00
#define	FTQ_RCVDATA_COMP_FULL_CNT   0x00005d04
#define	FTQ_RCVDATA_COMP_FIFO_ENQDEQ   0x00005d08
#define	FTQ_RCVDATA_COMP_WRITE_PEEK   0x00005d0c
#define	FTQ_SWTYPE2_CTL   0x00005d10
#define	FTQ_SWTYPE2_FULL_CNT   0x00005d14
#define	FTQ_SWTYPE2_FIFO_ENQDEQ   0x00005d18
#define	FTQ_SWTYPE2_WRITE_PEEK   0x00005d1c
#define	MSGINT_MODE   0x00006000
#define	MSGINT_MODE_RESET   0x00000001
#define	MSGINT_MODE_ENABLE   0x00000002
#define	MSGINT_MODE_ONE_SHOT_DISABLE   0x00000020
#define	MSGINT_MODE_MULTIVEC_EN   0x00000080
#define	MSGINT_STATUS   0x00006004
#define	MSGINT_STATUS_MSI_REQ   0x00000001
#define	MSGINT_FIFO   0x00006008
#define	DMAC_MODE   0x00006400
#define	DMAC_MODE_RESET   0x00000001
#define	DMAC_MODE_ENABLE   0x00000002
#define	GRC_MODE   0x00006800
#define	GRC_MODE_UPD_ON_COAL   0x00000001
#define	GRC_MODE_BSWAP_NONFRM_DATA   0x00000002
#define	GRC_MODE_WSWAP_NONFRM_DATA   0x00000004
#define	GRC_MODE_BSWAP_DATA   0x00000010
#define	GRC_MODE_WSWAP_DATA   0x00000020
#define	GRC_MODE_BYTE_SWAP_B2HRX_DATA   0x00000040
#define	GRC_MODE_WORD_SWAP_B2HRX_DATA   0x00000080
#define	GRC_MODE_SPLITHDR   0x00000100
#define	GRC_MODE_NOFRM_CRACKING   0x00000200
#define	GRC_MODE_INCL_CRC   0x00000400
#define	GRC_MODE_ALLOW_BAD_FRMS   0x00000800
#define	GRC_MODE_NOIRQ_ON_SENDS   0x00002000
#define	GRC_MODE_NOIRQ_ON_RCV   0x00004000
#define	GRC_MODE_FORCE_PCI32BIT   0x00008000
#define	GRC_MODE_B2HRX_ENABLE   0x00008000
#define	GRC_MODE_HOST_STACKUP   0x00010000
#define	GRC_MODE_HOST_SENDBDS   0x00020000
#define	GRC_MODE_HTX2B_ENABLE   0x00040000
#define	GRC_MODE_NO_TX_PHDR_CSUM   0x00100000
#define	GRC_MODE_NVRAM_WR_ENABLE   0x00200000
#define	GRC_MODE_PCIE_TL_SEL   0x00000000
#define	GRC_MODE_PCIE_PL_SEL   0x00400000
#define	GRC_MODE_NO_RX_PHDR_CSUM   0x00800000
#define	GRC_MODE_IRQ_ON_TX_CPU_ATTN   0x01000000
#define	GRC_MODE_IRQ_ON_RX_CPU_ATTN   0x02000000
#define	GRC_MODE_IRQ_ON_MAC_ATTN   0x04000000
#define	GRC_MODE_IRQ_ON_DMA_ATTN   0x08000000
#define	GRC_MODE_IRQ_ON_FLOW_ATTN   0x10000000
#define	GRC_MODE_4X_NIC_SEND_RINGS   0x20000000
#define	GRC_MODE_PCIE_DL_SEL   0x20000000
#define	GRC_MODE_MCAST_FRM_ENABLE   0x40000000
#define	GRC_MODE_PCIE_HI_1K_EN   0x80000000
#define	GRC_MODE_PCIE_PORT_MASK
#define	GRC_MISC_CFG   0x00006804
#define	GRC_MISC_CFG_CORECLK_RESET   0x00000001
#define	GRC_MISC_CFG_PRESCALAR_MASK   0x000000fe
#define	GRC_MISC_CFG_PRESCALAR_SHIFT   1
#define	GRC_MISC_CFG_BOARD_ID_MASK   0x0001e000
#define	GRC_MISC_CFG_BOARD_ID_5700   0x0001e000
#define	GRC_MISC_CFG_BOARD_ID_5701   0x00000000
#define	GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000
#define	GRC_MISC_CFG_BOARD_ID_5703   0x00000000
#define	GRC_MISC_CFG_BOARD_ID_5703S   0x00002000
#define	GRC_MISC_CFG_BOARD_ID_5704   0x00000000
#define	GRC_MISC_CFG_BOARD_ID_5704CIOBE   0x00004000
#define	GRC_MISC_CFG_BOARD_ID_5704_A2   0x00008000
#define	GRC_MISC_CFG_BOARD_ID_5788   0x00010000
#define	GRC_MISC_CFG_BOARD_ID_5788M   0x00018000
#define	GRC_MISC_CFG_BOARD_ID_AC91002A1   0x00018000
#define	GRC_MISC_CFG_EPHY_IDDQ   0x00200000
#define	GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000
#define	GRC_LOCAL_CTRL   0x00006808
#define	GRC_LCLCTRL_INT_ACTIVE   0x00000001
#define	GRC_LCLCTRL_CLEARINT   0x00000002
#define	GRC_LCLCTRL_SETINT   0x00000004
#define	GRC_LCLCTRL_INT_ON_ATTN   0x00000008
#define	GRC_LCLCTRL_GPIO_UART_SEL   0x00000010 /* 5755 only */
#define	GRC_LCLCTRL_USE_SIG_DETECT   0x00000010 /* 5714/5780 only */
#define	GRC_LCLCTRL_USE_EXT_SIG_DETECT   0x00000020 /* 5714/5780 only */
#define	GRC_LCLCTRL_GPIO_INPUT3   0x00000020
#define	GRC_LCLCTRL_GPIO_OE3   0x00000040
#define	GRC_LCLCTRL_GPIO_OUTPUT3   0x00000080
#define	GRC_LCLCTRL_GPIO_INPUT0   0x00000100
#define	GRC_LCLCTRL_GPIO_INPUT1   0x00000200
#define	GRC_LCLCTRL_GPIO_INPUT2   0x00000400
#define	GRC_LCLCTRL_GPIO_OE0   0x00000800
#define	GRC_LCLCTRL_GPIO_OE1   0x00001000
#define	GRC_LCLCTRL_GPIO_OE2   0x00002000
#define	GRC_LCLCTRL_GPIO_OUTPUT0   0x00004000
#define	GRC_LCLCTRL_GPIO_OUTPUT1   0x00008000
#define	GRC_LCLCTRL_GPIO_OUTPUT2   0x00010000
#define	GRC_LCLCTRL_EXTMEM_ENABLE   0x00020000
#define	GRC_LCLCTRL_MEMSZ_MASK   0x001c0000
#define	GRC_LCLCTRL_MEMSZ_256K   0x00000000
#define	GRC_LCLCTRL_MEMSZ_512K   0x00040000
#define	GRC_LCLCTRL_MEMSZ_1M   0x00080000
#define	GRC_LCLCTRL_MEMSZ_2M   0x000c0000
#define	GRC_LCLCTRL_MEMSZ_4M   0x00100000
#define	GRC_LCLCTRL_MEMSZ_8M   0x00140000
#define	GRC_LCLCTRL_MEMSZ_16M   0x00180000
#define	GRC_LCLCTRL_BANK_SELECT   0x00200000
#define	GRC_LCLCTRL_SSRAM_TYPE   0x00400000
#define	GRC_LCLCTRL_AUTO_SEEPROM   0x01000000
#define	GRC_TIMER   0x0000680c
#define	GRC_RX_CPU_EVENT   0x00006810
#define	GRC_RX_CPU_DRIVER_EVENT   0x00004000
#define	GRC_RX_TIMER_REF   0x00006814
#define	GRC_RX_CPU_SEM   0x00006818
#define	GRC_REMOTE_RX_CPU_ATTN   0x0000681c
#define	GRC_TX_CPU_EVENT   0x00006820
#define	GRC_TX_TIMER_REF   0x00006824
#define	GRC_TX_CPU_SEM   0x00006828
#define	GRC_REMOTE_TX_CPU_ATTN   0x0000682c
#define	GRC_MEM_POWER_UP   0x00006830 /* 64-bit */
#define	GRC_EEPROM_ADDR   0x00006838
#define	EEPROM_ADDR_WRITE   0x00000000
#define	EEPROM_ADDR_READ   0x80000000
#define	EEPROM_ADDR_COMPLETE   0x40000000
#define	EEPROM_ADDR_FSM_RESET   0x20000000
#define	EEPROM_ADDR_DEVID_MASK   0x1c000000
#define	EEPROM_ADDR_DEVID_SHIFT   26
#define	EEPROM_ADDR_START   0x02000000
#define	EEPROM_ADDR_CLKPERD_SHIFT   16
#define	EEPROM_ADDR_ADDR_MASK   0x0000ffff
#define	EEPROM_ADDR_ADDR_SHIFT   0
#define	EEPROM_DEFAULT_CLOCK_PERIOD   0x60
#define	EEPROM_CHIP_SIZE   (64 * 1024)
#define	GRC_EEPROM_DATA   0x0000683c
#define	GRC_EEPROM_CTRL   0x00006840
#define	GRC_MDI_CTRL   0x00006844
#define	GRC_SEEPROM_DELAY   0x00006848
#define	GRC_VCPU_EXT_CTRL   0x00006890
#define	GRC_VCPU_EXT_CTRL_HALT_CPU   0x00400000
#define	GRC_VCPU_EXT_CTRL_DISABLE_WOL   0x20000000
#define	GRC_FASTBOOT_PC   0x00006894 /* 5752, 5755, 5787 */
#define	NVRAM_CMD   0x00007000
#define	NVRAM_CMD_RESET   0x00000001
#define	NVRAM_CMD_DONE   0x00000008
#define	NVRAM_CMD_GO   0x00000010
#define	NVRAM_CMD_WR   0x00000020
#define	NVRAM_CMD_RD   0x00000000
#define	NVRAM_CMD_ERASE   0x00000040
#define	NVRAM_CMD_FIRST   0x00000080
#define	NVRAM_CMD_LAST   0x00000100
#define	NVRAM_CMD_WREN   0x00010000
#define	NVRAM_CMD_WRDI   0x00020000
#define	NVRAM_STAT   0x00007004
#define	NVRAM_WRDATA   0x00007008
#define	NVRAM_ADDR   0x0000700c
#define	NVRAM_ADDR_MSK   0x00ffffff
#define	NVRAM_RDDATA   0x00007010
#define	NVRAM_CFG1   0x00007014
#define	NVRAM_CFG1_FLASHIF_ENAB   0x00000001
#define	NVRAM_CFG1_BUFFERED_MODE   0x00000002
#define	NVRAM_CFG1_PASS_THRU   0x00000004
#define	NVRAM_CFG1_STATUS_BITS   0x00000070
#define	NVRAM_CFG1_BIT_BANG   0x00000008
#define	NVRAM_CFG1_FLASH_SIZE   0x02000000
#define	NVRAM_CFG1_COMPAT_BYPASS   0x80000000
#define	NVRAM_CFG1_VENDOR_MASK   0x03000003
#define	FLASH_VENDOR_ATMEL_EEPROM   0x02000000
#define	FLASH_VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
#define	FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED   0x00000003
#define	FLASH_VENDOR_ST   0x03000001
#define	FLASH_VENDOR_SAIFUN   0x01000003
#define	FLASH_VENDOR_SST_SMALL   0x00000001
#define	FLASH_VENDOR_SST_LARGE   0x02000001
#define	NVRAM_CFG1_5752VENDOR_MASK   0x03c00003
#define	FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ   0x00000000
#define	FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000
#define	FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003
#define	FLASH_5752VENDOR_ST_M45PE10   0x02400000
#define	FLASH_5752VENDOR_ST_M45PE20   0x02400002
#define	FLASH_5752VENDOR_ST_M45PE40   0x02400001
#define	FLASH_5755VENDOR_ATMEL_FLASH_1   0x03400001
#define	FLASH_5755VENDOR_ATMEL_FLASH_2   0x03400002
#define	FLASH_5755VENDOR_ATMEL_FLASH_3   0x03400000
#define	FLASH_5755VENDOR_ATMEL_FLASH_4   0x00000003
#define	FLASH_5755VENDOR_ATMEL_FLASH_5   0x02000003
#define	FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ   0x03c00003
#define	FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ   0x03c00002
#define	FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ   0x03000003
#define	FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ   0x03000002
#define	FLASH_5787VENDOR_MICRO_EEPROM_64KHZ   0x03000000
#define	FLASH_5787VENDOR_MICRO_EEPROM_376KHZ   0x02000000
#define	FLASH_5761VENDOR_ATMEL_MDB021D   0x00800003
#define	FLASH_5761VENDOR_ATMEL_MDB041D   0x00800000
#define	FLASH_5761VENDOR_ATMEL_MDB081D   0x00800002
#define	FLASH_5761VENDOR_ATMEL_MDB161D   0x00800001
#define	FLASH_5761VENDOR_ATMEL_ADB021D   0x00000003
#define	FLASH_5761VENDOR_ATMEL_ADB041D   0x00000000
#define	FLASH_5761VENDOR_ATMEL_ADB081D   0x00000002
#define	FLASH_5761VENDOR_ATMEL_ADB161D   0x00000001
#define	FLASH_5761VENDOR_ST_M_M45PE20   0x02800001
#define	FLASH_5761VENDOR_ST_M_M45PE40   0x02800000
#define	FLASH_5761VENDOR_ST_M_M45PE80   0x02800002
#define	FLASH_5761VENDOR_ST_M_M45PE16   0x02800003
#define	FLASH_5761VENDOR_ST_A_M45PE20   0x02000001
#define	FLASH_5761VENDOR_ST_A_M45PE40   0x02000000
#define	FLASH_5761VENDOR_ST_A_M45PE80   0x02000002
#define	FLASH_5761VENDOR_ST_A_M45PE16   0x02000003
#define	FLASH_57780VENDOR_ATMEL_AT45DB011D   0x00400000
#define	FLASH_57780VENDOR_ATMEL_AT45DB011B   0x03400000
#define	FLASH_57780VENDOR_ATMEL_AT45DB021D   0x00400002
#define	FLASH_57780VENDOR_ATMEL_AT45DB021B   0x03400002
#define	FLASH_57780VENDOR_ATMEL_AT45DB041D   0x00400001
#define	FLASH_57780VENDOR_ATMEL_AT45DB041B   0x03400001
#define	FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001
#define	FLASH_5717VENDOR_MICRO_EEPROM   0x02000003
#define	FLASH_5717VENDOR_ATMEL_MDB011D   0x01000001
#define	FLASH_5717VENDOR_ATMEL_MDB021D   0x01000003
#define	FLASH_5717VENDOR_ST_M_M25PE10   0x02000000
#define	FLASH_5717VENDOR_ST_M_M25PE20   0x02000002
#define	FLASH_5717VENDOR_ST_M_M45PE10   0x00000001
#define	FLASH_5717VENDOR_ST_M_M45PE20   0x00000003
#define	FLASH_5717VENDOR_ATMEL_ADB011B   0x01400000
#define	FLASH_5717VENDOR_ATMEL_ADB021B   0x01400002
#define	FLASH_5717VENDOR_ATMEL_ADB011D   0x01400001
#define	FLASH_5717VENDOR_ATMEL_ADB021D   0x01400003
#define	FLASH_5717VENDOR_ST_A_M25PE10   0x02400000
#define	FLASH_5717VENDOR_ST_A_M25PE20   0x02400002
#define	FLASH_5717VENDOR_ST_A_M45PE10   0x02400001
#define	FLASH_5717VENDOR_ST_A_M45PE20   0x02400003
#define	FLASH_5717VENDOR_ATMEL_45USPT   0x03400000
#define	FLASH_5717VENDOR_ST_25USPT   0x03400002
#define	FLASH_5717VENDOR_ST_45USPT   0x03400001
#define	FLASH_5720_EEPROM_HD   0x00000001
#define	FLASH_5720_EEPROM_LD   0x00000003
#define	FLASH_5720VENDOR_M_ATMEL_DB011D   0x01000000
#define	FLASH_5720VENDOR_M_ATMEL_DB021D   0x01000002
#define	FLASH_5720VENDOR_M_ATMEL_DB041D   0x01000001
#define	FLASH_5720VENDOR_M_ATMEL_DB081D   0x01000003
#define	FLASH_5720VENDOR_M_ST_M25PE10   0x02000000
#define	FLASH_5720VENDOR_M_ST_M25PE20   0x02000002
#define	FLASH_5720VENDOR_M_ST_M25PE40   0x02000001
#define	FLASH_5720VENDOR_M_ST_M25PE80   0x02000003
#define	FLASH_5720VENDOR_M_ST_M45PE10   0x03000000
#define	FLASH_5720VENDOR_M_ST_M45PE20   0x03000002
#define	FLASH_5720VENDOR_M_ST_M45PE40   0x03000001
#define	FLASH_5720VENDOR_M_ST_M45PE80   0x03000003
#define	FLASH_5720VENDOR_A_ATMEL_DB011B   0x01800000
#define	FLASH_5720VENDOR_A_ATMEL_DB021B   0x01800002
#define	FLASH_5720VENDOR_A_ATMEL_DB041B   0x01800001
#define	FLASH_5720VENDOR_A_ATMEL_DB011D   0x01c00000
#define	FLASH_5720VENDOR_A_ATMEL_DB021D   0x01c00002
#define	FLASH_5720VENDOR_A_ATMEL_DB041D   0x01c00001
#define	FLASH_5720VENDOR_A_ATMEL_DB081D   0x01c00003
#define	FLASH_5720VENDOR_A_ST_M25PE10   0x02800000
#define	FLASH_5720VENDOR_A_ST_M25PE20   0x02800002
#define	FLASH_5720VENDOR_A_ST_M25PE40   0x02800001
#define	FLASH_5720VENDOR_A_ST_M25PE80   0x02800003
#define	FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000
#define	FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002
#define	FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001
#define	FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003
#define	FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000
#define	FLASH_5720VENDOR_ST_25USPT   0x03c00002
#define	FLASH_5720VENDOR_ST_45USPT   0x03c00001
#define	NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000
#define	FLASH_5752PAGE_SIZE_256   0x00000000
#define	FLASH_5752PAGE_SIZE_512   0x10000000
#define	FLASH_5752PAGE_SIZE_1K   0x20000000
#define	FLASH_5752PAGE_SIZE_2K   0x30000000
#define	FLASH_5752PAGE_SIZE_4K   0x40000000
#define	FLASH_5752PAGE_SIZE_264   0x50000000
#define	FLASH_5752PAGE_SIZE_528   0x60000000
#define	NVRAM_CFG2   0x00007018
#define	NVRAM_CFG3   0x0000701c
#define	NVRAM_SWARB   0x00007020
#define	SWARB_REQ_SET0   0x00000001
#define	SWARB_REQ_SET1   0x00000002
#define	SWARB_REQ_SET2   0x00000004
#define	SWARB_REQ_SET3   0x00000008
#define	SWARB_REQ_CLR0   0x00000010
#define	SWARB_REQ_CLR1   0x00000020
#define	SWARB_REQ_CLR2   0x00000040
#define	SWARB_REQ_CLR3   0x00000080
#define	SWARB_GNT0   0x00000100
#define	SWARB_GNT1   0x00000200
#define	SWARB_GNT2   0x00000400
#define	SWARB_GNT3   0x00000800
#define	SWARB_REQ0   0x00001000
#define	SWARB_REQ1   0x00002000
#define	SWARB_REQ2   0x00004000
#define	SWARB_REQ3   0x00008000
#define	NVRAM_ACCESS   0x00007024
#define	ACCESS_ENABLE   0x00000001
#define	ACCESS_WR_ENABLE   0x00000002
#define	NVRAM_WRITE1   0x00007028
#define	NVRAM_ADDR_LOCKOUT   0x00007030
#define	OTP_MODE   0x00007500
#define	OTP_MODE_OTP_THRU_GRC   0x00000001
#define	OTP_CTRL   0x00007504
#define	OTP_CTRL_OTP_PROG_ENABLE   0x00200000
#define	OTP_CTRL_OTP_CMD_READ   0x00000000
#define	OTP_CTRL_OTP_CMD_INIT   0x00000008
#define	OTP_CTRL_OTP_CMD_START   0x00000001
#define	OTP_STATUS   0x00007508
#define	OTP_STATUS_CMD_DONE   0x00000001
#define	OTP_ADDRESS   0x0000750c
#define	OTP_ADDRESS_MAGIC1   0x000000a0
#define	OTP_ADDRESS_MAGIC2   0x00000080
#define	OTP_READ_DATA   0x00007514
#define	PCIE_TRANSACTION_CFG   0x00007c04
#define	PCIE_TRANS_CFG_1SHOT_MSI   0x20000000
#define	PCIE_TRANS_CFG_LOM   0x00000020
#define	PCIE_PWR_MGMT_THRESH   0x00007d28
#define	PCIE_PWR_MGMT_L1_THRESH_MSK   0x0000ff00
#define	PCIE_PWR_MGMT_L1_THRESH_4MS   0x0000ff00
#define	PCIE_PWR_MGMT_EXT_ASPM_TMR_EN   0x01000000
#define	TG3_PCIE_LNKCTL   0x00007d54
#define	TG3_PCIE_LNKCTL_L1_PLL_PD_EN   0x00000008
#define	TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080
#define	TG3_PCIE_PHY_TSTCTL   0x00007e2c
#define	TG3_PCIE_PHY_TSTCTL_PCIE10   0x00000040
#define	TG3_PCIE_PHY_TSTCTL_PSCRAM   0x00000020
#define	TG3_PCIE_EIDLE_DELAY   0x00007e70
#define	TG3_PCIE_EIDLE_DELAY_MASK   0x0000001f
#define	TG3_PCIE_EIDLE_DELAY_13_CLKS   0x0000000c
#define	TG3_PCIE_TLDLPL_PORT   0x00007c00
#define	TG3_PCIE_DL_LO_FTSMAX   0x0000000c
#define	TG3_PCIE_DL_LO_FTSMAX_MSK   0x000000ff
#define	TG3_PCIE_DL_LO_FTSMAX_VAL   0x0000002c
#define	TG3_PCIE_PL_LO_PHYCTL1   0x00000004
#define	TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN   0x00001000
#define	TG3_PCIE_PL_LO_PHYCTL5   0x00000014
#define	TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ   0x80000000
#define	TG3_REG_BLK_SIZE   0x00008000
#define	TG3_OTP_AGCTGT_MASK   0x000000e0
#define	TG3_OTP_AGCTGT_SHIFT   1
#define	TG3_OTP_HPFFLTR_MASK   0x00000300
#define	TG3_OTP_HPFFLTR_SHIFT   1
#define	TG3_OTP_HPFOVER_MASK   0x00000400
#define	TG3_OTP_HPFOVER_SHIFT   1
#define	TG3_OTP_LPFDIS_MASK   0x00000800
#define	TG3_OTP_LPFDIS_SHIFT   11
#define	TG3_OTP_VDAC_MASK   0xff000000
#define	TG3_OTP_VDAC_SHIFT   24
#define	TG3_OTP_10BTAMP_MASK   0x0000f000
#define	TG3_OTP_10BTAMP_SHIFT   8
#define	TG3_OTP_ROFF_MASK   0x00e00000
#define	TG3_OTP_ROFF_SHIFT   11
#define	TG3_OTP_RCOFF_MASK   0x001c0000
#define	TG3_OTP_RCOFF_SHIFT   16
#define	TG3_OTP_DEFAULT   0x286c1640
#define	TG3_NVM_VPD_OFF   0x100
#define	TG3_NVM_VPD_LEN   256
#define	TG3_NVM_HWSB_CFG1   0x00000004
#define	TG3_NVM_HWSB_CFG1_MAJMSK   0xf8000000
#define	TG3_NVM_HWSB_CFG1_MAJSFT   27
#define	TG3_NVM_HWSB_CFG1_MINMSK   0x07c00000
#define	TG3_NVM_HWSB_CFG1_MINSFT   22
#define	TG3_EEPROM_MAGIC   0x669955aa
#define	TG3_EEPROM_MAGIC_FW   0xa5000000
#define	TG3_EEPROM_MAGIC_FW_MSK   0xff000000
#define	TG3_EEPROM_SB_FORMAT_MASK   0x00e00000
#define	TG3_EEPROM_SB_FORMAT_1   0x00200000
#define	TG3_EEPROM_SB_REVISION_MASK   0x001f0000
#define	TG3_EEPROM_SB_REVISION_0   0x00000000
#define	TG3_EEPROM_SB_REVISION_2   0x00020000
#define	TG3_EEPROM_SB_REVISION_3   0x00030000
#define	TG3_EEPROM_SB_REVISION_4   0x00040000
#define	TG3_EEPROM_SB_REVISION_5   0x00050000
#define	TG3_EEPROM_SB_REVISION_6   0x00060000
#define	TG3_EEPROM_MAGIC_HW   0xabcd
#define	TG3_EEPROM_MAGIC_HW_MSK   0xffff
#define	TG3_NVM_DIR_START   0x18
#define	TG3_NVM_DIR_END   0x78
#define	TG3_NVM_DIRENT_SIZE   0xc
#define	TG3_NVM_DIRTYPE_SHIFT   24
#define	TG3_NVM_DIRTYPE_LENMSK   0x003fffff
#define	TG3_NVM_DIRTYPE_ASFINI   1
#define	TG3_NVM_DIRTYPE_EXTVPD   20
#define	TG3_NVM_PTREV_BCVER   0x94
#define	TG3_NVM_BCVER_MAJMSK   0x0000ff00
#define	TG3_NVM_BCVER_MAJSFT   8
#define	TG3_NVM_BCVER_MINMSK   0x000000ff
#define	TG3_EEPROM_SB_F1R0_EDH_OFF   0x10
#define	TG3_EEPROM_SB_F1R2_EDH_OFF   0x14
#define	TG3_EEPROM_SB_F1R2_MBA_OFF   0x10
#define	TG3_EEPROM_SB_F1R3_EDH_OFF   0x18
#define	TG3_EEPROM_SB_F1R4_EDH_OFF   0x1c
#define	TG3_EEPROM_SB_F1R5_EDH_OFF   0x20
#define	TG3_EEPROM_SB_F1R6_EDH_OFF   0x4c
#define	TG3_EEPROM_SB_EDH_MAJ_MASK   0x00000700
#define	TG3_EEPROM_SB_EDH_MAJ_SHFT   8
#define	TG3_EEPROM_SB_EDH_MIN_MASK   0x000000ff
#define	TG3_EEPROM_SB_EDH_BLD_MASK   0x0000f800
#define	TG3_EEPROM_SB_EDH_BLD_SHFT   11
#define	NIC_SRAM_WIN_BASE   0x00008000
#define	NIC_SRAM_PAGE_ZERO   0x00000000
#define	NIC_SRAM_SEND_RCB   0x00000100 /* 16 * TG3_BDINFO_... */
#define	NIC_SRAM_RCV_RET_RCB   0x00000200 /* 16 * TG3_BDINFO_... */
#define	NIC_SRAM_STATS_BLK   0x00000300
#define	NIC_SRAM_STATUS_BLK   0x00000b00
#define	NIC_SRAM_FIRMWARE_MBOX   0x00000b50
#define	NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654
#define	NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */
#define	NIC_SRAM_DATA_SIG   0x00000b54
#define	NIC_SRAM_DATA_SIG_MAGIC   0x4b657654 /* ascii for 'KevT' */
#define	NIC_SRAM_DATA_CFG   0x00000b58
#define	NIC_SRAM_DATA_CFG_LED_MODE_MASK   0x0000000c
#define	NIC_SRAM_DATA_CFG_LED_MODE_MAC   0x00000000
#define	NIC_SRAM_DATA_CFG_LED_MODE_PHY_1   0x00000004
#define	NIC_SRAM_DATA_CFG_LED_MODE_PHY_2   0x00000008
#define	NIC_SRAM_DATA_CFG_PHY_TYPE_MASK   0x00000030
#define	NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN   0x00000000
#define	NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER   0x00000010
#define	NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER   0x00000020
#define	NIC_SRAM_DATA_CFG_WOL_ENABLE   0x00000040
#define	NIC_SRAM_DATA_CFG_ASF_ENABLE   0x00000080
#define	NIC_SRAM_DATA_CFG_EEPROM_WP   0x00000100
#define	NIC_SRAM_DATA_CFG_MINI_PCI   0x00001000
#define	NIC_SRAM_DATA_CFG_FIBER_WOL   0x00004000
#define	NIC_SRAM_DATA_CFG_NO_GPIO2   0x00100000
#define	NIC_SRAM_DATA_CFG_APE_ENABLE   0x00200000
#define	NIC_SRAM_DATA_VER   0x00000b5c
#define	NIC_SRAM_DATA_VER_SHIFT   16
#define	NIC_SRAM_DATA_PHY_ID   0x00000b74
#define	NIC_SRAM_DATA_PHY_ID1_MASK   0xffff0000
#define	NIC_SRAM_DATA_PHY_ID2_MASK   0x0000ffff
#define	NIC_SRAM_FW_CMD_MBOX   0x00000b78
#define	FWCMD_NICDRV_ALIVE   0x00000001
#define	FWCMD_NICDRV_PAUSE_FW   0x00000002
#define	FWCMD_NICDRV_IPV4ADDR_CHG   0x00000003
#define	FWCMD_NICDRV_IPV6ADDR_CHG   0x00000004
#define	FWCMD_NICDRV_FIX_DMAR   0x00000005
#define	FWCMD_NICDRV_FIX_DMAW   0x00000006
#define	FWCMD_NICDRV_LINK_UPDATE   0x0000000c
#define	FWCMD_NICDRV_ALIVE2   0x0000000d
#define	FWCMD_NICDRV_ALIVE3   0x0000000e
#define	NIC_SRAM_FW_CMD_LEN_MBOX   0x00000b7c
#define	NIC_SRAM_FW_CMD_DATA_MBOX   0x00000b80
#define	NIC_SRAM_FW_ASF_STATUS_MBOX   0x00000c00
#define	NIC_SRAM_FW_DRV_STATE_MBOX   0x00000c04
#define	DRV_STATE_START   0x00000001
#define	DRV_STATE_START_DONE   0x80000001
#define	DRV_STATE_UNLOAD   0x00000002
#define	DRV_STATE_UNLOAD_DONE   0x80000002
#define	DRV_STATE_WOL   0x00000003
#define	DRV_STATE_SUSPEND   0x00000004
#define	NIC_SRAM_FW_RESET_TYPE_MBOX   0x00000c08
#define	NIC_SRAM_MAC_ADDR_HIGH_MBOX   0x00000c14
#define	NIC_SRAM_MAC_ADDR_LOW_MBOX   0x00000c18
#define	NIC_SRAM_WOL_MBOX   0x00000d30
#define	WOL_SIGNATURE   0x474c0000
#define	WOL_DRV_STATE_SHUTDOWN   0x00000001
#define	WOL_DRV_WOL   0x00000002
#define	WOL_SET_MAGIC_PKT   0x00000004
#define	NIC_SRAM_DATA_CFG_2   0x00000d38
#define	NIC_SRAM_DATA_CFG_2_APD_EN   0x00000400
#define	SHASTA_EXT_LED_MODE_MASK   0x00018000
#define	SHASTA_EXT_LED_LEGACY   0x00000000
#define	SHASTA_EXT_LED_SHARED   0x00008000
#define	SHASTA_EXT_LED_MAC   0x00010000
#define	SHASTA_EXT_LED_COMBO   0x00018000
#define	NIC_SRAM_DATA_CFG_3   0x00000d3c
#define	NIC_SRAM_ASPM_DEBOUNCE   0x00000002
#define	NIC_SRAM_DATA_CFG_4   0x00000d60
#define	NIC_SRAM_GMII_MODE   0x00000002
#define	NIC_SRAM_RGMII_INBAND_DISABLE   0x00000004
#define	NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008
#define	NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010
#define	NIC_SRAM_RX_MINI_BUFFER_DESC   0x00001000
#define	NIC_SRAM_DMA_DESC_POOL_BASE   0x00002000
#define	NIC_SRAM_DMA_DESC_POOL_SIZE   0x00002000
#define	NIC_SRAM_TX_BUFFER_DESC   0x00004000 /* 512 entries */
#define	NIC_SRAM_RX_BUFFER_DESC   0x00006000 /* 256 entries */
#define	NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */
#define	NIC_SRAM_MBUF_POOL_BASE   0x00008000
#define	NIC_SRAM_MBUF_POOL_SIZE96   0x00018000
#define	NIC_SRAM_MBUF_POOL_SIZE64   0x00010000
#define	NIC_SRAM_MBUF_POOL_BASE5705   0x00010000
#define	NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000
#define	TG3_SRAM_RX_STD_BDCACHE_SIZE_5700   128
#define	TG3_SRAM_RX_STD_BDCACHE_SIZE_5755   64
#define	TG3_SRAM_RX_STD_BDCACHE_SIZE_5906   32
#define	TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700   64
#define	TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717   16
#define	TG3_PHY_MII_ADDR   0x01
#define	TG3_BMCR_SPEED1000   0x0040
#define	MII_TG3_CTRL   0x09 /* 1000-baseT control register */
#define	MII_TG3_CTRL_ADV_1000_HALF   0x0100
#define	MII_TG3_CTRL_ADV_1000_FULL   0x0200
#define	MII_TG3_CTRL_AS_MASTER   0x0800
#define	MII_TG3_CTRL_ENABLE_AS_MASTER   0x1000
#define	MII_TG3_MMD_CTRL   0x0d /* MMD Access Control register */
#define	MII_TG3_MMD_CTRL_DATA_NOINC   0x4000
#define	MII_TG3_MMD_ADDRESS   0x0e /* MMD Address Data register */
#define	MII_TG3_EXT_CTRL   0x10 /* Extended control register */
#define	MII_TG3_EXT_CTRL_FIFO_ELASTIC   0x0001
#define	MII_TG3_EXT_CTRL_LNK3_LED_MODE   0x0002
#define	MII_TG3_EXT_CTRL_FORCE_LED_OFF   0x0008
#define	MII_TG3_EXT_CTRL_TBI   0x8000
#define	MII_TG3_EXT_STAT   0x11 /* Extended status register */
#define	MII_TG3_EXT_STAT_LPASS   0x0100
#define	MII_TG3_RXR_COUNTERS   0x14 /* Local/Remote Receiver Counts */
#define	MII_TG3_DSP_RW_PORT   0x15 /* DSP coefficient read/write port */
#define	MII_TG3_DSP_CONTROL   0x16 /* DSP control register */
#define	MII_TG3_DSP_ADDRESS   0x17 /* DSP address register */
#define	MII_TG3_DSP_TAP1   0x0001
#define	MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
#define	MII_TG3_DSP_TAP26   0x001a
#define	MII_TG3_DSP_TAP26_ALNOKO   0x0001
#define	MII_TG3_DSP_TAP26_RMRXSTO   0x0002
#define	MII_TG3_DSP_TAP26_OPCSINPT   0x0004
#define	MII_TG3_DSP_AADJ1CH0   0x001f
#define	MII_TG3_DSP_CH34TP2   0x4022
#define	MII_TG3_DSP_CH34TP2_HIBW01   0x017b
#define	MII_TG3_DSP_AADJ1CH3   0x601f
#define	MII_TG3_DSP_AADJ1CH3_ADCCKADJ   0x0002
#define	MII_TG3_DSP_EXP1_INT_STAT   0x0f01
#define	MII_TG3_DSP_EXP8   0x0f08
#define	MII_TG3_DSP_EXP8_REJ2MHz   0x0001
#define	MII_TG3_DSP_EXP8_AEDW   0x0200
#define	MII_TG3_DSP_EXP75   0x0f75
#define	MII_TG3_DSP_EXP96   0x0f96
#define	MII_TG3_DSP_EXP97   0x0f97
#define	MII_TG3_AUX_CTRL   0x18 /* auxiliary control register */
#define	MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000
#define	MII_TG3_AUXCTL_ACTL_TX_6DB   0x0400
#define	MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800
#define	MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000
#define	MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002
#define	MII_TG3_AUXCTL_PCTL_WOL_EN   0x0008
#define	MII_TG3_AUXCTL_PCTL_100TX_LPWR   0x0010
#define	MII_TG3_AUXCTL_PCTL_SPR_ISOLATE   0x0020
#define	MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC   0x0040
#define	MII_TG3_AUXCTL_PCTL_VREG_11V   0x0180
#define	MII_TG3_AUXCTL_SHDWSEL_MISCTEST   0x0004
#define	MII_TG3_AUXCTL_SHDWSEL_MISC   0x0007
#define	MII_TG3_AUXCTL_MISC_WIRESPD_EN   0x0010
#define	MII_TG3_AUXCTL_MISC_FORCE_AMDIX   0x0200
#define	MII_TG3_AUXCTL_MISC_RDSEL_SHIFT   12
#define	MII_TG3_AUXCTL_MISC_WREN   0x8000
#define	MII_TG3_AUX_STAT   0x19 /* auxiliary status register */
#define	MII_TG3_AUX_STAT_LPASS   0x0004
#define	MII_TG3_AUX_STAT_SPDMASK   0x0700
#define	MII_TG3_AUX_STAT_10HALF   0x0100
#define	MII_TG3_AUX_STAT_10FULL   0x0200
#define	MII_TG3_AUX_STAT_100HALF   0x0300
#define	MII_TG3_AUX_STAT_100_4   0x0400
#define	MII_TG3_AUX_STAT_100FULL   0x0500
#define	MII_TG3_AUX_STAT_1000HALF   0x0600
#define	MII_TG3_AUX_STAT_1000FULL   0x0700
#define	MII_TG3_AUX_STAT_100   0x0008
#define	MII_TG3_AUX_STAT_FULL   0x0001
#define	MII_TG3_ISTAT   0x1a /* IRQ status register */
#define	MII_TG3_IMASK   0x1b /* IRQ mask register */
#define	MII_TG3_INT_LINKCHG   0x0002
#define	MII_TG3_INT_SPEEDCHG   0x0004
#define	MII_TG3_INT_DUPLEXCHG   0x0008
#define	MII_TG3_INT_ANEG_PAGE_RX   0x0400
#define	MII_TG3_MISC_SHDW   0x1c
#define	MII_TG3_MISC_SHDW_WREN   0x8000
#define	MII_TG3_MISC_SHDW_APD_WKTM_84MS   0x0001
#define	MII_TG3_MISC_SHDW_APD_ENABLE   0x0020
#define	MII_TG3_MISC_SHDW_APD_SEL   0x2800
#define	MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001
#define	MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002
#define	MII_TG3_MISC_SHDW_SCR5_SDTL   0x0004
#define	MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008
#define	MII_TG3_MISC_SHDW_SCR5_LPED   0x0010
#define	MII_TG3_MISC_SHDW_SCR5_SEL   0x1400
#define	MII_TG3_TEST1   0x1e
#define	MII_TG3_TEST1_TRIM_EN   0x0010
#define	MII_TG3_TEST1_CRC_EN   0x8000
#define	TG3_CL45_D7_EEERES_STAT   0x803e
#define	TG3_CL45_D7_EEERES_STAT_LP_100TX   0x0002
#define	TG3_CL45_D7_EEERES_STAT_LP_1000T   0x0004
#define	MII_TG3_FET_PTEST   0x17
#define	MII_TG3_FET_PTEST_FRC_TX_LINK   0x1000
#define	MII_TG3_FET_PTEST_FRC_TX_LOCK   0x0800
#define	MII_TG3_FET_TEST   0x1f
#define	MII_TG3_FET_SHADOW_EN   0x0080
#define	MII_TG3_FET_SHDW_MISCCTRL   0x10
#define	MII_TG3_FET_SHDW_MISCCTRL_MDIX   0x4000
#define	MII_TG3_FET_SHDW_AUXMODE4   0x1a
#define	MII_TG3_FET_SHDW_AUXMODE4_SBPD   0x0008
#define	MII_TG3_FET_SHDW_AUXSTAT2   0x1b
#define	MII_TG3_FET_SHDW_AUXSTAT2_APD   0x0020
#define	SERDES_TG3_1000X_STATUS   0x14
#define	SERDES_TG3_SGMII_MODE   0x0001
#define	SERDES_TG3_LINK_UP   0x0002
#define	SERDES_TG3_FULL_DUPLEX   0x0004
#define	SERDES_TG3_SPEED_100   0x0008
#define	SERDES_TG3_SPEED_1000   0x0010
#define	TG3_APE_EVENT   0x000c
#define	APE_EVENT_1   0x00000001
#define	TG3_APE_LOCK_REQ   0x002c
#define	APE_LOCK_REQ_DRIVER   0x00001000
#define	TG3_APE_LOCK_GRANT   0x004c
#define	APE_LOCK_GRANT_DRIVER   0x00001000
#define	TG3_APE_SEG_SIG   0x4000
#define	APE_SEG_SIG_MAGIC   0x41504521
#define	TG3_APE_FW_STATUS   0x400c
#define	APE_FW_STATUS_READY   0x00000100
#define	TG3_APE_FW_FEATURES   0x4010
#define	TG3_APE_FW_FEATURE_NCSI   0x00000002
#define	TG3_APE_FW_VERSION   0x4018
#define	APE_FW_VERSION_MAJMSK   0xff000000
#define	APE_FW_VERSION_MAJSFT   24
#define	APE_FW_VERSION_MINMSK   0x00ff0000
#define	APE_FW_VERSION_MINSFT   16
#define	APE_FW_VERSION_REVMSK   0x0000ff00
#define	APE_FW_VERSION_REVSFT   8
#define	APE_FW_VERSION_BLDMSK   0x000000ff
#define	TG3_APE_HOST_SEG_SIG   0x4200
#define	APE_HOST_SEG_SIG_MAGIC   0x484f5354
#define	TG3_APE_HOST_SEG_LEN   0x4204
#define	APE_HOST_SEG_LEN_MAGIC   0x00000020
#define	TG3_APE_HOST_INIT_COUNT   0x4208
#define	TG3_APE_HOST_DRIVER_ID   0x420c
#define	APE_HOST_DRIVER_ID_LINUX   0xf0000000
#define	APE_HOST_DRIVER_ID_MAGIC(maj, min)
#define	TG3_APE_HOST_BEHAVIOR   0x4210
#define	APE_HOST_BEHAV_NO_PHYLOCK   0x00000001
#define	TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214
#define	APE_HOST_HEARTBEAT_INT_DISABLE   0
#define	APE_HOST_HEARTBEAT_INT_5SEC   5000
#define	TG3_APE_HOST_HEARTBEAT_COUNT   0x4218
#define	TG3_APE_HOST_DRVR_STATE   0x421c
#define	TG3_APE_HOST_DRVR_STATE_START   0x00000001
#define	TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002
#define	TG3_APE_HOST_DRVR_STATE_WOL   0x00000003
#define	TG3_APE_HOST_WOL_SPEED   0x4224
#define	TG3_APE_HOST_WOL_SPEED_AUTO   0x00008000
#define	TG3_APE_EVENT_STATUS   0x4300
#define	APE_EVENT_STATUS_DRIVER_EVNT   0x00000010
#define	APE_EVENT_STATUS_STATE_CHNGE   0x00000500
#define	APE_EVENT_STATUS_STATE_START   0x00010000
#define	APE_EVENT_STATUS_STATE_UNLOAD   0x00020000
#define	APE_EVENT_STATUS_STATE_WOL   0x00030000
#define	APE_EVENT_STATUS_STATE_SUSPEND   0x00040000
#define	APE_EVENT_STATUS_EVENT_PENDING   0x80000000
#define	TG3_APE_PER_LOCK_REQ   0x8400
#define	APE_LOCK_PER_REQ_DRIVER   0x00001000
#define	TG3_APE_PER_LOCK_GRANT   0x8420
#define	APE_PER_LOCK_GRANT_DRIVER   0x00001000
#define	TG3_APE_LOCK_GRC   1
#define	TG3_APE_LOCK_MEM   4
#define	TG3_EEPROM_SB_F1R2_MBA_OFF   0x10
#define	TXD_FLAG_TCPUDP_CSUM   0x0001
#define	TXD_FLAG_IP_CSUM   0x0002
#define	TXD_FLAG_END   0x0004
#define	TXD_FLAG_IP_FRAG   0x0008
#define	TXD_FLAG_JMB_PKT   0x0008
#define	TXD_FLAG_IP_FRAG_END   0x0010
#define	TXD_FLAG_VLAN   0x0040
#define	TXD_FLAG_COAL_NOW   0x0080
#define	TXD_FLAG_CPU_PRE_DMA   0x0100
#define	TXD_FLAG_CPU_POST_DMA   0x0200
#define	TXD_FLAG_ADD_SRC_ADDR   0x1000
#define	TXD_FLAG_CHOOSE_SRC_ADDR   0x6000
#define	TXD_FLAG_NO_CRC   0x8000
#define	TXD_LEN_SHIFT   16
#define	TXD_VLAN_TAG_SHIFT   0
#define	TXD_MSS_SHIFT   16
#define	TXD_ADDR   0x00UL /* 64-bit */
#define	TXD_LEN_FLAGS   0x08UL /* 32-bit (upper 16-bits are len) */
#define	TXD_VLAN_TAG   0x0cUL /* 32-bit (upper 16-bits are tag) */
#define	TXD_SIZE   0x10UL
#define	RXD_IDX_MASK   0xffff0000
#define	RXD_IDX_SHIFT   16
#define	RXD_LEN_MASK   0x0000ffff
#define	RXD_LEN_SHIFT   0
#define	RXD_TYPE_SHIFT   16
#define	RXD_FLAGS_SHIFT   0
#define	RXD_FLAG_END   0x0004
#define	RXD_FLAG_MINI   0x0800
#define	RXD_FLAG_JUMBO   0x0020
#define	RXD_FLAG_VLAN   0x0040
#define	RXD_FLAG_ERROR   0x0400
#define	RXD_FLAG_IP_CSUM   0x1000
#define	RXD_FLAG_TCPUDP_CSUM   0x2000
#define	RXD_FLAG_IS_TCP   0x4000
#define	RXD_IPCSUM_MASK   0xffff0000
#define	RXD_IPCSUM_SHIFT   16
#define	RXD_TCPCSUM_MASK   0x0000ffff
#define	RXD_TCPCSUM_SHIFT   0
#define	RXD_VLAN_MASK   0x0000ffff
#define	RXD_ERR_BAD_CRC   0x00010000
#define	RXD_ERR_COLLISION   0x00020000
#define	RXD_ERR_LINK_LOST   0x00040000
#define	RXD_ERR_PHY_DECODE   0x00080000
#define	RXD_ERR_ODD_NIBBLE_RCVD_MII   0x00100000
#define	RXD_ERR_MAC_ABRT   0x00200000
#define	RXD_ERR_TOO_SMALL   0x00400000
#define	RXD_ERR_NO_RESOURCES   0x00800000
#define	RXD_ERR_HUGE_FRAME   0x01000000
#define	RXD_ERR_MASK   0xffff0000
#define	RXD_OPAQUE_INDEX_MASK   0x0000ffff
#define	RXD_OPAQUE_INDEX_SHIFT   0
#define	RXD_OPAQUE_RING_STD   0x00010000
#define	RXD_OPAQUE_RING_JUMBO   0x00020000
#define	RXD_OPAQUE_RING_MINI   0x00040000
#define	RXD_OPAQUE_RING_MASK   0x00070000
#define	TG3_HW_STATUS_SIZE   0x50
#define	SD_STATUS_UPDATED   0x00000001
#define	SD_STATUS_LINK_CHG   0x00000002
#define	SD_STATUS_ERROR   0x00000004
#define	SPEED_INVALID   0xffff
#define	DUPLEX_INVALID   0xff
#define	AUTONEG_INVALID   0xff
#define	TG3_DEF_RX_RING_PENDING   8
#define	TG3_IRQ_MAX_VECS_RSS   5
#define	TG3_IRQ_MAX_VECS   TG3_IRQ_MAX_VECS_RSS
#define	DIV_ROUND_UP(n, d)
#define	BITS_PER_BYTE   8
#define	BITS_TO_LONGS(nr)
#define	DECLARE_BITMAP(name, bits)
#define	SERDES_AN_TIMEOUT_5704S   2
#define	SERDES_PARALLEL_DET_TIMEOUT   1
#define	SERDES_AN_TIMEOUT_5714S   1
#define	TG3_PHY_ID_MASK   0xfffffff0
#define	TG3_PHY_ID_BCM5400   0x60008040
#define	TG3_PHY_ID_BCM5401   0x60008050
#define	TG3_PHY_ID_BCM5411   0x60008070
#define	TG3_PHY_ID_BCM5701   0x60008110
#define	TG3_PHY_ID_BCM5703   0x60008160
#define	TG3_PHY_ID_BCM5704   0x60008190
#define	TG3_PHY_ID_BCM5705   0x600081a0
#define	TG3_PHY_ID_BCM5750   0x60008180
#define	TG3_PHY_ID_BCM5752   0x60008100
#define	TG3_PHY_ID_BCM5714   0x60008340
#define	TG3_PHY_ID_BCM5780   0x60008350
#define	TG3_PHY_ID_BCM5755   0xbc050cc0
#define	TG3_PHY_ID_BCM5787   0xbc050ce0
#define	TG3_PHY_ID_BCM5756   0xbc050ed0
#define	TG3_PHY_ID_BCM5784   0xbc050fa0
#define	TG3_PHY_ID_BCM5761   0xbc050fd0
#define	TG3_PHY_ID_BCM5718C   0x5c0d8a00
#define	TG3_PHY_ID_BCM5718S   0xbc050ff0
#define	TG3_PHY_ID_BCM57765   0x5c0d8a40
#define	TG3_PHY_ID_BCM5719C   0x5c0d8a20
#define	TG3_PHY_ID_BCM5720C   0x5c0d8b60
#define	TG3_PHY_ID_BCM5906   0xdc00ac40
#define	TG3_PHY_ID_BCM8002   0x60010140
#define	TG3_PHY_ID_INVALID   0xffffffff
#define	PHY_ID_RTL8211C   0x001cc910
#define	PHY_ID_RTL8201E   0x00008200
#define	TG3_PHY_ID_REV_MASK   0x0000000f
#define	TG3_PHY_REV_BCM5401_B0   0x1
#define	TG3_KNOWN_PHY_ID(X)
#define	TG3_PHYFLG_IS_LOW_POWER   0x00000001
#define	TG3_PHYFLG_IS_CONNECTED   0x00000002
#define	TG3_PHYFLG_USE_MI_INTERRUPT   0x00000004
#define	TG3_PHYFLG_PHY_SERDES   0x00000010
#define	TG3_PHYFLG_MII_SERDES   0x00000020
#define	TG3_PHYFLG_ANY_SERDES
#define	TG3_PHYFLG_IS_FET   0x00000040
#define	TG3_PHYFLG_10_100_ONLY   0x00000080
#define	TG3_PHYFLG_ENABLE_APD   0x00000100
#define	TG3_PHYFLG_CAPACITIVE_COUPLING   0x00000200
#define	TG3_PHYFLG_NO_ETH_WIRE_SPEED   0x00000400
#define	TG3_PHYFLG_JITTER_BUG   0x00000800
#define	TG3_PHYFLG_ADJUST_TRIM   0x00001000
#define	TG3_PHYFLG_ADC_BUG   0x00002000
#define	TG3_PHYFLG_5704_A0_BUG   0x00004000
#define	TG3_PHYFLG_BER_BUG   0x00008000
#define	TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
#define	TG3_PHYFLG_PARALLEL_DETECT   0x00020000
#define	TG3_PHYFLG_EEE_CAP   0x00040000
#define	TG3_BPN_SIZE   24
#define	TG3_VER_SIZE   32
#define	TG3_NVRAM_SIZE_2KB   0x00000800
#define	TG3_NVRAM_SIZE_64KB   0x00010000
#define	TG3_NVRAM_SIZE_128KB   0x00020000
#define	TG3_NVRAM_SIZE_256KB   0x00040000
#define	TG3_NVRAM_SIZE_512KB   0x00080000
#define	TG3_NVRAM_SIZE_1MB   0x00100000
#define	TG3_NVRAM_SIZE_2MB   0x00200000
#define	JEDEC_ATMEL   0x1f
#define	JEDEC_ST   0x20
#define	JEDEC_SAIFUN   0x4f
#define	JEDEC_SST   0xbf
#define	ATMEL_AT24C02_CHIP_SIZE   TG3_NVRAM_SIZE_2KB
#define	ATMEL_AT24C02_PAGE_SIZE   (8)
#define	ATMEL_AT24C64_CHIP_SIZE   TG3_NVRAM_SIZE_64KB
#define	ATMEL_AT24C64_PAGE_SIZE   (32)
#define	ATMEL_AT24C512_CHIP_SIZE   TG3_NVRAM_SIZE_512KB
#define	ATMEL_AT24C512_PAGE_SIZE   (128)
#define	ATMEL_AT45DB0X1B_PAGE_POS   9
#define	ATMEL_AT45DB0X1B_PAGE_SIZE   264
#define	ATMEL_AT25F512_PAGE_SIZE   256
#define	ST_M45PEX0_PAGE_SIZE   256
#define	SAIFUN_SA25F0XX_PAGE_SIZE   256
#define	SST_25VF0X0_PAGE_SIZE   4098
#define	TG3_TX_RING_SIZE   512
#define	TG3_DEF_TX_RING_PENDING   (TG3_TX_RING_SIZE - 1)
#define	TG3_DMA_ALIGNMENT   16
#define	TG3_RX_STD_DMA_SZ   (1536 + 64 + 2)
#define	tw32(reg, val)
#define	tw32_mailbox(reg, val)
	#define tw32_mailbox(reg, val) tg3_write_indirect_mbox(((val) & 0xffffffff), tp->regs + (reg))
#define	tw32_mailbox_f(reg, val)
#define	tw32_f(reg, val)
#define	tw32_wait_f(reg, val, us)
#define	tw32_tx_mbox(reg, val)
#define	tw32_rx_mbox(reg, val)
#define	tr32(reg)
#define	tr32_mailbox(reg)
#define	tg3_flag(tp, flag)
#define	tg3_flag_set(tp, flag)
#define	tg3_flag_clear(tp, flag)
#define	ETH_FCS_LEN   4

Enumerations

enum

TG3_FLAGS {   TG3_FLAG_TAGGED_STATUS = 0 , TG3_FLAG_TXD_MBOX_HWBUG , TG3_FLAG_USE_LINKCHG_REG , TG3_FLAG_ERROR_PROCESSED ,   TG3_FLAG_ENABLE_ASF , TG3_FLAG_ASPM_WORKAROUND , TG3_FLAG_POLL_SERDES , TG3_FLAG_MBOX_WRITE_REORDER ,   TG3_FLAG_PCIX_TARGET_HWBUG , TG3_FLAG_WOL_SPEED_100MB , TG3_FLAG_WOL_ENABLE , TG3_FLAG_EEPROM_WRITE_PROT ,   TG3_FLAG_NVRAM , TG3_FLAG_NVRAM_BUFFERED , TG3_FLAG_SUPPORT_MSI , TG3_FLAG_SUPPORT_MSIX ,   TG3_FLAG_PCIX_MODE , TG3_FLAG_PCI_HIGH_SPEED , TG3_FLAG_PCI_32BIT , TG3_FLAG_SRAM_USE_CONFIG ,   TG3_FLAG_TX_RECOVERY_PENDING , TG3_FLAG_WOL_CAP , TG3_FLAG_JUMBO_RING_ENABLE , TG3_FLAG_PAUSE_AUTONEG ,   TG3_FLAG_CPMU_PRESENT , TG3_FLAG_BROKEN_CHECKSUMS , TG3_FLAG_JUMBO_CAPABLE , TG3_FLAG_CHIP_RESETTING ,   TG3_FLAG_INIT_COMPLETE , TG3_FLAG_RESTART_TIMER , TG3_FLAG_TSO_BUG , TG3_FLAG_IS_5788 ,   TG3_FLAG_MAX_RXPEND_64 , TG3_FLAG_TSO_CAPABLE , TG3_FLAG_PCI_EXPRESS , TG3_FLAG_ASF_NEW_HANDSHAKE ,   TG3_FLAG_HW_AUTONEG , TG3_FLAG_IS_NIC , TG3_FLAG_FLASH , TG3_FLAG_HW_TSO_1 ,   TG3_FLAG_5705_PLUS , TG3_FLAG_5750_PLUS , TG3_FLAG_HW_TSO_3 , TG3_FLAG_USING_MSI ,   TG3_FLAG_USING_MSIX , TG3_FLAG_ICH_WORKAROUND , TG3_FLAG_5780_CLASS , TG3_FLAG_HW_TSO_2 ,   TG3_FLAG_1SHOT_MSI , TG3_FLAG_NO_FWARE_REPORTED , TG3_FLAG_NO_NVRAM_ADDR_TRANS , TG3_FLAG_ENABLE_APE ,   TG3_FLAG_PROTECTED_NVRAM , TG3_FLAG_MDIOBUS_INITED , TG3_FLAG_LRG_PROD_RING_CAP , TG3_FLAG_RGMII_INBAND_DISABLE ,   TG3_FLAG_RGMII_EXT_IBND_RX_EN , TG3_FLAG_RGMII_EXT_IBND_TX_EN , TG3_FLAG_CLKREQ_BUG , TG3_FLAG_5755_PLUS ,   TG3_FLAG_NO_NVRAM , TG3_FLAG_ENABLE_RSS , TG3_FLAG_ENABLE_TSS , TG3_FLAG_4G_DMA_BNDRY_BUG ,   TG3_FLAG_USE_JUMBO_BDFLAG , TG3_FLAG_L1PLLPD_EN , TG3_FLAG_57765_PLUS , TG3_FLAG_APE_HAS_NCSI ,   TG3_FLAG_5717_PLUS , TG3_FLAG_NUMBER_OF_FLAGS }

Functions
static void	tw32_mailbox_flush (struct tg3 *tp, u32 off, u32 val)
u32	tg3_read_indirect_reg32 (struct tg3 *tp, u32 off)
void	tg3_write_indirect_reg32 (struct tg3 *tp, u32 off, u32 val)
u32	tg3_read_indirect_mbox (struct tg3 *tp, u32 off)
void	tg3_write_indirect_mbox (struct tg3 *tp, u32 off, u32 val)
static int	_tg3_flag (enum TG3_FLAGS flag, unsigned long *bits)
static void	_tg3_flag_set (enum TG3_FLAGS flag, unsigned long *bits)
static void	_tg3_flag_clear (enum TG3_FLAGS flag, unsigned long *bits)
int	tg3_init_rings (struct tg3 *tp)
void	tg3_rx_prodring_fini (struct tg3_rx_prodring_set *tpr)
u32	tg3_read_otp_phycfg (struct tg3 *tp)
	int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
void	tg3_mdio_init (struct tg3 *tp)
int	tg3_phy_probe (struct tg3 *tp)
int	tg3_phy_reset (struct tg3 *tp)
int	tg3_setup_phy (struct tg3 *tp, int force_reset)
int	tg3_readphy (struct tg3 *tp, int reg, u32 *val)
int	tg3_writephy (struct tg3 *tp, int reg, u32 val)
void	_tw32_flush (struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
void	tg3_write_mem (struct tg3 *tp, u32 off, u32 val)
int	tg3_get_invariants (struct tg3 *tp)
void	tg3_init_bufmgr_config (struct tg3 *tp)
int	tg3_get_device_address (struct tg3 *tp)
int	tg3_halt (struct tg3 *tp)
void	tg3_set_txd (struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags)
void	tg3_set_power_state_0 (struct tg3 *tp)
int	tg3_alloc_consistent (struct tg3 *tp)
int	tg3_init_hw (struct tg3 *tp, int reset_phy)
void	tg3_poll_link (struct tg3 *tp)
void	tg3_wait_for_event_ack (struct tg3 *tp)
void	__tg3_set_mac_addr (struct tg3 *tp, int skip_mac_1)
void	tg3_disable_ints (struct tg3 *tp)
void	tg3_enable_ints (struct tg3 *tp)
static void	tg3_generate_fw_event (struct tg3 *tp)
static u8	mii_resolve_flowctrl_fdx (u16 lcladv, u16 rmtadv)
	mii_resolve_flowctrl_fdx @lcladv: value of MII ADVERTISE register @rmtadv: value of MII LPA register
static u32	mii_adv_to_ethtool_adv_x (u32 adv)
static u32	ethtool_adv_to_mii_adv_x (u32 ethadv)

Macro Definition Documentation

ERRFILE

#define ERRFILE   ERRFILE_tg3

Definition at line 14 of file tg3.h.

PCI_EXP_LNKCTL

#define PCI_EXP_LNKCTL   16 /* Link Control */

Definition at line 17 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_copper_phy().

PCI_EXP_LNKCTL_CLKREQ_EN

#define PCI_EXP_LNKCTL_CLKREQ_EN   0x100 /* Enable clkreq */

Definition at line 18 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_copper_phy().

PCI_CAP_ID_PCIX

#define PCI_CAP_ID_PCIX   0x07 /* PCI-X */

Definition at line 19 of file tg3.h.

PCI_X_CMD_READ_2K

#define PCI_X_CMD_READ_2K   0x0008 /* 2Kbyte maximum read byte count */

Definition at line 21 of file tg3.h.

Referenced by tg3_reset_hw().

PCI_X_CMD_MAX_READ

#define PCI_X_CMD_MAX_READ   0x000c /* Max Memory Read Byte Count */

Definition at line 22 of file tg3.h.

Referenced by tg3_reset_hw().

PCI_X_CMD_MAX_SPLIT

#define PCI_X_CMD_MAX_SPLIT   0x0070 /* Max Outstanding Split Transactions */

Definition at line 24 of file tg3.h.

Referenced by tg3_reset_hw().

ADVERTISED_10baseT_Half

#define ADVERTISED_10baseT_Half   (1 << 0)

Definition at line 28 of file tg3.h.

ADVERTISED_10baseT_Full

#define ADVERTISED_10baseT_Full   (1 << 1)

Definition at line 29 of file tg3.h.

ADVERTISED_100baseT_Half

#define ADVERTISED_100baseT_Half   (1 << 2)

Definition at line 30 of file tg3.h.

ADVERTISED_100baseT_Full

#define ADVERTISED_100baseT_Full   (1 << 3)

Definition at line 31 of file tg3.h.

ADVERTISED_1000baseT_Half

#define ADVERTISED_1000baseT_Half   (1 << 4)

Definition at line 32 of file tg3.h.

ADVERTISED_1000baseT_Full

#define ADVERTISED_1000baseT_Full   (1 << 5)

Definition at line 33 of file tg3.h.

ADVERTISED_Autoneg

#define ADVERTISED_Autoneg   (1 << 6)

Definition at line 34 of file tg3.h.

ADVERTISED_Pause

#define ADVERTISED_Pause   (1 << 13)

Definition at line 38 of file tg3.h.

Referenced by ethtool_adv_to_mii_adv_x(), mii_adv_to_ethtool_adv_x(), and tg3_phy_init_link_config().

ADVERTISED_Asym_Pause

#define ADVERTISED_Asym_Pause   (1 << 14)

Definition at line 41 of file tg3.h.

Referenced by ethtool_adv_to_mii_adv_x(), and mii_adv_to_ethtool_adv_x().

MDIO_AN_EEE_ADV

#define MDIO_AN_EEE_ADV   60 /* EEE advertisement */

Definition at line 45 of file tg3.h.

MDIO_MMD_AN

#define MDIO_MMD_AN   7 /* Auto-Negotiation */

Definition at line 47 of file tg3.h.

MDIO_AN_EEE_ADV_100TX

#define MDIO_AN_EEE_ADV_100TX   0x0002 /* Advertise 100TX EEE cap */

Definition at line 49 of file tg3.h.

MDIO_AN_EEE_ADV_1000T

#define MDIO_AN_EEE_ADV_1000T   0x0004 /* Advertise 1000T EEE cap */

Definition at line 50 of file tg3.h.

FLOW_CTRL_TX

#define FLOW_CTRL_TX   0x01

Definition at line 54 of file tg3.h.

FLOW_CTRL_RX

#define FLOW_CTRL_RX   0x02

Definition at line 55 of file tg3.h.

PCI_X_CMD

#define PCI_X_CMD   2 /* Modes & Features */

Definition at line 59 of file tg3.h.

PCI_X_CMD_ERO

#define PCI_X_CMD_ERO   0x0002 /* Enable Relaxed Ordering */

Definition at line 60 of file tg3.h.

PCI_EXP_DEVCTL_RELAX_EN

#define PCI_EXP_DEVCTL_RELAX_EN   0x0010 /* Enable relaxed ordering */

Definition at line 62 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVCTL_NOSNOOP_EN

#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800 /* Enable No Snoop */

Definition at line 63 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVCTL_PAYLOAD

#define PCI_EXP_DEVCTL_PAYLOAD   0x00e0 /* Max_Payload_Size */

Definition at line 64 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVSTA

#define PCI_EXP_DEVSTA   10 /* Device Status */

Definition at line 65 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVSTA_CED

#define PCI_EXP_DEVSTA_CED   0x01 /* Correctable Error Detected */

Definition at line 66 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVSTA_NFED

#define PCI_EXP_DEVSTA_NFED   0x02 /* Non-Fatal Error Detected */

Definition at line 67 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVSTA_FED

#define PCI_EXP_DEVSTA_FED   0x04 /* Fatal Error Detected */

Definition at line 68 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_EXP_DEVSTA_URD

#define PCI_EXP_DEVSTA_URD   0x08 /* Unsupported Request Detected */

Definition at line 69 of file tg3.h.

Referenced by tg3_chip_reset().

PCI_VENDOR_ID_BROADCOM

#define PCI_VENDOR_ID_BROADCOM   0x14e4

Definition at line 73 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5752

#define PCI_DEVICE_ID_TIGON3_5752   0x1600

Definition at line 74 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5752M

#define PCI_DEVICE_ID_TIGON3_5752M   0x1601

Definition at line 75 of file tg3.h.

PCI_DEVICE_ID_NX2_5709

#define PCI_DEVICE_ID_NX2_5709   0x1639

Definition at line 76 of file tg3.h.

PCI_DEVICE_ID_NX2_5709S

#define PCI_DEVICE_ID_NX2_5709S   0x163a

Definition at line 77 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5700

#define PCI_DEVICE_ID_TIGON3_5700   0x1644

Definition at line 78 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5701

#define PCI_DEVICE_ID_TIGON3_5701   0x1645

Definition at line 79 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5702

#define PCI_DEVICE_ID_TIGON3_5702   0x1646

Definition at line 80 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5703

#define PCI_DEVICE_ID_TIGON3_5703   0x1647

Definition at line 81 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5704

#define PCI_DEVICE_ID_TIGON3_5704   0x1648

Definition at line 82 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5704S_2

#define PCI_DEVICE_ID_TIGON3_5704S_2   0x1649

Definition at line 83 of file tg3.h.

PCI_DEVICE_ID_NX2_5706

#define PCI_DEVICE_ID_NX2_5706   0x164a

Definition at line 84 of file tg3.h.

PCI_DEVICE_ID_NX2_5708

#define PCI_DEVICE_ID_NX2_5708   0x164c

Definition at line 85 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5702FE

#define PCI_DEVICE_ID_TIGON3_5702FE   0x164d

Definition at line 86 of file tg3.h.

PCI_DEVICE_ID_NX2_57710

#define PCI_DEVICE_ID_NX2_57710   0x164e

Definition at line 87 of file tg3.h.

PCI_DEVICE_ID_NX2_57711

#define PCI_DEVICE_ID_NX2_57711   0x164f

Definition at line 88 of file tg3.h.

PCI_DEVICE_ID_NX2_57711E

#define PCI_DEVICE_ID_NX2_57711E   0x1650

Definition at line 89 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5705

#define PCI_DEVICE_ID_TIGON3_5705   0x1653

Definition at line 90 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5705_2

#define PCI_DEVICE_ID_TIGON3_5705_2   0x1654

Definition at line 91 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5721

#define PCI_DEVICE_ID_TIGON3_5721   0x1659

Definition at line 92 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5722

#define PCI_DEVICE_ID_TIGON3_5722   0x165a

Definition at line 93 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5723

#define PCI_DEVICE_ID_TIGON3_5723   0x165b

Definition at line 94 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5705M

#define PCI_DEVICE_ID_TIGON3_5705M   0x165d

Definition at line 95 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5705M_2

#define PCI_DEVICE_ID_TIGON3_5705M_2   0x165e

Definition at line 96 of file tg3.h.

PCI_DEVICE_ID_NX2_57712

#define PCI_DEVICE_ID_NX2_57712   0x1662

Definition at line 97 of file tg3.h.

PCI_DEVICE_ID_NX2_57712E

#define PCI_DEVICE_ID_NX2_57712E   0x1663

Definition at line 98 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5714

#define PCI_DEVICE_ID_TIGON3_5714   0x1668

Definition at line 99 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5714S

#define PCI_DEVICE_ID_TIGON3_5714S   0x1669

Definition at line 100 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5780

#define PCI_DEVICE_ID_TIGON3_5780   0x166a

Definition at line 101 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5780S

#define PCI_DEVICE_ID_TIGON3_5780S   0x166b

Definition at line 102 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5705F

#define PCI_DEVICE_ID_TIGON3_5705F   0x166e

Definition at line 103 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5754M

#define PCI_DEVICE_ID_TIGON3_5754M   0x1672

Definition at line 104 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5755M

#define PCI_DEVICE_ID_TIGON3_5755M   0x1673

Definition at line 105 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5756

#define PCI_DEVICE_ID_TIGON3_5756   0x1674

Definition at line 106 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5751

#define PCI_DEVICE_ID_TIGON3_5751   0x1677

Definition at line 107 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5715

#define PCI_DEVICE_ID_TIGON3_5715   0x1678

Definition at line 108 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5715S

#define PCI_DEVICE_ID_TIGON3_5715S   0x1679

Definition at line 109 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5754

#define PCI_DEVICE_ID_TIGON3_5754   0x167a

Definition at line 110 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5755

#define PCI_DEVICE_ID_TIGON3_5755   0x167b

Definition at line 111 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5751M

#define PCI_DEVICE_ID_TIGON3_5751M   0x167d

Definition at line 112 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5751F

#define PCI_DEVICE_ID_TIGON3_5751F   0x167e

Definition at line 113 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5787F

#define PCI_DEVICE_ID_TIGON3_5787F   0x167f

Definition at line 114 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5761E

#define PCI_DEVICE_ID_TIGON3_5761E   0x1680

Definition at line 115 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5761

#define PCI_DEVICE_ID_TIGON3_5761   0x1681

Definition at line 116 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5764

#define PCI_DEVICE_ID_TIGON3_5764   0x1684

Definition at line 117 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5787M

#define PCI_DEVICE_ID_TIGON3_5787M   0x1693

Definition at line 118 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5782

#define PCI_DEVICE_ID_TIGON3_5782   0x1696

Definition at line 119 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5784

#define PCI_DEVICE_ID_TIGON3_5784   0x1698

Definition at line 120 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5786

#define PCI_DEVICE_ID_TIGON3_5786   0x169a

Definition at line 121 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5787

#define PCI_DEVICE_ID_TIGON3_5787   0x169b

Definition at line 122 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5788

#define PCI_DEVICE_ID_TIGON3_5788   0x169c

Definition at line 123 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5789

#define PCI_DEVICE_ID_TIGON3_5789   0x169d

Definition at line 124 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5702X

#define PCI_DEVICE_ID_TIGON3_5702X   0x16a6

Definition at line 125 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5703X

#define PCI_DEVICE_ID_TIGON3_5703X   0x16a7

Definition at line 126 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5704S

#define PCI_DEVICE_ID_TIGON3_5704S   0x16a8

Definition at line 127 of file tg3.h.

PCI_DEVICE_ID_NX2_5706S

#define PCI_DEVICE_ID_NX2_5706S   0x16aa

Definition at line 128 of file tg3.h.

PCI_DEVICE_ID_NX2_5708S

#define PCI_DEVICE_ID_NX2_5708S   0x16ac

Definition at line 129 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5702A3

#define PCI_DEVICE_ID_TIGON3_5702A3   0x16c6

Definition at line 130 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5703A3

#define PCI_DEVICE_ID_TIGON3_5703A3   0x16c7

Definition at line 131 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5781

#define PCI_DEVICE_ID_TIGON3_5781   0x16dd

Definition at line 132 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5753

#define PCI_DEVICE_ID_TIGON3_5753   0x16f7

Definition at line 133 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5753M

#define PCI_DEVICE_ID_TIGON3_5753M   0x16fd

Definition at line 134 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5753F

#define PCI_DEVICE_ID_TIGON3_5753F   0x16fe

Definition at line 135 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5901

#define PCI_DEVICE_ID_TIGON3_5901   0x170d

Definition at line 136 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5901_2

#define PCI_DEVICE_ID_TIGON3_5901_2   0x170e

Definition at line 137 of file tg3.h.

Referenced by tg3_get_invariants().

PCI_DEVICE_ID_TIGON3_5906

#define PCI_DEVICE_ID_TIGON3_5906   0x1712

Definition at line 138 of file tg3.h.

PCI_DEVICE_ID_TIGON3_5906M

#define PCI_DEVICE_ID_TIGON3_5906M   0x1713

Definition at line 139 of file tg3.h.

PCI_VENDOR_ID_COMPAQ

#define PCI_VENDOR_ID_COMPAQ   0x0e11

Definition at line 140 of file tg3.h.

PCI_VENDOR_ID_IBM

#define PCI_VENDOR_ID_IBM   0x1014

Definition at line 141 of file tg3.h.

PCI_VENDOR_ID_DELL

#define PCI_VENDOR_ID_DELL   0x1028

Definition at line 142 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

PCI_VENDOR_ID_3COM

#define PCI_VENDOR_ID_3COM   0x10b7

Definition at line 143 of file tg3.h.

SPEED_10

#define SPEED_10   10

Definition at line 146 of file tg3.h.

SPEED_100

#define SPEED_100   100

Definition at line 147 of file tg3.h.

SPEED_1000

#define SPEED_1000   1000

Definition at line 148 of file tg3.h.

SPEED_UNKNOWN

#define SPEED_UNKNOWN   -1

Definition at line 150 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

DUPLEX_HALF

#define DUPLEX_HALF   0x00

Definition at line 153 of file tg3.h.

DUPLEX_FULL

#define DUPLEX_FULL   0x01

Definition at line 154 of file tg3.h.

DUPLEX_UNKNOWN

#define DUPLEX_UNKNOWN   0xff

Definition at line 156 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

TG3_64BIT_REG_HIGH

#define TG3_64BIT_REG_HIGH   0x00UL

Definition at line 159 of file tg3.h.

Referenced by tg3_reset_hw(), tg3_rings_reset(), and tg3_set_bdinfo().

TG3_64BIT_REG_LOW

#define TG3_64BIT_REG_LOW   0x04UL

Definition at line 160 of file tg3.h.

Referenced by tg3_init_one(), tg3_reset_hw(), tg3_rings_reset(), tg3_set_bdinfo(), and tg3_write_indirect_mbox().

TG3_BDINFO_HOST_ADDR

#define TG3_BDINFO_HOST_ADDR   0x0UL /* 64-bit */

Definition at line 163 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_set_bdinfo().

TG3_BDINFO_MAXLEN_FLAGS

#define TG3_BDINFO_MAXLEN_FLAGS   0x8UL /* 32-bit */

Definition at line 164 of file tg3.h.

Referenced by tg3_reset_hw(), tg3_rings_reset(), and tg3_set_bdinfo().

BDINFO_FLAGS_USE_EXT_RECV

#define BDINFO_FLAGS_USE_EXT_RECV   0x00000001 /* ext rx_buffer_desc */

Definition at line 165 of file tg3.h.

BDINFO_FLAGS_DISABLED

#define BDINFO_FLAGS_DISABLED   0x00000002

Definition at line 166 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_rings_reset().

BDINFO_FLAGS_MAXLEN_MASK

#define BDINFO_FLAGS_MAXLEN_MASK   0xffff0000

Definition at line 167 of file tg3.h.

BDINFO_FLAGS_MAXLEN_SHIFT

#define BDINFO_FLAGS_MAXLEN_SHIFT   16

Definition at line 168 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_rings_reset().

TG3_BDINFO_NIC_ADDR

#define TG3_BDINFO_NIC_ADDR   0xcUL /* 32-bit */

Definition at line 169 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_set_bdinfo().

TG3_BDINFO_SIZE

#define TG3_BDINFO_SIZE   0x10UL

Definition at line 170 of file tg3.h.

Referenced by tg3_rings_reset().

RX_STD_MAX_SIZE

#define RX_STD_MAX_SIZE   1536

Definition at line 172 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RX_STD_MAX_SIZE_5700

#define TG3_RX_STD_MAX_SIZE_5700   512

Definition at line 173 of file tg3.h.

Referenced by tg3_alloc_rx_iob(), tg3_refill_prod_ring(), tg3_reset_hw(), and tg3_rx_prodring_alloc().

TG3_RX_STD_MAX_SIZE_5717

#define TG3_RX_STD_MAX_SIZE_5717   2048

Definition at line 174 of file tg3.h.

TG3_RX_JMB_MAX_SIZE_5700

#define TG3_RX_JMB_MAX_SIZE_5700   256

Definition at line 175 of file tg3.h.

TG3_RX_JMB_MAX_SIZE_5717

#define TG3_RX_JMB_MAX_SIZE_5717   1024

Definition at line 176 of file tg3.h.

TG3_RX_RET_MAX_SIZE_5700

#define TG3_RX_RET_MAX_SIZE_5700   1024

Definition at line 177 of file tg3.h.

TG3_RX_RET_MAX_SIZE_5705

#define TG3_RX_RET_MAX_SIZE_5705   512

Definition at line 178 of file tg3.h.

Referenced by tg3_rings_reset(), and tg3_rx_complete().

TG3_RX_RET_MAX_SIZE_5717

#define TG3_RX_RET_MAX_SIZE_5717   4096

Definition at line 179 of file tg3.h.

TG3PCI_VENDOR

#define TG3PCI_VENDOR   0x00000000

Definition at line 182 of file tg3.h.

TG3PCI_VENDOR_BROADCOM

#define TG3PCI_VENDOR_BROADCOM   0x14e4

Definition at line 183 of file tg3.h.

TG3PCI_DEVICE

#define TG3PCI_DEVICE   0x00000002

Definition at line 184 of file tg3.h.

TG3PCI_DEVICE_TIGON3_1

#define TG3PCI_DEVICE_TIGON3_1   0x1644 /* BCM5700 */

Definition at line 185 of file tg3.h.

TG3PCI_DEVICE_TIGON3_2

#define TG3PCI_DEVICE_TIGON3_2   0x1645 /* BCM5701 */

Definition at line 186 of file tg3.h.

TG3PCI_DEVICE_TIGON3_3

#define TG3PCI_DEVICE_TIGON3_3   0x1646 /* BCM5702 */

Definition at line 187 of file tg3.h.

TG3PCI_DEVICE_TIGON3_4

#define TG3PCI_DEVICE_TIGON3_4   0x1647 /* BCM5703 */

Definition at line 188 of file tg3.h.

TG3PCI_DEVICE_TIGON3_5761S

#define TG3PCI_DEVICE_TIGON3_5761S   0x1688

Definition at line 189 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_5761SE

#define TG3PCI_DEVICE_TIGON3_5761SE   0x1689

Definition at line 190 of file tg3.h.

TG3PCI_DEVICE_TIGON3_57780

#define TG3PCI_DEVICE_TIGON3_57780   0x1692

Definition at line 191 of file tg3.h.

TG3PCI_DEVICE_TIGON3_57760

#define TG3PCI_DEVICE_TIGON3_57760   0x1690

Definition at line 192 of file tg3.h.

TG3PCI_DEVICE_TIGON3_57790

#define TG3PCI_DEVICE_TIGON3_57790   0x1694

Definition at line 193 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57788

#define TG3PCI_DEVICE_TIGON3_57788   0x1691

Definition at line 194 of file tg3.h.

TG3PCI_DEVICE_TIGON3_5785_G

#define TG3PCI_DEVICE_TIGON3_5785_G   0x1699 /* GPHY */

Definition at line 195 of file tg3.h.

TG3PCI_DEVICE_TIGON3_5785_F

#define TG3PCI_DEVICE_TIGON3_5785_F   0x16a0 /* 10/100 only */

Definition at line 196 of file tg3.h.

TG3PCI_DEVICE_TIGON3_5717

#define TG3PCI_DEVICE_TIGON3_5717   0x1655

Definition at line 197 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_5718

#define TG3PCI_DEVICE_TIGON3_5718   0x1656

Definition at line 198 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_probe().

TG3PCI_DEVICE_TIGON3_57781

#define TG3PCI_DEVICE_TIGON3_57781   0x16b1

Definition at line 199 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57785

#define TG3PCI_DEVICE_TIGON3_57785   0x16b5

Definition at line 200 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57761

#define TG3PCI_DEVICE_TIGON3_57761   0x16b0

Definition at line 201 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57762

#define TG3PCI_DEVICE_TIGON3_57762   0x1682

Definition at line 202 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57765

#define TG3PCI_DEVICE_TIGON3_57765   0x16b4

Definition at line 203 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57766

#define TG3PCI_DEVICE_TIGON3_57766   0x1686

Definition at line 204 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57791

#define TG3PCI_DEVICE_TIGON3_57791   0x16b2

Definition at line 205 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_57795

#define TG3PCI_DEVICE_TIGON3_57795   0x16b6

Definition at line 206 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_5719

#define TG3PCI_DEVICE_TIGON3_5719   0x1657

Definition at line 207 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_DEVICE_TIGON3_5720

#define TG3PCI_DEVICE_TIGON3_5720   0x165f

Definition at line 208 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_SUBVENDOR_ID_BROADCOM

#define TG3PCI_SUBVENDOR_ID_BROADCOM   PCI_VENDOR_ID_BROADCOM

Definition at line 210 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644

Definition at line 211 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5   0x0001

Definition at line 212 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6   0x0002

Definition at line 213 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9   0x0003

Definition at line 214 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1   0x0005

Definition at line 215 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8   0x0006

Definition at line 216 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7   0x0007

Definition at line 217 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10   0x0008

Definition at line 218 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12   0x8008

Definition at line 219 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1   0x0009

Definition at line 220 of file tg3.h.

TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2

#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2   0x8009

Definition at line 221 of file tg3.h.

TG3PCI_SUBVENDOR_ID_3COM

#define TG3PCI_SUBVENDOR_ID_3COM   PCI_VENDOR_ID_3COM

Definition at line 222 of file tg3.h.

TG3PCI_SUBDEVICE_ID_3COM_3C996T

#define TG3PCI_SUBDEVICE_ID_3COM_3C996T   0x1000

Definition at line 223 of file tg3.h.

TG3PCI_SUBDEVICE_ID_3COM_3C996BT

#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT   0x1006

Definition at line 224 of file tg3.h.

TG3PCI_SUBDEVICE_ID_3COM_3C996SX

#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX   0x1004

Definition at line 225 of file tg3.h.

TG3PCI_SUBDEVICE_ID_3COM_3C1000T

#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T   0x1007

Definition at line 226 of file tg3.h.

TG3PCI_SUBDEVICE_ID_3COM_3C940BR01

#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01   0x1008

Definition at line 227 of file tg3.h.

TG3PCI_SUBVENDOR_ID_DELL

#define TG3PCI_SUBVENDOR_ID_DELL   PCI_VENDOR_ID_DELL

Definition at line 228 of file tg3.h.

TG3PCI_SUBDEVICE_ID_DELL_VIPER

#define TG3PCI_SUBDEVICE_ID_DELL_VIPER   0x00d1

Definition at line 229 of file tg3.h.

TG3PCI_SUBDEVICE_ID_DELL_JAGUAR

#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR   0x0106

Definition at line 230 of file tg3.h.

TG3PCI_SUBDEVICE_ID_DELL_MERLOT

#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT   0x0109

Definition at line 231 of file tg3.h.

TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT

#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT   0x010a

Definition at line 232 of file tg3.h.

TG3PCI_SUBVENDOR_ID_COMPAQ

#define TG3PCI_SUBVENDOR_ID_COMPAQ   PCI_VENDOR_ID_COMPAQ

Definition at line 233 of file tg3.h.

TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE

#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE   0x007c

Definition at line 234 of file tg3.h.

TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2

#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2   0x009a

Definition at line 235 of file tg3.h.

TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING

#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING   0x007d

Definition at line 236 of file tg3.h.

TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780

#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780   0x0085

Definition at line 237 of file tg3.h.

TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2

#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2   0x0099

Definition at line 238 of file tg3.h.

TG3PCI_SUBVENDOR_ID_IBM

#define TG3PCI_SUBVENDOR_ID_IBM   PCI_VENDOR_ID_IBM

Definition at line 239 of file tg3.h.

TG3PCI_SUBDEVICE_ID_IBM_5703SAX2

#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2   0x0281

Definition at line 240 of file tg3.h.

TG3PCI_MSI_DATA

#define TG3PCI_MSI_DATA   0x00000064

Definition at line 242 of file tg3.h.

Referenced by tg3_reset_hw().

TG3PCI_MISC_HOST_CTRL

#define TG3PCI_MISC_HOST_CTRL   0x00000068

Definition at line 244 of file tg3.h.

Referenced by tg3_disable_ints(), tg3_enable_ints(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_restore_pci_state(), and tg3_set_power_state_0().

MISC_HOST_CTRL_CLEAR_INT

#define MISC_HOST_CTRL_CLEAR_INT   0x00000001

Definition at line 245 of file tg3.h.

MISC_HOST_CTRL_MASK_PCI_INT

#define MISC_HOST_CTRL_MASK_PCI_INT   0x00000002

Definition at line 246 of file tg3.h.

Referenced by tg3_disable_ints(), tg3_enable_ints(), and tg3_init_one().

MISC_HOST_CTRL_BYTE_SWAP

#define MISC_HOST_CTRL_BYTE_SWAP   0x00000004

Definition at line 247 of file tg3.h.

MISC_HOST_CTRL_WORD_SWAP

#define MISC_HOST_CTRL_WORD_SWAP   0x00000008

Definition at line 248 of file tg3.h.

Referenced by tg3_init_one().

MISC_HOST_CTRL_PCISTATE_RW

#define MISC_HOST_CTRL_PCISTATE_RW   0x00000010

Definition at line 249 of file tg3.h.

Referenced by tg3_init_one().

MISC_HOST_CTRL_CLKREG_RW

#define MISC_HOST_CTRL_CLKREG_RW   0x00000020

Definition at line 250 of file tg3.h.

MISC_HOST_CTRL_REGWORD_SWAP

#define MISC_HOST_CTRL_REGWORD_SWAP   0x00000040

Definition at line 251 of file tg3.h.

MISC_HOST_CTRL_INDIR_ACCESS

#define MISC_HOST_CTRL_INDIR_ACCESS   0x00000080

Definition at line 252 of file tg3.h.

Referenced by tg3_init_one().

MISC_HOST_CTRL_IRQ_MASK_MODE

#define MISC_HOST_CTRL_IRQ_MASK_MODE   0x00000100

Definition at line 253 of file tg3.h.

MISC_HOST_CTRL_TAGGED_STATUS

#define MISC_HOST_CTRL_TAGGED_STATUS   0x00000200

Definition at line 254 of file tg3.h.

Referenced by tg3_get_invariants().

MISC_HOST_CTRL_CHIPREV

#define MISC_HOST_CTRL_CHIPREV   0xffff0000

Definition at line 255 of file tg3.h.

Referenced by tg3_get_invariants().

MISC_HOST_CTRL_CHIPREV_SHIFT

#define MISC_HOST_CTRL_CHIPREV_SHIFT   16

Definition at line 256 of file tg3.h.

Referenced by tg3_get_invariants().

GET_CHIP_REV_ID

#define GET_CHIP_REV_ID

(

MISC_HOST_CTRL

)

Value:

         (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
          MISC_HOST_CTRL_CHIPREV_SHIFT)

Definition at line 257 of file tg3.h.

#define  GET_CHIP_REV_ID(MISC_HOST_CTRL) \
         (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
          MISC_HOST_CTRL_CHIPREV_SHIFT)

Referenced by tg3_get_invariants().

CHIPREV_ID_5700_A0

#define CHIPREV_ID_5700_A0   0x7000

Definition at line 260 of file tg3.h.

CHIPREV_ID_5700_A1

#define CHIPREV_ID_5700_A1   0x7001

Definition at line 261 of file tg3.h.

CHIPREV_ID_5700_B0

#define CHIPREV_ID_5700_B0   0x7100

Definition at line 262 of file tg3.h.

CHIPREV_ID_5700_B1

#define CHIPREV_ID_5700_B1   0x7101

Definition at line 263 of file tg3.h.

CHIPREV_ID_5700_B3

#define CHIPREV_ID_5700_B3   0x7102

Definition at line 264 of file tg3.h.

CHIPREV_ID_5700_ALTIMA

#define CHIPREV_ID_5700_ALTIMA   0x7104

Definition at line 265 of file tg3.h.

Referenced by tg3_setup_copper_phy().

CHIPREV_ID_5700_C0

#define CHIPREV_ID_5700_C0   0x7200

Definition at line 266 of file tg3.h.

CHIPREV_ID_5701_A0

#define CHIPREV_ID_5701_A0   0x0000

Definition at line 267 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_autoneg_cfg(), tg3_reset_hw(), and tg3_setup_copper_phy().

CHIPREV_ID_5701_B0

#define CHIPREV_ID_5701_B0   0x0100

Definition at line 268 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_autoneg_cfg(), and tg3_setup_copper_phy().

CHIPREV_ID_5701_B2

#define CHIPREV_ID_5701_B2   0x0102

Definition at line 269 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5701_B5

#define CHIPREV_ID_5701_B5   0x0105

Definition at line 270 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5703_A0

#define CHIPREV_ID_5703_A0   0x1000

Definition at line 271 of file tg3.h.

CHIPREV_ID_5703_A1

#define CHIPREV_ID_5703_A1   0x1001

Definition at line 272 of file tg3.h.

Referenced by tg3_reset_hw().

CHIPREV_ID_5703_A2

#define CHIPREV_ID_5703_A2   0x1002

Definition at line 273 of file tg3.h.

CHIPREV_ID_5703_A3

#define CHIPREV_ID_5703_A3   0x1003

Definition at line 274 of file tg3.h.

CHIPREV_ID_5704_A0

#define CHIPREV_ID_5704_A0   0x2000

Definition at line 275 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_reset_hw(), tg3_restore_pci_state(), and tg3_setup_fiber_hw_autoneg().

CHIPREV_ID_5704_A1

#define CHIPREV_ID_5704_A1   0x2001

Definition at line 276 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

CHIPREV_ID_5704_A2

#define CHIPREV_ID_5704_A2   0x2002

Definition at line 277 of file tg3.h.

CHIPREV_ID_5704_A3

#define CHIPREV_ID_5704_A3   0x2003

Definition at line 278 of file tg3.h.

CHIPREV_ID_5705_A0

#define CHIPREV_ID_5705_A0   0x3000

Definition at line 279 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_reset_hw().

CHIPREV_ID_5705_A1

#define CHIPREV_ID_5705_A1   0x3001

Definition at line 280 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5705_A2

#define CHIPREV_ID_5705_A2   0x3002

Definition at line 281 of file tg3.h.

CHIPREV_ID_5705_A3

#define CHIPREV_ID_5705_A3   0x3003

Definition at line 282 of file tg3.h.

CHIPREV_ID_5750_A0

#define CHIPREV_ID_5750_A0   0x4000

Definition at line 283 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_get_eeprom_hw_cfg().

CHIPREV_ID_5750_A1

#define CHIPREV_ID_5750_A1   0x4001

Definition at line 284 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

CHIPREV_ID_5750_A3

#define CHIPREV_ID_5750_A3   0x4003

Definition at line 285 of file tg3.h.

Referenced by tg3_chip_reset().

CHIPREV_ID_5750_C2

#define CHIPREV_ID_5750_C2   0x4202

Definition at line 286 of file tg3.h.

CHIPREV_ID_5752_A0_HW

#define CHIPREV_ID_5752_A0_HW   0x5000

Definition at line 287 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5752_A0

#define CHIPREV_ID_5752_A0   0x6000

Definition at line 288 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5752_A1

#define CHIPREV_ID_5752_A1   0x6001

Definition at line 289 of file tg3.h.

CHIPREV_ID_5714_A2

#define CHIPREV_ID_5714_A2   0x9002

Definition at line 290 of file tg3.h.

CHIPREV_ID_5906_A1

#define CHIPREV_ID_5906_A1   0xc001

Definition at line 291 of file tg3.h.

Referenced by tg3_reset_hw().

CHIPREV_ID_57780_A0

#define CHIPREV_ID_57780_A0   0x57780000

Definition at line 292 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_57780_A1

#define CHIPREV_ID_57780_A1   0x57780001

Definition at line 293 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_ID_5717_A0

#define CHIPREV_ID_5717_A0   0x05717000

Definition at line 294 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_mdio_init(), and tg3_phy_probe().

CHIPREV_ID_57765_A0

#define CHIPREV_ID_57765_A0   0x57785000

Definition at line 295 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_poll_fw(), and tg3_reset_hw().

CHIPREV_ID_5719_A0

#define CHIPREV_ID_5719_A0   0x05719000

Definition at line 296 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

CHIPREV_ID_5720_A0

#define CHIPREV_ID_5720_A0   0x05720000

Definition at line 297 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GET_ASIC_REV

#define GET_ASIC_REV

(

CHIP_REV_ID

)

Value:

((CHIP_REV_ID) >> 12)

Definition at line 298 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_chip_reset(), tg3_get_device_address(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_init_bufmgr_config(), tg3_phy_probe(), tg3_phy_reset(), tg3_poll_fw(), tg3_read_mem(), tg3_reset_hw(), tg3_restore_pci_state(), tg3_rings_reset(), tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), tg3_setup_phy(), tg3_setup_rxbd_thresholds(), tg3_test_dma(), and tg3_write_mem().

ASIC_REV_5700

#define ASIC_REV_5700   0x07

Definition at line 299 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_test_dma().

ASIC_REV_5701

#define ASIC_REV_5701   0x00

Definition at line 300 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), tg3_setup_copper_phy(), and tg3_test_dma().

ASIC_REV_5703

#define ASIC_REV_5703   0x01

Definition at line 301 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_phy_reset(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_test_dma().

ASIC_REV_5704

#define ASIC_REV_5704   0x02

Definition at line 302 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_get_device_address(), tg3_phy_reset(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_test_dma().

ASIC_REV_5705

#define ASIC_REV_5705   0x03

Definition at line 303 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_phy_reset(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_test_dma().

ASIC_REV_5750

#define ASIC_REV_5750   0x04

Definition at line 304 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_setup_rxbd_thresholds(), and tg3_test_dma().

ASIC_REV_5752

#define ASIC_REV_5752   0x06

Definition at line 305 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_reset_hw(), and tg3_setup_rxbd_thresholds().

ASIC_REV_5780

#define ASIC_REV_5780   0x08

Definition at line 306 of file tg3.h.

Referenced by tg3_test_dma().

ASIC_REV_5714

#define ASIC_REV_5714   0x09

Definition at line 307 of file tg3.h.

Referenced by tg3_reset_hw(), tg3_setup_fiber_mii_phy(), and tg3_test_dma().

ASIC_REV_5755

#define ASIC_REV_5755   0x0a

Definition at line 308 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_reset_hw(), tg3_rings_reset(), and tg3_setup_rxbd_thresholds().

ASIC_REV_5787

#define ASIC_REV_5787   0x0b

Definition at line 309 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_rxbd_thresholds().

ASIC_REV_5906

#define ASIC_REV_5906   0x0c

Definition at line 310 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_device_address(), tg3_get_invariants(), tg3_init_bufmgr_config(), tg3_phy_reset(), tg3_poll_fw(), tg3_read_mem(), tg3_reset_hw(), and tg3_write_mem().

ASIC_REV_USE_PROD_ID_REG

#define ASIC_REV_USE_PROD_ID_REG   0x0f

Definition at line 311 of file tg3.h.

Referenced by tg3_get_invariants().

ASIC_REV_5784

#define ASIC_REV_5784   0x5784

Definition at line 312 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_phy_reset(), and tg3_reset_hw().

ASIC_REV_5761

#define ASIC_REV_5761   0x5761

Definition at line 313 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

ASIC_REV_5785

#define ASIC_REV_5785   0x5785

Definition at line 314 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_reset_hw(), and tg3_restore_pci_state().

ASIC_REV_57780

#define ASIC_REV_57780   0x57780

Definition at line 315 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_reset_hw().

ASIC_REV_5717

#define ASIC_REV_5717   0x5717

Definition at line 316 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

ASIC_REV_57765

#define ASIC_REV_57765   0x57785

Definition at line 317 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_probe(), tg3_reset_hw(), and tg3_rings_reset().

ASIC_REV_57766

#define ASIC_REV_57766   0x57766

Definition at line 318 of file tg3.h.

Referenced by tg3_get_invariants().

ASIC_REV_5719

#define ASIC_REV_5719   0x5719

Definition at line 319 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_reset_hw(), and tg3_setup_fiber_mii_phy().

ASIC_REV_5720

#define ASIC_REV_5720   0x5720

Definition at line 320 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_reset_hw(), tg3_setup_fiber_mii_phy(), and tg3_setup_phy().

GET_CHIP_REV

#define GET_CHIP_REV

(

CHIP_REV_ID

)

Value:

((CHIP_REV_ID) >> 8)

Definition at line 321 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_phy_reset(), and tg3_reset_hw().

CHIPREV_5700_AX

#define CHIPREV_5700_AX   0x70

Definition at line 322 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_5700_BX

#define CHIPREV_5700_BX   0x71

Definition at line 323 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_5700_CX

#define CHIPREV_5700_CX   0x72

Definition at line 324 of file tg3.h.

CHIPREV_5701_AX

#define CHIPREV_5701_AX   0x00

Definition at line 325 of file tg3.h.

CHIPREV_5703_AX

#define CHIPREV_5703_AX   0x10

Definition at line 326 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_5704_AX

#define CHIPREV_5704_AX   0x20

Definition at line 327 of file tg3.h.

Referenced by tg3_get_invariants().

CHIPREV_5704_BX

#define CHIPREV_5704_BX   0x21

Definition at line 328 of file tg3.h.

Referenced by tg3_reset_hw().

CHIPREV_5750_AX

#define CHIPREV_5750_AX   0x40

Definition at line 329 of file tg3.h.

CHIPREV_5750_BX

#define CHIPREV_5750_BX   0x41

Definition at line 330 of file tg3.h.

CHIPREV_5784_AX

#define CHIPREV_5784_AX   0x57840

Definition at line 331 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), and tg3_phy_reset().

CHIPREV_5761_AX

#define CHIPREV_5761_AX   0x57610

Definition at line 332 of file tg3.h.

Referenced by tg3_phy_reset().

CHIPREV_57765_AX

#define CHIPREV_57765_AX   0x577650

Definition at line 333 of file tg3.h.

Referenced by tg3_reset_hw().

GET_METAL_REV

#define GET_METAL_REV

(

CHIP_REV_ID

)

Value:

((CHIP_REV_ID) & 0xff)

Definition at line 334 of file tg3.h.

METAL_REV_A0

#define METAL_REV_A0   0x00

Definition at line 335 of file tg3.h.

METAL_REV_A1

#define METAL_REV_A1   0x01

Definition at line 336 of file tg3.h.

METAL_REV_B0

#define METAL_REV_B0   0x00

Definition at line 337 of file tg3.h.

METAL_REV_B1

#define METAL_REV_B1   0x01

Definition at line 338 of file tg3.h.

METAL_REV_B2

#define METAL_REV_B2   0x02

Definition at line 339 of file tg3.h.

TG3PCI_DMA_RW_CTRL

#define TG3PCI_DMA_RW_CTRL   0x0000006c

Definition at line 340 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_test_dma().

DMA_RWCTRL_DIS_CACHE_ALIGNMENT

#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT   0x00000001

Definition at line 341 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_test_dma().

DMA_RWCTRL_TAGGED_STAT_WA

#define DMA_RWCTRL_TAGGED_STAT_WA   0x00000080

Definition at line 342 of file tg3.h.

Referenced by tg3_reset_hw().

DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK

#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK   0x00000380

Definition at line 343 of file tg3.h.

Referenced by tg3_reset_hw().

DMA_RWCTRL_READ_BNDRY_MASK

#define DMA_RWCTRL_READ_BNDRY_MASK   0x00000700

Definition at line 344 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_DISAB

#define DMA_RWCTRL_READ_BNDRY_DISAB   0x00000000

Definition at line 345 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_16

#define DMA_RWCTRL_READ_BNDRY_16   0x00000100

Definition at line 346 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_128_PCIX

#define DMA_RWCTRL_READ_BNDRY_128_PCIX   0x00000100

Definition at line 347 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_32

#define DMA_RWCTRL_READ_BNDRY_32   0x00000200

Definition at line 348 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_256_PCIX

#define DMA_RWCTRL_READ_BNDRY_256_PCIX   0x00000200

Definition at line 349 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_64

#define DMA_RWCTRL_READ_BNDRY_64   0x00000300

Definition at line 350 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_384_PCIX

#define DMA_RWCTRL_READ_BNDRY_384_PCIX   0x00000300

Definition at line 351 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_128

#define DMA_RWCTRL_READ_BNDRY_128   0x00000400

Definition at line 352 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_256

#define DMA_RWCTRL_READ_BNDRY_256   0x00000500

Definition at line 353 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_512

#define DMA_RWCTRL_READ_BNDRY_512   0x00000600

Definition at line 354 of file tg3.h.

DMA_RWCTRL_READ_BNDRY_1024

#define DMA_RWCTRL_READ_BNDRY_1024   0x00000700

Definition at line 355 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_MASK

#define DMA_RWCTRL_WRITE_BNDRY_MASK   0x00003800

Definition at line 356 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_WRITE_BNDRY_DISAB

#define DMA_RWCTRL_WRITE_BNDRY_DISAB   0x00000000

Definition at line 357 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_16

#define DMA_RWCTRL_WRITE_BNDRY_16   0x00000800

Definition at line 358 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_WRITE_BNDRY_128_PCIX

#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX   0x00000800

Definition at line 359 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_32

#define DMA_RWCTRL_WRITE_BNDRY_32   0x00001000

Definition at line 360 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_256_PCIX

#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX   0x00001000

Definition at line 361 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_64

#define DMA_RWCTRL_WRITE_BNDRY_64   0x00001800

Definition at line 362 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_384_PCIX

#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX   0x00001800

Definition at line 363 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_128

#define DMA_RWCTRL_WRITE_BNDRY_128   0x00002000

Definition at line 364 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_256

#define DMA_RWCTRL_WRITE_BNDRY_256   0x00002800

Definition at line 365 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_512

#define DMA_RWCTRL_WRITE_BNDRY_512   0x00003000

Definition at line 366 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_1024

#define DMA_RWCTRL_WRITE_BNDRY_1024   0x00003800

Definition at line 367 of file tg3.h.

DMA_RWCTRL_ONE_DMA

#define DMA_RWCTRL_ONE_DMA   0x00004000

Definition at line 368 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_READ_WATER

#define DMA_RWCTRL_READ_WATER   0x00070000

Definition at line 369 of file tg3.h.

DMA_RWCTRL_READ_WATER_SHIFT

#define DMA_RWCTRL_READ_WATER_SHIFT   16

Definition at line 370 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_WRITE_WATER

#define DMA_RWCTRL_WRITE_WATER   0x00380000

Definition at line 371 of file tg3.h.

DMA_RWCTRL_WRITE_WATER_SHIFT

#define DMA_RWCTRL_WRITE_WATER_SHIFT   19

Definition at line 372 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_USE_MEM_READ_MULT

#define DMA_RWCTRL_USE_MEM_READ_MULT   0x00400000

Definition at line 373 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_ASSERT_ALL_BE

#define DMA_RWCTRL_ASSERT_ALL_BE   0x00800000

Definition at line 374 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_PCI_READ_CMD

#define DMA_RWCTRL_PCI_READ_CMD   0x0f000000

Definition at line 375 of file tg3.h.

DMA_RWCTRL_PCI_READ_CMD_SHIFT

#define DMA_RWCTRL_PCI_READ_CMD_SHIFT   24

Definition at line 376 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_PCI_WRITE_CMD

#define DMA_RWCTRL_PCI_WRITE_CMD   0xf0000000

Definition at line 377 of file tg3.h.

DMA_RWCTRL_PCI_WRITE_CMD_SHIFT

#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT   28

Definition at line 378 of file tg3.h.

Referenced by tg3_test_dma().

DMA_RWCTRL_WRITE_BNDRY_64_PCIE

#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE   0x10000000

Definition at line 379 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_128_PCIE

#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE   0x30000000

Definition at line 380 of file tg3.h.

DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE

#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE   0x70000000

Definition at line 381 of file tg3.h.

TG3PCI_PCISTATE

#define TG3PCI_PCISTATE   0x00000070

Definition at line 382 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_reset_hw(), and tg3_restore_pci_state().

PCISTATE_FORCE_RESET

#define PCISTATE_FORCE_RESET   0x00000001

Definition at line 383 of file tg3.h.

PCISTATE_INT_NOT_ACTIVE

#define PCISTATE_INT_NOT_ACTIVE   0x00000002

Definition at line 384 of file tg3.h.

PCISTATE_CONV_PCI_MODE

#define PCISTATE_CONV_PCI_MODE   0x00000004

Definition at line 385 of file tg3.h.

Referenced by tg3_get_invariants().

PCISTATE_BUS_SPEED_HIGH

#define PCISTATE_BUS_SPEED_HIGH   0x00000008

Definition at line 386 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

PCISTATE_BUS_32BIT

#define PCISTATE_BUS_32BIT   0x00000010

Definition at line 387 of file tg3.h.

Referenced by tg3_get_invariants().

PCISTATE_ROM_ENABLE

#define PCISTATE_ROM_ENABLE   0x00000020

Definition at line 388 of file tg3.h.

Referenced by tg3_restore_pci_state().

PCISTATE_ROM_RETRY_ENABLE

#define PCISTATE_ROM_RETRY_ENABLE   0x00000040

Definition at line 389 of file tg3.h.

Referenced by tg3_restore_pci_state().

PCISTATE_FLAT_VIEW

#define PCISTATE_FLAT_VIEW   0x00000100

Definition at line 390 of file tg3.h.

PCISTATE_RETRY_SAME_DMA

#define PCISTATE_RETRY_SAME_DMA   0x00002000

Definition at line 391 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_reset_hw(), and tg3_restore_pci_state().

PCISTATE_ALLOW_APE_CTLSPC_WR

#define PCISTATE_ALLOW_APE_CTLSPC_WR   0x00010000

Definition at line 392 of file tg3.h.

PCISTATE_ALLOW_APE_SHMEM_WR

#define PCISTATE_ALLOW_APE_SHMEM_WR   0x00020000

Definition at line 393 of file tg3.h.

PCISTATE_ALLOW_APE_PSPACE_WR

#define PCISTATE_ALLOW_APE_PSPACE_WR   0x00040000

Definition at line 394 of file tg3.h.

TG3PCI_CLOCK_CTRL

#define TG3PCI_CLOCK_CTRL   0x00000074

Definition at line 395 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_reset_hw(), tg3_switch_clocks(), and tg3_test_dma().

CLOCK_CTRL_CORECLK_DISABLE

#define CLOCK_CTRL_CORECLK_DISABLE   0x00000200

Definition at line 396 of file tg3.h.

CLOCK_CTRL_RXCLK_DISABLE

#define CLOCK_CTRL_RXCLK_DISABLE   0x00000400

Definition at line 397 of file tg3.h.

CLOCK_CTRL_TXCLK_DISABLE

#define CLOCK_CTRL_TXCLK_DISABLE   0x00000800

Definition at line 398 of file tg3.h.

CLOCK_CTRL_ALTCLK

#define CLOCK_CTRL_ALTCLK   0x00001000

Definition at line 399 of file tg3.h.

Referenced by tg3_switch_clocks().

CLOCK_CTRL_PWRDOWN_PLL133

#define CLOCK_CTRL_PWRDOWN_PLL133   0x00008000

Definition at line 400 of file tg3.h.

CLOCK_CTRL_44MHZ_CORE

#define CLOCK_CTRL_44MHZ_CORE   0x00040000

Definition at line 401 of file tg3.h.

Referenced by tg3_switch_clocks().

CLOCK_CTRL_625_CORE

#define CLOCK_CTRL_625_CORE   0x00100000

Definition at line 402 of file tg3.h.

Referenced by tg3_switch_clocks().

CLOCK_CTRL_FORCE_CLKRUN

#define CLOCK_CTRL_FORCE_CLKRUN   0x00200000

Definition at line 403 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_switch_clocks().

CLOCK_CTRL_CLKRUN_OENABLE

#define CLOCK_CTRL_CLKRUN_OENABLE   0x00400000

Definition at line 404 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_switch_clocks().

CLOCK_CTRL_DELAY_PCI_GRANT

#define CLOCK_CTRL_DELAY_PCI_GRANT   0x80000000

Definition at line 405 of file tg3.h.

Referenced by tg3_reset_hw().

TG3PCI_REG_BASE_ADDR

#define TG3PCI_REG_BASE_ADDR   0x00000078

Definition at line 406 of file tg3.h.

Referenced by tg3_read_indirect_mbox(), tg3_read_indirect_reg32(), tg3_write_indirect_mbox(), and tg3_write_indirect_reg32().

TG3PCI_MEM_WIN_BASE_ADDR

#define TG3PCI_MEM_WIN_BASE_ADDR   0x0000007c

Definition at line 407 of file tg3.h.

Referenced by tg3_do_test_dma(), tg3_get_invariants(), tg3_init_hw(), tg3_read_mem(), and tg3_write_mem().

TG3PCI_REG_DATA

#define TG3PCI_REG_DATA   0x00000080

Definition at line 408 of file tg3.h.

Referenced by tg3_read_indirect_mbox(), tg3_read_indirect_reg32(), tg3_write_indirect_mbox(), and tg3_write_indirect_reg32().

TG3PCI_MEM_WIN_DATA

#define TG3PCI_MEM_WIN_DATA   0x00000084

Definition at line 409 of file tg3.h.

Referenced by tg3_do_test_dma(), tg3_read_mem(), and tg3_write_mem().

TG3PCI_MISC_LOCAL_CTRL

#define TG3PCI_MISC_LOCAL_CTRL   0x00000090

Definition at line 410 of file tg3.h.

Referenced by tg3_write_indirect_mbox().

TG3PCI_STD_RING_PROD_IDX

#define TG3PCI_STD_RING_PROD_IDX   0x00000098 /* 64-bit */

Definition at line 412 of file tg3.h.

Referenced by tg3_write_indirect_mbox().

TG3PCI_RCV_RET_RING_CON_IDX

#define TG3PCI_RCV_RET_RING_CON_IDX   0x000000a0 /* 64-bit */

Definition at line 413 of file tg3.h.

Referenced by tg3_write_indirect_mbox().

TG3PCI_DUAL_MAC_CTRL

#define TG3PCI_DUAL_MAC_CTRL   0x000000b8

Definition at line 415 of file tg3.h.

Referenced by tg3_get_device_address(), and tg3_setup_fiber_hw_autoneg().

DUAL_MAC_CTRL_CH_MASK

#define DUAL_MAC_CTRL_CH_MASK   0x00000003

Definition at line 416 of file tg3.h.

DUAL_MAC_CTRL_ID

#define DUAL_MAC_CTRL_ID   0x00000004

Definition at line 417 of file tg3.h.

Referenced by tg3_get_device_address(), and tg3_setup_fiber_hw_autoneg().

TG3PCI_PRODID_ASICREV

#define TG3PCI_PRODID_ASICREV   0x000000bc

Definition at line 418 of file tg3.h.

Referenced by tg3_get_invariants().

PROD_ID_ASIC_REV_MASK

#define PROD_ID_ASIC_REV_MASK   0x0fffffff

Definition at line 419 of file tg3.h.

TG3PCI_GEN2_PRODID_ASICREV

#define TG3PCI_GEN2_PRODID_ASICREV   0x000000f4

Definition at line 422 of file tg3.h.

Referenced by tg3_get_invariants().

TG3PCI_GEN15_PRODID_ASICREV

#define TG3PCI_GEN15_PRODID_ASICREV   0x000000fc

Definition at line 423 of file tg3.h.

Referenced by tg3_get_invariants().

TG3_CORR_ERR_STAT

#define TG3_CORR_ERR_STAT   0x00000110

Definition at line 426 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_CORR_ERR_STAT_CLEAR

#define TG3_CORR_ERR_STAT_CLEAR   0xffffffff

Definition at line 427 of file tg3.h.

Referenced by tg3_reset_hw().

MAILBOX_INTERRUPT_0

#define MAILBOX_INTERRUPT_0   0x00000200 /* 64-bit */

Definition at line 431 of file tg3.h.

Referenced by tg3_init_one(), and tg3_write_indirect_mbox().

MAILBOX_INTERRUPT_1

#define MAILBOX_INTERRUPT_1   0x00000208 /* 64-bit */

Definition at line 432 of file tg3.h.

MAILBOX_INTERRUPT_2

#define MAILBOX_INTERRUPT_2   0x00000210 /* 64-bit */

Definition at line 433 of file tg3.h.

MAILBOX_INTERRUPT_3

#define MAILBOX_INTERRUPT_3   0x00000218 /* 64-bit */

Definition at line 434 of file tg3.h.

MAILBOX_GENERAL_0

#define MAILBOX_GENERAL_0   0x00000220 /* 64-bit */

Definition at line 435 of file tg3.h.

MAILBOX_GENERAL_1

#define MAILBOX_GENERAL_1   0x00000228 /* 64-bit */

Definition at line 436 of file tg3.h.

MAILBOX_GENERAL_2

#define MAILBOX_GENERAL_2   0x00000230 /* 64-bit */

Definition at line 437 of file tg3.h.

MAILBOX_GENERAL_3

#define MAILBOX_GENERAL_3   0x00000238 /* 64-bit */

Definition at line 438 of file tg3.h.

MAILBOX_GENERAL_4

#define MAILBOX_GENERAL_4   0x00000240 /* 64-bit */

Definition at line 439 of file tg3.h.

MAILBOX_GENERAL_5

#define MAILBOX_GENERAL_5   0x00000248 /* 64-bit */

Definition at line 440 of file tg3.h.

MAILBOX_GENERAL_6

#define MAILBOX_GENERAL_6   0x00000250 /* 64-bit */

Definition at line 441 of file tg3.h.

MAILBOX_GENERAL_7

#define MAILBOX_GENERAL_7   0x00000258 /* 64-bit */

Definition at line 442 of file tg3.h.

MAILBOX_RELOAD_STAT

#define MAILBOX_RELOAD_STAT   0x00000260 /* 64-bit */

Definition at line 443 of file tg3.h.

MAILBOX_RCV_STD_PROD_IDX

#define MAILBOX_RCV_STD_PROD_IDX   0x00000268 /* 64-bit */

Definition at line 444 of file tg3.h.

TG3_RX_STD_PROD_IDX_REG

#define TG3_RX_STD_PROD_IDX_REG

Value:

                                         (MAILBOX_RCV_STD_PROD_IDX + \
                                         TG3_64BIT_REG_LOW)

Definition at line 445 of file tg3.h.

#define TG3_RX_STD_PROD_IDX_REG         (MAILBOX_RCV_STD_PROD_IDX + \
                                         TG3_64BIT_REG_LOW)

Referenced by tg3_refill_prod_ring(), tg3_reset_hw(), and tg3_write_indirect_mbox().

MAILBOX_RCV_JUMBO_PROD_IDX

#define MAILBOX_RCV_JUMBO_PROD_IDX   0x00000270 /* 64-bit */

Definition at line 447 of file tg3.h.

TG3_RX_JMB_PROD_IDX_REG

#define TG3_RX_JMB_PROD_IDX_REG

Value:

                                         (MAILBOX_RCV_JUMBO_PROD_IDX + \
                                         TG3_64BIT_REG_LOW)

Definition at line 448 of file tg3.h.

#define TG3_RX_JMB_PROD_IDX_REG         (MAILBOX_RCV_JUMBO_PROD_IDX + \
                                         TG3_64BIT_REG_LOW)

Referenced by tg3_reset_hw().

MAILBOX_RCV_MINI_PROD_IDX

#define MAILBOX_RCV_MINI_PROD_IDX   0x00000278 /* 64-bit */

Definition at line 450 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_0

#define MAILBOX_RCVRET_CON_IDX_0   0x00000280 /* 64-bit */

Definition at line 451 of file tg3.h.

Referenced by tg3_init_one(), and tg3_write_indirect_mbox().

MAILBOX_RCVRET_CON_IDX_1

#define MAILBOX_RCVRET_CON_IDX_1   0x00000288 /* 64-bit */

Definition at line 452 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_2

#define MAILBOX_RCVRET_CON_IDX_2   0x00000290 /* 64-bit */

Definition at line 453 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_3

#define MAILBOX_RCVRET_CON_IDX_3   0x00000298 /* 64-bit */

Definition at line 454 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_4

#define MAILBOX_RCVRET_CON_IDX_4   0x000002a0 /* 64-bit */

Definition at line 455 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_5

#define MAILBOX_RCVRET_CON_IDX_5   0x000002a8 /* 64-bit */

Definition at line 456 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_6

#define MAILBOX_RCVRET_CON_IDX_6   0x000002b0 /* 64-bit */

Definition at line 457 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_7

#define MAILBOX_RCVRET_CON_IDX_7   0x000002b8 /* 64-bit */

Definition at line 458 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_8

#define MAILBOX_RCVRET_CON_IDX_8   0x000002c0 /* 64-bit */

Definition at line 459 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_9

#define MAILBOX_RCVRET_CON_IDX_9   0x000002c8 /* 64-bit */

Definition at line 460 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_10

#define MAILBOX_RCVRET_CON_IDX_10   0x000002d0 /* 64-bit */

Definition at line 461 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_11

#define MAILBOX_RCVRET_CON_IDX_11   0x000002d8 /* 64-bit */

Definition at line 462 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_12

#define MAILBOX_RCVRET_CON_IDX_12   0x000002e0 /* 64-bit */

Definition at line 463 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_13

#define MAILBOX_RCVRET_CON_IDX_13   0x000002e8 /* 64-bit */

Definition at line 464 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_14

#define MAILBOX_RCVRET_CON_IDX_14   0x000002f0 /* 64-bit */

Definition at line 465 of file tg3.h.

MAILBOX_RCVRET_CON_IDX_15

#define MAILBOX_RCVRET_CON_IDX_15   0x000002f8 /* 64-bit */

Definition at line 466 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_0

#define MAILBOX_SNDHOST_PROD_IDX_0   0x00000300 /* 64-bit */

Definition at line 467 of file tg3.h.

Referenced by tg3_init_one().

MAILBOX_SNDHOST_PROD_IDX_1

#define MAILBOX_SNDHOST_PROD_IDX_1   0x00000308 /* 64-bit */

Definition at line 468 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_2

#define MAILBOX_SNDHOST_PROD_IDX_2   0x00000310 /* 64-bit */

Definition at line 469 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_3

#define MAILBOX_SNDHOST_PROD_IDX_3   0x00000318 /* 64-bit */

Definition at line 470 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_4

#define MAILBOX_SNDHOST_PROD_IDX_4   0x00000320 /* 64-bit */

Definition at line 471 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_5

#define MAILBOX_SNDHOST_PROD_IDX_5   0x00000328 /* 64-bit */

Definition at line 472 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_6

#define MAILBOX_SNDHOST_PROD_IDX_6   0x00000330 /* 64-bit */

Definition at line 473 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_7

#define MAILBOX_SNDHOST_PROD_IDX_7   0x00000338 /* 64-bit */

Definition at line 474 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_8

#define MAILBOX_SNDHOST_PROD_IDX_8   0x00000340 /* 64-bit */

Definition at line 475 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_9

#define MAILBOX_SNDHOST_PROD_IDX_9   0x00000348 /* 64-bit */

Definition at line 476 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_10

#define MAILBOX_SNDHOST_PROD_IDX_10   0x00000350 /* 64-bit */

Definition at line 477 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_11

#define MAILBOX_SNDHOST_PROD_IDX_11   0x00000358 /* 64-bit */

Definition at line 478 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_12

#define MAILBOX_SNDHOST_PROD_IDX_12   0x00000360 /* 64-bit */

Definition at line 479 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_13

#define MAILBOX_SNDHOST_PROD_IDX_13   0x00000368 /* 64-bit */

Definition at line 480 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_14

#define MAILBOX_SNDHOST_PROD_IDX_14   0x00000370 /* 64-bit */

Definition at line 481 of file tg3.h.

MAILBOX_SNDHOST_PROD_IDX_15

#define MAILBOX_SNDHOST_PROD_IDX_15   0x00000378 /* 64-bit */

Definition at line 482 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_0

#define MAILBOX_SNDNIC_PROD_IDX_0   0x00000380 /* 64-bit */

Definition at line 483 of file tg3.h.

Referenced by tg3_rings_reset().

MAILBOX_SNDNIC_PROD_IDX_1

#define MAILBOX_SNDNIC_PROD_IDX_1   0x00000388 /* 64-bit */

Definition at line 484 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_2

#define MAILBOX_SNDNIC_PROD_IDX_2   0x00000390 /* 64-bit */

Definition at line 485 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_3

#define MAILBOX_SNDNIC_PROD_IDX_3   0x00000398 /* 64-bit */

Definition at line 486 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_4

#define MAILBOX_SNDNIC_PROD_IDX_4   0x000003a0 /* 64-bit */

Definition at line 487 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_5

#define MAILBOX_SNDNIC_PROD_IDX_5   0x000003a8 /* 64-bit */

Definition at line 488 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_6

#define MAILBOX_SNDNIC_PROD_IDX_6   0x000003b0 /* 64-bit */

Definition at line 489 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_7

#define MAILBOX_SNDNIC_PROD_IDX_7   0x000003b8 /* 64-bit */

Definition at line 490 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_8

#define MAILBOX_SNDNIC_PROD_IDX_8   0x000003c0 /* 64-bit */

Definition at line 491 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_9

#define MAILBOX_SNDNIC_PROD_IDX_9   0x000003c8 /* 64-bit */

Definition at line 492 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_10

#define MAILBOX_SNDNIC_PROD_IDX_10   0x000003d0 /* 64-bit */

Definition at line 493 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_11

#define MAILBOX_SNDNIC_PROD_IDX_11   0x000003d8 /* 64-bit */

Definition at line 494 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_12

#define MAILBOX_SNDNIC_PROD_IDX_12   0x000003e0 /* 64-bit */

Definition at line 495 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_13

#define MAILBOX_SNDNIC_PROD_IDX_13   0x000003e8 /* 64-bit */

Definition at line 496 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_14

#define MAILBOX_SNDNIC_PROD_IDX_14   0x000003f0 /* 64-bit */

Definition at line 497 of file tg3.h.

MAILBOX_SNDNIC_PROD_IDX_15

#define MAILBOX_SNDNIC_PROD_IDX_15   0x000003f8 /* 64-bit */

Definition at line 498 of file tg3.h.

MAC_MODE

#define MAC_MODE   0x00000400

Definition at line 501 of file tg3.h.

Referenced by fiber_autoneg(), tg3_abort_hw(), tg3_chip_reset(), tg3_fiber_aneg_smachine(), tg3_reset_hw(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

MAC_MODE_RESET

#define MAC_MODE_RESET   0x00000001

Definition at line 502 of file tg3.h.

MAC_MODE_HALF_DUPLEX

#define MAC_MODE_HALF_DUPLEX   0x00000002

Definition at line 503 of file tg3.h.

Referenced by tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

MAC_MODE_PORT_MODE_MASK

#define MAC_MODE_PORT_MODE_MASK   0x0000000c

Definition at line 504 of file tg3.h.

Referenced by fiber_autoneg(), tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

MAC_MODE_PORT_MODE_TBI

#define MAC_MODE_PORT_MODE_TBI   0x0000000c

Definition at line 505 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_setup_fiber_phy().

MAC_MODE_PORT_MODE_GMII

#define MAC_MODE_PORT_MODE_GMII   0x00000008

Definition at line 506 of file tg3.h.

Referenced by fiber_autoneg(), tg3_chip_reset(), tg3_setup_copper_phy(), and tg3_setup_fiber_mii_phy().

MAC_MODE_PORT_MODE_MII

#define MAC_MODE_PORT_MODE_MII   0x00000004

Definition at line 507 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_mii_phy().

MAC_MODE_PORT_MODE_NONE

#define MAC_MODE_PORT_MODE_NONE   0x00000000

Definition at line 508 of file tg3.h.

MAC_MODE_PORT_INT_LPBACK

#define MAC_MODE_PORT_INT_LPBACK   0x00000010

Definition at line 509 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MAC_MODE_TAGGED_MAC_CTRL

#define MAC_MODE_TAGGED_MAC_CTRL   0x00000080

Definition at line 510 of file tg3.h.

MAC_MODE_TX_BURSTING

#define MAC_MODE_TX_BURSTING   0x00000100

Definition at line 511 of file tg3.h.

MAC_MODE_MAX_DEFER

#define MAC_MODE_MAX_DEFER   0x00000200

Definition at line 512 of file tg3.h.

MAC_MODE_LINK_POLARITY

#define MAC_MODE_LINK_POLARITY   0x00000400

Definition at line 513 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_copper_phy().

MAC_MODE_RXSTAT_ENABLE

#define MAC_MODE_RXSTAT_ENABLE   0x00000800

Definition at line 514 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_RXSTAT_CLEAR

#define MAC_MODE_RXSTAT_CLEAR   0x00001000

Definition at line 515 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_RXSTAT_FLUSH

#define MAC_MODE_RXSTAT_FLUSH   0x00002000

Definition at line 516 of file tg3.h.

MAC_MODE_TXSTAT_ENABLE

#define MAC_MODE_TXSTAT_ENABLE   0x00004000

Definition at line 517 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_TXSTAT_CLEAR

#define MAC_MODE_TXSTAT_CLEAR   0x00008000

Definition at line 518 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_TXSTAT_FLUSH

#define MAC_MODE_TXSTAT_FLUSH   0x00010000

Definition at line 519 of file tg3.h.

MAC_MODE_SEND_CONFIGS

#define MAC_MODE_SEND_CONFIGS   0x00020000

Definition at line 520 of file tg3.h.

Referenced by fiber_autoneg(), tg3_fiber_aneg_smachine(), tg3_setup_fiber_by_hand(), and tg3_setup_fiber_phy().

MAC_MODE_MAGIC_PKT_ENABLE

#define MAC_MODE_MAGIC_PKT_ENABLE   0x00040000

Definition at line 521 of file tg3.h.

MAC_MODE_ACPI_ENABLE

#define MAC_MODE_ACPI_ENABLE   0x00080000

Definition at line 522 of file tg3.h.

MAC_MODE_MIP_ENABLE

#define MAC_MODE_MIP_ENABLE   0x00100000

Definition at line 523 of file tg3.h.

MAC_MODE_TDE_ENABLE

#define MAC_MODE_TDE_ENABLE   0x00200000

Definition at line 524 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

MAC_MODE_RDE_ENABLE

#define MAC_MODE_RDE_ENABLE   0x00400000

Definition at line 525 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_FHDE_ENABLE

#define MAC_MODE_FHDE_ENABLE   0x00800000

Definition at line 526 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MODE_KEEP_FRAME_IN_WOL

#define MAC_MODE_KEEP_FRAME_IN_WOL   0x01000000

Definition at line 527 of file tg3.h.

MAC_MODE_APE_RX_EN

#define MAC_MODE_APE_RX_EN   0x08000000

Definition at line 528 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

MAC_MODE_APE_TX_EN

#define MAC_MODE_APE_TX_EN   0x10000000

Definition at line 529 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

MAC_STATUS

#define MAC_STATUS   0x00000404

Definition at line 530 of file tg3.h.

Referenced by tg3_clear_mac_status(), tg3_fiber_aneg_smachine(), tg3_init_bcm8002(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), and tg3_setup_fiber_phy().

MAC_STATUS_PCS_SYNCED

#define MAC_STATUS_PCS_SYNCED   0x00000001

Definition at line 531 of file tg3.h.

Referenced by tg3_init_bcm8002(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), and tg3_setup_fiber_phy().

MAC_STATUS_SIGNAL_DET

#define MAC_STATUS_SIGNAL_DET   0x00000002

Definition at line 532 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg(), and tg3_setup_fiber_phy().

MAC_STATUS_RCVD_CFG

#define MAC_STATUS_RCVD_CFG   0x00000004

Definition at line 533 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), and tg3_setup_fiber_phy().

MAC_STATUS_CFG_CHANGED

#define MAC_STATUS_CFG_CHANGED   0x00000008

Definition at line 534 of file tg3.h.

Referenced by tg3_clear_mac_status(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), and tg3_setup_fiber_phy().

MAC_STATUS_SYNC_CHANGED

#define MAC_STATUS_SYNC_CHANGED   0x00000010

Definition at line 535 of file tg3.h.

Referenced by tg3_clear_mac_status(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), and tg3_setup_fiber_phy().

MAC_STATUS_PORT_DEC_ERR

#define MAC_STATUS_PORT_DEC_ERR   0x00000400

Definition at line 536 of file tg3.h.

MAC_STATUS_LNKSTATE_CHANGED

#define MAC_STATUS_LNKSTATE_CHANGED   0x00001000

Definition at line 537 of file tg3.h.

Referenced by tg3_clear_mac_status(), tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

MAC_STATUS_MI_COMPLETION

#define MAC_STATUS_MI_COMPLETION   0x00400000

Definition at line 538 of file tg3.h.

Referenced by tg3_clear_mac_status(), and tg3_setup_copper_phy().

MAC_STATUS_MI_INTERRUPT

#define MAC_STATUS_MI_INTERRUPT   0x00800000

Definition at line 539 of file tg3.h.

MAC_STATUS_AP_ERROR

#define MAC_STATUS_AP_ERROR   0x01000000

Definition at line 540 of file tg3.h.

MAC_STATUS_ODI_ERROR

#define MAC_STATUS_ODI_ERROR   0x02000000

Definition at line 541 of file tg3.h.

MAC_STATUS_RXSTAT_OVERRUN

#define MAC_STATUS_RXSTAT_OVERRUN   0x04000000

Definition at line 542 of file tg3.h.

MAC_STATUS_TXSTAT_OVERRUN

#define MAC_STATUS_TXSTAT_OVERRUN   0x08000000

Definition at line 543 of file tg3.h.

MAC_EVENT

#define MAC_EVENT   0x00000408

Definition at line 544 of file tg3.h.

Referenced by tg3_clear_mac_status(), tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

MAC_EVENT_PORT_DECODE_ERR

#define MAC_EVENT_PORT_DECODE_ERR   0x00000400

Definition at line 545 of file tg3.h.

MAC_EVENT_LNKSTATE_CHANGED

#define MAC_EVENT_LNKSTATE_CHANGED   0x00001000

Definition at line 546 of file tg3.h.

Referenced by tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), and tg3_setup_fiber_phy().

MAC_EVENT_MI_COMPLETION

#define MAC_EVENT_MI_COMPLETION   0x00400000

Definition at line 547 of file tg3.h.

MAC_EVENT_MI_INTERRUPT

#define MAC_EVENT_MI_INTERRUPT   0x00800000

Definition at line 548 of file tg3.h.

MAC_EVENT_AP_ERROR

#define MAC_EVENT_AP_ERROR   0x01000000

Definition at line 549 of file tg3.h.

MAC_EVENT_ODI_ERROR

#define MAC_EVENT_ODI_ERROR   0x02000000

Definition at line 550 of file tg3.h.

MAC_EVENT_RXSTAT_OVERRUN

#define MAC_EVENT_RXSTAT_OVERRUN   0x04000000

Definition at line 551 of file tg3.h.

MAC_EVENT_TXSTAT_OVERRUN

#define MAC_EVENT_TXSTAT_OVERRUN   0x08000000

Definition at line 552 of file tg3.h.

MAC_LED_CTRL

#define MAC_LED_CTRL   0x0000040c

Definition at line 553 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_fiber_phy().

LED_CTRL_LNKLED_OVERRIDE

#define LED_CTRL_LNKLED_OVERRIDE   0x00000001

Definition at line 554 of file tg3.h.

Referenced by tg3_setup_fiber_phy().

LED_CTRL_1000MBPS_ON

#define LED_CTRL_1000MBPS_ON   0x00000002

Definition at line 555 of file tg3.h.

Referenced by tg3_setup_fiber_phy().

LED_CTRL_100MBPS_ON

#define LED_CTRL_100MBPS_ON   0x00000004

Definition at line 556 of file tg3.h.

LED_CTRL_10MBPS_ON

#define LED_CTRL_10MBPS_ON   0x00000008

Definition at line 557 of file tg3.h.

LED_CTRL_TRAFFIC_OVERRIDE

#define LED_CTRL_TRAFFIC_OVERRIDE   0x00000010

Definition at line 558 of file tg3.h.

Referenced by tg3_setup_fiber_phy().

LED_CTRL_TRAFFIC_BLINK

#define LED_CTRL_TRAFFIC_BLINK   0x00000020

Definition at line 559 of file tg3.h.

LED_CTRL_TRAFFIC_LED

#define LED_CTRL_TRAFFIC_LED   0x00000040

Definition at line 560 of file tg3.h.

LED_CTRL_1000MBPS_STATUS

#define LED_CTRL_1000MBPS_STATUS   0x00000080

Definition at line 561 of file tg3.h.

LED_CTRL_100MBPS_STATUS

#define LED_CTRL_100MBPS_STATUS   0x00000100

Definition at line 562 of file tg3.h.

LED_CTRL_10MBPS_STATUS

#define LED_CTRL_10MBPS_STATUS   0x00000200

Definition at line 563 of file tg3.h.

LED_CTRL_TRAFFIC_STATUS

#define LED_CTRL_TRAFFIC_STATUS   0x00000400

Definition at line 564 of file tg3.h.

LED_CTRL_MODE_MAC

#define LED_CTRL_MODE_MAC   0x00000000

Definition at line 565 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

LED_CTRL_MODE_PHY_1

#define LED_CTRL_MODE_PHY_1   0x00000800

Definition at line 566 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), and tg3_setup_copper_phy().

LED_CTRL_MODE_PHY_2

#define LED_CTRL_MODE_PHY_2   0x00001000

Definition at line 567 of file tg3.h.

Referenced by tg3_5700_link_polarity(), and tg3_get_eeprom_hw_cfg().

LED_CTRL_MODE_SHASTA_MAC

#define LED_CTRL_MODE_SHASTA_MAC   0x00002000

Definition at line 568 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

LED_CTRL_MODE_SHARED

#define LED_CTRL_MODE_SHARED   0x00004000

Definition at line 569 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

LED_CTRL_MODE_COMBO

#define LED_CTRL_MODE_COMBO   0x00008000

Definition at line 570 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

LED_CTRL_BLINK_RATE_MASK

#define LED_CTRL_BLINK_RATE_MASK   0x7ff80000

Definition at line 571 of file tg3.h.

LED_CTRL_BLINK_RATE_SHIFT

#define LED_CTRL_BLINK_RATE_SHIFT   19

Definition at line 572 of file tg3.h.

LED_CTRL_BLINK_PER_OVERRIDE

#define LED_CTRL_BLINK_PER_OVERRIDE   0x00080000

Definition at line 573 of file tg3.h.

LED_CTRL_BLINK_RATE_OVERRIDE

#define LED_CTRL_BLINK_RATE_OVERRIDE   0x80000000

Definition at line 574 of file tg3.h.

MAC_ADDR_0_HIGH

#define MAC_ADDR_0_HIGH   0x00000410 /* upper 2 bytes */

Definition at line 575 of file tg3.h.

Referenced by __tg3_set_mac_addr(), and tg3_get_device_address().

MAC_ADDR_0_LOW

#define MAC_ADDR_0_LOW   0x00000414 /* lower 4 bytes */

Definition at line 576 of file tg3.h.

Referenced by __tg3_set_mac_addr(), and tg3_get_device_address().

MAC_ADDR_1_HIGH

#define MAC_ADDR_1_HIGH   0x00000418 /* upper 2 bytes */

Definition at line 577 of file tg3.h.

MAC_ADDR_1_LOW

#define MAC_ADDR_1_LOW   0x0000041c /* lower 4 bytes */

Definition at line 578 of file tg3.h.

MAC_ADDR_2_HIGH

#define MAC_ADDR_2_HIGH   0x00000420 /* upper 2 bytes */

Definition at line 579 of file tg3.h.

MAC_ADDR_2_LOW

#define MAC_ADDR_2_LOW   0x00000424 /* lower 4 bytes */

Definition at line 580 of file tg3.h.

MAC_ADDR_3_HIGH

#define MAC_ADDR_3_HIGH   0x00000428 /* upper 2 bytes */

Definition at line 581 of file tg3.h.

MAC_ADDR_3_LOW

#define MAC_ADDR_3_LOW   0x0000042c /* lower 4 bytes */

Definition at line 582 of file tg3.h.

MAC_ACPI_MBUF_PTR

#define MAC_ACPI_MBUF_PTR   0x00000430

Definition at line 583 of file tg3.h.

MAC_ACPI_LEN_OFFSET

#define MAC_ACPI_LEN_OFFSET   0x00000434

Definition at line 584 of file tg3.h.

ACPI_LENOFF_LEN_MASK

#define ACPI_LENOFF_LEN_MASK   0x0000ffff

Definition at line 585 of file tg3.h.

ACPI_LENOFF_LEN_SHIFT

#define ACPI_LENOFF_LEN_SHIFT   0

Definition at line 586 of file tg3.h.

ACPI_LENOFF_OFF_MASK

#define ACPI_LENOFF_OFF_MASK   0x0fff0000

Definition at line 587 of file tg3.h.

ACPI_LENOFF_OFF_SHIFT

#define ACPI_LENOFF_OFF_SHIFT   16

Definition at line 588 of file tg3.h.

MAC_TX_BACKOFF_SEED

#define MAC_TX_BACKOFF_SEED   0x00000438

Definition at line 589 of file tg3.h.

Referenced by __tg3_set_mac_addr().

TX_BACKOFF_SEED_MASK

#define TX_BACKOFF_SEED_MASK   0x000003ff

Definition at line 590 of file tg3.h.

Referenced by __tg3_set_mac_addr().

MAC_RX_MTU_SIZE

#define MAC_RX_MTU_SIZE   0x0000043c

Definition at line 591 of file tg3.h.

Referenced by tg3_reset_hw().

RX_MTU_SIZE_MASK

#define RX_MTU_SIZE_MASK   0x0000ffff

Definition at line 592 of file tg3.h.

MAC_PCS_TEST

#define MAC_PCS_TEST   0x00000440

Definition at line 593 of file tg3.h.

PCS_TEST_PATTERN_MASK

#define PCS_TEST_PATTERN_MASK   0x000fffff

Definition at line 594 of file tg3.h.

PCS_TEST_PATTERN_SHIFT

#define PCS_TEST_PATTERN_SHIFT   0

Definition at line 595 of file tg3.h.

PCS_TEST_ENABLE

#define PCS_TEST_ENABLE   0x00100000

Definition at line 596 of file tg3.h.

MAC_TX_AUTO_NEG

#define MAC_TX_AUTO_NEG   0x00000444

Definition at line 597 of file tg3.h.

Referenced by fiber_autoneg(), tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().

TX_AUTO_NEG_MASK

#define TX_AUTO_NEG_MASK   0x0000ffff

Definition at line 598 of file tg3.h.

TX_AUTO_NEG_SHIFT

#define TX_AUTO_NEG_SHIFT   0

Definition at line 599 of file tg3.h.

MAC_RX_AUTO_NEG

#define MAC_RX_AUTO_NEG   0x00000448

Definition at line 600 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine().

RX_AUTO_NEG_MASK

#define RX_AUTO_NEG_MASK   0x0000ffff

Definition at line 601 of file tg3.h.

RX_AUTO_NEG_SHIFT

#define RX_AUTO_NEG_SHIFT   0

Definition at line 602 of file tg3.h.

MAC_MI_COM

#define MAC_MI_COM   0x0000044c

Definition at line 603 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_CMD_MASK

#define MI_COM_CMD_MASK   0x0c000000

Definition at line 604 of file tg3.h.

MI_COM_CMD_WRITE

#define MI_COM_CMD_WRITE   0x04000000

Definition at line 605 of file tg3.h.

Referenced by tg3_writephy().

MI_COM_CMD_READ

#define MI_COM_CMD_READ   0x08000000

Definition at line 606 of file tg3.h.

Referenced by tg3_readphy().

MI_COM_READ_FAILED

#define MI_COM_READ_FAILED   0x10000000

Definition at line 607 of file tg3.h.

MI_COM_START

#define MI_COM_START   0x20000000

Definition at line 608 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_BUSY

#define MI_COM_BUSY   0x20000000

Definition at line 609 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_PHY_ADDR_MASK

#define MI_COM_PHY_ADDR_MASK   0x03e00000

Definition at line 610 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_PHY_ADDR_SHIFT

#define MI_COM_PHY_ADDR_SHIFT   21

Definition at line 611 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_REG_ADDR_MASK

#define MI_COM_REG_ADDR_MASK   0x001f0000

Definition at line 612 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_REG_ADDR_SHIFT

#define MI_COM_REG_ADDR_SHIFT   16

Definition at line 613 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MI_COM_DATA_MASK

#define MI_COM_DATA_MASK   0x0000ffff

Definition at line 614 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

MAC_MI_STAT

#define MAC_MI_STAT   0x00000450

Definition at line 615 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MI_STAT_LNKSTAT_ATTN_ENAB

#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001

Definition at line 616 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_MI_STAT_10MBPS_MODE

#define MAC_MI_STAT_10MBPS_MODE   0x00000002

Definition at line 617 of file tg3.h.

MAC_MI_MODE

#define MAC_MI_MODE   0x00000454

Definition at line 618 of file tg3.h.

Referenced by tg3_readphy(), tg3_setup_copper_phy(), and tg3_writephy().

MAC_MI_MODE_CLK_10MHZ

#define MAC_MI_MODE_CLK_10MHZ   0x00000001

Definition at line 619 of file tg3.h.

MAC_MI_MODE_SHORT_PREAMBLE

#define MAC_MI_MODE_SHORT_PREAMBLE   0x00000002

Definition at line 620 of file tg3.h.

MAC_MI_MODE_AUTO_POLL

#define MAC_MI_MODE_AUTO_POLL   0x00000010

Definition at line 621 of file tg3.h.

Referenced by tg3_readphy(), tg3_setup_copper_phy(), and tg3_writephy().

MAC_MI_MODE_500KHZ_CONST

#define MAC_MI_MODE_500KHZ_CONST   0x00008000

Definition at line 622 of file tg3.h.

Referenced by tg3_get_invariants().

MAC_MI_MODE_BASE

#define MAC_MI_MODE_BASE   0x000c0000 /* XXX magic values XXX */

Definition at line 623 of file tg3.h.

Referenced by tg3_get_invariants().

MAC_AUTO_POLL_STATUS

#define MAC_AUTO_POLL_STATUS   0x00000458

Definition at line 624 of file tg3.h.

MAC_AUTO_POLL_ERROR

#define MAC_AUTO_POLL_ERROR   0x00000001

Definition at line 625 of file tg3.h.

MAC_TX_MODE

#define MAC_TX_MODE   0x0000045c

Definition at line 626 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_reset_hw(), and tg3_setup_flow_control().

TX_MODE_RESET

#define TX_MODE_RESET   0x00000001

Definition at line 627 of file tg3.h.

TX_MODE_ENABLE

#define TX_MODE_ENABLE   0x00000002

Definition at line 628 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

TX_MODE_FLOW_CTRL_ENABLE

#define TX_MODE_FLOW_CTRL_ENABLE   0x00000010

Definition at line 629 of file tg3.h.

Referenced by tg3_setup_flow_control().

TX_MODE_BIG_BCKOFF_ENABLE

#define TX_MODE_BIG_BCKOFF_ENABLE   0x00000020

Definition at line 630 of file tg3.h.

TX_MODE_LONG_PAUSE_ENABLE

#define TX_MODE_LONG_PAUSE_ENABLE   0x00000040

Definition at line 631 of file tg3.h.

TX_MODE_MBUF_LOCKUP_FIX

#define TX_MODE_MBUF_LOCKUP_FIX   0x00000100

Definition at line 632 of file tg3.h.

Referenced by tg3_reset_hw().

TX_MODE_JMB_FRM_LEN

#define TX_MODE_JMB_FRM_LEN   0x00400000

Definition at line 633 of file tg3.h.

Referenced by tg3_reset_hw().

TX_MODE_CNT_DN_MODE

#define TX_MODE_CNT_DN_MODE   0x00800000

Definition at line 634 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_TX_STATUS

#define MAC_TX_STATUS   0x00000460

Definition at line 635 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

TX_STATUS_XOFFED

#define TX_STATUS_XOFFED   0x00000001

Definition at line 636 of file tg3.h.

TX_STATUS_SENT_XOFF

#define TX_STATUS_SENT_XOFF   0x00000002

Definition at line 637 of file tg3.h.

TX_STATUS_SENT_XON

#define TX_STATUS_SENT_XON   0x00000004

Definition at line 638 of file tg3.h.

TX_STATUS_LINK_UP

#define TX_STATUS_LINK_UP   0x00000008

Definition at line 639 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

TX_STATUS_ODI_UNDERRUN

#define TX_STATUS_ODI_UNDERRUN   0x00000010

Definition at line 640 of file tg3.h.

TX_STATUS_ODI_OVERRUN

#define TX_STATUS_ODI_OVERRUN   0x00000020

Definition at line 641 of file tg3.h.

MAC_TX_LENGTHS

#define MAC_TX_LENGTHS   0x00000464

Definition at line 642 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

TX_LENGTHS_SLOT_TIME_MASK

#define TX_LENGTHS_SLOT_TIME_MASK   0x000000ff

Definition at line 643 of file tg3.h.

TX_LENGTHS_SLOT_TIME_SHIFT

#define TX_LENGTHS_SLOT_TIME_SHIFT   0

Definition at line 644 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

TX_LENGTHS_IPG_MASK

#define TX_LENGTHS_IPG_MASK   0x00000f00

Definition at line 645 of file tg3.h.

TX_LENGTHS_IPG_SHIFT

#define TX_LENGTHS_IPG_SHIFT   8

Definition at line 646 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

TX_LENGTHS_IPG_CRS_MASK

#define TX_LENGTHS_IPG_CRS_MASK   0x00003000

Definition at line 647 of file tg3.h.

TX_LENGTHS_IPG_CRS_SHIFT

#define TX_LENGTHS_IPG_CRS_SHIFT   12

Definition at line 648 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

TX_LENGTHS_JMB_FRM_LEN_MSK

#define TX_LENGTHS_JMB_FRM_LEN_MSK   0x00ff0000

Definition at line 649 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

TX_LENGTHS_CNT_DWN_VAL_MSK

#define TX_LENGTHS_CNT_DWN_VAL_MSK   0xff000000

Definition at line 650 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

MAC_RX_MODE

#define MAC_RX_MODE   0x00000468

Definition at line 651 of file tg3.h.

Referenced by __tg3_set_rx_mode(), tg3_abort_hw(), tg3_reset_hw(), and tg3_setup_flow_control().

RX_MODE_RESET

#define RX_MODE_RESET   0x00000001

Definition at line 652 of file tg3.h.

Referenced by tg3_reset_hw().

RX_MODE_ENABLE

#define RX_MODE_ENABLE   0x00000002

Definition at line 653 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RX_MODE_FLOW_CTRL_ENABLE

#define RX_MODE_FLOW_CTRL_ENABLE   0x00000004

Definition at line 654 of file tg3.h.

Referenced by tg3_setup_flow_control().

RX_MODE_KEEP_MAC_CTRL

#define RX_MODE_KEEP_MAC_CTRL   0x00000008

Definition at line 655 of file tg3.h.

RX_MODE_KEEP_PAUSE

#define RX_MODE_KEEP_PAUSE   0x00000010

Definition at line 656 of file tg3.h.

RX_MODE_ACCEPT_OVERSIZED

#define RX_MODE_ACCEPT_OVERSIZED   0x00000020

Definition at line 657 of file tg3.h.

RX_MODE_ACCEPT_RUNTS

#define RX_MODE_ACCEPT_RUNTS   0x00000040

Definition at line 658 of file tg3.h.

RX_MODE_LEN_CHECK

#define RX_MODE_LEN_CHECK   0x00000080

Definition at line 659 of file tg3.h.

RX_MODE_PROMISC

#define RX_MODE_PROMISC   0x00000100

Definition at line 660 of file tg3.h.

Referenced by __tg3_set_rx_mode().

RX_MODE_NO_CRC_CHECK

#define RX_MODE_NO_CRC_CHECK   0x00000200

Definition at line 661 of file tg3.h.

RX_MODE_KEEP_VLAN_TAG

#define RX_MODE_KEEP_VLAN_TAG   0x00000400

Definition at line 662 of file tg3.h.

Referenced by __tg3_set_rx_mode().

RX_MODE_RSS_IPV4_HASH_EN

#define RX_MODE_RSS_IPV4_HASH_EN   0x00010000

Definition at line 663 of file tg3.h.

RX_MODE_RSS_TCP_IPV4_HASH_EN

#define RX_MODE_RSS_TCP_IPV4_HASH_EN   0x00020000

Definition at line 664 of file tg3.h.

RX_MODE_RSS_IPV6_HASH_EN

#define RX_MODE_RSS_IPV6_HASH_EN   0x00040000

Definition at line 665 of file tg3.h.

RX_MODE_RSS_TCP_IPV6_HASH_EN

#define RX_MODE_RSS_TCP_IPV6_HASH_EN   0x00080000

Definition at line 666 of file tg3.h.

RX_MODE_RSS_ITBL_HASH_BITS_7

#define RX_MODE_RSS_ITBL_HASH_BITS_7   0x00700000

Definition at line 667 of file tg3.h.

RX_MODE_RSS_ENABLE

#define RX_MODE_RSS_ENABLE   0x00800000

Definition at line 668 of file tg3.h.

RX_MODE_IPV6_CSUM_ENABLE

#define RX_MODE_IPV6_CSUM_ENABLE   0x01000000

Definition at line 669 of file tg3.h.

MAC_RX_STATUS

#define MAC_RX_STATUS   0x0000046c

Definition at line 670 of file tg3.h.

RX_STATUS_REMOTE_TX_XOFFED

#define RX_STATUS_REMOTE_TX_XOFFED   0x00000001

Definition at line 671 of file tg3.h.

RX_STATUS_XOFF_RCVD

#define RX_STATUS_XOFF_RCVD   0x00000002

Definition at line 672 of file tg3.h.

RX_STATUS_XON_RCVD

#define RX_STATUS_XON_RCVD   0x00000004

Definition at line 673 of file tg3.h.

MAC_HASH_REG_0

#define MAC_HASH_REG_0   0x00000470

Definition at line 674 of file tg3.h.

Referenced by __tg3_set_rx_mode().

MAC_HASH_REG_1

#define MAC_HASH_REG_1   0x00000474

Definition at line 675 of file tg3.h.

Referenced by __tg3_set_rx_mode().

MAC_HASH_REG_2

#define MAC_HASH_REG_2   0x00000478

Definition at line 676 of file tg3.h.

Referenced by __tg3_set_rx_mode().

MAC_HASH_REG_3

#define MAC_HASH_REG_3   0x0000047c

Definition at line 677 of file tg3.h.

Referenced by __tg3_set_rx_mode().

MAC_RCV_RULE_0

#define MAC_RCV_RULE_0   0x00000480

Definition at line 678 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_0

#define MAC_RCV_VALUE_0   0x00000484

Definition at line 679 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_1

#define MAC_RCV_RULE_1   0x00000488

Definition at line 680 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_1

#define MAC_RCV_VALUE_1   0x0000048c

Definition at line 681 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_2

#define MAC_RCV_RULE_2   0x00000490

Definition at line 682 of file tg3.h.

MAC_RCV_VALUE_2

#define MAC_RCV_VALUE_2   0x00000494

Definition at line 683 of file tg3.h.

MAC_RCV_RULE_3

#define MAC_RCV_RULE_3   0x00000498

Definition at line 684 of file tg3.h.

MAC_RCV_VALUE_3

#define MAC_RCV_VALUE_3   0x0000049c

Definition at line 685 of file tg3.h.

MAC_RCV_RULE_4

#define MAC_RCV_RULE_4   0x000004a0

Definition at line 686 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_4

#define MAC_RCV_VALUE_4   0x000004a4

Definition at line 687 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_5

#define MAC_RCV_RULE_5   0x000004a8

Definition at line 688 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_5

#define MAC_RCV_VALUE_5   0x000004ac

Definition at line 689 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_6

#define MAC_RCV_RULE_6   0x000004b0

Definition at line 690 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_6

#define MAC_RCV_VALUE_6   0x000004b4

Definition at line 691 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_7

#define MAC_RCV_RULE_7   0x000004b8

Definition at line 692 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_7

#define MAC_RCV_VALUE_7   0x000004bc

Definition at line 693 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_8

#define MAC_RCV_RULE_8   0x000004c0

Definition at line 694 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_8

#define MAC_RCV_VALUE_8   0x000004c4

Definition at line 695 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_9

#define MAC_RCV_RULE_9   0x000004c8

Definition at line 696 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_9

#define MAC_RCV_VALUE_9   0x000004cc

Definition at line 697 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_10

#define MAC_RCV_RULE_10   0x000004d0

Definition at line 698 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_10

#define MAC_RCV_VALUE_10   0x000004d4

Definition at line 699 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_11

#define MAC_RCV_RULE_11   0x000004d8

Definition at line 700 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_11

#define MAC_RCV_VALUE_11   0x000004dc

Definition at line 701 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_12

#define MAC_RCV_RULE_12   0x000004e0

Definition at line 702 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_12

#define MAC_RCV_VALUE_12   0x000004e4

Definition at line 703 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_13

#define MAC_RCV_RULE_13   0x000004e8

Definition at line 704 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_13

#define MAC_RCV_VALUE_13   0x000004ec

Definition at line 705 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_14

#define MAC_RCV_RULE_14   0x000004f0

Definition at line 706 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_14

#define MAC_RCV_VALUE_14   0x000004f4

Definition at line 707 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_15

#define MAC_RCV_RULE_15   0x000004f8

Definition at line 708 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_VALUE_15

#define MAC_RCV_VALUE_15   0x000004fc

Definition at line 709 of file tg3.h.

Referenced by tg3_reset_hw().

RCV_RULE_DISABLE_MASK

#define RCV_RULE_DISABLE_MASK   0x7fffffff

Definition at line 710 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_RCV_RULE_CFG

#define MAC_RCV_RULE_CFG   0x00000500

Definition at line 711 of file tg3.h.

Referenced by tg3_reset_hw().

RCV_RULE_CFG_DEFAULT_CLASS

#define RCV_RULE_CFG_DEFAULT_CLASS   0x00000008

Definition at line 712 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_LOW_WMARK_MAX_RX_FRAME

#define MAC_LOW_WMARK_MAX_RX_FRAME   0x00000504

Definition at line 713 of file tg3.h.

Referenced by tg3_reset_hw().

MAC_HASHREGU_0

#define MAC_HASHREGU_0   0x00000520

Definition at line 715 of file tg3.h.

MAC_HASHREGU_1

#define MAC_HASHREGU_1   0x00000524

Definition at line 716 of file tg3.h.

MAC_HASHREGU_2

#define MAC_HASHREGU_2   0x00000528

Definition at line 717 of file tg3.h.

MAC_HASHREGU_3

#define MAC_HASHREGU_3   0x0000052c

Definition at line 718 of file tg3.h.

MAC_EXTADDR_0_HIGH

#define MAC_EXTADDR_0_HIGH   0x00000530

Definition at line 719 of file tg3.h.

Referenced by __tg3_set_mac_addr().

MAC_EXTADDR_0_LOW

#define MAC_EXTADDR_0_LOW   0x00000534

Definition at line 720 of file tg3.h.

Referenced by __tg3_set_mac_addr().

MAC_EXTADDR_1_HIGH

#define MAC_EXTADDR_1_HIGH   0x00000538

Definition at line 721 of file tg3.h.

MAC_EXTADDR_1_LOW

#define MAC_EXTADDR_1_LOW   0x0000053c

Definition at line 722 of file tg3.h.

MAC_EXTADDR_2_HIGH

#define MAC_EXTADDR_2_HIGH   0x00000540

Definition at line 723 of file tg3.h.

MAC_EXTADDR_2_LOW

#define MAC_EXTADDR_2_LOW   0x00000544

Definition at line 724 of file tg3.h.

MAC_EXTADDR_3_HIGH

#define MAC_EXTADDR_3_HIGH   0x00000548

Definition at line 725 of file tg3.h.

MAC_EXTADDR_3_LOW

#define MAC_EXTADDR_3_LOW   0x0000054c

Definition at line 726 of file tg3.h.

MAC_EXTADDR_4_HIGH

#define MAC_EXTADDR_4_HIGH   0x00000550

Definition at line 727 of file tg3.h.

MAC_EXTADDR_4_LOW

#define MAC_EXTADDR_4_LOW   0x00000554

Definition at line 728 of file tg3.h.

MAC_EXTADDR_5_HIGH

#define MAC_EXTADDR_5_HIGH   0x00000558

Definition at line 729 of file tg3.h.

MAC_EXTADDR_5_LOW

#define MAC_EXTADDR_5_LOW   0x0000055c

Definition at line 730 of file tg3.h.

MAC_EXTADDR_6_HIGH

#define MAC_EXTADDR_6_HIGH   0x00000560

Definition at line 731 of file tg3.h.

MAC_EXTADDR_6_LOW

#define MAC_EXTADDR_6_LOW   0x00000564

Definition at line 732 of file tg3.h.

MAC_EXTADDR_7_HIGH

#define MAC_EXTADDR_7_HIGH   0x00000568

Definition at line 733 of file tg3.h.

MAC_EXTADDR_7_LOW

#define MAC_EXTADDR_7_LOW   0x0000056c

Definition at line 734 of file tg3.h.

MAC_EXTADDR_8_HIGH

#define MAC_EXTADDR_8_HIGH   0x00000570

Definition at line 735 of file tg3.h.

MAC_EXTADDR_8_LOW

#define MAC_EXTADDR_8_LOW   0x00000574

Definition at line 736 of file tg3.h.

MAC_EXTADDR_9_HIGH

#define MAC_EXTADDR_9_HIGH   0x00000578

Definition at line 737 of file tg3.h.

MAC_EXTADDR_9_LOW

#define MAC_EXTADDR_9_LOW   0x0000057c

Definition at line 738 of file tg3.h.

MAC_EXTADDR_10_HIGH

#define MAC_EXTADDR_10_HIGH   0x00000580

Definition at line 739 of file tg3.h.

MAC_EXTADDR_10_LOW

#define MAC_EXTADDR_10_LOW   0x00000584

Definition at line 740 of file tg3.h.

MAC_EXTADDR_11_HIGH

#define MAC_EXTADDR_11_HIGH   0x00000588

Definition at line 741 of file tg3.h.

MAC_EXTADDR_11_LOW

#define MAC_EXTADDR_11_LOW   0x0000058c

Definition at line 742 of file tg3.h.

MAC_SERDES_CFG

#define MAC_SERDES_CFG   0x00000590

Definition at line 743 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_fiber_hw_autoneg().

MAC_SERDES_CFG_EDGE_SELECT

#define MAC_SERDES_CFG_EDGE_SELECT   0x00001000

Definition at line 744 of file tg3.h.

MAC_SERDES_STAT

#define MAC_SERDES_STAT   0x00000594

Definition at line 745 of file tg3.h.

MAC_PHYCFG1

#define MAC_PHYCFG1   0x000005a0

Definition at line 747 of file tg3.h.

MAC_PHYCFG1_RGMII_INT

#define MAC_PHYCFG1_RGMII_INT   0x00000001

Definition at line 748 of file tg3.h.

MAC_PHYCFG1_RXCLK_TO_MASK

#define MAC_PHYCFG1_RXCLK_TO_MASK   0x00001ff0

Definition at line 749 of file tg3.h.

MAC_PHYCFG1_RXCLK_TIMEOUT

#define MAC_PHYCFG1_RXCLK_TIMEOUT   0x00001000

Definition at line 750 of file tg3.h.

MAC_PHYCFG1_TXCLK_TO_MASK

#define MAC_PHYCFG1_TXCLK_TO_MASK   0x01ff0000

Definition at line 751 of file tg3.h.

MAC_PHYCFG1_TXCLK_TIMEOUT

#define MAC_PHYCFG1_TXCLK_TIMEOUT   0x01000000

Definition at line 752 of file tg3.h.

MAC_PHYCFG1_RGMII_EXT_RX_DEC

#define MAC_PHYCFG1_RGMII_EXT_RX_DEC   0x02000000

Definition at line 753 of file tg3.h.

MAC_PHYCFG1_RGMII_SND_STAT_EN

#define MAC_PHYCFG1_RGMII_SND_STAT_EN   0x04000000

Definition at line 754 of file tg3.h.

MAC_PHYCFG1_TXC_DRV

#define MAC_PHYCFG1_TXC_DRV   0x20000000

Definition at line 755 of file tg3.h.

MAC_PHYCFG2

#define MAC_PHYCFG2   0x000005a4

Definition at line 756 of file tg3.h.

MAC_PHYCFG2_INBAND_ENABLE

#define MAC_PHYCFG2_INBAND_ENABLE   0x00000001

Definition at line 757 of file tg3.h.

MAC_PHYCFG2_EMODE_MASK_MASK

#define MAC_PHYCFG2_EMODE_MASK_MASK   0x000001c0

Definition at line 758 of file tg3.h.

MAC_PHYCFG2_EMODE_MASK_AC131

#define MAC_PHYCFG2_EMODE_MASK_AC131   0x000000c0

Definition at line 759 of file tg3.h.

MAC_PHYCFG2_EMODE_MASK_50610

#define MAC_PHYCFG2_EMODE_MASK_50610   0x00000100

Definition at line 760 of file tg3.h.

MAC_PHYCFG2_EMODE_MASK_RT8211

#define MAC_PHYCFG2_EMODE_MASK_RT8211   0x00000000

Definition at line 761 of file tg3.h.

MAC_PHYCFG2_EMODE_MASK_RT8201

#define MAC_PHYCFG2_EMODE_MASK_RT8201   0x000001c0

Definition at line 762 of file tg3.h.

MAC_PHYCFG2_EMODE_COMP_MASK

#define MAC_PHYCFG2_EMODE_COMP_MASK   0x00000e00

Definition at line 763 of file tg3.h.

MAC_PHYCFG2_EMODE_COMP_AC131

#define MAC_PHYCFG2_EMODE_COMP_AC131   0x00000600

Definition at line 764 of file tg3.h.

MAC_PHYCFG2_EMODE_COMP_50610

#define MAC_PHYCFG2_EMODE_COMP_50610   0x00000400

Definition at line 765 of file tg3.h.

MAC_PHYCFG2_EMODE_COMP_RT8211

#define MAC_PHYCFG2_EMODE_COMP_RT8211   0x00000800

Definition at line 766 of file tg3.h.

MAC_PHYCFG2_EMODE_COMP_RT8201

#define MAC_PHYCFG2_EMODE_COMP_RT8201   0x00000000

Definition at line 767 of file tg3.h.

MAC_PHYCFG2_FMODE_MASK_MASK

#define MAC_PHYCFG2_FMODE_MASK_MASK   0x00007000

Definition at line 768 of file tg3.h.

MAC_PHYCFG2_FMODE_MASK_AC131

#define MAC_PHYCFG2_FMODE_MASK_AC131   0x00006000

Definition at line 769 of file tg3.h.

MAC_PHYCFG2_FMODE_MASK_50610

#define MAC_PHYCFG2_FMODE_MASK_50610   0x00004000

Definition at line 770 of file tg3.h.

MAC_PHYCFG2_FMODE_MASK_RT8211

#define MAC_PHYCFG2_FMODE_MASK_RT8211   0x00000000

Definition at line 771 of file tg3.h.

MAC_PHYCFG2_FMODE_MASK_RT8201

#define MAC_PHYCFG2_FMODE_MASK_RT8201   0x00007000

Definition at line 772 of file tg3.h.

MAC_PHYCFG2_FMODE_COMP_MASK

#define MAC_PHYCFG2_FMODE_COMP_MASK   0x00038000

Definition at line 773 of file tg3.h.

MAC_PHYCFG2_FMODE_COMP_AC131

#define MAC_PHYCFG2_FMODE_COMP_AC131   0x00030000

Definition at line 774 of file tg3.h.

MAC_PHYCFG2_FMODE_COMP_50610

#define MAC_PHYCFG2_FMODE_COMP_50610   0x00008000

Definition at line 775 of file tg3.h.

MAC_PHYCFG2_FMODE_COMP_RT8211

#define MAC_PHYCFG2_FMODE_COMP_RT8211   0x00038000

Definition at line 776 of file tg3.h.

MAC_PHYCFG2_FMODE_COMP_RT8201

#define MAC_PHYCFG2_FMODE_COMP_RT8201   0x00000000

Definition at line 777 of file tg3.h.

MAC_PHYCFG2_GMODE_MASK_MASK

#define MAC_PHYCFG2_GMODE_MASK_MASK   0x001c0000

Definition at line 778 of file tg3.h.

MAC_PHYCFG2_GMODE_MASK_AC131

#define MAC_PHYCFG2_GMODE_MASK_AC131   0x001c0000

Definition at line 779 of file tg3.h.

MAC_PHYCFG2_GMODE_MASK_50610

#define MAC_PHYCFG2_GMODE_MASK_50610   0x00100000

Definition at line 780 of file tg3.h.

MAC_PHYCFG2_GMODE_MASK_RT8211

#define MAC_PHYCFG2_GMODE_MASK_RT8211   0x00000000

Definition at line 781 of file tg3.h.

MAC_PHYCFG2_GMODE_MASK_RT8201

#define MAC_PHYCFG2_GMODE_MASK_RT8201   0x001c0000

Definition at line 782 of file tg3.h.

MAC_PHYCFG2_GMODE_COMP_MASK

#define MAC_PHYCFG2_GMODE_COMP_MASK   0x00e00000

Definition at line 783 of file tg3.h.

MAC_PHYCFG2_GMODE_COMP_AC131

#define MAC_PHYCFG2_GMODE_COMP_AC131   0x00e00000

Definition at line 784 of file tg3.h.

MAC_PHYCFG2_GMODE_COMP_50610

#define MAC_PHYCFG2_GMODE_COMP_50610   0x00000000

Definition at line 785 of file tg3.h.

MAC_PHYCFG2_GMODE_COMP_RT8211

#define MAC_PHYCFG2_GMODE_COMP_RT8211   0x00200000

Definition at line 786 of file tg3.h.

MAC_PHYCFG2_GMODE_COMP_RT8201

#define MAC_PHYCFG2_GMODE_COMP_RT8201   0x00000000

Definition at line 787 of file tg3.h.

MAC_PHYCFG2_ACT_MASK_MASK

#define MAC_PHYCFG2_ACT_MASK_MASK   0x03000000

Definition at line 788 of file tg3.h.

MAC_PHYCFG2_ACT_MASK_AC131

#define MAC_PHYCFG2_ACT_MASK_AC131   0x03000000

Definition at line 789 of file tg3.h.

MAC_PHYCFG2_ACT_MASK_50610

#define MAC_PHYCFG2_ACT_MASK_50610   0x01000000

Definition at line 790 of file tg3.h.

MAC_PHYCFG2_ACT_MASK_RT8211

#define MAC_PHYCFG2_ACT_MASK_RT8211   0x03000000

Definition at line 791 of file tg3.h.

MAC_PHYCFG2_ACT_MASK_RT8201

#define MAC_PHYCFG2_ACT_MASK_RT8201   0x01000000

Definition at line 792 of file tg3.h.

MAC_PHYCFG2_ACT_COMP_MASK

#define MAC_PHYCFG2_ACT_COMP_MASK   0x0c000000

Definition at line 793 of file tg3.h.

MAC_PHYCFG2_ACT_COMP_AC131

#define MAC_PHYCFG2_ACT_COMP_AC131   0x00000000

Definition at line 794 of file tg3.h.

MAC_PHYCFG2_ACT_COMP_50610

#define MAC_PHYCFG2_ACT_COMP_50610   0x00000000

Definition at line 795 of file tg3.h.

MAC_PHYCFG2_ACT_COMP_RT8211

#define MAC_PHYCFG2_ACT_COMP_RT8211   0x00000000

Definition at line 796 of file tg3.h.

MAC_PHYCFG2_ACT_COMP_RT8201

#define MAC_PHYCFG2_ACT_COMP_RT8201   0x08000000

Definition at line 797 of file tg3.h.

MAC_PHYCFG2_QUAL_MASK_MASK

#define MAC_PHYCFG2_QUAL_MASK_MASK   0x30000000

Definition at line 798 of file tg3.h.

MAC_PHYCFG2_QUAL_MASK_AC131

#define MAC_PHYCFG2_QUAL_MASK_AC131   0x30000000

Definition at line 799 of file tg3.h.

MAC_PHYCFG2_QUAL_MASK_50610

#define MAC_PHYCFG2_QUAL_MASK_50610   0x30000000

Definition at line 800 of file tg3.h.

MAC_PHYCFG2_QUAL_MASK_RT8211

#define MAC_PHYCFG2_QUAL_MASK_RT8211   0x30000000

Definition at line 801 of file tg3.h.

MAC_PHYCFG2_QUAL_MASK_RT8201

#define MAC_PHYCFG2_QUAL_MASK_RT8201   0x30000000

Definition at line 802 of file tg3.h.

MAC_PHYCFG2_QUAL_COMP_MASK

#define MAC_PHYCFG2_QUAL_COMP_MASK   0xc0000000

Definition at line 803 of file tg3.h.

MAC_PHYCFG2_QUAL_COMP_AC131

#define MAC_PHYCFG2_QUAL_COMP_AC131   0x00000000

Definition at line 804 of file tg3.h.

MAC_PHYCFG2_QUAL_COMP_50610

#define MAC_PHYCFG2_QUAL_COMP_50610   0x00000000

Definition at line 805 of file tg3.h.

MAC_PHYCFG2_QUAL_COMP_RT8211

#define MAC_PHYCFG2_QUAL_COMP_RT8211   0x00000000

Definition at line 806 of file tg3.h.

MAC_PHYCFG2_QUAL_COMP_RT8201

#define MAC_PHYCFG2_QUAL_COMP_RT8201   0x00000000

Definition at line 807 of file tg3.h.

MAC_PHYCFG2_50610_LED_MODES

#define MAC_PHYCFG2_50610_LED_MODES

Value:

        (MAC_PHYCFG2_EMODE_MASK_50610 | \
         MAC_PHYCFG2_EMODE_COMP_50610 | \
         MAC_PHYCFG2_FMODE_MASK_50610 | \
         MAC_PHYCFG2_FMODE_COMP_50610 | \
         MAC_PHYCFG2_GMODE_MASK_50610 | \
         MAC_PHYCFG2_GMODE_COMP_50610 | \
         MAC_PHYCFG2_ACT_MASK_50610 | \
         MAC_PHYCFG2_ACT_COMP_50610 | \
         MAC_PHYCFG2_QUAL_MASK_50610 | \
         MAC_PHYCFG2_QUAL_COMP_50610)

Definition at line 808 of file tg3.h.

#define MAC_PHYCFG2_50610_LED_MODES \
        (MAC_PHYCFG2_EMODE_MASK_50610 | \
         MAC_PHYCFG2_EMODE_COMP_50610 | \
         MAC_PHYCFG2_FMODE_MASK_50610 | \
         MAC_PHYCFG2_FMODE_COMP_50610 | \
         MAC_PHYCFG2_GMODE_MASK_50610 | \
         MAC_PHYCFG2_GMODE_COMP_50610 | \
         MAC_PHYCFG2_ACT_MASK_50610 | \
         MAC_PHYCFG2_ACT_COMP_50610 | \
         MAC_PHYCFG2_QUAL_MASK_50610 | \
         MAC_PHYCFG2_QUAL_COMP_50610)

MAC_PHYCFG2_AC131_LED_MODES

#define MAC_PHYCFG2_AC131_LED_MODES

Value:

        (MAC_PHYCFG2_EMODE_MASK_AC131 | \
         MAC_PHYCFG2_EMODE_COMP_AC131 | \
         MAC_PHYCFG2_FMODE_MASK_AC131 | \
         MAC_PHYCFG2_FMODE_COMP_AC131 | \
         MAC_PHYCFG2_GMODE_MASK_AC131 | \
         MAC_PHYCFG2_GMODE_COMP_AC131 | \
         MAC_PHYCFG2_ACT_MASK_AC131 | \
         MAC_PHYCFG2_ACT_COMP_AC131 | \
         MAC_PHYCFG2_QUAL_MASK_AC131 | \
         MAC_PHYCFG2_QUAL_COMP_AC131)

Definition at line 819 of file tg3.h.

#define MAC_PHYCFG2_AC131_LED_MODES \
        (MAC_PHYCFG2_EMODE_MASK_AC131 | \
         MAC_PHYCFG2_EMODE_COMP_AC131 | \
         MAC_PHYCFG2_FMODE_MASK_AC131 | \
         MAC_PHYCFG2_FMODE_COMP_AC131 | \
         MAC_PHYCFG2_GMODE_MASK_AC131 | \
         MAC_PHYCFG2_GMODE_COMP_AC131 | \
         MAC_PHYCFG2_ACT_MASK_AC131 | \
         MAC_PHYCFG2_ACT_COMP_AC131 | \
         MAC_PHYCFG2_QUAL_MASK_AC131 | \
         MAC_PHYCFG2_QUAL_COMP_AC131)

MAC_PHYCFG2_RTL8211C_LED_MODES

#define MAC_PHYCFG2_RTL8211C_LED_MODES

Value:

        (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
         MAC_PHYCFG2_EMODE_COMP_RT8211 | \
         MAC_PHYCFG2_FMODE_MASK_RT8211 | \
         MAC_PHYCFG2_FMODE_COMP_RT8211 | \
         MAC_PHYCFG2_GMODE_MASK_RT8211 | \
         MAC_PHYCFG2_GMODE_COMP_RT8211 | \
         MAC_PHYCFG2_ACT_MASK_RT8211 | \
         MAC_PHYCFG2_ACT_COMP_RT8211 | \
         MAC_PHYCFG2_QUAL_MASK_RT8211 | \
         MAC_PHYCFG2_QUAL_COMP_RT8211)

Definition at line 830 of file tg3.h.

#define MAC_PHYCFG2_RTL8211C_LED_MODES \
        (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
         MAC_PHYCFG2_EMODE_COMP_RT8211 | \
         MAC_PHYCFG2_FMODE_MASK_RT8211 | \
         MAC_PHYCFG2_FMODE_COMP_RT8211 | \
         MAC_PHYCFG2_GMODE_MASK_RT8211 | \
         MAC_PHYCFG2_GMODE_COMP_RT8211 | \
         MAC_PHYCFG2_ACT_MASK_RT8211 | \
         MAC_PHYCFG2_ACT_COMP_RT8211 | \
         MAC_PHYCFG2_QUAL_MASK_RT8211 | \
         MAC_PHYCFG2_QUAL_COMP_RT8211)

MAC_PHYCFG2_RTL8201E_LED_MODES

#define MAC_PHYCFG2_RTL8201E_LED_MODES

Value:

        (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
         MAC_PHYCFG2_EMODE_COMP_RT8201 | \
         MAC_PHYCFG2_FMODE_MASK_RT8201 | \
         MAC_PHYCFG2_FMODE_COMP_RT8201 | \
         MAC_PHYCFG2_GMODE_MASK_RT8201 | \
         MAC_PHYCFG2_GMODE_COMP_RT8201 | \
         MAC_PHYCFG2_ACT_MASK_RT8201 | \
         MAC_PHYCFG2_ACT_COMP_RT8201 | \
         MAC_PHYCFG2_QUAL_MASK_RT8201 | \
         MAC_PHYCFG2_QUAL_COMP_RT8201)

Definition at line 841 of file tg3.h.

#define MAC_PHYCFG2_RTL8201E_LED_MODES \
        (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
         MAC_PHYCFG2_EMODE_COMP_RT8201 | \
         MAC_PHYCFG2_FMODE_MASK_RT8201 | \
         MAC_PHYCFG2_FMODE_COMP_RT8201 | \
         MAC_PHYCFG2_GMODE_MASK_RT8201 | \
         MAC_PHYCFG2_GMODE_COMP_RT8201 | \
         MAC_PHYCFG2_ACT_MASK_RT8201 | \
         MAC_PHYCFG2_ACT_COMP_RT8201 | \
         MAC_PHYCFG2_QUAL_MASK_RT8201 | \
         MAC_PHYCFG2_QUAL_COMP_RT8201)

MAC_EXT_RGMII_MODE

#define MAC_EXT_RGMII_MODE   0x000005a8

Definition at line 852 of file tg3.h.

MAC_RGMII_MODE_TX_ENABLE

#define MAC_RGMII_MODE_TX_ENABLE   0x00000001

Definition at line 853 of file tg3.h.

MAC_RGMII_MODE_TX_LOWPWR

#define MAC_RGMII_MODE_TX_LOWPWR   0x00000002

Definition at line 854 of file tg3.h.

MAC_RGMII_MODE_TX_RESET

#define MAC_RGMII_MODE_TX_RESET   0x00000004

Definition at line 855 of file tg3.h.

MAC_RGMII_MODE_RX_INT_B

#define MAC_RGMII_MODE_RX_INT_B   0x00000100

Definition at line 856 of file tg3.h.

MAC_RGMII_MODE_RX_QUALITY

#define MAC_RGMII_MODE_RX_QUALITY   0x00000200

Definition at line 857 of file tg3.h.

MAC_RGMII_MODE_RX_ACTIVITY

#define MAC_RGMII_MODE_RX_ACTIVITY   0x00000400

Definition at line 858 of file tg3.h.

MAC_RGMII_MODE_RX_ENG_DET

#define MAC_RGMII_MODE_RX_ENG_DET   0x00000800

Definition at line 859 of file tg3.h.

SERDES_RX_CTRL

#define SERDES_RX_CTRL   0x000005b0 /* 5780/5714 only */

Definition at line 861 of file tg3.h.

Referenced by tg3_reset_hw().

SERDES_RX_SIG_DETECT

#define SERDES_RX_SIG_DETECT   0x00000400

Definition at line 862 of file tg3.h.

Referenced by tg3_reset_hw().

SG_DIG_CTRL

#define SG_DIG_CTRL   0x000005b0

Definition at line 863 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_USING_HW_AUTONEG

#define SG_DIG_USING_HW_AUTONEG   0x80000000

Definition at line 864 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_SOFT_RESET

#define SG_DIG_SOFT_RESET   0x40000000

Definition at line 865 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_DISABLE_LINKRDY

#define SG_DIG_DISABLE_LINKRDY   0x20000000

Definition at line 866 of file tg3.h.

SG_DIG_CRC16_CLEAR_N

#define SG_DIG_CRC16_CLEAR_N   0x01000000

Definition at line 867 of file tg3.h.

SG_DIG_EN10B

#define SG_DIG_EN10B   0x00800000

Definition at line 868 of file tg3.h.

SG_DIG_CLEAR_STATUS

#define SG_DIG_CLEAR_STATUS   0x00400000

Definition at line 869 of file tg3.h.

SG_DIG_LOCAL_DUPLEX_STATUS

#define SG_DIG_LOCAL_DUPLEX_STATUS   0x00200000

Definition at line 870 of file tg3.h.

SG_DIG_LOCAL_LINK_STATUS

#define SG_DIG_LOCAL_LINK_STATUS   0x00100000

Definition at line 871 of file tg3.h.

SG_DIG_SPEED_STATUS_MASK

#define SG_DIG_SPEED_STATUS_MASK   0x000c0000

Definition at line 872 of file tg3.h.

SG_DIG_SPEED_STATUS_SHIFT

#define SG_DIG_SPEED_STATUS_SHIFT   18

Definition at line 873 of file tg3.h.

SG_DIG_JUMBO_PACKET_DISABLE

#define SG_DIG_JUMBO_PACKET_DISABLE   0x00020000

Definition at line 874 of file tg3.h.

SG_DIG_RESTART_AUTONEG

#define SG_DIG_RESTART_AUTONEG   0x00010000

Definition at line 875 of file tg3.h.

SG_DIG_FIBER_MODE

#define SG_DIG_FIBER_MODE   0x00008000

Definition at line 876 of file tg3.h.

SG_DIG_REMOTE_FAULT_MASK

#define SG_DIG_REMOTE_FAULT_MASK   0x00006000

Definition at line 877 of file tg3.h.

SG_DIG_PAUSE_MASK

#define SG_DIG_PAUSE_MASK   0x00001800

Definition at line 878 of file tg3.h.

SG_DIG_PAUSE_CAP

#define SG_DIG_PAUSE_CAP   0x00000800

Definition at line 879 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_ASYM_PAUSE

#define SG_DIG_ASYM_PAUSE   0x00001000

Definition at line 880 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_GBIC_ENABLE

#define SG_DIG_GBIC_ENABLE   0x00000400

Definition at line 881 of file tg3.h.

SG_DIG_CHECK_END_ENABLE

#define SG_DIG_CHECK_END_ENABLE   0x00000200

Definition at line 882 of file tg3.h.

SG_DIG_SGMII_AUTONEG_TIMER

#define SG_DIG_SGMII_AUTONEG_TIMER   0x00000100

Definition at line 883 of file tg3.h.

SG_DIG_CLOCK_PHASE_SELECT

#define SG_DIG_CLOCK_PHASE_SELECT   0x00000080

Definition at line 884 of file tg3.h.

SG_DIG_GMII_INPUT_SELECT

#define SG_DIG_GMII_INPUT_SELECT   0x00000040

Definition at line 885 of file tg3.h.

SG_DIG_MRADV_CRC16_SELECT

#define SG_DIG_MRADV_CRC16_SELECT   0x00000020

Definition at line 886 of file tg3.h.

SG_DIG_COMMA_DETECT_ENABLE

#define SG_DIG_COMMA_DETECT_ENABLE   0x00000010

Definition at line 887 of file tg3.h.

SG_DIG_AUTONEG_TIMER_REDUCE

#define SG_DIG_AUTONEG_TIMER_REDUCE   0x00000008

Definition at line 888 of file tg3.h.

SG_DIG_AUTONEG_LOW_ENABLE

#define SG_DIG_AUTONEG_LOW_ENABLE   0x00000004

Definition at line 889 of file tg3.h.

SG_DIG_REMOTE_LOOPBACK

#define SG_DIG_REMOTE_LOOPBACK   0x00000002

Definition at line 890 of file tg3.h.

SG_DIG_LOOPBACK

#define SG_DIG_LOOPBACK   0x00000001

Definition at line 891 of file tg3.h.

SG_DIG_COMMON_SETUP

#define SG_DIG_COMMON_SETUP

Value:

                              (SG_DIG_CRC16_CLEAR_N | \
                              SG_DIG_LOCAL_DUPLEX_STATUS | \
                              SG_DIG_LOCAL_LINK_STATUS | \
                              (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
                              SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)

Definition at line 892 of file tg3.h.

#define  SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
                              SG_DIG_LOCAL_DUPLEX_STATUS | \
                              SG_DIG_LOCAL_LINK_STATUS | \
                              (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
                              SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_STATUS

#define SG_DIG_STATUS   0x000005b4

Definition at line 897 of file tg3.h.

Referenced by tg3_mdio_init(), and tg3_setup_fiber_hw_autoneg().

SG_DIG_CRC16_BUS_MASK

#define SG_DIG_CRC16_BUS_MASK   0xffff0000

Definition at line 898 of file tg3.h.

SG_DIG_PARTNER_FAULT_MASK

#define SG_DIG_PARTNER_FAULT_MASK   0x00600000 /* If !MRADV_CRC16_SELECT */

Definition at line 899 of file tg3.h.

SG_DIG_PARTNER_ASYM_PAUSE

#define SG_DIG_PARTNER_ASYM_PAUSE   0x00100000 /* If !MRADV_CRC16_SELECT */

Definition at line 900 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_PARTNER_PAUSE_CAPABLE

#define SG_DIG_PARTNER_PAUSE_CAPABLE   0x00080000 /* If !MRADV_CRC16_SELECT */

Definition at line 901 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_PARTNER_HALF_DUPLEX

#define SG_DIG_PARTNER_HALF_DUPLEX   0x00040000 /* If !MRADV_CRC16_SELECT */

Definition at line 902 of file tg3.h.

SG_DIG_PARTNER_FULL_DUPLEX

#define SG_DIG_PARTNER_FULL_DUPLEX   0x00020000 /* If !MRADV_CRC16_SELECT */

Definition at line 903 of file tg3.h.

SG_DIG_PARTNER_NEXT_PAGE

#define SG_DIG_PARTNER_NEXT_PAGE   0x00010000 /* If !MRADV_CRC16_SELECT */

Definition at line 904 of file tg3.h.

SG_DIG_AUTONEG_STATE_MASK

#define SG_DIG_AUTONEG_STATE_MASK   0x00000ff0

Definition at line 905 of file tg3.h.

SG_DIG_IS_SERDES

#define SG_DIG_IS_SERDES   0x00000100

Definition at line 906 of file tg3.h.

Referenced by tg3_mdio_init().

SG_DIG_COMMA_DETECTOR

#define SG_DIG_COMMA_DETECTOR   0x00000008

Definition at line 907 of file tg3.h.

SG_DIG_MAC_ACK_STATUS

#define SG_DIG_MAC_ACK_STATUS   0x00000004

Definition at line 908 of file tg3.h.

SG_DIG_AUTONEG_COMPLETE

#define SG_DIG_AUTONEG_COMPLETE   0x00000002

Definition at line 909 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SG_DIG_AUTONEG_ERROR

#define SG_DIG_AUTONEG_ERROR   0x00000001

Definition at line 910 of file tg3.h.

MAC_TX_MAC_STATE_BASE

#define MAC_TX_MAC_STATE_BASE   0x00000600 /* 16 bytes */

Definition at line 912 of file tg3.h.

MAC_RX_MAC_STATE_BASE

#define MAC_RX_MAC_STATE_BASE   0x00000610 /* 20 bytes */

Definition at line 913 of file tg3.h.

MAC_RSS_INDIR_TBL_0

#define MAC_RSS_INDIR_TBL_0   0x00000630

Definition at line 916 of file tg3.h.

MAC_RSS_HASH_KEY_0

#define MAC_RSS_HASH_KEY_0   0x00000670

Definition at line 918 of file tg3.h.

MAC_RSS_HASH_KEY_1

#define MAC_RSS_HASH_KEY_1   0x00000674

Definition at line 919 of file tg3.h.

MAC_RSS_HASH_KEY_2

#define MAC_RSS_HASH_KEY_2   0x00000678

Definition at line 920 of file tg3.h.

MAC_RSS_HASH_KEY_3

#define MAC_RSS_HASH_KEY_3   0x0000067c

Definition at line 921 of file tg3.h.

MAC_RSS_HASH_KEY_4

#define MAC_RSS_HASH_KEY_4   0x00000680

Definition at line 922 of file tg3.h.

MAC_RSS_HASH_KEY_5

#define MAC_RSS_HASH_KEY_5   0x00000684

Definition at line 923 of file tg3.h.

MAC_RSS_HASH_KEY_6

#define MAC_RSS_HASH_KEY_6   0x00000688

Definition at line 924 of file tg3.h.

MAC_RSS_HASH_KEY_7

#define MAC_RSS_HASH_KEY_7   0x0000068c

Definition at line 925 of file tg3.h.

MAC_RSS_HASH_KEY_8

#define MAC_RSS_HASH_KEY_8   0x00000690

Definition at line 926 of file tg3.h.

MAC_RSS_HASH_KEY_9

#define MAC_RSS_HASH_KEY_9   0x00000694

Definition at line 927 of file tg3.h.

MAC_TX_STATS_OCTETS

#define MAC_TX_STATS_OCTETS   0x00000800

Definition at line 930 of file tg3.h.

MAC_TX_STATS_RESV1

#define MAC_TX_STATS_RESV1   0x00000804

Definition at line 931 of file tg3.h.

MAC_TX_STATS_COLLISIONS

#define MAC_TX_STATS_COLLISIONS   0x00000808

Definition at line 932 of file tg3.h.

MAC_TX_STATS_XON_SENT

#define MAC_TX_STATS_XON_SENT   0x0000080c

Definition at line 933 of file tg3.h.

MAC_TX_STATS_XOFF_SENT

#define MAC_TX_STATS_XOFF_SENT   0x00000810

Definition at line 934 of file tg3.h.

MAC_TX_STATS_RESV2

#define MAC_TX_STATS_RESV2   0x00000814

Definition at line 935 of file tg3.h.

MAC_TX_STATS_MAC_ERRORS

#define MAC_TX_STATS_MAC_ERRORS   0x00000818

Definition at line 936 of file tg3.h.

MAC_TX_STATS_SINGLE_COLLISIONS

#define MAC_TX_STATS_SINGLE_COLLISIONS   0x0000081c

Definition at line 937 of file tg3.h.

MAC_TX_STATS_MULT_COLLISIONS

#define MAC_TX_STATS_MULT_COLLISIONS   0x00000820

Definition at line 938 of file tg3.h.

MAC_TX_STATS_DEFERRED

#define MAC_TX_STATS_DEFERRED   0x00000824

Definition at line 939 of file tg3.h.

MAC_TX_STATS_RESV3

#define MAC_TX_STATS_RESV3   0x00000828

Definition at line 940 of file tg3.h.

MAC_TX_STATS_EXCESSIVE_COL

#define MAC_TX_STATS_EXCESSIVE_COL   0x0000082c

Definition at line 941 of file tg3.h.

MAC_TX_STATS_LATE_COL

#define MAC_TX_STATS_LATE_COL   0x00000830

Definition at line 942 of file tg3.h.

MAC_TX_STATS_RESV4_1

#define MAC_TX_STATS_RESV4_1   0x00000834

Definition at line 943 of file tg3.h.

MAC_TX_STATS_RESV4_2

#define MAC_TX_STATS_RESV4_2   0x00000838

Definition at line 944 of file tg3.h.

MAC_TX_STATS_RESV4_3

#define MAC_TX_STATS_RESV4_3   0x0000083c

Definition at line 945 of file tg3.h.

MAC_TX_STATS_RESV4_4

#define MAC_TX_STATS_RESV4_4   0x00000840

Definition at line 946 of file tg3.h.

MAC_TX_STATS_RESV4_5

#define MAC_TX_STATS_RESV4_5   0x00000844

Definition at line 947 of file tg3.h.

MAC_TX_STATS_RESV4_6

#define MAC_TX_STATS_RESV4_6   0x00000848

Definition at line 948 of file tg3.h.

MAC_TX_STATS_RESV4_7

#define MAC_TX_STATS_RESV4_7   0x0000084c

Definition at line 949 of file tg3.h.

MAC_TX_STATS_RESV4_8

#define MAC_TX_STATS_RESV4_8   0x00000850

Definition at line 950 of file tg3.h.

MAC_TX_STATS_RESV4_9

#define MAC_TX_STATS_RESV4_9   0x00000854

Definition at line 951 of file tg3.h.

MAC_TX_STATS_RESV4_10

#define MAC_TX_STATS_RESV4_10   0x00000858

Definition at line 952 of file tg3.h.

MAC_TX_STATS_RESV4_11

#define MAC_TX_STATS_RESV4_11   0x0000085c

Definition at line 953 of file tg3.h.

MAC_TX_STATS_RESV4_12

#define MAC_TX_STATS_RESV4_12   0x00000860

Definition at line 954 of file tg3.h.

MAC_TX_STATS_RESV4_13

#define MAC_TX_STATS_RESV4_13   0x00000864

Definition at line 955 of file tg3.h.

MAC_TX_STATS_RESV4_14

#define MAC_TX_STATS_RESV4_14   0x00000868

Definition at line 956 of file tg3.h.

MAC_TX_STATS_UCAST

#define MAC_TX_STATS_UCAST   0x0000086c

Definition at line 957 of file tg3.h.

MAC_TX_STATS_MCAST

#define MAC_TX_STATS_MCAST   0x00000870

Definition at line 958 of file tg3.h.

MAC_TX_STATS_BCAST

#define MAC_TX_STATS_BCAST   0x00000874

Definition at line 959 of file tg3.h.

MAC_TX_STATS_RESV5_1

#define MAC_TX_STATS_RESV5_1   0x00000878

Definition at line 960 of file tg3.h.

MAC_TX_STATS_RESV5_2

#define MAC_TX_STATS_RESV5_2   0x0000087c

Definition at line 961 of file tg3.h.

MAC_RX_STATS_OCTETS

#define MAC_RX_STATS_OCTETS   0x00000880

Definition at line 962 of file tg3.h.

MAC_RX_STATS_RESV1

#define MAC_RX_STATS_RESV1   0x00000884

Definition at line 963 of file tg3.h.

MAC_RX_STATS_FRAGMENTS

#define MAC_RX_STATS_FRAGMENTS   0x00000888

Definition at line 964 of file tg3.h.

MAC_RX_STATS_UCAST

#define MAC_RX_STATS_UCAST   0x0000088c

Definition at line 965 of file tg3.h.

MAC_RX_STATS_MCAST

#define MAC_RX_STATS_MCAST   0x00000890

Definition at line 966 of file tg3.h.

MAC_RX_STATS_BCAST

#define MAC_RX_STATS_BCAST   0x00000894

Definition at line 967 of file tg3.h.

MAC_RX_STATS_FCS_ERRORS

#define MAC_RX_STATS_FCS_ERRORS   0x00000898

Definition at line 968 of file tg3.h.

MAC_RX_STATS_ALIGN_ERRORS

#define MAC_RX_STATS_ALIGN_ERRORS   0x0000089c

Definition at line 969 of file tg3.h.

MAC_RX_STATS_XON_PAUSE_RECVD

#define MAC_RX_STATS_XON_PAUSE_RECVD   0x000008a0

Definition at line 970 of file tg3.h.

MAC_RX_STATS_XOFF_PAUSE_RECVD

#define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4

Definition at line 971 of file tg3.h.

MAC_RX_STATS_MAC_CTRL_RECVD

#define MAC_RX_STATS_MAC_CTRL_RECVD   0x000008a8

Definition at line 972 of file tg3.h.

MAC_RX_STATS_XOFF_ENTERED

#define MAC_RX_STATS_XOFF_ENTERED   0x000008ac

Definition at line 973 of file tg3.h.

MAC_RX_STATS_FRAME_TOO_LONG

#define MAC_RX_STATS_FRAME_TOO_LONG   0x000008b0

Definition at line 974 of file tg3.h.

MAC_RX_STATS_JABBERS

#define MAC_RX_STATS_JABBERS   0x000008b4

Definition at line 975 of file tg3.h.

MAC_RX_STATS_UNDERSIZE

#define MAC_RX_STATS_UNDERSIZE   0x000008b8

Definition at line 976 of file tg3.h.

SNDDATAI_MODE

#define SNDDATAI_MODE   0x00000c00

Definition at line 980 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDDATAI_MODE_RESET

#define SNDDATAI_MODE_RESET   0x00000001

Definition at line 981 of file tg3.h.

SNDDATAI_MODE_ENABLE

#define SNDDATAI_MODE_ENABLE   0x00000002

Definition at line 982 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDDATAI_MODE_STAT_OFLOW_ENAB

#define SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004

Definition at line 983 of file tg3.h.

SNDDATAI_STATUS

#define SNDDATAI_STATUS   0x00000c04

Definition at line 984 of file tg3.h.

SNDDATAI_STATUS_STAT_OFLOW

#define SNDDATAI_STATUS_STAT_OFLOW   0x00000004

Definition at line 985 of file tg3.h.

SNDDATAI_STATSCTRL

#define SNDDATAI_STATSCTRL   0x00000c08

Definition at line 986 of file tg3.h.

Referenced by tg3_reset_hw().

SNDDATAI_SCTRL_ENABLE

#define SNDDATAI_SCTRL_ENABLE   0x00000001

Definition at line 987 of file tg3.h.

Referenced by tg3_reset_hw().

SNDDATAI_SCTRL_FASTUPD

#define SNDDATAI_SCTRL_FASTUPD   0x00000002

Definition at line 988 of file tg3.h.

Referenced by tg3_reset_hw().

SNDDATAI_SCTRL_CLEAR

#define SNDDATAI_SCTRL_CLEAR   0x00000004

Definition at line 989 of file tg3.h.

SNDDATAI_SCTRL_FLUSH

#define SNDDATAI_SCTRL_FLUSH   0x00000008

Definition at line 990 of file tg3.h.

SNDDATAI_SCTRL_FORCE_ZERO

#define SNDDATAI_SCTRL_FORCE_ZERO   0x00000010

Definition at line 991 of file tg3.h.

SNDDATAI_STATSENAB

#define SNDDATAI_STATSENAB   0x00000c0c

Definition at line 992 of file tg3.h.

Referenced by tg3_reset_hw().

SNDDATAI_STATSINCMASK

#define SNDDATAI_STATSINCMASK   0x00000c10

Definition at line 993 of file tg3.h.

ISO_PKT_TX

#define ISO_PKT_TX   0x00000c20

Definition at line 994 of file tg3.h.

Referenced by tg3_reset_hw().

SNDDATAI_COS_CNT_0

#define SNDDATAI_COS_CNT_0   0x00000c80

Definition at line 996 of file tg3.h.

SNDDATAI_COS_CNT_1

#define SNDDATAI_COS_CNT_1   0x00000c84

Definition at line 997 of file tg3.h.

SNDDATAI_COS_CNT_2

#define SNDDATAI_COS_CNT_2   0x00000c88

Definition at line 998 of file tg3.h.

SNDDATAI_COS_CNT_3

#define SNDDATAI_COS_CNT_3   0x00000c8c

Definition at line 999 of file tg3.h.

SNDDATAI_COS_CNT_4

#define SNDDATAI_COS_CNT_4   0x00000c90

Definition at line 1000 of file tg3.h.

SNDDATAI_COS_CNT_5

#define SNDDATAI_COS_CNT_5   0x00000c94

Definition at line 1001 of file tg3.h.

SNDDATAI_COS_CNT_6

#define SNDDATAI_COS_CNT_6   0x00000c98

Definition at line 1002 of file tg3.h.

SNDDATAI_COS_CNT_7

#define SNDDATAI_COS_CNT_7   0x00000c9c

Definition at line 1003 of file tg3.h.

SNDDATAI_COS_CNT_8

#define SNDDATAI_COS_CNT_8   0x00000ca0

Definition at line 1004 of file tg3.h.

SNDDATAI_COS_CNT_9

#define SNDDATAI_COS_CNT_9   0x00000ca4

Definition at line 1005 of file tg3.h.

SNDDATAI_COS_CNT_10

#define SNDDATAI_COS_CNT_10   0x00000ca8

Definition at line 1006 of file tg3.h.

SNDDATAI_COS_CNT_11

#define SNDDATAI_COS_CNT_11   0x00000cac

Definition at line 1007 of file tg3.h.

SNDDATAI_COS_CNT_12

#define SNDDATAI_COS_CNT_12   0x00000cb0

Definition at line 1008 of file tg3.h.

SNDDATAI_COS_CNT_13

#define SNDDATAI_COS_CNT_13   0x00000cb4

Definition at line 1009 of file tg3.h.

SNDDATAI_COS_CNT_14

#define SNDDATAI_COS_CNT_14   0x00000cb8

Definition at line 1010 of file tg3.h.

SNDDATAI_COS_CNT_15

#define SNDDATAI_COS_CNT_15   0x00000cbc

Definition at line 1011 of file tg3.h.

SNDDATAI_DMA_RDQ_FULL_CNT

#define SNDDATAI_DMA_RDQ_FULL_CNT   0x00000cc0

Definition at line 1012 of file tg3.h.

SNDDATAI_DMA_PRIO_RDQ_FULL_CNT

#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT   0x00000cc4

Definition at line 1013 of file tg3.h.

SNDDATAI_SDCQ_FULL_CNT

#define SNDDATAI_SDCQ_FULL_CNT   0x00000cc8

Definition at line 1014 of file tg3.h.

SNDDATAI_NICRNG_SSND_PIDX_CNT

#define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc

Definition at line 1015 of file tg3.h.

SNDDATAI_STATS_UPDATED_CNT

#define SNDDATAI_STATS_UPDATED_CNT   0x00000cd0

Definition at line 1016 of file tg3.h.

SNDDATAI_INTERRUPTS_CNT

#define SNDDATAI_INTERRUPTS_CNT   0x00000cd4

Definition at line 1017 of file tg3.h.

SNDDATAI_AVOID_INTERRUPTS_CNT

#define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8

Definition at line 1018 of file tg3.h.

SNDDATAI_SND_THRESH_HIT_CNT

#define SNDDATAI_SND_THRESH_HIT_CNT   0x00000cdc

Definition at line 1019 of file tg3.h.

SNDDATAC_MODE

#define SNDDATAC_MODE   0x00001000

Definition at line 1023 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDDATAC_MODE_RESET

#define SNDDATAC_MODE_RESET   0x00000001

Definition at line 1024 of file tg3.h.

SNDDATAC_MODE_ENABLE

#define SNDDATAC_MODE_ENABLE   0x00000002

Definition at line 1025 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDDATAC_MODE_CDELAY

#define SNDDATAC_MODE_CDELAY   0x00000010

Definition at line 1026 of file tg3.h.

Referenced by tg3_reset_hw().

SNDBDS_MODE

#define SNDBDS_MODE   0x00001400

Definition at line 1030 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDS_MODE_RESET

#define SNDBDS_MODE_RESET   0x00000001

Definition at line 1031 of file tg3.h.

SNDBDS_MODE_ENABLE

#define SNDBDS_MODE_ENABLE   0x00000002

Definition at line 1032 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDS_MODE_ATTN_ENABLE

#define SNDBDS_MODE_ATTN_ENABLE   0x00000004

Definition at line 1033 of file tg3.h.

Referenced by tg3_reset_hw().

SNDBDS_STATUS

#define SNDBDS_STATUS   0x00001404

Definition at line 1034 of file tg3.h.

SNDBDS_STATUS_ERROR_ATTN

#define SNDBDS_STATUS_ERROR_ATTN   0x00000004

Definition at line 1035 of file tg3.h.

SNDBDS_HWDIAG

#define SNDBDS_HWDIAG   0x00001408

Definition at line 1036 of file tg3.h.

SNDBDS_SEL_CON_IDX_0

#define SNDBDS_SEL_CON_IDX_0   0x00001440

Definition at line 1038 of file tg3.h.

SNDBDS_SEL_CON_IDX_1

#define SNDBDS_SEL_CON_IDX_1   0x00001444

Definition at line 1039 of file tg3.h.

SNDBDS_SEL_CON_IDX_2

#define SNDBDS_SEL_CON_IDX_2   0x00001448

Definition at line 1040 of file tg3.h.

SNDBDS_SEL_CON_IDX_3

#define SNDBDS_SEL_CON_IDX_3   0x0000144c

Definition at line 1041 of file tg3.h.

SNDBDS_SEL_CON_IDX_4

#define SNDBDS_SEL_CON_IDX_4   0x00001450

Definition at line 1042 of file tg3.h.

SNDBDS_SEL_CON_IDX_5

#define SNDBDS_SEL_CON_IDX_5   0x00001454

Definition at line 1043 of file tg3.h.

SNDBDS_SEL_CON_IDX_6

#define SNDBDS_SEL_CON_IDX_6   0x00001458

Definition at line 1044 of file tg3.h.

SNDBDS_SEL_CON_IDX_7

#define SNDBDS_SEL_CON_IDX_7   0x0000145c

Definition at line 1045 of file tg3.h.

SNDBDS_SEL_CON_IDX_8

#define SNDBDS_SEL_CON_IDX_8   0x00001460

Definition at line 1046 of file tg3.h.

SNDBDS_SEL_CON_IDX_9

#define SNDBDS_SEL_CON_IDX_9   0x00001464

Definition at line 1047 of file tg3.h.

SNDBDS_SEL_CON_IDX_10

#define SNDBDS_SEL_CON_IDX_10   0x00001468

Definition at line 1048 of file tg3.h.

SNDBDS_SEL_CON_IDX_11

#define SNDBDS_SEL_CON_IDX_11   0x0000146c

Definition at line 1049 of file tg3.h.

SNDBDS_SEL_CON_IDX_12

#define SNDBDS_SEL_CON_IDX_12   0x00001470

Definition at line 1050 of file tg3.h.

SNDBDS_SEL_CON_IDX_13

#define SNDBDS_SEL_CON_IDX_13   0x00001474

Definition at line 1051 of file tg3.h.

SNDBDS_SEL_CON_IDX_14

#define SNDBDS_SEL_CON_IDX_14   0x00001478

Definition at line 1052 of file tg3.h.

SNDBDS_SEL_CON_IDX_15

#define SNDBDS_SEL_CON_IDX_15   0x0000147c

Definition at line 1053 of file tg3.h.

SNDBDI_MODE

#define SNDBDI_MODE   0x00001800

Definition at line 1057 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDI_MODE_RESET

#define SNDBDI_MODE_RESET   0x00000001

Definition at line 1058 of file tg3.h.

SNDBDI_MODE_ENABLE

#define SNDBDI_MODE_ENABLE   0x00000002

Definition at line 1059 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDI_MODE_ATTN_ENABLE

#define SNDBDI_MODE_ATTN_ENABLE   0x00000004

Definition at line 1060 of file tg3.h.

Referenced by tg3_reset_hw().

SNDBDI_MODE_MULTI_TXQ_EN

#define SNDBDI_MODE_MULTI_TXQ_EN   0x00000020

Definition at line 1061 of file tg3.h.

Referenced by tg3_reset_hw().

SNDBDI_STATUS

#define SNDBDI_STATUS   0x00001804

Definition at line 1062 of file tg3.h.

SNDBDI_STATUS_ERROR_ATTN

#define SNDBDI_STATUS_ERROR_ATTN   0x00000004

Definition at line 1063 of file tg3.h.

SNDBDI_IN_PROD_IDX_0

#define SNDBDI_IN_PROD_IDX_0   0x00001808

Definition at line 1064 of file tg3.h.

SNDBDI_IN_PROD_IDX_1

#define SNDBDI_IN_PROD_IDX_1   0x0000180c

Definition at line 1065 of file tg3.h.

SNDBDI_IN_PROD_IDX_2

#define SNDBDI_IN_PROD_IDX_2   0x00001810

Definition at line 1066 of file tg3.h.

SNDBDI_IN_PROD_IDX_3

#define SNDBDI_IN_PROD_IDX_3   0x00001814

Definition at line 1067 of file tg3.h.

SNDBDI_IN_PROD_IDX_4

#define SNDBDI_IN_PROD_IDX_4   0x00001818

Definition at line 1068 of file tg3.h.

SNDBDI_IN_PROD_IDX_5

#define SNDBDI_IN_PROD_IDX_5   0x0000181c

Definition at line 1069 of file tg3.h.

SNDBDI_IN_PROD_IDX_6

#define SNDBDI_IN_PROD_IDX_6   0x00001820

Definition at line 1070 of file tg3.h.

SNDBDI_IN_PROD_IDX_7

#define SNDBDI_IN_PROD_IDX_7   0x00001824

Definition at line 1071 of file tg3.h.

SNDBDI_IN_PROD_IDX_8

#define SNDBDI_IN_PROD_IDX_8   0x00001828

Definition at line 1072 of file tg3.h.

SNDBDI_IN_PROD_IDX_9

#define SNDBDI_IN_PROD_IDX_9   0x0000182c

Definition at line 1073 of file tg3.h.

SNDBDI_IN_PROD_IDX_10

#define SNDBDI_IN_PROD_IDX_10   0x00001830

Definition at line 1074 of file tg3.h.

SNDBDI_IN_PROD_IDX_11

#define SNDBDI_IN_PROD_IDX_11   0x00001834

Definition at line 1075 of file tg3.h.

SNDBDI_IN_PROD_IDX_12

#define SNDBDI_IN_PROD_IDX_12   0x00001838

Definition at line 1076 of file tg3.h.

SNDBDI_IN_PROD_IDX_13

#define SNDBDI_IN_PROD_IDX_13   0x0000183c

Definition at line 1077 of file tg3.h.

SNDBDI_IN_PROD_IDX_14

#define SNDBDI_IN_PROD_IDX_14   0x00001840

Definition at line 1078 of file tg3.h.

SNDBDI_IN_PROD_IDX_15

#define SNDBDI_IN_PROD_IDX_15   0x00001844

Definition at line 1079 of file tg3.h.

SNDBDC_MODE

#define SNDBDC_MODE   0x00001c00

Definition at line 1083 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDC_MODE_RESET

#define SNDBDC_MODE_RESET   0x00000001

Definition at line 1084 of file tg3.h.

SNDBDC_MODE_ENABLE

#define SNDBDC_MODE_ENABLE   0x00000002

Definition at line 1085 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

SNDBDC_MODE_ATTN_ENABLE

#define SNDBDC_MODE_ATTN_ENABLE   0x00000004

Definition at line 1086 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_MODE

#define RCVLPC_MODE   0x00002000

Definition at line 1090 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVLPC_MODE_RESET

#define RCVLPC_MODE_RESET   0x00000001

Definition at line 1091 of file tg3.h.

RCVLPC_MODE_ENABLE

#define RCVLPC_MODE_ENABLE   0x00000002

Definition at line 1092 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVLPC_MODE_CLASS0_ATTN_ENAB

#define RCVLPC_MODE_CLASS0_ATTN_ENAB   0x00000004

Definition at line 1093 of file tg3.h.

RCVLPC_MODE_MAPOOR_AATTN_ENAB

#define RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008

Definition at line 1094 of file tg3.h.

RCVLPC_MODE_STAT_OFLOW_ENAB

#define RCVLPC_MODE_STAT_OFLOW_ENAB   0x00000010

Definition at line 1095 of file tg3.h.

RCVLPC_STATUS

#define RCVLPC_STATUS   0x00002004

Definition at line 1096 of file tg3.h.

RCVLPC_STATUS_CLASS0

#define RCVLPC_STATUS_CLASS0   0x00000004

Definition at line 1097 of file tg3.h.

RCVLPC_STATUS_MAPOOR

#define RCVLPC_STATUS_MAPOOR   0x00000008

Definition at line 1098 of file tg3.h.

RCVLPC_STATUS_STAT_OFLOW

#define RCVLPC_STATUS_STAT_OFLOW   0x00000010

Definition at line 1099 of file tg3.h.

RCVLPC_LOCK

#define RCVLPC_LOCK   0x00002008

Definition at line 1100 of file tg3.h.

RCVLPC_LOCK_REQ_MASK

#define RCVLPC_LOCK_REQ_MASK   0x0000ffff

Definition at line 1101 of file tg3.h.

RCVLPC_LOCK_REQ_SHIFT

#define RCVLPC_LOCK_REQ_SHIFT   0

Definition at line 1102 of file tg3.h.

RCVLPC_LOCK_GRANT_MASK

#define RCVLPC_LOCK_GRANT_MASK   0xffff0000

Definition at line 1103 of file tg3.h.

RCVLPC_LOCK_GRANT_SHIFT

#define RCVLPC_LOCK_GRANT_SHIFT   16

Definition at line 1104 of file tg3.h.

RCVLPC_NON_EMPTY_BITS

#define RCVLPC_NON_EMPTY_BITS   0x0000200c

Definition at line 1105 of file tg3.h.

RCVLPC_NON_EMPTY_BITS_MASK

#define RCVLPC_NON_EMPTY_BITS_MASK   0x0000ffff

Definition at line 1106 of file tg3.h.

RCVLPC_CONFIG

#define RCVLPC_CONFIG   0x00002010

Definition at line 1107 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATSCTRL

#define RCVLPC_STATSCTRL   0x00002014

Definition at line 1108 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATSCTRL_ENABLE

#define RCVLPC_STATSCTRL_ENABLE   0x00000001

Definition at line 1109 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATSCTRL_FASTUPD

#define RCVLPC_STATSCTRL_FASTUPD   0x00000002

Definition at line 1110 of file tg3.h.

RCVLPC_STATS_ENABLE

#define RCVLPC_STATS_ENABLE   0x00002018

Definition at line 1111 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATSENAB_ASF_FIX

#define RCVLPC_STATSENAB_ASF_FIX   0x00000002

Definition at line 1112 of file tg3.h.

RCVLPC_STATSENAB_DACK_FIX

#define RCVLPC_STATSENAB_DACK_FIX   0x00040000

Definition at line 1113 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATSENAB_LNGBRST_RFIX

#define RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000

Definition at line 1114 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLPC_STATS_INCMASK

#define RCVLPC_STATS_INCMASK   0x0000201c

Definition at line 1115 of file tg3.h.

RCVLPC_SELLST_BASE

#define RCVLPC_SELLST_BASE   0x00002100 /* 16 16-byte entries */

Definition at line 1117 of file tg3.h.

SELLST_TAIL

#define SELLST_TAIL   0x00000004

Definition at line 1118 of file tg3.h.

SELLST_CONT

#define SELLST_CONT   0x00000008

Definition at line 1119 of file tg3.h.

SELLST_UNUSED

#define SELLST_UNUSED   0x0000000c

Definition at line 1120 of file tg3.h.

RCVLPC_COS_CNTL_BASE

#define RCVLPC_COS_CNTL_BASE   0x00002200 /* 16 4-byte entries */

Definition at line 1121 of file tg3.h.

RCVLPC_DROP_FILTER_CNT

#define RCVLPC_DROP_FILTER_CNT   0x00002240

Definition at line 1122 of file tg3.h.

RCVLPC_DMA_WQ_FULL_CNT

#define RCVLPC_DMA_WQ_FULL_CNT   0x00002244

Definition at line 1123 of file tg3.h.

RCVLPC_DMA_HIPRIO_WQ_FULL_CNT

#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248

Definition at line 1124 of file tg3.h.

RCVLPC_NO_RCV_BD_CNT

#define RCVLPC_NO_RCV_BD_CNT   0x0000224c

Definition at line 1125 of file tg3.h.

RCVLPC_IN_DISCARDS_CNT

#define RCVLPC_IN_DISCARDS_CNT   0x00002250

Definition at line 1126 of file tg3.h.

RCVLPC_IN_ERRORS_CNT

#define RCVLPC_IN_ERRORS_CNT   0x00002254

Definition at line 1127 of file tg3.h.

RCVLPC_RCV_THRESH_HIT_CNT

#define RCVLPC_RCV_THRESH_HIT_CNT   0x00002258

Definition at line 1128 of file tg3.h.

RCVDBDI_MODE

#define RCVDBDI_MODE   0x00002400

Definition at line 1132 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVDBDI_MODE_RESET

#define RCVDBDI_MODE_RESET   0x00000001

Definition at line 1133 of file tg3.h.

RCVDBDI_MODE_ENABLE

#define RCVDBDI_MODE_ENABLE   0x00000002

Definition at line 1134 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVDBDI_MODE_JUMBOBD_NEEDED

#define RCVDBDI_MODE_JUMBOBD_NEEDED   0x00000004

Definition at line 1135 of file tg3.h.

RCVDBDI_MODE_FRM_TOO_BIG

#define RCVDBDI_MODE_FRM_TOO_BIG   0x00000008

Definition at line 1136 of file tg3.h.

RCVDBDI_MODE_INV_RING_SZ

#define RCVDBDI_MODE_INV_RING_SZ   0x00000010

Definition at line 1137 of file tg3.h.

Referenced by tg3_reset_hw().

RCVDBDI_MODE_LRG_RING_SZ

#define RCVDBDI_MODE_LRG_RING_SZ   0x00010000

Definition at line 1138 of file tg3.h.

Referenced by tg3_reset_hw().

RCVDBDI_STATUS

#define RCVDBDI_STATUS   0x00002404

Definition at line 1139 of file tg3.h.

RCVDBDI_STATUS_JUMBOBD_NEEDED

#define RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004

Definition at line 1140 of file tg3.h.

RCVDBDI_STATUS_FRM_TOO_BIG

#define RCVDBDI_STATUS_FRM_TOO_BIG   0x00000008

Definition at line 1141 of file tg3.h.

RCVDBDI_STATUS_INV_RING_SZ

#define RCVDBDI_STATUS_INV_RING_SZ   0x00000010

Definition at line 1142 of file tg3.h.

RCVDBDI_SPLIT_FRAME_MINSZ

#define RCVDBDI_SPLIT_FRAME_MINSZ   0x00002408

Definition at line 1143 of file tg3.h.

RCVDBDI_JUMBO_BD

#define RCVDBDI_JUMBO_BD   0x00002440 /* TG3_BDINFO_... */

Definition at line 1145 of file tg3.h.

RCVDBDI_STD_BD

#define RCVDBDI_STD_BD   0x00002450 /* TG3_BDINFO_... */

Definition at line 1146 of file tg3.h.

Referenced by tg3_reset_hw().

RCVDBDI_MINI_BD

#define RCVDBDI_MINI_BD   0x00002460 /* TG3_BDINFO_... */

Definition at line 1147 of file tg3.h.

Referenced by tg3_reset_hw().

RCVDBDI_JUMBO_CON_IDX

#define RCVDBDI_JUMBO_CON_IDX   0x00002470

Definition at line 1148 of file tg3.h.

RCVDBDI_STD_CON_IDX

#define RCVDBDI_STD_CON_IDX   0x00002474

Definition at line 1149 of file tg3.h.

RCVDBDI_MINI_CON_IDX

#define RCVDBDI_MINI_CON_IDX   0x00002478

Definition at line 1150 of file tg3.h.

RCVDBDI_BD_PROD_IDX_0

#define RCVDBDI_BD_PROD_IDX_0   0x00002480

Definition at line 1152 of file tg3.h.

RCVDBDI_BD_PROD_IDX_1

#define RCVDBDI_BD_PROD_IDX_1   0x00002484

Definition at line 1153 of file tg3.h.

RCVDBDI_BD_PROD_IDX_2

#define RCVDBDI_BD_PROD_IDX_2   0x00002488

Definition at line 1154 of file tg3.h.

RCVDBDI_BD_PROD_IDX_3

#define RCVDBDI_BD_PROD_IDX_3   0x0000248c

Definition at line 1155 of file tg3.h.

RCVDBDI_BD_PROD_IDX_4

#define RCVDBDI_BD_PROD_IDX_4   0x00002490

Definition at line 1156 of file tg3.h.

RCVDBDI_BD_PROD_IDX_5

#define RCVDBDI_BD_PROD_IDX_5   0x00002494

Definition at line 1157 of file tg3.h.

RCVDBDI_BD_PROD_IDX_6

#define RCVDBDI_BD_PROD_IDX_6   0x00002498

Definition at line 1158 of file tg3.h.

RCVDBDI_BD_PROD_IDX_7

#define RCVDBDI_BD_PROD_IDX_7   0x0000249c

Definition at line 1159 of file tg3.h.

RCVDBDI_BD_PROD_IDX_8

#define RCVDBDI_BD_PROD_IDX_8   0x000024a0

Definition at line 1160 of file tg3.h.

RCVDBDI_BD_PROD_IDX_9

#define RCVDBDI_BD_PROD_IDX_9   0x000024a4

Definition at line 1161 of file tg3.h.

RCVDBDI_BD_PROD_IDX_10

#define RCVDBDI_BD_PROD_IDX_10   0x000024a8

Definition at line 1162 of file tg3.h.

RCVDBDI_BD_PROD_IDX_11

#define RCVDBDI_BD_PROD_IDX_11   0x000024ac

Definition at line 1163 of file tg3.h.

RCVDBDI_BD_PROD_IDX_12

#define RCVDBDI_BD_PROD_IDX_12   0x000024b0

Definition at line 1164 of file tg3.h.

RCVDBDI_BD_PROD_IDX_13

#define RCVDBDI_BD_PROD_IDX_13   0x000024b4

Definition at line 1165 of file tg3.h.

RCVDBDI_BD_PROD_IDX_14

#define RCVDBDI_BD_PROD_IDX_14   0x000024b8

Definition at line 1166 of file tg3.h.

RCVDBDI_BD_PROD_IDX_15

#define RCVDBDI_BD_PROD_IDX_15   0x000024bc

Definition at line 1167 of file tg3.h.

RCVDBDI_HWDIAG

#define RCVDBDI_HWDIAG   0x000024c0

Definition at line 1168 of file tg3.h.

RCVDCC_MODE

#define RCVDCC_MODE   0x00002800

Definition at line 1172 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVDCC_MODE_RESET

#define RCVDCC_MODE_RESET   0x00000001

Definition at line 1173 of file tg3.h.

RCVDCC_MODE_ENABLE

#define RCVDCC_MODE_ENABLE   0x00000002

Definition at line 1174 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVDCC_MODE_ATTN_ENABLE

#define RCVDCC_MODE_ATTN_ENABLE   0x00000004

Definition at line 1175 of file tg3.h.

Referenced by tg3_reset_hw().

RCVBDI_MODE

#define RCVBDI_MODE   0x00002c00

Definition at line 1179 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVBDI_MODE_RESET

#define RCVBDI_MODE_RESET   0x00000001

Definition at line 1180 of file tg3.h.

RCVBDI_MODE_ENABLE

#define RCVBDI_MODE_ENABLE   0x00000002

Definition at line 1181 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVBDI_MODE_RCB_ATTN_ENAB

#define RCVBDI_MODE_RCB_ATTN_ENAB   0x00000004

Definition at line 1182 of file tg3.h.

Referenced by tg3_reset_hw().

RCVBDI_STATUS

#define RCVBDI_STATUS   0x00002c04

Definition at line 1183 of file tg3.h.

RCVBDI_STATUS_RCB_ATTN

#define RCVBDI_STATUS_RCB_ATTN   0x00000004

Definition at line 1184 of file tg3.h.

RCVBDI_JUMBO_PROD_IDX

#define RCVBDI_JUMBO_PROD_IDX   0x00002c08

Definition at line 1185 of file tg3.h.

RCVBDI_STD_PROD_IDX

#define RCVBDI_STD_PROD_IDX   0x00002c0c

Definition at line 1186 of file tg3.h.

RCVBDI_MINI_PROD_IDX

#define RCVBDI_MINI_PROD_IDX   0x00002c10

Definition at line 1187 of file tg3.h.

RCVBDI_MINI_THRESH

#define RCVBDI_MINI_THRESH   0x00002c14

Definition at line 1188 of file tg3.h.

RCVBDI_STD_THRESH

#define RCVBDI_STD_THRESH   0x00002c18

Definition at line 1189 of file tg3.h.

Referenced by tg3_setup_rxbd_thresholds().

RCVBDI_JUMBO_THRESH

#define RCVBDI_JUMBO_THRESH   0x00002c1c

Definition at line 1190 of file tg3.h.

STD_REPLENISH_LWM

#define STD_REPLENISH_LWM   0x00002d00

Definition at line 1193 of file tg3.h.

Referenced by tg3_setup_rxbd_thresholds().

JMB_REPLENISH_LWM

#define JMB_REPLENISH_LWM   0x00002d04

Definition at line 1194 of file tg3.h.

RCVCC_MODE

#define RCVCC_MODE   0x00003000

Definition at line 1198 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVCC_MODE_RESET

#define RCVCC_MODE_RESET   0x00000001

Definition at line 1199 of file tg3.h.

RCVCC_MODE_ENABLE

#define RCVCC_MODE_ENABLE   0x00000002

Definition at line 1200 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVCC_MODE_ATTN_ENABLE

#define RCVCC_MODE_ATTN_ENABLE   0x00000004

Definition at line 1201 of file tg3.h.

Referenced by tg3_reset_hw().

RCVCC_STATUS

#define RCVCC_STATUS   0x00003004

Definition at line 1202 of file tg3.h.

RCVCC_STATUS_ERROR_ATTN

#define RCVCC_STATUS_ERROR_ATTN   0x00000004

Definition at line 1203 of file tg3.h.

RCVCC_JUMP_PROD_IDX

#define RCVCC_JUMP_PROD_IDX   0x00003008

Definition at line 1204 of file tg3.h.

RCVCC_STD_PROD_IDX

#define RCVCC_STD_PROD_IDX   0x0000300c

Definition at line 1205 of file tg3.h.

RCVCC_MINI_PROD_IDX

#define RCVCC_MINI_PROD_IDX   0x00003010

Definition at line 1206 of file tg3.h.

RCVLSC_MODE

#define RCVLSC_MODE   0x00003400

Definition at line 1210 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_reset_hw(), and tg3_stop_block().

RCVLSC_MODE_RESET

#define RCVLSC_MODE_RESET   0x00000001

Definition at line 1211 of file tg3.h.

RCVLSC_MODE_ENABLE

#define RCVLSC_MODE_ENABLE   0x00000002

Definition at line 1212 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

RCVLSC_MODE_ATTN_ENABLE

#define RCVLSC_MODE_ATTN_ENABLE   0x00000004

Definition at line 1213 of file tg3.h.

Referenced by tg3_reset_hw().

RCVLSC_STATUS

#define RCVLSC_STATUS   0x00003404

Definition at line 1214 of file tg3.h.

RCVLSC_STATUS_ERROR_ATTN

#define RCVLSC_STATUS_ERROR_ATTN   0x00000004

Definition at line 1215 of file tg3.h.

TG3_CPMU_CTRL

#define TG3_CPMU_CTRL   0x00003600

Definition at line 1219 of file tg3.h.

Referenced by tg3_phy_reset().

CPMU_CTRL_LINK_IDLE_MODE

#define CPMU_CTRL_LINK_IDLE_MODE   0x00000200

Definition at line 1220 of file tg3.h.

CPMU_CTRL_LINK_AWARE_MODE

#define CPMU_CTRL_LINK_AWARE_MODE   0x00000400

Definition at line 1221 of file tg3.h.

CPMU_CTRL_LINK_SPEED_MODE

#define CPMU_CTRL_LINK_SPEED_MODE   0x00004000

Definition at line 1222 of file tg3.h.

CPMU_CTRL_GPHY_10MB_RXONLY

#define CPMU_CTRL_GPHY_10MB_RXONLY   0x00010000

Definition at line 1223 of file tg3.h.

Referenced by tg3_phy_reset().

TG3_CPMU_LSPD_10MB_CLK

#define TG3_CPMU_LSPD_10MB_CLK   0x00003604

Definition at line 1224 of file tg3.h.

Referenced by tg3_reset_hw().

CPMU_LSPD_10MB_MACCLK_MASK

#define CPMU_LSPD_10MB_MACCLK_MASK   0x001f0000

Definition at line 1225 of file tg3.h.

Referenced by tg3_reset_hw().

CPMU_LSPD_10MB_MACCLK_6_25

#define CPMU_LSPD_10MB_MACCLK_6_25   0x00130000

Definition at line 1226 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_CPMU_LSPD_1000MB_CLK

#define TG3_CPMU_LSPD_1000MB_CLK   0x0000360c

Definition at line 1229 of file tg3.h.

Referenced by tg3_phy_reset().

CPMU_LSPD_1000MB_MACCLK_62_5

#define CPMU_LSPD_1000MB_MACCLK_62_5   0x00000000

Definition at line 1230 of file tg3.h.

CPMU_LSPD_1000MB_MACCLK_12_5

#define CPMU_LSPD_1000MB_MACCLK_12_5   0x00110000

Definition at line 1231 of file tg3.h.

Referenced by tg3_phy_reset().

CPMU_LSPD_1000MB_MACCLK_MASK

#define CPMU_LSPD_1000MB_MACCLK_MASK   0x001f0000

Definition at line 1232 of file tg3.h.

Referenced by tg3_phy_reset().

TG3_CPMU_LNK_AWARE_PWRMD

#define TG3_CPMU_LNK_AWARE_PWRMD   0x00003610

Definition at line 1233 of file tg3.h.

CPMU_LNK_AWARE_MACCLK_MASK

#define CPMU_LNK_AWARE_MACCLK_MASK   0x001f0000

Definition at line 1234 of file tg3.h.

CPMU_LNK_AWARE_MACCLK_6_25

#define CPMU_LNK_AWARE_MACCLK_6_25   0x00130000

Definition at line 1235 of file tg3.h.

TG3_CPMU_D0_CLCK_POLICY

#define TG3_CPMU_D0_CLCK_POLICY   0x00003614

Definition at line 1237 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_CPMU_HST_ACC

#define TG3_CPMU_HST_ACC   0x0000361c

Definition at line 1240 of file tg3.h.

CPMU_HST_ACC_MACCLK_MASK

#define CPMU_HST_ACC_MACCLK_MASK   0x001f0000

Definition at line 1241 of file tg3.h.

CPMU_HST_ACC_MACCLK_6_25

#define CPMU_HST_ACC_MACCLK_6_25   0x00130000

Definition at line 1242 of file tg3.h.

TG3_CPMU_CLCK_ORIDE

#define TG3_CPMU_CLCK_ORIDE   0x00003624

Definition at line 1245 of file tg3.h.

Referenced by tg3_chip_reset().

CPMU_CLCK_ORIDE_MAC_ORIDE_EN

#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000

Definition at line 1246 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_CPMU_CLCK_ORIDE_EN

#define TG3_CPMU_CLCK_ORIDE_EN   0x00003628

Definition at line 1248 of file tg3.h.

Referenced by tg3_chip_reset().

CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN

#define CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN   0x00002000

Definition at line 1249 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_CPMU_CLCK_STAT

#define TG3_CPMU_CLCK_STAT   0x00003630

Definition at line 1251 of file tg3.h.

CPMU_CLCK_STAT_MAC_CLCK_MASK

#define CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000

Definition at line 1252 of file tg3.h.

CPMU_CLCK_STAT_MAC_CLCK_62_5

#define CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000

Definition at line 1253 of file tg3.h.

CPMU_CLCK_STAT_MAC_CLCK_12_5

#define CPMU_CLCK_STAT_MAC_CLCK_12_5   0x00110000

Definition at line 1254 of file tg3.h.

CPMU_CLCK_STAT_MAC_CLCK_6_25

#define CPMU_CLCK_STAT_MAC_CLCK_6_25   0x00130000

Definition at line 1255 of file tg3.h.

TG3_CPMU_MUTEX_REQ

#define TG3_CPMU_MUTEX_REQ   0x0000365c

Definition at line 1258 of file tg3.h.

CPMU_MUTEX_REQ_DRIVER

#define CPMU_MUTEX_REQ_DRIVER   0x00001000

Definition at line 1259 of file tg3.h.

TG3_CPMU_MUTEX_GNT

#define TG3_CPMU_MUTEX_GNT   0x00003660

Definition at line 1260 of file tg3.h.

CPMU_MUTEX_GNT_DRIVER

#define CPMU_MUTEX_GNT_DRIVER   0x00001000

Definition at line 1261 of file tg3.h.

TG3_CPMU_PHY_STRAP

#define TG3_CPMU_PHY_STRAP   0x00003664

Definition at line 1262 of file tg3.h.

Referenced by tg3_mdio_init().

TG3_CPMU_PHY_STRAP_IS_SERDES

#define TG3_CPMU_PHY_STRAP_IS_SERDES   0x00000020

Definition at line 1263 of file tg3.h.

Referenced by tg3_mdio_init().

TG3_CPMU_EEE_MODE

#define TG3_CPMU_EEE_MODE   0x000036b0

Definition at line 1266 of file tg3.h.

TG3_CPMU_EEEMD_APE_TX_DET_EN

#define TG3_CPMU_EEEMD_APE_TX_DET_EN   0x00000004

Definition at line 1267 of file tg3.h.

TG3_CPMU_EEEMD_ERLY_L1_XIT_DET

#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008

Definition at line 1268 of file tg3.h.

TG3_CPMU_EEEMD_SND_IDX_DET_EN

#define TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040

Definition at line 1269 of file tg3.h.

TG3_CPMU_EEEMD_LPI_ENABLE

#define TG3_CPMU_EEEMD_LPI_ENABLE   0x00000080

Definition at line 1270 of file tg3.h.

TG3_CPMU_EEEMD_LPI_IN_TX

#define TG3_CPMU_EEEMD_LPI_IN_TX   0x00000100

Definition at line 1271 of file tg3.h.

TG3_CPMU_EEEMD_LPI_IN_RX

#define TG3_CPMU_EEEMD_LPI_IN_RX   0x00000200

Definition at line 1272 of file tg3.h.

TG3_CPMU_EEEMD_EEE_ENABLE

#define TG3_CPMU_EEEMD_EEE_ENABLE   0x00100000

Definition at line 1273 of file tg3.h.

TG3_CPMU_EEE_DBTMR1

#define TG3_CPMU_EEE_DBTMR1   0x000036b4

Definition at line 1274 of file tg3.h.

TG3_CPMU_DBTMR1_PCIEXIT_2047US

#define TG3_CPMU_DBTMR1_PCIEXIT_2047US   0x07ff0000

Definition at line 1275 of file tg3.h.

TG3_CPMU_DBTMR1_LNKIDLE_2047US

#define TG3_CPMU_DBTMR1_LNKIDLE_2047US   0x000070ff

Definition at line 1276 of file tg3.h.

TG3_CPMU_EEE_DBTMR2

#define TG3_CPMU_EEE_DBTMR2   0x000036b8

Definition at line 1277 of file tg3.h.

TG3_CPMU_DBTMR2_APE_TX_2047US

#define TG3_CPMU_DBTMR2_APE_TX_2047US   0x07ff0000

Definition at line 1278 of file tg3.h.

TG3_CPMU_DBTMR2_TXIDXEQ_2047US

#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US   0x000070ff

Definition at line 1279 of file tg3.h.

TG3_CPMU_EEE_LNKIDL_CTRL

#define TG3_CPMU_EEE_LNKIDL_CTRL   0x000036bc

Definition at line 1280 of file tg3.h.

TG3_CPMU_EEE_LNKIDL_PCIE_NL0

#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000

Definition at line 1281 of file tg3.h.

TG3_CPMU_EEE_LNKIDL_UART_IDL

#define TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004

Definition at line 1282 of file tg3.h.

TG3_CPMU_EEE_CTRL

#define TG3_CPMU_EEE_CTRL   0x000036d0

Definition at line 1285 of file tg3.h.

TG3_CPMU_EEE_CTRL_EXIT_16_5_US

#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d

Definition at line 1286 of file tg3.h.

TG3_CPMU_EEE_CTRL_EXIT_36_US

#define TG3_CPMU_EEE_CTRL_EXIT_36_US   0x00000384

Definition at line 1287 of file tg3.h.

TG3_CPMU_EEE_CTRL_EXIT_20_1_US

#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8

Definition at line 1288 of file tg3.h.

MBFREE_MODE

#define MBFREE_MODE   0x00003800

Definition at line 1292 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_reset_hw(), and tg3_stop_block().

MBFREE_MODE_RESET

#define MBFREE_MODE_RESET   0x00000001

Definition at line 1293 of file tg3.h.

MBFREE_MODE_ENABLE

#define MBFREE_MODE_ENABLE   0x00000002

Definition at line 1294 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

MBFREE_STATUS

#define MBFREE_STATUS   0x00003804

Definition at line 1295 of file tg3.h.

HOSTCC_MODE

#define HOSTCC_MODE   0x00003c00

Definition at line 1299 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_enable_ints(), tg3_init_one(), and tg3_reset_hw().

HOSTCC_MODE_RESET

#define HOSTCC_MODE_RESET   0x00000001

Definition at line 1300 of file tg3.h.

HOSTCC_MODE_ENABLE

#define HOSTCC_MODE_ENABLE   0x00000002

Definition at line 1301 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_enable_ints(), tg3_init_one(), and tg3_reset_hw().

HOSTCC_MODE_ATTN

#define HOSTCC_MODE_ATTN   0x00000004

Definition at line 1302 of file tg3.h.

Referenced by tg3_get_invariants().

HOSTCC_MODE_NOW

#define HOSTCC_MODE_NOW   0x00000008

Definition at line 1303 of file tg3.h.

Referenced by tg3_init_one().

HOSTCC_MODE_FULL_STATUS

#define HOSTCC_MODE_FULL_STATUS   0x00000000

Definition at line 1304 of file tg3.h.

HOSTCC_MODE_64BYTE

#define HOSTCC_MODE_64BYTE   0x00000080

Definition at line 1305 of file tg3.h.

HOSTCC_MODE_32BYTE

#define HOSTCC_MODE_32BYTE   0x00000100

Definition at line 1306 of file tg3.h.

Referenced by tg3_get_invariants().

HOSTCC_MODE_CLRTICK_RXBD

#define HOSTCC_MODE_CLRTICK_RXBD   0x00000200

Definition at line 1307 of file tg3.h.

Referenced by tg3_get_invariants().

HOSTCC_MODE_CLRTICK_TXBD

#define HOSTCC_MODE_CLRTICK_TXBD   0x00000400

Definition at line 1308 of file tg3.h.

Referenced by tg3_get_invariants().

HOSTCC_MODE_NOINT_ON_NOW

#define HOSTCC_MODE_NOINT_ON_NOW   0x00000800

Definition at line 1309 of file tg3.h.

HOSTCC_MODE_NOINT_ON_FORCE

#define HOSTCC_MODE_NOINT_ON_FORCE   0x00001000

Definition at line 1310 of file tg3.h.

HOSTCC_MODE_COAL_VEC1_NOW

#define HOSTCC_MODE_COAL_VEC1_NOW   0x00002000

Definition at line 1311 of file tg3.h.

HOSTCC_STATUS

#define HOSTCC_STATUS   0x00003c04

Definition at line 1312 of file tg3.h.

HOSTCC_STATUS_ERROR_ATTN

#define HOSTCC_STATUS_ERROR_ATTN   0x00000004

Definition at line 1313 of file tg3.h.

HOSTCC_RXCOL_TICKS

#define HOSTCC_RXCOL_TICKS   0x00003c08

Definition at line 1314 of file tg3.h.

Referenced by __tg3_set_coalesce().

LOW_RXCOL_TICKS

#define LOW_RXCOL_TICKS   0x00000032

Definition at line 1315 of file tg3.h.

LOW_RXCOL_TICKS_CLRTCKS

#define LOW_RXCOL_TICKS_CLRTCKS   0x00000014

Definition at line 1316 of file tg3.h.

DEFAULT_RXCOL_TICKS

#define DEFAULT_RXCOL_TICKS   0x00000048

Definition at line 1317 of file tg3.h.

HIGH_RXCOL_TICKS

#define HIGH_RXCOL_TICKS   0x00000096

Definition at line 1318 of file tg3.h.

MAX_RXCOL_TICKS

#define MAX_RXCOL_TICKS   0x000003ff

Definition at line 1319 of file tg3.h.

HOSTCC_TXCOL_TICKS

#define HOSTCC_TXCOL_TICKS   0x00003c0c

Definition at line 1320 of file tg3.h.

Referenced by __tg3_set_coalesce().

LOW_TXCOL_TICKS

#define LOW_TXCOL_TICKS   0x00000096

Definition at line 1321 of file tg3.h.

Referenced by __tg3_set_coalesce().

LOW_TXCOL_TICKS_CLRTCKS

#define LOW_TXCOL_TICKS_CLRTCKS   0x00000048

Definition at line 1322 of file tg3.h.

DEFAULT_TXCOL_TICKS

#define DEFAULT_TXCOL_TICKS   0x0000012c

Definition at line 1323 of file tg3.h.

HIGH_TXCOL_TICKS

#define HIGH_TXCOL_TICKS   0x00000145

Definition at line 1324 of file tg3.h.

MAX_TXCOL_TICKS

#define MAX_TXCOL_TICKS   0x000003ff

Definition at line 1325 of file tg3.h.

HOSTCC_RXMAX_FRAMES

#define HOSTCC_RXMAX_FRAMES   0x00003c10

Definition at line 1326 of file tg3.h.

Referenced by __tg3_set_coalesce().

LOW_RXMAX_FRAMES

#define LOW_RXMAX_FRAMES   0x00000005

Definition at line 1327 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_RXMAX_FRAMES

#define DEFAULT_RXMAX_FRAMES   0x00000008

Definition at line 1328 of file tg3.h.

HIGH_RXMAX_FRAMES

#define HIGH_RXMAX_FRAMES   0x00000012

Definition at line 1329 of file tg3.h.

MAX_RXMAX_FRAMES

#define MAX_RXMAX_FRAMES   0x000000ff

Definition at line 1330 of file tg3.h.

HOSTCC_TXMAX_FRAMES

#define HOSTCC_TXMAX_FRAMES   0x00003c14

Definition at line 1331 of file tg3.h.

Referenced by __tg3_set_coalesce().

LOW_TXMAX_FRAMES

#define LOW_TXMAX_FRAMES   0x00000035

Definition at line 1332 of file tg3.h.

DEFAULT_TXMAX_FRAMES

#define DEFAULT_TXMAX_FRAMES   0x0000004b

Definition at line 1333 of file tg3.h.

HIGH_TXMAX_FRAMES

#define HIGH_TXMAX_FRAMES   0x00000052

Definition at line 1334 of file tg3.h.

MAX_TXMAX_FRAMES

#define MAX_TXMAX_FRAMES   0x000000ff

Definition at line 1335 of file tg3.h.

HOSTCC_RXCOAL_TICK_INT

#define HOSTCC_RXCOAL_TICK_INT   0x00003c18

Definition at line 1336 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_RXCOAL_TICK_INT

#define DEFAULT_RXCOAL_TICK_INT   0x00000019

Definition at line 1337 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_RXCOAL_TICK_INT_CLRTCKS

#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS   0x00000014

Definition at line 1338 of file tg3.h.

MAX_RXCOAL_TICK_INT

#define MAX_RXCOAL_TICK_INT   0x000003ff

Definition at line 1339 of file tg3.h.

HOSTCC_TXCOAL_TICK_INT

#define HOSTCC_TXCOAL_TICK_INT   0x00003c1c

Definition at line 1340 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_TXCOAL_TICK_INT

#define DEFAULT_TXCOAL_TICK_INT   0x00000019

Definition at line 1341 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_TXCOAL_TICK_INT_CLRTCKS

#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS   0x00000014

Definition at line 1342 of file tg3.h.

MAX_TXCOAL_TICK_INT

#define MAX_TXCOAL_TICK_INT   0x000003ff

Definition at line 1343 of file tg3.h.

HOSTCC_RXCOAL_MAXF_INT

#define HOSTCC_RXCOAL_MAXF_INT   0x00003c20

Definition at line 1344 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_RXCOAL_MAXF_INT

#define DEFAULT_RXCOAL_MAXF_INT   0x00000005

Definition at line 1345 of file tg3.h.

MAX_RXCOAL_MAXF_INT

#define MAX_RXCOAL_MAXF_INT   0x000000ff

Definition at line 1346 of file tg3.h.

HOSTCC_TXCOAL_MAXF_INT

#define HOSTCC_TXCOAL_MAXF_INT   0x00003c24

Definition at line 1347 of file tg3.h.

Referenced by __tg3_set_coalesce().

DEFAULT_TXCOAL_MAXF_INT

#define DEFAULT_TXCOAL_MAXF_INT   0x00000005

Definition at line 1348 of file tg3.h.

MAX_TXCOAL_MAXF_INT

#define MAX_TXCOAL_MAXF_INT   0x000000ff

Definition at line 1349 of file tg3.h.

HOSTCC_STAT_COAL_TICKS

#define HOSTCC_STAT_COAL_TICKS   0x00003c28

Definition at line 1350 of file tg3.h.

Referenced by __tg3_set_coalesce(), and tg3_setup_phy().

DEFAULT_STAT_COAL_TICKS

#define DEFAULT_STAT_COAL_TICKS   0x000f4240

Definition at line 1351 of file tg3.h.

Referenced by __tg3_set_coalesce(), and tg3_setup_phy().

MAX_STAT_COAL_TICKS

#define MAX_STAT_COAL_TICKS   0xd693d400

Definition at line 1352 of file tg3.h.

MIN_STAT_COAL_TICKS

#define MIN_STAT_COAL_TICKS   0x00000064

Definition at line 1353 of file tg3.h.

HOSTCC_STATS_BLK_HOST_ADDR

#define HOSTCC_STATS_BLK_HOST_ADDR   0x00003c30 /* 64-bit */

Definition at line 1355 of file tg3.h.

HOSTCC_STATUS_BLK_HOST_ADDR

#define HOSTCC_STATUS_BLK_HOST_ADDR   0x00003c38 /* 64-bit */

Definition at line 1356 of file tg3.h.

Referenced by tg3_rings_reset().

HOSTCC_STATS_BLK_NIC_ADDR

#define HOSTCC_STATS_BLK_NIC_ADDR   0x00003c40

Definition at line 1357 of file tg3.h.

HOSTCC_STATUS_BLK_NIC_ADDR

#define HOSTCC_STATUS_BLK_NIC_ADDR   0x00003c44

Definition at line 1358 of file tg3.h.

Referenced by tg3_reset_hw().

HOSTCC_FLOW_ATTN

#define HOSTCC_FLOW_ATTN   0x00003c48

Definition at line 1359 of file tg3.h.

HOSTCC_FLOW_ATTN_MBUF_LWM

#define HOSTCC_FLOW_ATTN_MBUF_LWM   0x00000040

Definition at line 1360 of file tg3.h.

HOSTCC_JUMBO_CON_IDX

#define HOSTCC_JUMBO_CON_IDX   0x00003c50

Definition at line 1362 of file tg3.h.

HOSTCC_STD_CON_IDX

#define HOSTCC_STD_CON_IDX   0x00003c54

Definition at line 1363 of file tg3.h.

HOSTCC_MINI_CON_IDX

#define HOSTCC_MINI_CON_IDX   0x00003c58

Definition at line 1364 of file tg3.h.

HOSTCC_RET_PROD_IDX_0

#define HOSTCC_RET_PROD_IDX_0   0x00003c80

Definition at line 1366 of file tg3.h.

HOSTCC_RET_PROD_IDX_1

#define HOSTCC_RET_PROD_IDX_1   0x00003c84

Definition at line 1367 of file tg3.h.

HOSTCC_RET_PROD_IDX_2

#define HOSTCC_RET_PROD_IDX_2   0x00003c88

Definition at line 1368 of file tg3.h.

HOSTCC_RET_PROD_IDX_3

#define HOSTCC_RET_PROD_IDX_3   0x00003c8c

Definition at line 1369 of file tg3.h.

HOSTCC_RET_PROD_IDX_4

#define HOSTCC_RET_PROD_IDX_4   0x00003c90

Definition at line 1370 of file tg3.h.

HOSTCC_RET_PROD_IDX_5

#define HOSTCC_RET_PROD_IDX_5   0x00003c94

Definition at line 1371 of file tg3.h.

HOSTCC_RET_PROD_IDX_6

#define HOSTCC_RET_PROD_IDX_6   0x00003c98

Definition at line 1372 of file tg3.h.

HOSTCC_RET_PROD_IDX_7

#define HOSTCC_RET_PROD_IDX_7   0x00003c9c

Definition at line 1373 of file tg3.h.

HOSTCC_RET_PROD_IDX_8

#define HOSTCC_RET_PROD_IDX_8   0x00003ca0

Definition at line 1374 of file tg3.h.

HOSTCC_RET_PROD_IDX_9

#define HOSTCC_RET_PROD_IDX_9   0x00003ca4

Definition at line 1375 of file tg3.h.

HOSTCC_RET_PROD_IDX_10

#define HOSTCC_RET_PROD_IDX_10   0x00003ca8

Definition at line 1376 of file tg3.h.

HOSTCC_RET_PROD_IDX_11

#define HOSTCC_RET_PROD_IDX_11   0x00003cac

Definition at line 1377 of file tg3.h.

HOSTCC_RET_PROD_IDX_12

#define HOSTCC_RET_PROD_IDX_12   0x00003cb0

Definition at line 1378 of file tg3.h.

HOSTCC_RET_PROD_IDX_13

#define HOSTCC_RET_PROD_IDX_13   0x00003cb4

Definition at line 1379 of file tg3.h.

HOSTCC_RET_PROD_IDX_14

#define HOSTCC_RET_PROD_IDX_14   0x00003cb8

Definition at line 1380 of file tg3.h.

HOSTCC_RET_PROD_IDX_15

#define HOSTCC_RET_PROD_IDX_15   0x00003cbc

Definition at line 1381 of file tg3.h.

HOSTCC_SND_CON_IDX_0

#define HOSTCC_SND_CON_IDX_0   0x00003cc0

Definition at line 1382 of file tg3.h.

HOSTCC_SND_CON_IDX_1

#define HOSTCC_SND_CON_IDX_1   0x00003cc4

Definition at line 1383 of file tg3.h.

HOSTCC_SND_CON_IDX_2

#define HOSTCC_SND_CON_IDX_2   0x00003cc8

Definition at line 1384 of file tg3.h.

HOSTCC_SND_CON_IDX_3

#define HOSTCC_SND_CON_IDX_3   0x00003ccc

Definition at line 1385 of file tg3.h.

HOSTCC_SND_CON_IDX_4

#define HOSTCC_SND_CON_IDX_4   0x00003cd0

Definition at line 1386 of file tg3.h.

HOSTCC_SND_CON_IDX_5

#define HOSTCC_SND_CON_IDX_5   0x00003cd4

Definition at line 1387 of file tg3.h.

HOSTCC_SND_CON_IDX_6

#define HOSTCC_SND_CON_IDX_6   0x00003cd8

Definition at line 1388 of file tg3.h.

HOSTCC_SND_CON_IDX_7

#define HOSTCC_SND_CON_IDX_7   0x00003cdc

Definition at line 1389 of file tg3.h.

HOSTCC_SND_CON_IDX_8

#define HOSTCC_SND_CON_IDX_8   0x00003ce0

Definition at line 1390 of file tg3.h.

HOSTCC_SND_CON_IDX_9

#define HOSTCC_SND_CON_IDX_9   0x00003ce4

Definition at line 1391 of file tg3.h.

HOSTCC_SND_CON_IDX_10

#define HOSTCC_SND_CON_IDX_10   0x00003ce8

Definition at line 1392 of file tg3.h.

HOSTCC_SND_CON_IDX_11

#define HOSTCC_SND_CON_IDX_11   0x00003cec

Definition at line 1393 of file tg3.h.

HOSTCC_SND_CON_IDX_12

#define HOSTCC_SND_CON_IDX_12   0x00003cf0

Definition at line 1394 of file tg3.h.

HOSTCC_SND_CON_IDX_13

#define HOSTCC_SND_CON_IDX_13   0x00003cf4

Definition at line 1395 of file tg3.h.

HOSTCC_SND_CON_IDX_14

#define HOSTCC_SND_CON_IDX_14   0x00003cf8

Definition at line 1396 of file tg3.h.

HOSTCC_SND_CON_IDX_15

#define HOSTCC_SND_CON_IDX_15   0x00003cfc

Definition at line 1397 of file tg3.h.

HOSTCC_STATBLCK_RING1

#define HOSTCC_STATBLCK_RING1   0x00003d00

Definition at line 1398 of file tg3.h.

HOSTCC_RXCOL_TICKS_VEC1

#define HOSTCC_RXCOL_TICKS_VEC1   0x00003d80

Definition at line 1401 of file tg3.h.

HOSTCC_TXCOL_TICKS_VEC1

#define HOSTCC_TXCOL_TICKS_VEC1   0x00003d84

Definition at line 1402 of file tg3.h.

HOSTCC_RXMAX_FRAMES_VEC1

#define HOSTCC_RXMAX_FRAMES_VEC1   0x00003d88

Definition at line 1403 of file tg3.h.

HOSTCC_TXMAX_FRAMES_VEC1

#define HOSTCC_TXMAX_FRAMES_VEC1   0x00003d8c

Definition at line 1404 of file tg3.h.

HOSTCC_RXCOAL_MAXF_INT_VEC1

#define HOSTCC_RXCOAL_MAXF_INT_VEC1   0x00003d90

Definition at line 1405 of file tg3.h.

HOSTCC_TXCOAL_MAXF_INT_VEC1

#define HOSTCC_TXCOAL_MAXF_INT_VEC1   0x00003d94

Definition at line 1406 of file tg3.h.

MEMARB_MODE

#define MEMARB_MODE   0x00004000

Definition at line 1410 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), tg3_init_one(), and tg3_stop_block().

MEMARB_MODE_RESET

#define MEMARB_MODE_RESET   0x00000001

Definition at line 1411 of file tg3.h.

MEMARB_MODE_ENABLE

#define MEMARB_MODE_ENABLE   0x00000002

Definition at line 1412 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), and tg3_init_one().

MEMARB_STATUS

#define MEMARB_STATUS   0x00004004

Definition at line 1413 of file tg3.h.

MEMARB_TRAP_ADDR_LOW

#define MEMARB_TRAP_ADDR_LOW   0x00004008

Definition at line 1414 of file tg3.h.

MEMARB_TRAP_ADDR_HIGH

#define MEMARB_TRAP_ADDR_HIGH   0x0000400c

Definition at line 1415 of file tg3.h.

BUFMGR_MODE

#define BUFMGR_MODE   0x00004400

Definition at line 1419 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_do_test_dma(), tg3_reset_hw(), and tg3_stop_block().

BUFMGR_MODE_RESET

#define BUFMGR_MODE_RESET   0x00000001

Definition at line 1420 of file tg3.h.

BUFMGR_MODE_ENABLE

#define BUFMGR_MODE_ENABLE   0x00000002

Definition at line 1421 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

BUFMGR_MODE_ATTN_ENABLE

#define BUFMGR_MODE_ATTN_ENABLE   0x00000004

Definition at line 1422 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_MODE_BM_TEST

#define BUFMGR_MODE_BM_TEST   0x00000008

Definition at line 1423 of file tg3.h.

BUFMGR_MODE_MBLOW_ATTN_ENAB

#define BUFMGR_MODE_MBLOW_ATTN_ENAB   0x00000010

Definition at line 1424 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_MODE_NO_TX_UNDERRUN

#define BUFMGR_MODE_NO_TX_UNDERRUN   0x80000000

Definition at line 1425 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_STATUS

#define BUFMGR_STATUS   0x00004404

Definition at line 1426 of file tg3.h.

BUFMGR_STATUS_ERROR

#define BUFMGR_STATUS_ERROR   0x00000004

Definition at line 1427 of file tg3.h.

BUFMGR_STATUS_MBLOW

#define BUFMGR_STATUS_MBLOW   0x00000010

Definition at line 1428 of file tg3.h.

BUFMGR_MB_POOL_ADDR

#define BUFMGR_MB_POOL_ADDR   0x00004408

Definition at line 1429 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_MB_POOL_SIZE

#define BUFMGR_MB_POOL_SIZE   0x0000440c

Definition at line 1430 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_MB_RDMA_LOW_WATER

#define BUFMGR_MB_RDMA_LOW_WATER   0x00004410

Definition at line 1431 of file tg3.h.

Referenced by tg3_reset_hw().

DEFAULT_MB_RDMA_LOW_WATER

#define DEFAULT_MB_RDMA_LOW_WATER   0x00000050

Definition at line 1432 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_RDMA_LOW_WATER_5705

#define DEFAULT_MB_RDMA_LOW_WATER_5705   0x00000000

Definition at line 1433 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_RDMA_LOW_WATER_JUMBO

#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO   0x00000130

Definition at line 1434 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780

#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780   0x00000000

Definition at line 1435 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

BUFMGR_MB_MACRX_LOW_WATER

#define BUFMGR_MB_MACRX_LOW_WATER   0x00004414

Definition at line 1436 of file tg3.h.

Referenced by tg3_reset_hw().

DEFAULT_MB_MACRX_LOW_WATER

#define DEFAULT_MB_MACRX_LOW_WATER   0x00000020

Definition at line 1437 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_5705

#define DEFAULT_MB_MACRX_LOW_WATER_5705   0x00000010

Definition at line 1438 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_5906

#define DEFAULT_MB_MACRX_LOW_WATER_5906   0x00000004

Definition at line 1439 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_57765

#define DEFAULT_MB_MACRX_LOW_WATER_57765   0x0000002a

Definition at line 1440 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_JUMBO

#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO   0x00000098

Definition at line 1441 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780

#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780   0x0000004b

Definition at line 1442 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765

#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765   0x0000007e

Definition at line 1443 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

BUFMGR_MB_HIGH_WATER

#define BUFMGR_MB_HIGH_WATER   0x00004418

Definition at line 1444 of file tg3.h.

Referenced by tg3_reset_hw().

DEFAULT_MB_HIGH_WATER

#define DEFAULT_MB_HIGH_WATER   0x00000060

Definition at line 1445 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_5705

#define DEFAULT_MB_HIGH_WATER_5705   0x00000060

Definition at line 1446 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_5906

#define DEFAULT_MB_HIGH_WATER_5906   0x00000010

Definition at line 1447 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_57765

#define DEFAULT_MB_HIGH_WATER_57765   0x000000a0

Definition at line 1448 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_JUMBO

#define DEFAULT_MB_HIGH_WATER_JUMBO   0x0000017c

Definition at line 1449 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_JUMBO_5780

#define DEFAULT_MB_HIGH_WATER_JUMBO_5780   0x00000096

Definition at line 1450 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

DEFAULT_MB_HIGH_WATER_JUMBO_57765

#define DEFAULT_MB_HIGH_WATER_JUMBO_57765   0x000000ea

Definition at line 1451 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

BUFMGR_RX_MB_ALLOC_REQ

#define BUFMGR_RX_MB_ALLOC_REQ   0x0000441c

Definition at line 1452 of file tg3.h.

BUFMGR_MB_ALLOC_BIT

#define BUFMGR_MB_ALLOC_BIT   0x10000000

Definition at line 1453 of file tg3.h.

BUFMGR_RX_MB_ALLOC_RESP

#define BUFMGR_RX_MB_ALLOC_RESP   0x00004420

Definition at line 1454 of file tg3.h.

BUFMGR_TX_MB_ALLOC_REQ

#define BUFMGR_TX_MB_ALLOC_REQ   0x00004424

Definition at line 1455 of file tg3.h.

BUFMGR_TX_MB_ALLOC_RESP

#define BUFMGR_TX_MB_ALLOC_RESP   0x00004428

Definition at line 1456 of file tg3.h.

BUFMGR_DMA_DESC_POOL_ADDR

#define BUFMGR_DMA_DESC_POOL_ADDR   0x0000442c

Definition at line 1457 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_DMA_DESC_POOL_SIZE

#define BUFMGR_DMA_DESC_POOL_SIZE   0x00004430

Definition at line 1458 of file tg3.h.

Referenced by tg3_reset_hw().

BUFMGR_DMA_LOW_WATER

#define BUFMGR_DMA_LOW_WATER   0x00004434

Definition at line 1459 of file tg3.h.

Referenced by tg3_reset_hw().

DEFAULT_DMA_LOW_WATER

#define DEFAULT_DMA_LOW_WATER   0x00000005

Definition at line 1460 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

BUFMGR_DMA_HIGH_WATER

#define BUFMGR_DMA_HIGH_WATER   0x00004438

Definition at line 1461 of file tg3.h.

Referenced by tg3_reset_hw().

DEFAULT_DMA_HIGH_WATER

#define DEFAULT_DMA_HIGH_WATER   0x0000000a

Definition at line 1462 of file tg3.h.

Referenced by tg3_init_bufmgr_config().

BUFMGR_RX_DMA_ALLOC_REQ

#define BUFMGR_RX_DMA_ALLOC_REQ   0x0000443c

Definition at line 1463 of file tg3.h.

BUFMGR_RX_DMA_ALLOC_RESP

#define BUFMGR_RX_DMA_ALLOC_RESP   0x00004440

Definition at line 1464 of file tg3.h.

BUFMGR_TX_DMA_ALLOC_REQ

#define BUFMGR_TX_DMA_ALLOC_REQ   0x00004444

Definition at line 1465 of file tg3.h.

BUFMGR_TX_DMA_ALLOC_RESP

#define BUFMGR_TX_DMA_ALLOC_RESP   0x00004448

Definition at line 1466 of file tg3.h.

BUFMGR_HWDIAG_0

#define BUFMGR_HWDIAG_0   0x0000444c

Definition at line 1467 of file tg3.h.

BUFMGR_HWDIAG_1

#define BUFMGR_HWDIAG_1   0x00004450

Definition at line 1468 of file tg3.h.

BUFMGR_HWDIAG_2

#define BUFMGR_HWDIAG_2   0x00004454

Definition at line 1469 of file tg3.h.

RDMAC_MODE

#define RDMAC_MODE   0x00004800

Definition at line 1473 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_do_test_dma(), and tg3_reset_hw().

RDMAC_MODE_RESET

#define RDMAC_MODE_RESET   0x00000001

Definition at line 1474 of file tg3.h.

RDMAC_MODE_ENABLE

#define RDMAC_MODE_ENABLE   0x00000002

Definition at line 1475 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_do_test_dma(), and tg3_reset_hw().

RDMAC_MODE_TGTABORT_ENAB

#define RDMAC_MODE_TGTABORT_ENAB   0x00000004

Definition at line 1476 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_MSTABORT_ENAB

#define RDMAC_MODE_MSTABORT_ENAB   0x00000008

Definition at line 1477 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_PARITYERR_ENAB

#define RDMAC_MODE_PARITYERR_ENAB   0x00000010

Definition at line 1478 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_ADDROFLOW_ENAB

#define RDMAC_MODE_ADDROFLOW_ENAB   0x00000020

Definition at line 1479 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_FIFOOFLOW_ENAB

#define RDMAC_MODE_FIFOOFLOW_ENAB   0x00000040

Definition at line 1480 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_FIFOURUN_ENAB

#define RDMAC_MODE_FIFOURUN_ENAB   0x00000080

Definition at line 1481 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_FIFOOREAD_ENAB

#define RDMAC_MODE_FIFOOREAD_ENAB   0x00000100

Definition at line 1482 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_LNGREAD_ENAB

#define RDMAC_MODE_LNGREAD_ENAB   0x00000200

Definition at line 1483 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_SPLIT_ENABLE

#define RDMAC_MODE_SPLIT_ENABLE   0x00000800

Definition at line 1484 of file tg3.h.

RDMAC_MODE_BD_SBD_CRPT_ENAB

#define RDMAC_MODE_BD_SBD_CRPT_ENAB   0x00000800

Definition at line 1485 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_SPLIT_RESET

#define RDMAC_MODE_SPLIT_RESET   0x00001000

Definition at line 1486 of file tg3.h.

RDMAC_MODE_MBUF_RBD_CRPT_ENAB

#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB   0x00001000

Definition at line 1487 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_MBUF_SBD_CRPT_ENAB

#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB   0x00002000

Definition at line 1488 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_FIFO_SIZE_128

#define RDMAC_MODE_FIFO_SIZE_128   0x00020000

Definition at line 1489 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_FIFO_LONG_BURST

#define RDMAC_MODE_FIFO_LONG_BURST   0x00030000

Definition at line 1490 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_MULT_DMA_RD_DIS

#define RDMAC_MODE_MULT_DMA_RD_DIS   0x01000000

Definition at line 1491 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_MODE_IPV4_LSO_EN

#define RDMAC_MODE_IPV4_LSO_EN   0x08000000

Definition at line 1492 of file tg3.h.

RDMAC_MODE_IPV6_LSO_EN

#define RDMAC_MODE_IPV6_LSO_EN   0x10000000

Definition at line 1493 of file tg3.h.

RDMAC_MODE_H2BNC_VLAN_DET

#define RDMAC_MODE_H2BNC_VLAN_DET   0x20000000

Definition at line 1494 of file tg3.h.

Referenced by tg3_reset_hw().

RDMAC_STATUS

#define RDMAC_STATUS   0x00004804

Definition at line 1495 of file tg3.h.

Referenced by tg3_do_test_dma().

RDMAC_STATUS_TGTABORT

#define RDMAC_STATUS_TGTABORT   0x00000004

Definition at line 1496 of file tg3.h.

RDMAC_STATUS_MSTABORT

#define RDMAC_STATUS_MSTABORT   0x00000008

Definition at line 1497 of file tg3.h.

RDMAC_STATUS_PARITYERR

#define RDMAC_STATUS_PARITYERR   0x00000010

Definition at line 1498 of file tg3.h.

RDMAC_STATUS_ADDROFLOW

#define RDMAC_STATUS_ADDROFLOW   0x00000020

Definition at line 1499 of file tg3.h.

RDMAC_STATUS_FIFOOFLOW

#define RDMAC_STATUS_FIFOOFLOW   0x00000040

Definition at line 1500 of file tg3.h.

RDMAC_STATUS_FIFOURUN

#define RDMAC_STATUS_FIFOURUN   0x00000080

Definition at line 1501 of file tg3.h.

RDMAC_STATUS_FIFOOREAD

#define RDMAC_STATUS_FIFOOREAD   0x00000100

Definition at line 1502 of file tg3.h.

RDMAC_STATUS_LNGREAD

#define RDMAC_STATUS_LNGREAD   0x00000200

Definition at line 1503 of file tg3.h.

TG3_RDMA_RSRVCTRL_REG

#define TG3_RDMA_RSRVCTRL_REG   0x00004900

Definition at line 1506 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX

#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX   0x00000004

Definition at line 1507 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K

#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K   0x00000c00

Definition at line 1508 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK

#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK   0x00000ff0

Definition at line 1509 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K

#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K   0x000c0000

Definition at line 1510 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK

#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK   0x000ff000

Definition at line 1511 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_TXMRGN_320B

#define TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000

Definition at line 1512 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_RDMA_RSRVCTRL_TXMRGN_MASK

#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000

Definition at line 1513 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_LSO_RD_DMA_CRPTEN_CTRL

#define TG3_LSO_RD_DMA_CRPTEN_CTRL   0x00004910

Definition at line 1516 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K   0x00030000

Definition at line 1517 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K

#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000

Definition at line 1518 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE

#define WDMAC_MODE   0x00004c00

Definition at line 1522 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_do_test_dma(), tg3_init_one(), and tg3_reset_hw().

WDMAC_MODE_RESET

#define WDMAC_MODE_RESET   0x00000001

Definition at line 1523 of file tg3.h.

WDMAC_MODE_ENABLE

#define WDMAC_MODE_ENABLE   0x00000002

Definition at line 1524 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_do_test_dma(), tg3_init_one(), and tg3_reset_hw().

WDMAC_MODE_TGTABORT_ENAB

#define WDMAC_MODE_TGTABORT_ENAB   0x00000004

Definition at line 1525 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_MSTABORT_ENAB

#define WDMAC_MODE_MSTABORT_ENAB   0x00000008

Definition at line 1526 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_PARITYERR_ENAB

#define WDMAC_MODE_PARITYERR_ENAB   0x00000010

Definition at line 1527 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_ADDROFLOW_ENAB

#define WDMAC_MODE_ADDROFLOW_ENAB   0x00000020

Definition at line 1528 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_FIFOOFLOW_ENAB

#define WDMAC_MODE_FIFOOFLOW_ENAB   0x00000040

Definition at line 1529 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_FIFOURUN_ENAB

#define WDMAC_MODE_FIFOURUN_ENAB   0x00000080

Definition at line 1530 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_FIFOOREAD_ENAB

#define WDMAC_MODE_FIFOOREAD_ENAB   0x00000100

Definition at line 1531 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_LNGREAD_ENAB

#define WDMAC_MODE_LNGREAD_ENAB   0x00000200

Definition at line 1532 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_RX_ACCEL

#define WDMAC_MODE_RX_ACCEL   0x00000400

Definition at line 1533 of file tg3.h.

WDMAC_MODE_STATUS_TAG_FIX

#define WDMAC_MODE_STATUS_TAG_FIX   0x20000000

Definition at line 1534 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_MODE_BURST_ALL_DATA

#define WDMAC_MODE_BURST_ALL_DATA   0xc0000000

Definition at line 1535 of file tg3.h.

Referenced by tg3_reset_hw().

WDMAC_STATUS

#define WDMAC_STATUS   0x00004c04

Definition at line 1536 of file tg3.h.

Referenced by tg3_do_test_dma().

WDMAC_STATUS_TGTABORT

#define WDMAC_STATUS_TGTABORT   0x00000004

Definition at line 1537 of file tg3.h.

WDMAC_STATUS_MSTABORT

#define WDMAC_STATUS_MSTABORT   0x00000008

Definition at line 1538 of file tg3.h.

WDMAC_STATUS_PARITYERR

#define WDMAC_STATUS_PARITYERR   0x00000010

Definition at line 1539 of file tg3.h.

WDMAC_STATUS_ADDROFLOW

#define WDMAC_STATUS_ADDROFLOW   0x00000020

Definition at line 1540 of file tg3.h.

WDMAC_STATUS_FIFOOFLOW

#define WDMAC_STATUS_FIFOOFLOW   0x00000040

Definition at line 1541 of file tg3.h.

WDMAC_STATUS_FIFOURUN

#define WDMAC_STATUS_FIFOURUN   0x00000080

Definition at line 1542 of file tg3.h.

WDMAC_STATUS_FIFOOREAD

#define WDMAC_STATUS_FIFOOREAD   0x00000100

Definition at line 1543 of file tg3.h.

WDMAC_STATUS_LNGREAD

#define WDMAC_STATUS_LNGREAD   0x00000200

Definition at line 1544 of file tg3.h.

CPU_MODE

#define CPU_MODE   0x00000000

Definition at line 1548 of file tg3.h.

CPU_MODE_RESET

#define CPU_MODE_RESET   0x00000001

Definition at line 1549 of file tg3.h.

CPU_MODE_HALT

#define CPU_MODE_HALT   0x00000400

Definition at line 1550 of file tg3.h.

CPU_STATE

#define CPU_STATE   0x00000004

Definition at line 1551 of file tg3.h.

CPU_EVTMASK

#define CPU_EVTMASK   0x00000008

Definition at line 1552 of file tg3.h.

CPU_PC

#define CPU_PC   0x0000001c

Definition at line 1554 of file tg3.h.

CPU_INSN

#define CPU_INSN   0x00000020

Definition at line 1555 of file tg3.h.

CPU_SPAD_UFLOW

#define CPU_SPAD_UFLOW   0x00000024

Definition at line 1556 of file tg3.h.

CPU_WDOG_CLEAR

#define CPU_WDOG_CLEAR   0x00000028

Definition at line 1557 of file tg3.h.

CPU_WDOG_VECTOR

#define CPU_WDOG_VECTOR   0x0000002c

Definition at line 1558 of file tg3.h.

CPU_WDOG_PC

#define CPU_WDOG_PC   0x00000030

Definition at line 1559 of file tg3.h.

CPU_HW_BP

#define CPU_HW_BP   0x00000034

Definition at line 1560 of file tg3.h.

CPU_WDOG_SAVED_STATE

#define CPU_WDOG_SAVED_STATE   0x00000044

Definition at line 1562 of file tg3.h.

CPU_LAST_BRANCH_ADDR

#define CPU_LAST_BRANCH_ADDR   0x00000048

Definition at line 1563 of file tg3.h.

CPU_SPAD_UFLOW_SET

#define CPU_SPAD_UFLOW_SET   0x0000004c

Definition at line 1564 of file tg3.h.

CPU_R0

#define CPU_R0   0x00000200

Definition at line 1566 of file tg3.h.

CPU_R1

#define CPU_R1   0x00000204

Definition at line 1567 of file tg3.h.

CPU_R2

#define CPU_R2   0x00000208

Definition at line 1568 of file tg3.h.

CPU_R3

#define CPU_R3   0x0000020c

Definition at line 1569 of file tg3.h.

CPU_R4

#define CPU_R4   0x00000210

Definition at line 1570 of file tg3.h.

CPU_R5

#define CPU_R5   0x00000214

Definition at line 1571 of file tg3.h.

CPU_R6

#define CPU_R6   0x00000218

Definition at line 1572 of file tg3.h.

CPU_R7

#define CPU_R7   0x0000021c

Definition at line 1573 of file tg3.h.

CPU_R8

#define CPU_R8   0x00000220

Definition at line 1574 of file tg3.h.

CPU_R9

#define CPU_R9   0x00000224

Definition at line 1575 of file tg3.h.

CPU_R10

#define CPU_R10   0x00000228

Definition at line 1576 of file tg3.h.

CPU_R11

#define CPU_R11   0x0000022c

Definition at line 1577 of file tg3.h.

CPU_R12

#define CPU_R12   0x00000230

Definition at line 1578 of file tg3.h.

CPU_R13

#define CPU_R13   0x00000234

Definition at line 1579 of file tg3.h.

CPU_R14

#define CPU_R14   0x00000238

Definition at line 1580 of file tg3.h.

CPU_R15

#define CPU_R15   0x0000023c

Definition at line 1581 of file tg3.h.

CPU_R16

#define CPU_R16   0x00000240

Definition at line 1582 of file tg3.h.

CPU_R17

#define CPU_R17   0x00000244

Definition at line 1583 of file tg3.h.

CPU_R18

#define CPU_R18   0x00000248

Definition at line 1584 of file tg3.h.

CPU_R19

#define CPU_R19   0x0000024c

Definition at line 1585 of file tg3.h.

CPU_R20

#define CPU_R20   0x00000250

Definition at line 1586 of file tg3.h.

CPU_R21

#define CPU_R21   0x00000254

Definition at line 1587 of file tg3.h.

CPU_R22

#define CPU_R22   0x00000258

Definition at line 1588 of file tg3.h.

CPU_R23

#define CPU_R23   0x0000025c

Definition at line 1589 of file tg3.h.

CPU_R24

#define CPU_R24   0x00000260

Definition at line 1590 of file tg3.h.

CPU_R25

#define CPU_R25   0x00000264

Definition at line 1591 of file tg3.h.

CPU_R26

#define CPU_R26   0x00000268

Definition at line 1592 of file tg3.h.

CPU_R27

#define CPU_R27   0x0000026c

Definition at line 1593 of file tg3.h.

CPU_R28

#define CPU_R28   0x00000270

Definition at line 1594 of file tg3.h.

CPU_R29

#define CPU_R29   0x00000274

Definition at line 1595 of file tg3.h.

CPU_R30

#define CPU_R30   0x00000278

Definition at line 1596 of file tg3.h.

CPU_R31

#define CPU_R31   0x0000027c

Definition at line 1597 of file tg3.h.

RX_CPU_BASE

#define RX_CPU_BASE   0x00005000

Definition at line 1600 of file tg3.h.

RX_CPU_MODE

#define RX_CPU_MODE   0x00005000

Definition at line 1601 of file tg3.h.

RX_CPU_STATE

#define RX_CPU_STATE   0x00005004

Definition at line 1602 of file tg3.h.

RX_CPU_PGMCTR

#define RX_CPU_PGMCTR   0x0000501c

Definition at line 1603 of file tg3.h.

RX_CPU_HWBKPT

#define RX_CPU_HWBKPT   0x00005034

Definition at line 1604 of file tg3.h.

TX_CPU_BASE

#define TX_CPU_BASE   0x00005400

Definition at line 1605 of file tg3.h.

TX_CPU_MODE

#define TX_CPU_MODE   0x00005400

Definition at line 1606 of file tg3.h.

TX_CPU_STATE

#define TX_CPU_STATE   0x00005404

Definition at line 1607 of file tg3.h.

TX_CPU_PGMCTR

#define TX_CPU_PGMCTR   0x0000541c

Definition at line 1608 of file tg3.h.

VCPU_STATUS

#define VCPU_STATUS   0x00005100

Definition at line 1610 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_poll_fw().

VCPU_STATUS_INIT_DONE

#define VCPU_STATUS_INIT_DONE   0x04000000

Definition at line 1611 of file tg3.h.

Referenced by tg3_poll_fw().

VCPU_STATUS_DRV_RESET

#define VCPU_STATUS_DRV_RESET   0x08000000

Definition at line 1612 of file tg3.h.

Referenced by tg3_chip_reset().

VCPU_CFGSHDW

#define VCPU_CFGSHDW   0x00005104

Definition at line 1614 of file tg3.h.

VCPU_CFGSHDW_WOL_ENABLE

#define VCPU_CFGSHDW_WOL_ENABLE   0x00000001

Definition at line 1615 of file tg3.h.

VCPU_CFGSHDW_WOL_MAGPKT

#define VCPU_CFGSHDW_WOL_MAGPKT   0x00000004

Definition at line 1616 of file tg3.h.

VCPU_CFGSHDW_ASPM_DBNC

#define VCPU_CFGSHDW_ASPM_DBNC   0x00001000

Definition at line 1617 of file tg3.h.

GRCMBOX_BASE

#define GRCMBOX_BASE   0x00005600

Definition at line 1620 of file tg3.h.

Referenced by tg3_read32_mbox_5906(), and tg3_write32_mbox_5906().

GRCMBOX_INTERRUPT_0

#define GRCMBOX_INTERRUPT_0   0x00005800 /* 64-bit */

Definition at line 1621 of file tg3.h.

GRCMBOX_INTERRUPT_1

#define GRCMBOX_INTERRUPT_1   0x00005808 /* 64-bit */

Definition at line 1622 of file tg3.h.

GRCMBOX_INTERRUPT_2

#define GRCMBOX_INTERRUPT_2   0x00005810 /* 64-bit */

Definition at line 1623 of file tg3.h.

GRCMBOX_INTERRUPT_3

#define GRCMBOX_INTERRUPT_3   0x00005818 /* 64-bit */

Definition at line 1624 of file tg3.h.

GRCMBOX_GENERAL_0

#define GRCMBOX_GENERAL_0   0x00005820 /* 64-bit */

Definition at line 1625 of file tg3.h.

GRCMBOX_GENERAL_1

#define GRCMBOX_GENERAL_1   0x00005828 /* 64-bit */

Definition at line 1626 of file tg3.h.

GRCMBOX_GENERAL_2

#define GRCMBOX_GENERAL_2   0x00005830 /* 64-bit */

Definition at line 1627 of file tg3.h.

GRCMBOX_GENERAL_3

#define GRCMBOX_GENERAL_3   0x00005838 /* 64-bit */

Definition at line 1628 of file tg3.h.

GRCMBOX_GENERAL_4

#define GRCMBOX_GENERAL_4   0x00005840 /* 64-bit */

Definition at line 1629 of file tg3.h.

GRCMBOX_GENERAL_5

#define GRCMBOX_GENERAL_5   0x00005848 /* 64-bit */

Definition at line 1630 of file tg3.h.

GRCMBOX_GENERAL_6

#define GRCMBOX_GENERAL_6   0x00005850 /* 64-bit */

Definition at line 1631 of file tg3.h.

GRCMBOX_GENERAL_7

#define GRCMBOX_GENERAL_7   0x00005858 /* 64-bit */

Definition at line 1632 of file tg3.h.

GRCMBOX_RELOAD_STAT

#define GRCMBOX_RELOAD_STAT   0x00005860 /* 64-bit */

Definition at line 1633 of file tg3.h.

GRCMBOX_RCVSTD_PROD_IDX

#define GRCMBOX_RCVSTD_PROD_IDX   0x00005868 /* 64-bit */

Definition at line 1634 of file tg3.h.

GRCMBOX_RCVJUMBO_PROD_IDX

#define GRCMBOX_RCVJUMBO_PROD_IDX   0x00005870 /* 64-bit */

Definition at line 1635 of file tg3.h.

GRCMBOX_RCVMINI_PROD_IDX

#define GRCMBOX_RCVMINI_PROD_IDX   0x00005878 /* 64-bit */

Definition at line 1636 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_0

#define GRCMBOX_RCVRET_CON_IDX_0   0x00005880 /* 64-bit */

Definition at line 1637 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_1

#define GRCMBOX_RCVRET_CON_IDX_1   0x00005888 /* 64-bit */

Definition at line 1638 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_2

#define GRCMBOX_RCVRET_CON_IDX_2   0x00005890 /* 64-bit */

Definition at line 1639 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_3

#define GRCMBOX_RCVRET_CON_IDX_3   0x00005898 /* 64-bit */

Definition at line 1640 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_4

#define GRCMBOX_RCVRET_CON_IDX_4   0x000058a0 /* 64-bit */

Definition at line 1641 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_5

#define GRCMBOX_RCVRET_CON_IDX_5   0x000058a8 /* 64-bit */

Definition at line 1642 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_6

#define GRCMBOX_RCVRET_CON_IDX_6   0x000058b0 /* 64-bit */

Definition at line 1643 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_7

#define GRCMBOX_RCVRET_CON_IDX_7   0x000058b8 /* 64-bit */

Definition at line 1644 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_8

#define GRCMBOX_RCVRET_CON_IDX_8   0x000058c0 /* 64-bit */

Definition at line 1645 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_9

#define GRCMBOX_RCVRET_CON_IDX_9   0x000058c8 /* 64-bit */

Definition at line 1646 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_10

#define GRCMBOX_RCVRET_CON_IDX_10   0x000058d0 /* 64-bit */

Definition at line 1647 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_11

#define GRCMBOX_RCVRET_CON_IDX_11   0x000058d8 /* 64-bit */

Definition at line 1648 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_12

#define GRCMBOX_RCVRET_CON_IDX_12   0x000058e0 /* 64-bit */

Definition at line 1649 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_13

#define GRCMBOX_RCVRET_CON_IDX_13   0x000058e8 /* 64-bit */

Definition at line 1650 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_14

#define GRCMBOX_RCVRET_CON_IDX_14   0x000058f0 /* 64-bit */

Definition at line 1651 of file tg3.h.

GRCMBOX_RCVRET_CON_IDX_15

#define GRCMBOX_RCVRET_CON_IDX_15   0x000058f8 /* 64-bit */

Definition at line 1652 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_0

#define GRCMBOX_SNDHOST_PROD_IDX_0   0x00005900 /* 64-bit */

Definition at line 1653 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_1

#define GRCMBOX_SNDHOST_PROD_IDX_1   0x00005908 /* 64-bit */

Definition at line 1654 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_2

#define GRCMBOX_SNDHOST_PROD_IDX_2   0x00005910 /* 64-bit */

Definition at line 1655 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_3

#define GRCMBOX_SNDHOST_PROD_IDX_3   0x00005918 /* 64-bit */

Definition at line 1656 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_4

#define GRCMBOX_SNDHOST_PROD_IDX_4   0x00005920 /* 64-bit */

Definition at line 1657 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_5

#define GRCMBOX_SNDHOST_PROD_IDX_5   0x00005928 /* 64-bit */

Definition at line 1658 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_6

#define GRCMBOX_SNDHOST_PROD_IDX_6   0x00005930 /* 64-bit */

Definition at line 1659 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_7

#define GRCMBOX_SNDHOST_PROD_IDX_7   0x00005938 /* 64-bit */

Definition at line 1660 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_8

#define GRCMBOX_SNDHOST_PROD_IDX_8   0x00005940 /* 64-bit */

Definition at line 1661 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_9

#define GRCMBOX_SNDHOST_PROD_IDX_9   0x00005948 /* 64-bit */

Definition at line 1662 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_10

#define GRCMBOX_SNDHOST_PROD_IDX_10   0x00005950 /* 64-bit */

Definition at line 1663 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_11

#define GRCMBOX_SNDHOST_PROD_IDX_11   0x00005958 /* 64-bit */

Definition at line 1664 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_12

#define GRCMBOX_SNDHOST_PROD_IDX_12   0x00005960 /* 64-bit */

Definition at line 1665 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_13

#define GRCMBOX_SNDHOST_PROD_IDX_13   0x00005968 /* 64-bit */

Definition at line 1666 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_14

#define GRCMBOX_SNDHOST_PROD_IDX_14   0x00005970 /* 64-bit */

Definition at line 1667 of file tg3.h.

GRCMBOX_SNDHOST_PROD_IDX_15

#define GRCMBOX_SNDHOST_PROD_IDX_15   0x00005978 /* 64-bit */

Definition at line 1668 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_0

#define GRCMBOX_SNDNIC_PROD_IDX_0   0x00005980 /* 64-bit */

Definition at line 1669 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_1

#define GRCMBOX_SNDNIC_PROD_IDX_1   0x00005988 /* 64-bit */

Definition at line 1670 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_2

#define GRCMBOX_SNDNIC_PROD_IDX_2   0x00005990 /* 64-bit */

Definition at line 1671 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_3

#define GRCMBOX_SNDNIC_PROD_IDX_3   0x00005998 /* 64-bit */

Definition at line 1672 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_4

#define GRCMBOX_SNDNIC_PROD_IDX_4   0x000059a0 /* 64-bit */

Definition at line 1673 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_5

#define GRCMBOX_SNDNIC_PROD_IDX_5   0x000059a8 /* 64-bit */

Definition at line 1674 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_6

#define GRCMBOX_SNDNIC_PROD_IDX_6   0x000059b0 /* 64-bit */

Definition at line 1675 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_7

#define GRCMBOX_SNDNIC_PROD_IDX_7   0x000059b8 /* 64-bit */

Definition at line 1676 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_8

#define GRCMBOX_SNDNIC_PROD_IDX_8   0x000059c0 /* 64-bit */

Definition at line 1677 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_9

#define GRCMBOX_SNDNIC_PROD_IDX_9   0x000059c8 /* 64-bit */

Definition at line 1678 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_10

#define GRCMBOX_SNDNIC_PROD_IDX_10   0x000059d0 /* 64-bit */

Definition at line 1679 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_11

#define GRCMBOX_SNDNIC_PROD_IDX_11   0x000059d8 /* 64-bit */

Definition at line 1680 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_12

#define GRCMBOX_SNDNIC_PROD_IDX_12   0x000059e0 /* 64-bit */

Definition at line 1681 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_13

#define GRCMBOX_SNDNIC_PROD_IDX_13   0x000059e8 /* 64-bit */

Definition at line 1682 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_14

#define GRCMBOX_SNDNIC_PROD_IDX_14   0x000059f0 /* 64-bit */

Definition at line 1683 of file tg3.h.

GRCMBOX_SNDNIC_PROD_IDX_15

#define GRCMBOX_SNDNIC_PROD_IDX_15   0x000059f8 /* 64-bit */

Definition at line 1684 of file tg3.h.

GRCMBOX_HIGH_PRIO_EV_VECTOR

#define GRCMBOX_HIGH_PRIO_EV_VECTOR   0x00005a00

Definition at line 1685 of file tg3.h.

GRCMBOX_HIGH_PRIO_EV_MASK

#define GRCMBOX_HIGH_PRIO_EV_MASK   0x00005a04

Definition at line 1686 of file tg3.h.

GRCMBOX_LOW_PRIO_EV_VEC

#define GRCMBOX_LOW_PRIO_EV_VEC   0x00005a08

Definition at line 1687 of file tg3.h.

GRCMBOX_LOW_PRIO_EV_MASK

#define GRCMBOX_LOW_PRIO_EV_MASK   0x00005a0c

Definition at line 1688 of file tg3.h.

FTQ_RESET

#define FTQ_RESET   0x00005c00

Definition at line 1692 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_do_test_dma().

FTQ_DMA_NORM_READ_CTL

#define FTQ_DMA_NORM_READ_CTL   0x00005c10

Definition at line 1694 of file tg3.h.

FTQ_DMA_NORM_READ_FULL_CNT

#define FTQ_DMA_NORM_READ_FULL_CNT   0x00005c14

Definition at line 1695 of file tg3.h.

FTQ_DMA_NORM_READ_FIFO_ENQDEQ

#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18

Definition at line 1696 of file tg3.h.

FTQ_DMA_NORM_READ_WRITE_PEEK

#define FTQ_DMA_NORM_READ_WRITE_PEEK   0x00005c1c

Definition at line 1697 of file tg3.h.

FTQ_DMA_HIGH_READ_CTL

#define FTQ_DMA_HIGH_READ_CTL   0x00005c20

Definition at line 1698 of file tg3.h.

FTQ_DMA_HIGH_READ_FULL_CNT

#define FTQ_DMA_HIGH_READ_FULL_CNT   0x00005c24

Definition at line 1699 of file tg3.h.

FTQ_DMA_HIGH_READ_FIFO_ENQDEQ

#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28

Definition at line 1700 of file tg3.h.

Referenced by tg3_do_test_dma().

FTQ_DMA_HIGH_READ_WRITE_PEEK

#define FTQ_DMA_HIGH_READ_WRITE_PEEK   0x00005c2c

Definition at line 1701 of file tg3.h.

FTQ_DMA_COMP_DISC_CTL

#define FTQ_DMA_COMP_DISC_CTL   0x00005c30

Definition at line 1702 of file tg3.h.

FTQ_DMA_COMP_DISC_FULL_CNT

#define FTQ_DMA_COMP_DISC_FULL_CNT   0x00005c34

Definition at line 1703 of file tg3.h.

FTQ_DMA_COMP_DISC_FIFO_ENQDEQ

#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38

Definition at line 1704 of file tg3.h.

FTQ_DMA_COMP_DISC_WRITE_PEEK

#define FTQ_DMA_COMP_DISC_WRITE_PEEK   0x00005c3c

Definition at line 1705 of file tg3.h.

FTQ_SEND_BD_COMP_CTL

#define FTQ_SEND_BD_COMP_CTL   0x00005c40

Definition at line 1706 of file tg3.h.

FTQ_SEND_BD_COMP_FULL_CNT

#define FTQ_SEND_BD_COMP_FULL_CNT   0x00005c44

Definition at line 1707 of file tg3.h.

FTQ_SEND_BD_COMP_FIFO_ENQDEQ

#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ   0x00005c48

Definition at line 1708 of file tg3.h.

FTQ_SEND_BD_COMP_WRITE_PEEK

#define FTQ_SEND_BD_COMP_WRITE_PEEK   0x00005c4c

Definition at line 1709 of file tg3.h.

FTQ_SEND_DATA_INIT_CTL

#define FTQ_SEND_DATA_INIT_CTL   0x00005c50

Definition at line 1710 of file tg3.h.

FTQ_SEND_DATA_INIT_FULL_CNT

#define FTQ_SEND_DATA_INIT_FULL_CNT   0x00005c54

Definition at line 1711 of file tg3.h.

FTQ_SEND_DATA_INIT_FIFO_ENQDEQ

#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ   0x00005c58

Definition at line 1712 of file tg3.h.

FTQ_SEND_DATA_INIT_WRITE_PEEK

#define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c

Definition at line 1713 of file tg3.h.

FTQ_DMA_NORM_WRITE_CTL

#define FTQ_DMA_NORM_WRITE_CTL   0x00005c60

Definition at line 1714 of file tg3.h.

FTQ_DMA_NORM_WRITE_FULL_CNT

#define FTQ_DMA_NORM_WRITE_FULL_CNT   0x00005c64

Definition at line 1715 of file tg3.h.

FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ

#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ   0x00005c68

Definition at line 1716 of file tg3.h.

FTQ_DMA_NORM_WRITE_WRITE_PEEK

#define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c

Definition at line 1717 of file tg3.h.

FTQ_DMA_HIGH_WRITE_CTL

#define FTQ_DMA_HIGH_WRITE_CTL   0x00005c70

Definition at line 1718 of file tg3.h.

FTQ_DMA_HIGH_WRITE_FULL_CNT

#define FTQ_DMA_HIGH_WRITE_FULL_CNT   0x00005c74

Definition at line 1719 of file tg3.h.

FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ

#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ   0x00005c78

Definition at line 1720 of file tg3.h.

Referenced by tg3_do_test_dma().

FTQ_DMA_HIGH_WRITE_WRITE_PEEK

#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c

Definition at line 1721 of file tg3.h.

FTQ_SWTYPE1_CTL

#define FTQ_SWTYPE1_CTL   0x00005c80

Definition at line 1722 of file tg3.h.

FTQ_SWTYPE1_FULL_CNT

#define FTQ_SWTYPE1_FULL_CNT   0x00005c84

Definition at line 1723 of file tg3.h.

FTQ_SWTYPE1_FIFO_ENQDEQ

#define FTQ_SWTYPE1_FIFO_ENQDEQ   0x00005c88

Definition at line 1724 of file tg3.h.

FTQ_SWTYPE1_WRITE_PEEK

#define FTQ_SWTYPE1_WRITE_PEEK   0x00005c8c

Definition at line 1725 of file tg3.h.

FTQ_SEND_DATA_COMP_CTL

#define FTQ_SEND_DATA_COMP_CTL   0x00005c90

Definition at line 1726 of file tg3.h.

FTQ_SEND_DATA_COMP_FULL_CNT

#define FTQ_SEND_DATA_COMP_FULL_CNT   0x00005c94

Definition at line 1727 of file tg3.h.

FTQ_SEND_DATA_COMP_FIFO_ENQDEQ

#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ   0x00005c98

Definition at line 1728 of file tg3.h.

FTQ_SEND_DATA_COMP_WRITE_PEEK

#define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c

Definition at line 1729 of file tg3.h.

FTQ_HOST_COAL_CTL

#define FTQ_HOST_COAL_CTL   0x00005ca0

Definition at line 1730 of file tg3.h.

FTQ_HOST_COAL_FULL_CNT

#define FTQ_HOST_COAL_FULL_CNT   0x00005ca4

Definition at line 1731 of file tg3.h.

FTQ_HOST_COAL_FIFO_ENQDEQ

#define FTQ_HOST_COAL_FIFO_ENQDEQ   0x00005ca8

Definition at line 1732 of file tg3.h.

FTQ_HOST_COAL_WRITE_PEEK

#define FTQ_HOST_COAL_WRITE_PEEK   0x00005cac

Definition at line 1733 of file tg3.h.

FTQ_MAC_TX_CTL

#define FTQ_MAC_TX_CTL   0x00005cb0

Definition at line 1734 of file tg3.h.

FTQ_MAC_TX_FULL_CNT

#define FTQ_MAC_TX_FULL_CNT   0x00005cb4

Definition at line 1735 of file tg3.h.

FTQ_MAC_TX_FIFO_ENQDEQ

#define FTQ_MAC_TX_FIFO_ENQDEQ   0x00005cb8

Definition at line 1736 of file tg3.h.

FTQ_MAC_TX_WRITE_PEEK

#define FTQ_MAC_TX_WRITE_PEEK   0x00005cbc

Definition at line 1737 of file tg3.h.

FTQ_MB_FREE_CTL

#define FTQ_MB_FREE_CTL   0x00005cc0

Definition at line 1738 of file tg3.h.

FTQ_MB_FREE_FULL_CNT

#define FTQ_MB_FREE_FULL_CNT   0x00005cc4

Definition at line 1739 of file tg3.h.

FTQ_MB_FREE_FIFO_ENQDEQ

#define FTQ_MB_FREE_FIFO_ENQDEQ   0x00005cc8

Definition at line 1740 of file tg3.h.

FTQ_MB_FREE_WRITE_PEEK

#define FTQ_MB_FREE_WRITE_PEEK   0x00005ccc

Definition at line 1741 of file tg3.h.

FTQ_RCVBD_COMP_CTL

#define FTQ_RCVBD_COMP_CTL   0x00005cd0

Definition at line 1742 of file tg3.h.

FTQ_RCVBD_COMP_FULL_CNT

#define FTQ_RCVBD_COMP_FULL_CNT   0x00005cd4

Definition at line 1743 of file tg3.h.

FTQ_RCVBD_COMP_FIFO_ENQDEQ

#define FTQ_RCVBD_COMP_FIFO_ENQDEQ   0x00005cd8

Definition at line 1744 of file tg3.h.

Referenced by tg3_do_test_dma().

FTQ_RCVBD_COMP_WRITE_PEEK

#define FTQ_RCVBD_COMP_WRITE_PEEK   0x00005cdc

Definition at line 1745 of file tg3.h.

FTQ_RCVLST_PLMT_CTL

#define FTQ_RCVLST_PLMT_CTL   0x00005ce0

Definition at line 1746 of file tg3.h.

FTQ_RCVLST_PLMT_FULL_CNT

#define FTQ_RCVLST_PLMT_FULL_CNT   0x00005ce4

Definition at line 1747 of file tg3.h.

FTQ_RCVLST_PLMT_FIFO_ENQDEQ

#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ   0x00005ce8

Definition at line 1748 of file tg3.h.

FTQ_RCVLST_PLMT_WRITE_PEEK

#define FTQ_RCVLST_PLMT_WRITE_PEEK   0x00005cec

Definition at line 1749 of file tg3.h.

FTQ_RCVDATA_INI_CTL

#define FTQ_RCVDATA_INI_CTL   0x00005cf0

Definition at line 1750 of file tg3.h.

FTQ_RCVDATA_INI_FULL_CNT

#define FTQ_RCVDATA_INI_FULL_CNT   0x00005cf4

Definition at line 1751 of file tg3.h.

FTQ_RCVDATA_INI_FIFO_ENQDEQ

#define FTQ_RCVDATA_INI_FIFO_ENQDEQ   0x00005cf8

Definition at line 1752 of file tg3.h.

FTQ_RCVDATA_INI_WRITE_PEEK

#define FTQ_RCVDATA_INI_WRITE_PEEK   0x00005cfc

Definition at line 1753 of file tg3.h.

FTQ_RCVDATA_COMP_CTL

#define FTQ_RCVDATA_COMP_CTL   0x00005d00

Definition at line 1754 of file tg3.h.

FTQ_RCVDATA_COMP_FULL_CNT

#define FTQ_RCVDATA_COMP_FULL_CNT   0x00005d04

Definition at line 1755 of file tg3.h.

FTQ_RCVDATA_COMP_FIFO_ENQDEQ

#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ   0x00005d08

Definition at line 1756 of file tg3.h.

Referenced by tg3_do_test_dma().

FTQ_RCVDATA_COMP_WRITE_PEEK

#define FTQ_RCVDATA_COMP_WRITE_PEEK   0x00005d0c

Definition at line 1757 of file tg3.h.

FTQ_SWTYPE2_CTL

#define FTQ_SWTYPE2_CTL   0x00005d10

Definition at line 1758 of file tg3.h.

FTQ_SWTYPE2_FULL_CNT

#define FTQ_SWTYPE2_FULL_CNT   0x00005d14

Definition at line 1759 of file tg3.h.

FTQ_SWTYPE2_FIFO_ENQDEQ

#define FTQ_SWTYPE2_FIFO_ENQDEQ   0x00005d18

Definition at line 1760 of file tg3.h.

FTQ_SWTYPE2_WRITE_PEEK

#define FTQ_SWTYPE2_WRITE_PEEK   0x00005d1c

Definition at line 1761 of file tg3.h.

MSGINT_MODE

#define MSGINT_MODE   0x00006000

Definition at line 1765 of file tg3.h.

MSGINT_MODE_RESET

#define MSGINT_MODE_RESET   0x00000001

Definition at line 1766 of file tg3.h.

MSGINT_MODE_ENABLE

#define MSGINT_MODE_ENABLE   0x00000002

Definition at line 1767 of file tg3.h.

MSGINT_MODE_ONE_SHOT_DISABLE

#define MSGINT_MODE_ONE_SHOT_DISABLE   0x00000020

Definition at line 1768 of file tg3.h.

MSGINT_MODE_MULTIVEC_EN

#define MSGINT_MODE_MULTIVEC_EN   0x00000080

Definition at line 1769 of file tg3.h.

MSGINT_STATUS

#define MSGINT_STATUS   0x00006004

Definition at line 1770 of file tg3.h.

MSGINT_STATUS_MSI_REQ

#define MSGINT_STATUS_MSI_REQ   0x00000001

Definition at line 1771 of file tg3.h.

MSGINT_FIFO

#define MSGINT_FIFO   0x00006008

Definition at line 1772 of file tg3.h.

DMAC_MODE

#define DMAC_MODE   0x00006400

Definition at line 1776 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_reset_hw(), and tg3_stop_block().

DMAC_MODE_RESET

#define DMAC_MODE_RESET   0x00000001

Definition at line 1777 of file tg3.h.

DMAC_MODE_ENABLE

#define DMAC_MODE_ENABLE   0x00000002

Definition at line 1778 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_reset_hw().

GRC_MODE

#define GRC_MODE   0x00006800

Definition at line 1782 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_reset_hw().

GRC_MODE_UPD_ON_COAL

#define GRC_MODE_UPD_ON_COAL   0x00000001

Definition at line 1783 of file tg3.h.

GRC_MODE_BSWAP_NONFRM_DATA

#define GRC_MODE_BSWAP_NONFRM_DATA   0x00000002

Definition at line 1784 of file tg3.h.

Referenced by tg3_init_one().

GRC_MODE_WSWAP_NONFRM_DATA

#define GRC_MODE_WSWAP_NONFRM_DATA   0x00000004

Definition at line 1785 of file tg3.h.

Referenced by tg3_init_one().

GRC_MODE_BSWAP_DATA

#define GRC_MODE_BSWAP_DATA   0x00000010

Definition at line 1786 of file tg3.h.

Referenced by tg3_init_one().

GRC_MODE_WSWAP_DATA

#define GRC_MODE_WSWAP_DATA   0x00000020

Definition at line 1787 of file tg3.h.

Referenced by tg3_init_one().

GRC_MODE_BYTE_SWAP_B2HRX_DATA

#define GRC_MODE_BYTE_SWAP_B2HRX_DATA   0x00000040

Definition at line 1788 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MODE_WORD_SWAP_B2HRX_DATA

#define GRC_MODE_WORD_SWAP_B2HRX_DATA   0x00000080

Definition at line 1789 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MODE_SPLITHDR

#define GRC_MODE_SPLITHDR   0x00000100

Definition at line 1790 of file tg3.h.

GRC_MODE_NOFRM_CRACKING

#define GRC_MODE_NOFRM_CRACKING   0x00000200

Definition at line 1791 of file tg3.h.

GRC_MODE_INCL_CRC

#define GRC_MODE_INCL_CRC   0x00000400

Definition at line 1792 of file tg3.h.

GRC_MODE_ALLOW_BAD_FRMS

#define GRC_MODE_ALLOW_BAD_FRMS   0x00000800

Definition at line 1793 of file tg3.h.

GRC_MODE_NOIRQ_ON_SENDS

#define GRC_MODE_NOIRQ_ON_SENDS   0x00002000

Definition at line 1794 of file tg3.h.

GRC_MODE_NOIRQ_ON_RCV

#define GRC_MODE_NOIRQ_ON_RCV   0x00004000

Definition at line 1795 of file tg3.h.

GRC_MODE_FORCE_PCI32BIT

#define GRC_MODE_FORCE_PCI32BIT   0x00008000

Definition at line 1796 of file tg3.h.

GRC_MODE_B2HRX_ENABLE

#define GRC_MODE_B2HRX_ENABLE   0x00008000

Definition at line 1797 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MODE_HOST_STACKUP

#define GRC_MODE_HOST_STACKUP   0x00010000

Definition at line 1798 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_MODE_HOST_SENDBDS

#define GRC_MODE_HOST_SENDBDS   0x00020000

Definition at line 1799 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_HTX2B_ENABLE

#define GRC_MODE_HTX2B_ENABLE   0x00040000

Definition at line 1800 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MODE_NO_TX_PHDR_CSUM

#define GRC_MODE_NO_TX_PHDR_CSUM   0x00100000

Definition at line 1801 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_NVRAM_WR_ENABLE

#define GRC_MODE_NVRAM_WR_ENABLE   0x00200000

Definition at line 1802 of file tg3.h.

GRC_MODE_PCIE_TL_SEL

#define GRC_MODE_PCIE_TL_SEL   0x00000000

Definition at line 1803 of file tg3.h.

GRC_MODE_PCIE_PL_SEL

#define GRC_MODE_PCIE_PL_SEL   0x00400000

Definition at line 1804 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_NO_RX_PHDR_CSUM

#define GRC_MODE_NO_RX_PHDR_CSUM   0x00800000

Definition at line 1805 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_IRQ_ON_TX_CPU_ATTN

#define GRC_MODE_IRQ_ON_TX_CPU_ATTN   0x01000000

Definition at line 1806 of file tg3.h.

GRC_MODE_IRQ_ON_RX_CPU_ATTN

#define GRC_MODE_IRQ_ON_RX_CPU_ATTN   0x02000000

Definition at line 1807 of file tg3.h.

GRC_MODE_IRQ_ON_MAC_ATTN

#define GRC_MODE_IRQ_ON_MAC_ATTN   0x04000000

Definition at line 1808 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_IRQ_ON_DMA_ATTN

#define GRC_MODE_IRQ_ON_DMA_ATTN   0x08000000

Definition at line 1809 of file tg3.h.

GRC_MODE_IRQ_ON_FLOW_ATTN

#define GRC_MODE_IRQ_ON_FLOW_ATTN   0x10000000

Definition at line 1810 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MODE_4X_NIC_SEND_RINGS

#define GRC_MODE_4X_NIC_SEND_RINGS   0x20000000

Definition at line 1811 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_PCIE_DL_SEL

#define GRC_MODE_PCIE_DL_SEL   0x20000000

Definition at line 1812 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MODE_MCAST_FRM_ENABLE

#define GRC_MODE_MCAST_FRM_ENABLE   0x40000000

Definition at line 1813 of file tg3.h.

GRC_MODE_PCIE_HI_1K_EN

#define GRC_MODE_PCIE_HI_1K_EN   0x80000000

Definition at line 1814 of file tg3.h.

GRC_MODE_PCIE_PORT_MASK

#define GRC_MODE_PCIE_PORT_MASK

Value:

                                         (GRC_MODE_PCIE_TL_SEL | \
                                         GRC_MODE_PCIE_PL_SEL | \
                                         GRC_MODE_PCIE_DL_SEL | \
                                         GRC_MODE_PCIE_HI_1K_EN)

Definition at line 1815 of file tg3.h.

#define  GRC_MODE_PCIE_PORT_MASK        (GRC_MODE_PCIE_TL_SEL | \
                                         GRC_MODE_PCIE_PL_SEL | \
                                         GRC_MODE_PCIE_DL_SEL | \
                                         GRC_MODE_PCIE_HI_1K_EN)

Referenced by tg3_reset_hw().

GRC_MISC_CFG

#define GRC_MISC_CFG   0x00006804

Definition at line 1819 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_phy_reset(), and tg3_reset_hw().

GRC_MISC_CFG_CORECLK_RESET

#define GRC_MISC_CFG_CORECLK_RESET   0x00000001

Definition at line 1820 of file tg3.h.

Referenced by tg3_chip_reset().

GRC_MISC_CFG_PRESCALAR_MASK

#define GRC_MISC_CFG_PRESCALAR_MASK   0x000000fe

Definition at line 1821 of file tg3.h.

GRC_MISC_CFG_PRESCALAR_SHIFT

#define GRC_MISC_CFG_PRESCALAR_SHIFT   1

Definition at line 1822 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_MISC_CFG_BOARD_ID_MASK

#define GRC_MISC_CFG_BOARD_ID_MASK   0x0001e000

Definition at line 1823 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MISC_CFG_BOARD_ID_5700

#define GRC_MISC_CFG_BOARD_ID_5700   0x0001e000

Definition at line 1824 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5701

#define GRC_MISC_CFG_BOARD_ID_5701   0x00000000

Definition at line 1825 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5702FE

#define GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000

Definition at line 1826 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5703

#define GRC_MISC_CFG_BOARD_ID_5703   0x00000000

Definition at line 1827 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5703S

#define GRC_MISC_CFG_BOARD_ID_5703S   0x00002000

Definition at line 1828 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5704

#define GRC_MISC_CFG_BOARD_ID_5704   0x00000000

Definition at line 1829 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5704CIOBE

#define GRC_MISC_CFG_BOARD_ID_5704CIOBE   0x00004000

Definition at line 1830 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5704_A2

#define GRC_MISC_CFG_BOARD_ID_5704_A2   0x00008000

Definition at line 1831 of file tg3.h.

GRC_MISC_CFG_BOARD_ID_5788

#define GRC_MISC_CFG_BOARD_ID_5788   0x00010000

Definition at line 1832 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MISC_CFG_BOARD_ID_5788M

#define GRC_MISC_CFG_BOARD_ID_5788M   0x00018000

Definition at line 1833 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_MISC_CFG_BOARD_ID_AC91002A1

#define GRC_MISC_CFG_BOARD_ID_AC91002A1   0x00018000

Definition at line 1834 of file tg3.h.

GRC_MISC_CFG_EPHY_IDDQ

#define GRC_MISC_CFG_EPHY_IDDQ   0x00200000

Definition at line 1835 of file tg3.h.

Referenced by tg3_phy_reset().

GRC_MISC_CFG_KEEP_GPHY_POWER

#define GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000

Definition at line 1836 of file tg3.h.

Referenced by tg3_chip_reset().

GRC_LOCAL_CTRL

#define GRC_LOCAL_CTRL   0x00006808

Definition at line 1837 of file tg3.h.

Referenced by tg3_enable_ints(), tg3_reset_hw(), and tg3_set_power_state_0().

GRC_LCLCTRL_INT_ACTIVE

#define GRC_LCLCTRL_INT_ACTIVE   0x00000001

Definition at line 1838 of file tg3.h.

GRC_LCLCTRL_CLEARINT

#define GRC_LCLCTRL_CLEARINT   0x00000002

Definition at line 1839 of file tg3.h.

Referenced by tg3_write_indirect_mbox().

GRC_LCLCTRL_SETINT

#define GRC_LCLCTRL_SETINT   0x00000004

Definition at line 1840 of file tg3.h.

Referenced by tg3_enable_ints().

GRC_LCLCTRL_INT_ON_ATTN

#define GRC_LCLCTRL_INT_ON_ATTN   0x00000008

Definition at line 1841 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_LCLCTRL_GPIO_UART_SEL

#define GRC_LCLCTRL_GPIO_UART_SEL   0x00000010 /* 5755 only */

Definition at line 1842 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_USE_SIG_DETECT

#define GRC_LCLCTRL_USE_SIG_DETECT   0x00000010 /* 5714/5780 only */

Definition at line 1843 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_LCLCTRL_USE_EXT_SIG_DETECT

#define GRC_LCLCTRL_USE_EXT_SIG_DETECT   0x00000020 /* 5714/5780 only */

Definition at line 1844 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_LCLCTRL_GPIO_INPUT3

#define GRC_LCLCTRL_GPIO_INPUT3   0x00000020

Definition at line 1845 of file tg3.h.

GRC_LCLCTRL_GPIO_OE3

#define GRC_LCLCTRL_GPIO_OE3   0x00000040

Definition at line 1846 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_GPIO_OUTPUT3

#define GRC_LCLCTRL_GPIO_OUTPUT3   0x00000080

Definition at line 1847 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_LCLCTRL_GPIO_INPUT0

#define GRC_LCLCTRL_GPIO_INPUT0   0x00000100

Definition at line 1848 of file tg3.h.

GRC_LCLCTRL_GPIO_INPUT1

#define GRC_LCLCTRL_GPIO_INPUT1   0x00000200

Definition at line 1849 of file tg3.h.

GRC_LCLCTRL_GPIO_INPUT2

#define GRC_LCLCTRL_GPIO_INPUT2   0x00000400

Definition at line 1850 of file tg3.h.

GRC_LCLCTRL_GPIO_OE0

#define GRC_LCLCTRL_GPIO_OE0   0x00000800

Definition at line 1851 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_GPIO_OE1

#define GRC_LCLCTRL_GPIO_OE1   0x00001000

Definition at line 1852 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_GPIO_OE2

#define GRC_LCLCTRL_GPIO_OE2   0x00002000

Definition at line 1853 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_LCLCTRL_GPIO_OUTPUT0

#define GRC_LCLCTRL_GPIO_OUTPUT0   0x00004000

Definition at line 1854 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_GPIO_OUTPUT1

#define GRC_LCLCTRL_GPIO_OUTPUT1   0x00008000

Definition at line 1855 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_reset_hw().

GRC_LCLCTRL_GPIO_OUTPUT2

#define GRC_LCLCTRL_GPIO_OUTPUT2   0x00010000

Definition at line 1856 of file tg3.h.

Referenced by tg3_reset_hw().

GRC_LCLCTRL_EXTMEM_ENABLE

#define GRC_LCLCTRL_EXTMEM_ENABLE   0x00020000

Definition at line 1857 of file tg3.h.

GRC_LCLCTRL_MEMSZ_MASK

#define GRC_LCLCTRL_MEMSZ_MASK   0x001c0000

Definition at line 1858 of file tg3.h.

GRC_LCLCTRL_MEMSZ_256K

#define GRC_LCLCTRL_MEMSZ_256K   0x00000000

Definition at line 1859 of file tg3.h.

GRC_LCLCTRL_MEMSZ_512K

#define GRC_LCLCTRL_MEMSZ_512K   0x00040000

Definition at line 1860 of file tg3.h.

GRC_LCLCTRL_MEMSZ_1M

#define GRC_LCLCTRL_MEMSZ_1M   0x00080000

Definition at line 1861 of file tg3.h.

GRC_LCLCTRL_MEMSZ_2M

#define GRC_LCLCTRL_MEMSZ_2M   0x000c0000

Definition at line 1862 of file tg3.h.

GRC_LCLCTRL_MEMSZ_4M

#define GRC_LCLCTRL_MEMSZ_4M   0x00100000

Definition at line 1863 of file tg3.h.

GRC_LCLCTRL_MEMSZ_8M

#define GRC_LCLCTRL_MEMSZ_8M   0x00140000

Definition at line 1864 of file tg3.h.

GRC_LCLCTRL_MEMSZ_16M

#define GRC_LCLCTRL_MEMSZ_16M   0x00180000

Definition at line 1865 of file tg3.h.

GRC_LCLCTRL_BANK_SELECT

#define GRC_LCLCTRL_BANK_SELECT   0x00200000

Definition at line 1866 of file tg3.h.

GRC_LCLCTRL_SSRAM_TYPE

#define GRC_LCLCTRL_SSRAM_TYPE   0x00400000

Definition at line 1867 of file tg3.h.

GRC_LCLCTRL_AUTO_SEEPROM

#define GRC_LCLCTRL_AUTO_SEEPROM   0x01000000

Definition at line 1868 of file tg3.h.

Referenced by tg3_get_invariants().

GRC_TIMER

#define GRC_TIMER   0x0000680c

Definition at line 1869 of file tg3.h.

GRC_RX_CPU_EVENT

#define GRC_RX_CPU_EVENT   0x00006810

Definition at line 1870 of file tg3.h.

Referenced by tg3_generate_fw_event(), and tg3_wait_for_event_ack().

GRC_RX_CPU_DRIVER_EVENT

#define GRC_RX_CPU_DRIVER_EVENT   0x00004000

Definition at line 1871 of file tg3.h.

Referenced by tg3_generate_fw_event(), and tg3_wait_for_event_ack().

GRC_RX_TIMER_REF

#define GRC_RX_TIMER_REF   0x00006814

Definition at line 1872 of file tg3.h.

GRC_RX_CPU_SEM

#define GRC_RX_CPU_SEM   0x00006818

Definition at line 1873 of file tg3.h.

GRC_REMOTE_RX_CPU_ATTN

#define GRC_REMOTE_RX_CPU_ATTN   0x0000681c

Definition at line 1874 of file tg3.h.

GRC_TX_CPU_EVENT

#define GRC_TX_CPU_EVENT   0x00006820

Definition at line 1875 of file tg3.h.

GRC_TX_TIMER_REF

#define GRC_TX_TIMER_REF   0x00006824

Definition at line 1876 of file tg3.h.

GRC_TX_CPU_SEM

#define GRC_TX_CPU_SEM   0x00006828

Definition at line 1877 of file tg3.h.

GRC_REMOTE_TX_CPU_ATTN

#define GRC_REMOTE_TX_CPU_ATTN   0x0000682c

Definition at line 1878 of file tg3.h.

GRC_MEM_POWER_UP

#define GRC_MEM_POWER_UP   0x00006830 /* 64-bit */

Definition at line 1879 of file tg3.h.

GRC_EEPROM_ADDR

#define GRC_EEPROM_ADDR   0x00006838

Definition at line 1880 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_WRITE

#define EEPROM_ADDR_WRITE   0x00000000

Definition at line 1881 of file tg3.h.

EEPROM_ADDR_READ

#define EEPROM_ADDR_READ   0x80000000

Definition at line 1882 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_COMPLETE

#define EEPROM_ADDR_COMPLETE   0x40000000

Definition at line 1883 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_FSM_RESET

#define EEPROM_ADDR_FSM_RESET   0x20000000

Definition at line 1884 of file tg3.h.

EEPROM_ADDR_DEVID_MASK

#define EEPROM_ADDR_DEVID_MASK   0x1c000000

Definition at line 1885 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_DEVID_SHIFT

#define EEPROM_ADDR_DEVID_SHIFT   26

Definition at line 1886 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_START

#define EEPROM_ADDR_START   0x02000000

Definition at line 1887 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_CLKPERD_SHIFT

#define EEPROM_ADDR_CLKPERD_SHIFT   16

Definition at line 1888 of file tg3.h.

EEPROM_ADDR_ADDR_MASK

#define EEPROM_ADDR_ADDR_MASK   0x0000ffff

Definition at line 1889 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_ADDR_ADDR_SHIFT

#define EEPROM_ADDR_ADDR_SHIFT   0

Definition at line 1890 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

EEPROM_DEFAULT_CLOCK_PERIOD

#define EEPROM_DEFAULT_CLOCK_PERIOD   0x60

Definition at line 1891 of file tg3.h.

EEPROM_CHIP_SIZE

#define EEPROM_CHIP_SIZE   (64 * 1024)

Definition at line 1892 of file tg3.h.

GRC_EEPROM_DATA

#define GRC_EEPROM_DATA   0x0000683c

Definition at line 1893 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

GRC_EEPROM_CTRL

#define GRC_EEPROM_CTRL   0x00006840

Definition at line 1894 of file tg3.h.

GRC_MDI_CTRL

#define GRC_MDI_CTRL   0x00006844

Definition at line 1895 of file tg3.h.

GRC_SEEPROM_DELAY

#define GRC_SEEPROM_DELAY   0x00006848

Definition at line 1896 of file tg3.h.

GRC_VCPU_EXT_CTRL

#define GRC_VCPU_EXT_CTRL   0x00006890

Definition at line 1898 of file tg3.h.

Referenced by tg3_chip_reset().

GRC_VCPU_EXT_CTRL_HALT_CPU

#define GRC_VCPU_EXT_CTRL_HALT_CPU   0x00400000

Definition at line 1899 of file tg3.h.

Referenced by tg3_chip_reset().

GRC_VCPU_EXT_CTRL_DISABLE_WOL

#define GRC_VCPU_EXT_CTRL_DISABLE_WOL   0x20000000

Definition at line 1900 of file tg3.h.

GRC_FASTBOOT_PC

#define GRC_FASTBOOT_PC   0x00006894 /* 5752, 5755, 5787 */

Definition at line 1901 of file tg3.h.

Referenced by tg3_chip_reset().

NVRAM_CMD

#define NVRAM_CMD   0x00007000

Definition at line 1906 of file tg3.h.

Referenced by tg3_get_device_address(), and tg3_nvram_exec_cmd().

NVRAM_CMD_RESET

#define NVRAM_CMD_RESET   0x00000001

Definition at line 1907 of file tg3.h.

Referenced by tg3_get_device_address().

NVRAM_CMD_DONE

#define NVRAM_CMD_DONE   0x00000008

Definition at line 1908 of file tg3.h.

Referenced by tg3_nvram_exec_cmd(), and tg3_nvram_read().

NVRAM_CMD_GO

#define NVRAM_CMD_GO   0x00000010

Definition at line 1909 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_CMD_WR

#define NVRAM_CMD_WR   0x00000020

Definition at line 1910 of file tg3.h.

NVRAM_CMD_RD

#define NVRAM_CMD_RD   0x00000000

Definition at line 1911 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_CMD_ERASE

#define NVRAM_CMD_ERASE   0x00000040

Definition at line 1912 of file tg3.h.

NVRAM_CMD_FIRST

#define NVRAM_CMD_FIRST   0x00000080

Definition at line 1913 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_CMD_LAST

#define NVRAM_CMD_LAST   0x00000100

Definition at line 1914 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_CMD_WREN

#define NVRAM_CMD_WREN   0x00010000

Definition at line 1915 of file tg3.h.

NVRAM_CMD_WRDI

#define NVRAM_CMD_WRDI   0x00020000

Definition at line 1916 of file tg3.h.

NVRAM_STAT

#define NVRAM_STAT   0x00007004

Definition at line 1917 of file tg3.h.

NVRAM_WRDATA

#define NVRAM_WRDATA   0x00007008

Definition at line 1918 of file tg3.h.

NVRAM_ADDR

#define NVRAM_ADDR   0x0000700c

Definition at line 1919 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_ADDR_MSK

#define NVRAM_ADDR_MSK   0x00ffffff

Definition at line 1920 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_RDDATA

#define NVRAM_RDDATA   0x00007010

Definition at line 1921 of file tg3.h.

Referenced by tg3_nvram_read().

NVRAM_CFG1

#define NVRAM_CFG1   0x00007014

Definition at line 1922 of file tg3.h.

NVRAM_CFG1_FLASHIF_ENAB

#define NVRAM_CFG1_FLASHIF_ENAB   0x00000001

Definition at line 1923 of file tg3.h.

NVRAM_CFG1_BUFFERED_MODE

#define NVRAM_CFG1_BUFFERED_MODE   0x00000002

Definition at line 1924 of file tg3.h.

NVRAM_CFG1_PASS_THRU

#define NVRAM_CFG1_PASS_THRU   0x00000004

Definition at line 1925 of file tg3.h.

NVRAM_CFG1_STATUS_BITS

#define NVRAM_CFG1_STATUS_BITS   0x00000070

Definition at line 1926 of file tg3.h.

NVRAM_CFG1_BIT_BANG

#define NVRAM_CFG1_BIT_BANG   0x00000008

Definition at line 1927 of file tg3.h.

NVRAM_CFG1_FLASH_SIZE

#define NVRAM_CFG1_FLASH_SIZE   0x02000000

Definition at line 1928 of file tg3.h.

NVRAM_CFG1_COMPAT_BYPASS

#define NVRAM_CFG1_COMPAT_BYPASS   0x80000000

Definition at line 1929 of file tg3.h.

NVRAM_CFG1_VENDOR_MASK

#define NVRAM_CFG1_VENDOR_MASK   0x03000003

Definition at line 1930 of file tg3.h.

FLASH_VENDOR_ATMEL_EEPROM

#define FLASH_VENDOR_ATMEL_EEPROM   0x02000000

Definition at line 1931 of file tg3.h.

FLASH_VENDOR_ATMEL_FLASH_BUFFERED

#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED   0x02000003

Definition at line 1932 of file tg3.h.

FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED

#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED   0x00000003

Definition at line 1933 of file tg3.h.

FLASH_VENDOR_ST

#define FLASH_VENDOR_ST   0x03000001

Definition at line 1934 of file tg3.h.

FLASH_VENDOR_SAIFUN

#define FLASH_VENDOR_SAIFUN   0x01000003

Definition at line 1935 of file tg3.h.

FLASH_VENDOR_SST_SMALL

#define FLASH_VENDOR_SST_SMALL   0x00000001

Definition at line 1936 of file tg3.h.

FLASH_VENDOR_SST_LARGE

#define FLASH_VENDOR_SST_LARGE   0x02000001

Definition at line 1937 of file tg3.h.

NVRAM_CFG1_5752VENDOR_MASK

#define NVRAM_CFG1_5752VENDOR_MASK   0x03c00003

Definition at line 1938 of file tg3.h.

FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ

#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ   0x00000000

Definition at line 1939 of file tg3.h.

FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ

#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ   0x02000000

Definition at line 1940 of file tg3.h.

FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED

#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED   0x02000003

Definition at line 1941 of file tg3.h.

FLASH_5752VENDOR_ST_M45PE10

#define FLASH_5752VENDOR_ST_M45PE10   0x02400000

Definition at line 1942 of file tg3.h.

FLASH_5752VENDOR_ST_M45PE20

#define FLASH_5752VENDOR_ST_M45PE20   0x02400002

Definition at line 1943 of file tg3.h.

FLASH_5752VENDOR_ST_M45PE40

#define FLASH_5752VENDOR_ST_M45PE40   0x02400001

Definition at line 1944 of file tg3.h.

FLASH_5755VENDOR_ATMEL_FLASH_1

#define FLASH_5755VENDOR_ATMEL_FLASH_1   0x03400001

Definition at line 1945 of file tg3.h.

FLASH_5755VENDOR_ATMEL_FLASH_2

#define FLASH_5755VENDOR_ATMEL_FLASH_2   0x03400002

Definition at line 1946 of file tg3.h.

FLASH_5755VENDOR_ATMEL_FLASH_3

#define FLASH_5755VENDOR_ATMEL_FLASH_3   0x03400000

Definition at line 1947 of file tg3.h.

FLASH_5755VENDOR_ATMEL_FLASH_4

#define FLASH_5755VENDOR_ATMEL_FLASH_4   0x00000003

Definition at line 1948 of file tg3.h.

FLASH_5755VENDOR_ATMEL_FLASH_5

#define FLASH_5755VENDOR_ATMEL_FLASH_5   0x02000003

Definition at line 1949 of file tg3.h.

FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ

#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ   0x03c00003

Definition at line 1950 of file tg3.h.

FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ

#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ   0x03c00002

Definition at line 1951 of file tg3.h.

FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ

#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ   0x03000003

Definition at line 1952 of file tg3.h.

FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ

#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ   0x03000002

Definition at line 1953 of file tg3.h.

FLASH_5787VENDOR_MICRO_EEPROM_64KHZ

#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ   0x03000000

Definition at line 1954 of file tg3.h.

FLASH_5787VENDOR_MICRO_EEPROM_376KHZ

#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ   0x02000000

Definition at line 1955 of file tg3.h.

FLASH_5761VENDOR_ATMEL_MDB021D

#define FLASH_5761VENDOR_ATMEL_MDB021D   0x00800003

Definition at line 1956 of file tg3.h.

FLASH_5761VENDOR_ATMEL_MDB041D

#define FLASH_5761VENDOR_ATMEL_MDB041D   0x00800000

Definition at line 1957 of file tg3.h.

FLASH_5761VENDOR_ATMEL_MDB081D

#define FLASH_5761VENDOR_ATMEL_MDB081D   0x00800002

Definition at line 1958 of file tg3.h.

FLASH_5761VENDOR_ATMEL_MDB161D

#define FLASH_5761VENDOR_ATMEL_MDB161D   0x00800001

Definition at line 1959 of file tg3.h.

FLASH_5761VENDOR_ATMEL_ADB021D

#define FLASH_5761VENDOR_ATMEL_ADB021D   0x00000003

Definition at line 1960 of file tg3.h.

FLASH_5761VENDOR_ATMEL_ADB041D

#define FLASH_5761VENDOR_ATMEL_ADB041D   0x00000000

Definition at line 1961 of file tg3.h.

FLASH_5761VENDOR_ATMEL_ADB081D

#define FLASH_5761VENDOR_ATMEL_ADB081D   0x00000002

Definition at line 1962 of file tg3.h.

FLASH_5761VENDOR_ATMEL_ADB161D

#define FLASH_5761VENDOR_ATMEL_ADB161D   0x00000001

Definition at line 1963 of file tg3.h.

FLASH_5761VENDOR_ST_M_M45PE20

#define FLASH_5761VENDOR_ST_M_M45PE20   0x02800001

Definition at line 1964 of file tg3.h.

FLASH_5761VENDOR_ST_M_M45PE40

#define FLASH_5761VENDOR_ST_M_M45PE40   0x02800000

Definition at line 1965 of file tg3.h.

FLASH_5761VENDOR_ST_M_M45PE80

#define FLASH_5761VENDOR_ST_M_M45PE80   0x02800002

Definition at line 1966 of file tg3.h.

FLASH_5761VENDOR_ST_M_M45PE16

#define FLASH_5761VENDOR_ST_M_M45PE16   0x02800003

Definition at line 1967 of file tg3.h.

FLASH_5761VENDOR_ST_A_M45PE20

#define FLASH_5761VENDOR_ST_A_M45PE20   0x02000001

Definition at line 1968 of file tg3.h.

FLASH_5761VENDOR_ST_A_M45PE40

#define FLASH_5761VENDOR_ST_A_M45PE40   0x02000000

Definition at line 1969 of file tg3.h.

FLASH_5761VENDOR_ST_A_M45PE80

#define FLASH_5761VENDOR_ST_A_M45PE80   0x02000002

Definition at line 1970 of file tg3.h.

FLASH_5761VENDOR_ST_A_M45PE16

#define FLASH_5761VENDOR_ST_A_M45PE16   0x02000003

Definition at line 1971 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB011D

#define FLASH_57780VENDOR_ATMEL_AT45DB011D   0x00400000

Definition at line 1972 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB011B

#define FLASH_57780VENDOR_ATMEL_AT45DB011B   0x03400000

Definition at line 1973 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB021D

#define FLASH_57780VENDOR_ATMEL_AT45DB021D   0x00400002

Definition at line 1974 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB021B

#define FLASH_57780VENDOR_ATMEL_AT45DB021B   0x03400002

Definition at line 1975 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB041D

#define FLASH_57780VENDOR_ATMEL_AT45DB041D   0x00400001

Definition at line 1976 of file tg3.h.

FLASH_57780VENDOR_ATMEL_AT45DB041B

#define FLASH_57780VENDOR_ATMEL_AT45DB041B   0x03400001

Definition at line 1977 of file tg3.h.

FLASH_5717VENDOR_ATMEL_EEPROM

#define FLASH_5717VENDOR_ATMEL_EEPROM   0x02000001

Definition at line 1978 of file tg3.h.

FLASH_5717VENDOR_MICRO_EEPROM

#define FLASH_5717VENDOR_MICRO_EEPROM   0x02000003

Definition at line 1979 of file tg3.h.

FLASH_5717VENDOR_ATMEL_MDB011D

#define FLASH_5717VENDOR_ATMEL_MDB011D   0x01000001

Definition at line 1980 of file tg3.h.

FLASH_5717VENDOR_ATMEL_MDB021D

#define FLASH_5717VENDOR_ATMEL_MDB021D   0x01000003

Definition at line 1981 of file tg3.h.

FLASH_5717VENDOR_ST_M_M25PE10

#define FLASH_5717VENDOR_ST_M_M25PE10   0x02000000

Definition at line 1982 of file tg3.h.

FLASH_5717VENDOR_ST_M_M25PE20

#define FLASH_5717VENDOR_ST_M_M25PE20   0x02000002

Definition at line 1983 of file tg3.h.

FLASH_5717VENDOR_ST_M_M45PE10

#define FLASH_5717VENDOR_ST_M_M45PE10   0x00000001

Definition at line 1984 of file tg3.h.

FLASH_5717VENDOR_ST_M_M45PE20

#define FLASH_5717VENDOR_ST_M_M45PE20   0x00000003

Definition at line 1985 of file tg3.h.

FLASH_5717VENDOR_ATMEL_ADB011B

#define FLASH_5717VENDOR_ATMEL_ADB011B   0x01400000

Definition at line 1986 of file tg3.h.

FLASH_5717VENDOR_ATMEL_ADB021B

#define FLASH_5717VENDOR_ATMEL_ADB021B   0x01400002

Definition at line 1987 of file tg3.h.

FLASH_5717VENDOR_ATMEL_ADB011D

#define FLASH_5717VENDOR_ATMEL_ADB011D   0x01400001

Definition at line 1988 of file tg3.h.

FLASH_5717VENDOR_ATMEL_ADB021D

#define FLASH_5717VENDOR_ATMEL_ADB021D   0x01400003

Definition at line 1989 of file tg3.h.

FLASH_5717VENDOR_ST_A_M25PE10

#define FLASH_5717VENDOR_ST_A_M25PE10   0x02400000

Definition at line 1990 of file tg3.h.

FLASH_5717VENDOR_ST_A_M25PE20

#define FLASH_5717VENDOR_ST_A_M25PE20   0x02400002

Definition at line 1991 of file tg3.h.

FLASH_5717VENDOR_ST_A_M45PE10

#define FLASH_5717VENDOR_ST_A_M45PE10   0x02400001

Definition at line 1992 of file tg3.h.

FLASH_5717VENDOR_ST_A_M45PE20

#define FLASH_5717VENDOR_ST_A_M45PE20   0x02400003

Definition at line 1993 of file tg3.h.

FLASH_5717VENDOR_ATMEL_45USPT

#define FLASH_5717VENDOR_ATMEL_45USPT   0x03400000

Definition at line 1994 of file tg3.h.

FLASH_5717VENDOR_ST_25USPT

#define FLASH_5717VENDOR_ST_25USPT   0x03400002

Definition at line 1995 of file tg3.h.

FLASH_5717VENDOR_ST_45USPT

#define FLASH_5717VENDOR_ST_45USPT   0x03400001

Definition at line 1996 of file tg3.h.

FLASH_5720_EEPROM_HD

#define FLASH_5720_EEPROM_HD   0x00000001

Definition at line 1997 of file tg3.h.

FLASH_5720_EEPROM_LD

#define FLASH_5720_EEPROM_LD   0x00000003

Definition at line 1998 of file tg3.h.

FLASH_5720VENDOR_M_ATMEL_DB011D

#define FLASH_5720VENDOR_M_ATMEL_DB011D   0x01000000

Definition at line 1999 of file tg3.h.

FLASH_5720VENDOR_M_ATMEL_DB021D

#define FLASH_5720VENDOR_M_ATMEL_DB021D   0x01000002

Definition at line 2000 of file tg3.h.

FLASH_5720VENDOR_M_ATMEL_DB041D

#define FLASH_5720VENDOR_M_ATMEL_DB041D   0x01000001

Definition at line 2001 of file tg3.h.

FLASH_5720VENDOR_M_ATMEL_DB081D

#define FLASH_5720VENDOR_M_ATMEL_DB081D   0x01000003

Definition at line 2002 of file tg3.h.

FLASH_5720VENDOR_M_ST_M25PE10

#define FLASH_5720VENDOR_M_ST_M25PE10   0x02000000

Definition at line 2003 of file tg3.h.

FLASH_5720VENDOR_M_ST_M25PE20

#define FLASH_5720VENDOR_M_ST_M25PE20   0x02000002

Definition at line 2004 of file tg3.h.

FLASH_5720VENDOR_M_ST_M25PE40

#define FLASH_5720VENDOR_M_ST_M25PE40   0x02000001

Definition at line 2005 of file tg3.h.

FLASH_5720VENDOR_M_ST_M25PE80

#define FLASH_5720VENDOR_M_ST_M25PE80   0x02000003

Definition at line 2006 of file tg3.h.

FLASH_5720VENDOR_M_ST_M45PE10

#define FLASH_5720VENDOR_M_ST_M45PE10   0x03000000

Definition at line 2007 of file tg3.h.

FLASH_5720VENDOR_M_ST_M45PE20

#define FLASH_5720VENDOR_M_ST_M45PE20   0x03000002

Definition at line 2008 of file tg3.h.

FLASH_5720VENDOR_M_ST_M45PE40

#define FLASH_5720VENDOR_M_ST_M45PE40   0x03000001

Definition at line 2009 of file tg3.h.

FLASH_5720VENDOR_M_ST_M45PE80

#define FLASH_5720VENDOR_M_ST_M45PE80   0x03000003

Definition at line 2010 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB011B

#define FLASH_5720VENDOR_A_ATMEL_DB011B   0x01800000

Definition at line 2011 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB021B

#define FLASH_5720VENDOR_A_ATMEL_DB021B   0x01800002

Definition at line 2012 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB041B

#define FLASH_5720VENDOR_A_ATMEL_DB041B   0x01800001

Definition at line 2013 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB011D

#define FLASH_5720VENDOR_A_ATMEL_DB011D   0x01c00000

Definition at line 2014 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB021D

#define FLASH_5720VENDOR_A_ATMEL_DB021D   0x01c00002

Definition at line 2015 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB041D

#define FLASH_5720VENDOR_A_ATMEL_DB041D   0x01c00001

Definition at line 2016 of file tg3.h.

FLASH_5720VENDOR_A_ATMEL_DB081D

#define FLASH_5720VENDOR_A_ATMEL_DB081D   0x01c00003

Definition at line 2017 of file tg3.h.

FLASH_5720VENDOR_A_ST_M25PE10

#define FLASH_5720VENDOR_A_ST_M25PE10   0x02800000

Definition at line 2018 of file tg3.h.

FLASH_5720VENDOR_A_ST_M25PE20

#define FLASH_5720VENDOR_A_ST_M25PE20   0x02800002

Definition at line 2019 of file tg3.h.

FLASH_5720VENDOR_A_ST_M25PE40

#define FLASH_5720VENDOR_A_ST_M25PE40   0x02800001

Definition at line 2020 of file tg3.h.

FLASH_5720VENDOR_A_ST_M25PE80

#define FLASH_5720VENDOR_A_ST_M25PE80   0x02800003

Definition at line 2021 of file tg3.h.

FLASH_5720VENDOR_A_ST_M45PE10

#define FLASH_5720VENDOR_A_ST_M45PE10   0x02c00000

Definition at line 2022 of file tg3.h.

FLASH_5720VENDOR_A_ST_M45PE20

#define FLASH_5720VENDOR_A_ST_M45PE20   0x02c00002

Definition at line 2023 of file tg3.h.

FLASH_5720VENDOR_A_ST_M45PE40

#define FLASH_5720VENDOR_A_ST_M45PE40   0x02c00001

Definition at line 2024 of file tg3.h.

FLASH_5720VENDOR_A_ST_M45PE80

#define FLASH_5720VENDOR_A_ST_M45PE80   0x02c00003

Definition at line 2025 of file tg3.h.

FLASH_5720VENDOR_ATMEL_45USPT

#define FLASH_5720VENDOR_ATMEL_45USPT   0x03c00000

Definition at line 2026 of file tg3.h.

FLASH_5720VENDOR_ST_25USPT

#define FLASH_5720VENDOR_ST_25USPT   0x03c00002

Definition at line 2027 of file tg3.h.

FLASH_5720VENDOR_ST_45USPT

#define FLASH_5720VENDOR_ST_45USPT   0x03c00001

Definition at line 2028 of file tg3.h.

NVRAM_CFG1_5752PAGE_SIZE_MASK

#define NVRAM_CFG1_5752PAGE_SIZE_MASK   0x70000000

Definition at line 2029 of file tg3.h.

FLASH_5752PAGE_SIZE_256

#define FLASH_5752PAGE_SIZE_256   0x00000000

Definition at line 2030 of file tg3.h.

FLASH_5752PAGE_SIZE_512

#define FLASH_5752PAGE_SIZE_512   0x10000000

Definition at line 2031 of file tg3.h.

FLASH_5752PAGE_SIZE_1K

#define FLASH_5752PAGE_SIZE_1K   0x20000000

Definition at line 2032 of file tg3.h.

FLASH_5752PAGE_SIZE_2K

#define FLASH_5752PAGE_SIZE_2K   0x30000000

Definition at line 2033 of file tg3.h.

FLASH_5752PAGE_SIZE_4K

#define FLASH_5752PAGE_SIZE_4K   0x40000000

Definition at line 2034 of file tg3.h.

FLASH_5752PAGE_SIZE_264

#define FLASH_5752PAGE_SIZE_264   0x50000000

Definition at line 2035 of file tg3.h.

FLASH_5752PAGE_SIZE_528

#define FLASH_5752PAGE_SIZE_528   0x60000000

Definition at line 2036 of file tg3.h.

NVRAM_CFG2

#define NVRAM_CFG2   0x00007018

Definition at line 2037 of file tg3.h.

NVRAM_CFG3

#define NVRAM_CFG3   0x0000701c

Definition at line 2038 of file tg3.h.

NVRAM_SWARB

#define NVRAM_SWARB   0x00007020

Definition at line 2039 of file tg3.h.

Referenced by tg3_nvram_lock(), and tg3_nvram_unlock().

SWARB_REQ_SET0

#define SWARB_REQ_SET0   0x00000001

Definition at line 2040 of file tg3.h.

SWARB_REQ_SET1

#define SWARB_REQ_SET1   0x00000002

Definition at line 2041 of file tg3.h.

Referenced by tg3_nvram_lock().

SWARB_REQ_SET2

#define SWARB_REQ_SET2   0x00000004

Definition at line 2042 of file tg3.h.

SWARB_REQ_SET3

#define SWARB_REQ_SET3   0x00000008

Definition at line 2043 of file tg3.h.

SWARB_REQ_CLR0

#define SWARB_REQ_CLR0   0x00000010

Definition at line 2044 of file tg3.h.

SWARB_REQ_CLR1

#define SWARB_REQ_CLR1   0x00000020

Definition at line 2045 of file tg3.h.

Referenced by tg3_nvram_lock(), and tg3_nvram_unlock().

SWARB_REQ_CLR2

#define SWARB_REQ_CLR2   0x00000040

Definition at line 2046 of file tg3.h.

SWARB_REQ_CLR3

#define SWARB_REQ_CLR3   0x00000080

Definition at line 2047 of file tg3.h.

SWARB_GNT0

#define SWARB_GNT0   0x00000100

Definition at line 2048 of file tg3.h.

SWARB_GNT1

#define SWARB_GNT1   0x00000200

Definition at line 2049 of file tg3.h.

Referenced by tg3_nvram_lock().

SWARB_GNT2

#define SWARB_GNT2   0x00000400

Definition at line 2050 of file tg3.h.

SWARB_GNT3

#define SWARB_GNT3   0x00000800

Definition at line 2051 of file tg3.h.

SWARB_REQ0

#define SWARB_REQ0   0x00001000

Definition at line 2052 of file tg3.h.

SWARB_REQ1

#define SWARB_REQ1   0x00002000

Definition at line 2053 of file tg3.h.

SWARB_REQ2

#define SWARB_REQ2   0x00004000

Definition at line 2054 of file tg3.h.

SWARB_REQ3

#define SWARB_REQ3   0x00008000

Definition at line 2055 of file tg3.h.

NVRAM_ACCESS

#define NVRAM_ACCESS   0x00007024

Definition at line 2056 of file tg3.h.

Referenced by tg3_disable_nvram_access(), and tg3_enable_nvram_access().

ACCESS_ENABLE

#define ACCESS_ENABLE   0x00000001

Definition at line 2057 of file tg3.h.

Referenced by tg3_disable_nvram_access(), and tg3_enable_nvram_access().

ACCESS_WR_ENABLE

#define ACCESS_WR_ENABLE   0x00000002

Definition at line 2058 of file tg3.h.

NVRAM_WRITE1

#define NVRAM_WRITE1   0x00007028

Definition at line 2059 of file tg3.h.

NVRAM_ADDR_LOCKOUT

#define NVRAM_ADDR_LOCKOUT   0x00007030

Definition at line 2062 of file tg3.h.

OTP_MODE

#define OTP_MODE   0x00007500

Definition at line 2065 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_MODE_OTP_THRU_GRC

#define OTP_MODE_OTP_THRU_GRC   0x00000001

Definition at line 2066 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_CTRL

#define OTP_CTRL   0x00007504

Definition at line 2067 of file tg3.h.

Referenced by tg3_issue_otp_command().

OTP_CTRL_OTP_PROG_ENABLE

#define OTP_CTRL_OTP_PROG_ENABLE   0x00200000

Definition at line 2068 of file tg3.h.

OTP_CTRL_OTP_CMD_READ

#define OTP_CTRL_OTP_CMD_READ   0x00000000

Definition at line 2069 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_CTRL_OTP_CMD_INIT

#define OTP_CTRL_OTP_CMD_INIT   0x00000008

Definition at line 2070 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_CTRL_OTP_CMD_START

#define OTP_CTRL_OTP_CMD_START   0x00000001

Definition at line 2071 of file tg3.h.

Referenced by tg3_issue_otp_command().

OTP_STATUS

#define OTP_STATUS   0x00007508

Definition at line 2072 of file tg3.h.

Referenced by tg3_issue_otp_command().

OTP_STATUS_CMD_DONE

#define OTP_STATUS_CMD_DONE   0x00000001

Definition at line 2073 of file tg3.h.

Referenced by tg3_issue_otp_command().

OTP_ADDRESS

#define OTP_ADDRESS   0x0000750c

Definition at line 2074 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_ADDRESS_MAGIC1

#define OTP_ADDRESS_MAGIC1   0x000000a0

Definition at line 2075 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_ADDRESS_MAGIC2

#define OTP_ADDRESS_MAGIC2   0x00000080

Definition at line 2076 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

OTP_READ_DATA

#define OTP_READ_DATA   0x00007514

Definition at line 2079 of file tg3.h.

Referenced by tg3_read_otp_phycfg().

PCIE_TRANSACTION_CFG

#define PCIE_TRANSACTION_CFG   0x00007c04

Definition at line 2082 of file tg3.h.

PCIE_TRANS_CFG_1SHOT_MSI

#define PCIE_TRANS_CFG_1SHOT_MSI   0x20000000

Definition at line 2083 of file tg3.h.

PCIE_TRANS_CFG_LOM

#define PCIE_TRANS_CFG_LOM   0x00000020

Definition at line 2084 of file tg3.h.

PCIE_PWR_MGMT_THRESH

#define PCIE_PWR_MGMT_THRESH   0x00007d28

Definition at line 2087 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

PCIE_PWR_MGMT_L1_THRESH_MSK

#define PCIE_PWR_MGMT_L1_THRESH_MSK   0x0000ff00

Definition at line 2088 of file tg3.h.

Referenced by tg3_reset_hw(), and tg3_setup_phy().

PCIE_PWR_MGMT_L1_THRESH_4MS

#define PCIE_PWR_MGMT_L1_THRESH_4MS   0x0000ff00

Definition at line 2089 of file tg3.h.

Referenced by tg3_reset_hw().

PCIE_PWR_MGMT_EXT_ASPM_TMR_EN

#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN   0x01000000

Definition at line 2090 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_LNKCTL

#define TG3_PCIE_LNKCTL   0x00007d54

Definition at line 2093 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_reset_hw().

TG3_PCIE_LNKCTL_L1_PLL_PD_EN

#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN   0x00000008

Definition at line 2094 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_reset_hw().

TG3_PCIE_LNKCTL_L1_PLL_PD_DIS

#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS   0x00000080

Definition at line 2095 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_reset_hw().

TG3_PCIE_PHY_TSTCTL

#define TG3_PCIE_PHY_TSTCTL   0x00007e2c

Definition at line 2098 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_PCIE_PHY_TSTCTL_PCIE10

#define TG3_PCIE_PHY_TSTCTL_PCIE10   0x00000040

Definition at line 2099 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_PCIE_PHY_TSTCTL_PSCRAM

#define TG3_PCIE_PHY_TSTCTL_PSCRAM   0x00000020

Definition at line 2100 of file tg3.h.

Referenced by tg3_chip_reset().

TG3_PCIE_EIDLE_DELAY

#define TG3_PCIE_EIDLE_DELAY   0x00007e70

Definition at line 2102 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_EIDLE_DELAY_MASK

#define TG3_PCIE_EIDLE_DELAY_MASK   0x0000001f

Definition at line 2103 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_EIDLE_DELAY_13_CLKS

#define TG3_PCIE_EIDLE_DELAY_13_CLKS   0x0000000c

Definition at line 2104 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_TLDLPL_PORT

#define TG3_PCIE_TLDLPL_PORT   0x00007c00

Definition at line 2109 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_DL_LO_FTSMAX

#define TG3_PCIE_DL_LO_FTSMAX   0x0000000c

Definition at line 2110 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_DL_LO_FTSMAX_MSK

#define TG3_PCIE_DL_LO_FTSMAX_MSK   0x000000ff

Definition at line 2111 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_DL_LO_FTSMAX_VAL

#define TG3_PCIE_DL_LO_FTSMAX_VAL   0x0000002c

Definition at line 2112 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_PL_LO_PHYCTL1

#define TG3_PCIE_PL_LO_PHYCTL1   0x00000004

Definition at line 2113 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN

#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN   0x00001000

Definition at line 2114 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_PL_LO_PHYCTL5

#define TG3_PCIE_PL_LO_PHYCTL5   0x00000014

Definition at line 2115 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ

#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ   0x80000000

Definition at line 2116 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_REG_BLK_SIZE

#define TG3_REG_BLK_SIZE   0x00008000

Definition at line 2118 of file tg3.h.

TG3_OTP_AGCTGT_MASK

#define TG3_OTP_AGCTGT_MASK   0x000000e0

Definition at line 2121 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_AGCTGT_SHIFT

#define TG3_OTP_AGCTGT_SHIFT   1

Definition at line 2122 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_HPFFLTR_MASK

#define TG3_OTP_HPFFLTR_MASK   0x00000300

Definition at line 2123 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_HPFFLTR_SHIFT

#define TG3_OTP_HPFFLTR_SHIFT   1

Definition at line 2124 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_HPFOVER_MASK

#define TG3_OTP_HPFOVER_MASK   0x00000400

Definition at line 2125 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_HPFOVER_SHIFT

#define TG3_OTP_HPFOVER_SHIFT   1

Definition at line 2126 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_LPFDIS_MASK

#define TG3_OTP_LPFDIS_MASK   0x00000800

Definition at line 2127 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_LPFDIS_SHIFT

#define TG3_OTP_LPFDIS_SHIFT   11

Definition at line 2128 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_VDAC_MASK

#define TG3_OTP_VDAC_MASK   0xff000000

Definition at line 2129 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_VDAC_SHIFT

#define TG3_OTP_VDAC_SHIFT   24

Definition at line 2130 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_10BTAMP_MASK

#define TG3_OTP_10BTAMP_MASK   0x0000f000

Definition at line 2131 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_10BTAMP_SHIFT

#define TG3_OTP_10BTAMP_SHIFT   8

Definition at line 2132 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_ROFF_MASK

#define TG3_OTP_ROFF_MASK   0x00e00000

Definition at line 2133 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_ROFF_SHIFT

#define TG3_OTP_ROFF_SHIFT   11

Definition at line 2134 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_RCOFF_MASK

#define TG3_OTP_RCOFF_MASK   0x001c0000

Definition at line 2135 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_RCOFF_SHIFT

#define TG3_OTP_RCOFF_SHIFT   16

Definition at line 2136 of file tg3.h.

Referenced by tg3_phy_apply_otp().

TG3_OTP_DEFAULT

#define TG3_OTP_DEFAULT   0x286c1640

Definition at line 2138 of file tg3.h.

Referenced by tg3_get_invariants().

TG3_NVM_VPD_OFF

#define TG3_NVM_VPD_OFF   0x100

Definition at line 2142 of file tg3.h.

TG3_NVM_VPD_LEN

#define TG3_NVM_VPD_LEN   256

Definition at line 2143 of file tg3.h.

TG3_NVM_HWSB_CFG1

#define TG3_NVM_HWSB_CFG1   0x00000004

Definition at line 2146 of file tg3.h.

TG3_NVM_HWSB_CFG1_MAJMSK

#define TG3_NVM_HWSB_CFG1_MAJMSK   0xf8000000

Definition at line 2147 of file tg3.h.

TG3_NVM_HWSB_CFG1_MAJSFT

#define TG3_NVM_HWSB_CFG1_MAJSFT   27

Definition at line 2148 of file tg3.h.

TG3_NVM_HWSB_CFG1_MINMSK

#define TG3_NVM_HWSB_CFG1_MINMSK   0x07c00000

Definition at line 2149 of file tg3.h.

TG3_NVM_HWSB_CFG1_MINSFT

#define TG3_NVM_HWSB_CFG1_MINSFT   22

Definition at line 2150 of file tg3.h.

TG3_EEPROM_MAGIC

#define TG3_EEPROM_MAGIC   0x669955aa

Definition at line 2152 of file tg3.h.

TG3_EEPROM_MAGIC_FW

#define TG3_EEPROM_MAGIC_FW   0xa5000000

Definition at line 2153 of file tg3.h.

TG3_EEPROM_MAGIC_FW_MSK

#define TG3_EEPROM_MAGIC_FW_MSK   0xff000000

Definition at line 2154 of file tg3.h.

TG3_EEPROM_SB_FORMAT_MASK

#define TG3_EEPROM_SB_FORMAT_MASK   0x00e00000

Definition at line 2155 of file tg3.h.

TG3_EEPROM_SB_FORMAT_1

#define TG3_EEPROM_SB_FORMAT_1   0x00200000

Definition at line 2156 of file tg3.h.

TG3_EEPROM_SB_REVISION_MASK

#define TG3_EEPROM_SB_REVISION_MASK   0x001f0000

Definition at line 2157 of file tg3.h.

TG3_EEPROM_SB_REVISION_0

#define TG3_EEPROM_SB_REVISION_0   0x00000000

Definition at line 2158 of file tg3.h.

TG3_EEPROM_SB_REVISION_2

#define TG3_EEPROM_SB_REVISION_2   0x00020000

Definition at line 2159 of file tg3.h.

TG3_EEPROM_SB_REVISION_3

#define TG3_EEPROM_SB_REVISION_3   0x00030000

Definition at line 2160 of file tg3.h.

TG3_EEPROM_SB_REVISION_4

#define TG3_EEPROM_SB_REVISION_4   0x00040000

Definition at line 2161 of file tg3.h.

TG3_EEPROM_SB_REVISION_5

#define TG3_EEPROM_SB_REVISION_5   0x00050000

Definition at line 2162 of file tg3.h.

TG3_EEPROM_SB_REVISION_6

#define TG3_EEPROM_SB_REVISION_6   0x00060000

Definition at line 2163 of file tg3.h.

TG3_EEPROM_MAGIC_HW

#define TG3_EEPROM_MAGIC_HW   0xabcd

Definition at line 2164 of file tg3.h.

TG3_EEPROM_MAGIC_HW_MSK

#define TG3_EEPROM_MAGIC_HW_MSK   0xffff

Definition at line 2165 of file tg3.h.

TG3_NVM_DIR_START

#define TG3_NVM_DIR_START   0x18

Definition at line 2167 of file tg3.h.

TG3_NVM_DIR_END

#define TG3_NVM_DIR_END   0x78

Definition at line 2168 of file tg3.h.

TG3_NVM_DIRENT_SIZE

#define TG3_NVM_DIRENT_SIZE   0xc

Definition at line 2169 of file tg3.h.

TG3_NVM_DIRTYPE_SHIFT

#define TG3_NVM_DIRTYPE_SHIFT   24

Definition at line 2170 of file tg3.h.

TG3_NVM_DIRTYPE_LENMSK

#define TG3_NVM_DIRTYPE_LENMSK   0x003fffff

Definition at line 2171 of file tg3.h.

TG3_NVM_DIRTYPE_ASFINI

#define TG3_NVM_DIRTYPE_ASFINI   1

Definition at line 2172 of file tg3.h.

TG3_NVM_DIRTYPE_EXTVPD

#define TG3_NVM_DIRTYPE_EXTVPD   20

Definition at line 2173 of file tg3.h.

TG3_NVM_PTREV_BCVER

#define TG3_NVM_PTREV_BCVER   0x94

Definition at line 2174 of file tg3.h.

TG3_NVM_BCVER_MAJMSK

#define TG3_NVM_BCVER_MAJMSK   0x0000ff00

Definition at line 2175 of file tg3.h.

TG3_NVM_BCVER_MAJSFT

#define TG3_NVM_BCVER_MAJSFT   8

Definition at line 2176 of file tg3.h.

TG3_NVM_BCVER_MINMSK

#define TG3_NVM_BCVER_MINMSK   0x000000ff

Definition at line 2177 of file tg3.h.

TG3_EEPROM_SB_F1R0_EDH_OFF

#define TG3_EEPROM_SB_F1R0_EDH_OFF   0x10

Definition at line 2179 of file tg3.h.

TG3_EEPROM_SB_F1R2_EDH_OFF

#define TG3_EEPROM_SB_F1R2_EDH_OFF   0x14

Definition at line 2180 of file tg3.h.

TG3_EEPROM_SB_F1R2_MBA_OFF [1/2]

#define TG3_EEPROM_SB_F1R2_MBA_OFF   0x10

Definition at line 2181 of file tg3.h.

TG3_EEPROM_SB_F1R3_EDH_OFF

#define TG3_EEPROM_SB_F1R3_EDH_OFF   0x18

Definition at line 2182 of file tg3.h.

TG3_EEPROM_SB_F1R4_EDH_OFF

#define TG3_EEPROM_SB_F1R4_EDH_OFF   0x1c

Definition at line 2183 of file tg3.h.

TG3_EEPROM_SB_F1R5_EDH_OFF

#define TG3_EEPROM_SB_F1R5_EDH_OFF   0x20

Definition at line 2184 of file tg3.h.

TG3_EEPROM_SB_F1R6_EDH_OFF

#define TG3_EEPROM_SB_F1R6_EDH_OFF   0x4c

Definition at line 2185 of file tg3.h.

TG3_EEPROM_SB_EDH_MAJ_MASK

#define TG3_EEPROM_SB_EDH_MAJ_MASK   0x00000700

Definition at line 2186 of file tg3.h.

TG3_EEPROM_SB_EDH_MAJ_SHFT

#define TG3_EEPROM_SB_EDH_MAJ_SHFT   8

Definition at line 2187 of file tg3.h.

TG3_EEPROM_SB_EDH_MIN_MASK

#define TG3_EEPROM_SB_EDH_MIN_MASK   0x000000ff

Definition at line 2188 of file tg3.h.

TG3_EEPROM_SB_EDH_BLD_MASK

#define TG3_EEPROM_SB_EDH_BLD_MASK   0x0000f800

Definition at line 2189 of file tg3.h.

TG3_EEPROM_SB_EDH_BLD_SHFT

#define TG3_EEPROM_SB_EDH_BLD_SHFT   11

Definition at line 2190 of file tg3.h.

NIC_SRAM_WIN_BASE

#define NIC_SRAM_WIN_BASE   0x00008000

Definition at line 2194 of file tg3.h.

Referenced by tg3_get_invariants().

NIC_SRAM_PAGE_ZERO

#define NIC_SRAM_PAGE_ZERO   0x00000000

Definition at line 2197 of file tg3.h.

NIC_SRAM_SEND_RCB

#define NIC_SRAM_SEND_RCB   0x00000100 /* 16 * TG3_BDINFO_... */

Definition at line 2198 of file tg3.h.

Referenced by tg3_rings_reset().

NIC_SRAM_RCV_RET_RCB

#define NIC_SRAM_RCV_RET_RCB   0x00000200 /* 16 * TG3_BDINFO_... */

Definition at line 2199 of file tg3.h.

Referenced by tg3_rings_reset().

NIC_SRAM_STATS_BLK

#define NIC_SRAM_STATS_BLK   0x00000300

Definition at line 2200 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_read_mem(), tg3_reset_hw(), and tg3_write_mem().

NIC_SRAM_STATUS_BLK

#define NIC_SRAM_STATUS_BLK   0x00000b00

Definition at line 2201 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_FIRMWARE_MBOX

#define NIC_SRAM_FIRMWARE_MBOX   0x00000b50

Definition at line 2203 of file tg3.h.

Referenced by tg3_poll_fw(), tg3_setup_copper_phy(), and tg3_write_sig_pre_reset().

NIC_SRAM_FIRMWARE_MBOX_MAGIC1

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654

Definition at line 2204 of file tg3.h.

Referenced by tg3_poll_fw(), and tg3_write_sig_pre_reset().

NIC_SRAM_FIRMWARE_MBOX_MAGIC2

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b /* !dma on linkchg */

Definition at line 2205 of file tg3.h.

Referenced by tg3_setup_copper_phy().

NIC_SRAM_DATA_SIG

#define NIC_SRAM_DATA_SIG   0x00000b54

Definition at line 2207 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_SIG_MAGIC

#define NIC_SRAM_DATA_SIG_MAGIC   0x4b657654 /* ascii for 'KevT' */

Definition at line 2208 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG

#define NIC_SRAM_DATA_CFG   0x00000b58

Definition at line 2210 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_LED_MODE_MASK

#define NIC_SRAM_DATA_CFG_LED_MODE_MASK   0x0000000c

Definition at line 2211 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_LED_MODE_MAC

#define NIC_SRAM_DATA_CFG_LED_MODE_MAC   0x00000000

Definition at line 2212 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_LED_MODE_PHY_1

#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1   0x00000004

Definition at line 2213 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_LED_MODE_PHY_2

#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2   0x00000008

Definition at line 2214 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_PHY_TYPE_MASK

#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK   0x00000030

Definition at line 2215 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN

#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN   0x00000000

Definition at line 2216 of file tg3.h.

NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER

#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER   0x00000010

Definition at line 2217 of file tg3.h.

NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER

#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER   0x00000020

Definition at line 2218 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_WOL_ENABLE

#define NIC_SRAM_DATA_CFG_WOL_ENABLE   0x00000040

Definition at line 2219 of file tg3.h.

NIC_SRAM_DATA_CFG_ASF_ENABLE

#define NIC_SRAM_DATA_CFG_ASF_ENABLE   0x00000080

Definition at line 2220 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_EEPROM_WP

#define NIC_SRAM_DATA_CFG_EEPROM_WP   0x00000100

Definition at line 2221 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_MINI_PCI

#define NIC_SRAM_DATA_CFG_MINI_PCI   0x00001000

Definition at line 2222 of file tg3.h.

Referenced by tg3_chip_reset().

NIC_SRAM_DATA_CFG_FIBER_WOL

#define NIC_SRAM_DATA_CFG_FIBER_WOL   0x00004000

Definition at line 2223 of file tg3.h.

NIC_SRAM_DATA_CFG_NO_GPIO2

#define NIC_SRAM_DATA_CFG_NO_GPIO2   0x00100000

Definition at line 2224 of file tg3.h.

NIC_SRAM_DATA_CFG_APE_ENABLE

#define NIC_SRAM_DATA_CFG_APE_ENABLE   0x00200000

Definition at line 2225 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_VER

#define NIC_SRAM_DATA_VER   0x00000b5c

Definition at line 2227 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_VER_SHIFT

#define NIC_SRAM_DATA_VER_SHIFT   16

Definition at line 2228 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_PHY_ID

#define NIC_SRAM_DATA_PHY_ID   0x00000b74

Definition at line 2230 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_PHY_ID1_MASK

#define NIC_SRAM_DATA_PHY_ID1_MASK   0xffff0000

Definition at line 2231 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_PHY_ID2_MASK

#define NIC_SRAM_DATA_PHY_ID2_MASK   0x0000ffff

Definition at line 2232 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_FW_CMD_MBOX

#define NIC_SRAM_FW_CMD_MBOX   0x00000b78

Definition at line 2234 of file tg3.h.

Referenced by tg3_stop_fw(), and tg3_ump_link_report().

FWCMD_NICDRV_ALIVE

#define FWCMD_NICDRV_ALIVE   0x00000001

Definition at line 2235 of file tg3.h.

FWCMD_NICDRV_PAUSE_FW

#define FWCMD_NICDRV_PAUSE_FW   0x00000002

Definition at line 2236 of file tg3.h.

Referenced by tg3_stop_fw().

FWCMD_NICDRV_IPV4ADDR_CHG

#define FWCMD_NICDRV_IPV4ADDR_CHG   0x00000003

Definition at line 2237 of file tg3.h.

FWCMD_NICDRV_IPV6ADDR_CHG

#define FWCMD_NICDRV_IPV6ADDR_CHG   0x00000004

Definition at line 2238 of file tg3.h.

FWCMD_NICDRV_FIX_DMAR

#define FWCMD_NICDRV_FIX_DMAR   0x00000005

Definition at line 2239 of file tg3.h.

FWCMD_NICDRV_FIX_DMAW

#define FWCMD_NICDRV_FIX_DMAW   0x00000006

Definition at line 2240 of file tg3.h.

FWCMD_NICDRV_LINK_UPDATE

#define FWCMD_NICDRV_LINK_UPDATE   0x0000000c

Definition at line 2241 of file tg3.h.

Referenced by tg3_ump_link_report().

FWCMD_NICDRV_ALIVE2

#define FWCMD_NICDRV_ALIVE2   0x0000000d

Definition at line 2242 of file tg3.h.

FWCMD_NICDRV_ALIVE3

#define FWCMD_NICDRV_ALIVE3   0x0000000e

Definition at line 2243 of file tg3.h.

NIC_SRAM_FW_CMD_LEN_MBOX

#define NIC_SRAM_FW_CMD_LEN_MBOX   0x00000b7c

Definition at line 2244 of file tg3.h.

Referenced by tg3_ump_link_report().

NIC_SRAM_FW_CMD_DATA_MBOX

#define NIC_SRAM_FW_CMD_DATA_MBOX   0x00000b80

Definition at line 2245 of file tg3.h.

Referenced by tg3_ump_link_report().

NIC_SRAM_FW_ASF_STATUS_MBOX

#define NIC_SRAM_FW_ASF_STATUS_MBOX   0x00000c00

Definition at line 2246 of file tg3.h.

NIC_SRAM_FW_DRV_STATE_MBOX

#define NIC_SRAM_FW_DRV_STATE_MBOX   0x00000c04

Definition at line 2247 of file tg3.h.

DRV_STATE_START

#define DRV_STATE_START   0x00000001

Definition at line 2248 of file tg3.h.

DRV_STATE_START_DONE

#define DRV_STATE_START_DONE   0x80000001

Definition at line 2249 of file tg3.h.

DRV_STATE_UNLOAD

#define DRV_STATE_UNLOAD   0x00000002

Definition at line 2250 of file tg3.h.

DRV_STATE_UNLOAD_DONE

#define DRV_STATE_UNLOAD_DONE   0x80000002

Definition at line 2251 of file tg3.h.

DRV_STATE_WOL

#define DRV_STATE_WOL   0x00000003

Definition at line 2252 of file tg3.h.

DRV_STATE_SUSPEND

#define DRV_STATE_SUSPEND   0x00000004

Definition at line 2253 of file tg3.h.

NIC_SRAM_FW_RESET_TYPE_MBOX

#define NIC_SRAM_FW_RESET_TYPE_MBOX   0x00000c08

Definition at line 2255 of file tg3.h.

NIC_SRAM_MAC_ADDR_HIGH_MBOX

#define NIC_SRAM_MAC_ADDR_HIGH_MBOX   0x00000c14

Definition at line 2257 of file tg3.h.

Referenced by tg3_get_device_address().

NIC_SRAM_MAC_ADDR_LOW_MBOX

#define NIC_SRAM_MAC_ADDR_LOW_MBOX   0x00000c18

Definition at line 2258 of file tg3.h.

Referenced by tg3_get_device_address().

NIC_SRAM_WOL_MBOX

#define NIC_SRAM_WOL_MBOX   0x00000d30

Definition at line 2260 of file tg3.h.

WOL_SIGNATURE

#define WOL_SIGNATURE   0x474c0000

Definition at line 2261 of file tg3.h.

WOL_DRV_STATE_SHUTDOWN

#define WOL_DRV_STATE_SHUTDOWN   0x00000001

Definition at line 2262 of file tg3.h.

WOL_DRV_WOL

#define WOL_DRV_WOL   0x00000002

Definition at line 2263 of file tg3.h.

WOL_SET_MAGIC_PKT

#define WOL_SET_MAGIC_PKT   0x00000004

Definition at line 2264 of file tg3.h.

NIC_SRAM_DATA_CFG_2

#define NIC_SRAM_DATA_CFG_2   0x00000d38

Definition at line 2266 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_2_APD_EN

#define NIC_SRAM_DATA_CFG_2_APD_EN   0x00000400

Definition at line 2268 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

SHASTA_EXT_LED_MODE_MASK

#define SHASTA_EXT_LED_MODE_MASK   0x00018000

Definition at line 2269 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

SHASTA_EXT_LED_LEGACY

#define SHASTA_EXT_LED_LEGACY   0x00000000

Definition at line 2270 of file tg3.h.

SHASTA_EXT_LED_SHARED

#define SHASTA_EXT_LED_SHARED   0x00008000

Definition at line 2271 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

SHASTA_EXT_LED_MAC

#define SHASTA_EXT_LED_MAC   0x00010000

Definition at line 2272 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

SHASTA_EXT_LED_COMBO

#define SHASTA_EXT_LED_COMBO   0x00018000

Definition at line 2273 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_DATA_CFG_3

#define NIC_SRAM_DATA_CFG_3   0x00000d3c

Definition at line 2275 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_ASPM_DEBOUNCE

#define NIC_SRAM_ASPM_DEBOUNCE   0x00000002

Definition at line 2276 of file tg3.h.

NIC_SRAM_DATA_CFG_4

#define NIC_SRAM_DATA_CFG_4   0x00000d60

Definition at line 2278 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_GMII_MODE

#define NIC_SRAM_GMII_MODE   0x00000002

Definition at line 2279 of file tg3.h.

NIC_SRAM_RGMII_INBAND_DISABLE

#define NIC_SRAM_RGMII_INBAND_DISABLE   0x00000004

Definition at line 2280 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_RGMII_EXT_IBND_RX_EN

#define NIC_SRAM_RGMII_EXT_IBND_RX_EN   0x00000008

Definition at line 2281 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_RGMII_EXT_IBND_TX_EN

#define NIC_SRAM_RGMII_EXT_IBND_TX_EN   0x00000010

Definition at line 2282 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

NIC_SRAM_RX_MINI_BUFFER_DESC

#define NIC_SRAM_RX_MINI_BUFFER_DESC   0x00001000

Definition at line 2284 of file tg3.h.

NIC_SRAM_DMA_DESC_POOL_BASE

#define NIC_SRAM_DMA_DESC_POOL_BASE   0x00002000

Definition at line 2286 of file tg3.h.

Referenced by tg3_do_test_dma(), and tg3_reset_hw().

NIC_SRAM_DMA_DESC_POOL_SIZE

#define NIC_SRAM_DMA_DESC_POOL_SIZE   0x00002000

Definition at line 2287 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_TX_BUFFER_DESC

#define NIC_SRAM_TX_BUFFER_DESC   0x00004000 /* 512 entries */

Definition at line 2288 of file tg3.h.

Referenced by tg3_read_mem(), tg3_rings_reset(), and tg3_write_mem().

NIC_SRAM_RX_BUFFER_DESC

#define NIC_SRAM_RX_BUFFER_DESC   0x00006000 /* 256 entries */

Definition at line 2289 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_RX_JUMBO_BUFFER_DESC

#define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000 /* 256 entries */

Definition at line 2290 of file tg3.h.

NIC_SRAM_MBUF_POOL_BASE

#define NIC_SRAM_MBUF_POOL_BASE   0x00008000

Definition at line 2291 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_MBUF_POOL_SIZE96

#define NIC_SRAM_MBUF_POOL_SIZE96   0x00018000

Definition at line 2292 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_MBUF_POOL_SIZE64

#define NIC_SRAM_MBUF_POOL_SIZE64   0x00010000

Definition at line 2293 of file tg3.h.

Referenced by tg3_reset_hw().

NIC_SRAM_MBUF_POOL_BASE5705

#define NIC_SRAM_MBUF_POOL_BASE5705   0x00010000

Definition at line 2294 of file tg3.h.

NIC_SRAM_MBUF_POOL_SIZE5705

#define NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000

Definition at line 2295 of file tg3.h.

TG3_SRAM_RX_STD_BDCACHE_SIZE_5700

#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700   128

Definition at line 2297 of file tg3.h.

Referenced by tg3_setup_rxbd_thresholds().

TG3_SRAM_RX_STD_BDCACHE_SIZE_5755

#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755   64

Definition at line 2298 of file tg3.h.

Referenced by tg3_setup_rxbd_thresholds().

TG3_SRAM_RX_STD_BDCACHE_SIZE_5906

#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906   32

Definition at line 2299 of file tg3.h.

Referenced by tg3_setup_rxbd_thresholds().

TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700

#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700   64

Definition at line 2301 of file tg3.h.

TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717

#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717   16

Definition at line 2302 of file tg3.h.

TG3_PHY_MII_ADDR

#define TG3_PHY_MII_ADDR   0x01

Definition at line 2306 of file tg3.h.

Referenced by tg3_mdio_init().

TG3_BMCR_SPEED1000

#define TG3_BMCR_SPEED1000   0x0040

Definition at line 2310 of file tg3.h.

Referenced by tg3_phy_reset_5703_4_5().

MII_TG3_CTRL

#define MII_TG3_CTRL   0x09 /* 1000-baseT control register */

Definition at line 2312 of file tg3.h.

Referenced by tg3_copper_is_advertising_all(), tg3_phy_autoneg_cfg(), tg3_phy_reset_5703_4_5(), and tg3_writephy().

MII_TG3_CTRL_ADV_1000_HALF

#define MII_TG3_CTRL_ADV_1000_HALF   0x0100

Definition at line 2313 of file tg3.h.

Referenced by tg3_phy_autoneg_cfg().

MII_TG3_CTRL_ADV_1000_FULL

#define MII_TG3_CTRL_ADV_1000_FULL   0x0200

Definition at line 2314 of file tg3.h.

Referenced by tg3_phy_autoneg_cfg().

MII_TG3_CTRL_AS_MASTER

#define MII_TG3_CTRL_AS_MASTER   0x0800

Definition at line 2315 of file tg3.h.

Referenced by tg3_phy_autoneg_cfg(), and tg3_phy_reset_5703_4_5().

MII_TG3_CTRL_ENABLE_AS_MASTER

#define MII_TG3_CTRL_ENABLE_AS_MASTER   0x1000

Definition at line 2316 of file tg3.h.

Referenced by tg3_phy_autoneg_cfg(), and tg3_phy_reset_5703_4_5().

MII_TG3_MMD_CTRL

#define MII_TG3_MMD_CTRL   0x0d /* MMD Access Control register */

Definition at line 2318 of file tg3.h.

MII_TG3_MMD_CTRL_DATA_NOINC

#define MII_TG3_MMD_CTRL_DATA_NOINC   0x4000

Definition at line 2319 of file tg3.h.

MII_TG3_MMD_ADDRESS

#define MII_TG3_MMD_ADDRESS   0x0e /* MMD Address Data register */

Definition at line 2320 of file tg3.h.

MII_TG3_EXT_CTRL

#define MII_TG3_EXT_CTRL   0x10 /* Extended control register */

Definition at line 2322 of file tg3.h.

Referenced by tg3_phy_reset_5703_4_5(), and tg3_setup_copper_phy().

MII_TG3_EXT_CTRL_FIFO_ELASTIC

#define MII_TG3_EXT_CTRL_FIFO_ELASTIC   0x0001

Definition at line 2323 of file tg3.h.

MII_TG3_EXT_CTRL_LNK3_LED_MODE

#define MII_TG3_EXT_CTRL_LNK3_LED_MODE   0x0002

Definition at line 2324 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_EXT_CTRL_FORCE_LED_OFF

#define MII_TG3_EXT_CTRL_FORCE_LED_OFF   0x0008

Definition at line 2325 of file tg3.h.

MII_TG3_EXT_CTRL_TBI

#define MII_TG3_EXT_CTRL_TBI   0x8000

Definition at line 2326 of file tg3.h.

MII_TG3_EXT_STAT

#define MII_TG3_EXT_STAT   0x11 /* Extended status register */

Definition at line 2328 of file tg3.h.

MII_TG3_EXT_STAT_LPASS

#define MII_TG3_EXT_STAT_LPASS   0x0100

Definition at line 2329 of file tg3.h.

MII_TG3_RXR_COUNTERS

#define MII_TG3_RXR_COUNTERS   0x14 /* Local/Remote Receiver Counts */

Definition at line 2331 of file tg3.h.

Referenced by tg3_reset_hw().

MII_TG3_DSP_RW_PORT

#define MII_TG3_DSP_RW_PORT   0x15 /* DSP coefficient read/write port */

Definition at line 2332 of file tg3.h.

Referenced by tg3_phy_reset(), tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), and tg3_phydsp_write().

MII_TG3_DSP_CONTROL

#define MII_TG3_DSP_CONTROL   0x16 /* DSP control register */

Definition at line 2333 of file tg3.h.

Referenced by tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), and tg3_wait_macro_done().

MII_TG3_DSP_ADDRESS

#define MII_TG3_DSP_ADDRESS   0x17 /* DSP address register */

Definition at line 2334 of file tg3.h.

Referenced by tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), and tg3_phydsp_write().

MII_TG3_DSP_TAP1

#define MII_TG3_DSP_TAP1   0x0001

Definition at line 2336 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_TAP1_AGCTGT_DFLT

#define MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007

Definition at line 2337 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_TAP26

#define MII_TG3_DSP_TAP26   0x001a

Definition at line 2338 of file tg3.h.

MII_TG3_DSP_TAP26_ALNOKO

#define MII_TG3_DSP_TAP26_ALNOKO   0x0001

Definition at line 2339 of file tg3.h.

MII_TG3_DSP_TAP26_RMRXSTO

#define MII_TG3_DSP_TAP26_RMRXSTO   0x0002

Definition at line 2340 of file tg3.h.

MII_TG3_DSP_TAP26_OPCSINPT

#define MII_TG3_DSP_TAP26_OPCSINPT   0x0004

Definition at line 2341 of file tg3.h.

MII_TG3_DSP_AADJ1CH0

#define MII_TG3_DSP_AADJ1CH0   0x001f

Definition at line 2342 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_CH34TP2

#define MII_TG3_DSP_CH34TP2   0x4022

Definition at line 2343 of file tg3.h.

MII_TG3_DSP_CH34TP2_HIBW01

#define MII_TG3_DSP_CH34TP2_HIBW01   0x017b

Definition at line 2344 of file tg3.h.

MII_TG3_DSP_AADJ1CH3

#define MII_TG3_DSP_AADJ1CH3   0x601f

Definition at line 2345 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_AADJ1CH3_ADCCKADJ

#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ   0x0002

Definition at line 2346 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_EXP1_INT_STAT

#define MII_TG3_DSP_EXP1_INT_STAT   0x0f01

Definition at line 2347 of file tg3.h.

MII_TG3_DSP_EXP8

#define MII_TG3_DSP_EXP8   0x0f08

Definition at line 2348 of file tg3.h.

Referenced by tg3_phy_reset().

MII_TG3_DSP_EXP8_REJ2MHz

#define MII_TG3_DSP_EXP8_REJ2MHz   0x0001

Definition at line 2349 of file tg3.h.

Referenced by tg3_phy_reset().

MII_TG3_DSP_EXP8_AEDW

#define MII_TG3_DSP_EXP8_AEDW   0x0200

Definition at line 2350 of file tg3.h.

Referenced by tg3_phy_reset().

MII_TG3_DSP_EXP75

#define MII_TG3_DSP_EXP75   0x0f75

Definition at line 2351 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_EXP96

#define MII_TG3_DSP_EXP96   0x0f96

Definition at line 2352 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_DSP_EXP97

#define MII_TG3_DSP_EXP97   0x0f97

Definition at line 2353 of file tg3.h.

Referenced by tg3_phy_apply_otp().

MII_TG3_AUX_CTRL

#define MII_TG3_AUX_CTRL   0x18 /* auxiliary control register */

Definition at line 2355 of file tg3.h.

Referenced by tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), and tg3_writephy().

MII_TG3_AUXCTL_SHDWSEL_AUXCTL

#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL   0x0000

Definition at line 2357 of file tg3.h.

Referenced by tg3_init_5401phy_dsp(), and tg3_phy_reset().

MII_TG3_AUXCTL_ACTL_TX_6DB

#define MII_TG3_AUXCTL_ACTL_TX_6DB   0x0400

Definition at line 2358 of file tg3.h.

MII_TG3_AUXCTL_ACTL_SMDSP_ENA

#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA   0x0800

Definition at line 2359 of file tg3.h.

MII_TG3_AUXCTL_ACTL_EXTPKTLEN

#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN   0x4000

Definition at line 2360 of file tg3.h.

MII_TG3_AUXCTL_SHDWSEL_PWRCTL

#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL   0x0002

Definition at line 2362 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_AUXCTL_PCTL_WOL_EN

#define MII_TG3_AUXCTL_PCTL_WOL_EN   0x0008

Definition at line 2363 of file tg3.h.

MII_TG3_AUXCTL_PCTL_100TX_LPWR

#define MII_TG3_AUXCTL_PCTL_100TX_LPWR   0x0010

Definition at line 2364 of file tg3.h.

MII_TG3_AUXCTL_PCTL_SPR_ISOLATE

#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE   0x0020

Definition at line 2365 of file tg3.h.

MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC

#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC   0x0040

Definition at line 2366 of file tg3.h.

MII_TG3_AUXCTL_PCTL_VREG_11V

#define MII_TG3_AUXCTL_PCTL_VREG_11V   0x0180

Definition at line 2367 of file tg3.h.

MII_TG3_AUXCTL_SHDWSEL_MISCTEST

#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST   0x0004

Definition at line 2369 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_AUXCTL_SHDWSEL_MISC

#define MII_TG3_AUXCTL_SHDWSEL_MISC   0x0007

Definition at line 2371 of file tg3.h.

Referenced by tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), tg3_phy_set_wirespeed(), and tg3_phy_toggle_automdix().

MII_TG3_AUXCTL_MISC_WIRESPD_EN

#define MII_TG3_AUXCTL_MISC_WIRESPD_EN   0x0010

Definition at line 2372 of file tg3.h.

Referenced by tg3_phy_set_wirespeed().

MII_TG3_AUXCTL_MISC_FORCE_AMDIX

#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX   0x0200

Definition at line 2373 of file tg3.h.

Referenced by tg3_phy_toggle_automdix().

MII_TG3_AUXCTL_MISC_RDSEL_SHIFT

#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT   12

Definition at line 2374 of file tg3.h.

Referenced by tg3_phy_auxctl_read().

MII_TG3_AUXCTL_MISC_WREN

#define MII_TG3_AUXCTL_MISC_WREN   0x8000

Definition at line 2375 of file tg3.h.

Referenced by tg3_phy_auxctl_write().

MII_TG3_AUX_STAT

#define MII_TG3_AUX_STAT   0x19 /* auxiliary status register */

Definition at line 2378 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_AUX_STAT_LPASS

#define MII_TG3_AUX_STAT_LPASS   0x0004

Definition at line 2379 of file tg3.h.

MII_TG3_AUX_STAT_SPDMASK

#define MII_TG3_AUX_STAT_SPDMASK   0x0700

Definition at line 2380 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_10HALF

#define MII_TG3_AUX_STAT_10HALF   0x0100

Definition at line 2381 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_10FULL

#define MII_TG3_AUX_STAT_10FULL   0x0200

Definition at line 2382 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_100HALF

#define MII_TG3_AUX_STAT_100HALF   0x0300

Definition at line 2383 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_100_4

#define MII_TG3_AUX_STAT_100_4   0x0400

Definition at line 2384 of file tg3.h.

MII_TG3_AUX_STAT_100FULL

#define MII_TG3_AUX_STAT_100FULL   0x0500

Definition at line 2385 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_1000HALF

#define MII_TG3_AUX_STAT_1000HALF   0x0600

Definition at line 2386 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_1000FULL

#define MII_TG3_AUX_STAT_1000FULL   0x0700

Definition at line 2387 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_100

#define MII_TG3_AUX_STAT_100   0x0008

Definition at line 2388 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_AUX_STAT_FULL

#define MII_TG3_AUX_STAT_FULL   0x0001

Definition at line 2389 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

MII_TG3_ISTAT

#define MII_TG3_ISTAT   0x1a /* IRQ status register */

Definition at line 2391 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_IMASK

#define MII_TG3_IMASK   0x1b /* IRQ mask register */

Definition at line 2392 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_INT_LINKCHG

#define MII_TG3_INT_LINKCHG   0x0002

Definition at line 2395 of file tg3.h.

Referenced by tg3_setup_copper_phy().

MII_TG3_INT_SPEEDCHG

#define MII_TG3_INT_SPEEDCHG   0x0004

Definition at line 2396 of file tg3.h.

MII_TG3_INT_DUPLEXCHG

#define MII_TG3_INT_DUPLEXCHG   0x0008

Definition at line 2397 of file tg3.h.

MII_TG3_INT_ANEG_PAGE_RX

#define MII_TG3_INT_ANEG_PAGE_RX   0x0400

Definition at line 2398 of file tg3.h.

MII_TG3_MISC_SHDW

#define MII_TG3_MISC_SHDW   0x1c

Definition at line 2400 of file tg3.h.

Referenced by tg3_phy_reset(), and tg3_setup_copper_phy().

MII_TG3_MISC_SHDW_WREN

#define MII_TG3_MISC_SHDW_WREN   0x8000

Definition at line 2401 of file tg3.h.

MII_TG3_MISC_SHDW_APD_WKTM_84MS

#define MII_TG3_MISC_SHDW_APD_WKTM_84MS   0x0001

Definition at line 2403 of file tg3.h.

MII_TG3_MISC_SHDW_APD_ENABLE

#define MII_TG3_MISC_SHDW_APD_ENABLE   0x0020

Definition at line 2404 of file tg3.h.

MII_TG3_MISC_SHDW_APD_SEL

#define MII_TG3_MISC_SHDW_APD_SEL   0x2800

Definition at line 2405 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_C125OE

#define MII_TG3_MISC_SHDW_SCR5_C125OE   0x0001

Definition at line 2407 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_DLLAPD

#define MII_TG3_MISC_SHDW_SCR5_DLLAPD   0x0002

Definition at line 2408 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_SDTL

#define MII_TG3_MISC_SHDW_SCR5_SDTL   0x0004

Definition at line 2409 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_DLPTLM

#define MII_TG3_MISC_SHDW_SCR5_DLPTLM   0x0008

Definition at line 2410 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_LPED

#define MII_TG3_MISC_SHDW_SCR5_LPED   0x0010

Definition at line 2411 of file tg3.h.

MII_TG3_MISC_SHDW_SCR5_SEL

#define MII_TG3_MISC_SHDW_SCR5_SEL   0x1400

Definition at line 2412 of file tg3.h.

MII_TG3_TEST1

#define MII_TG3_TEST1   0x1e

Definition at line 2414 of file tg3.h.

Referenced by tg3_phy_reset(), and tg3_reset_hw().

MII_TG3_TEST1_TRIM_EN

#define MII_TG3_TEST1_TRIM_EN   0x0010

Definition at line 2415 of file tg3.h.

Referenced by tg3_phy_reset().

MII_TG3_TEST1_CRC_EN

#define MII_TG3_TEST1_CRC_EN   0x8000

Definition at line 2416 of file tg3.h.

Referenced by tg3_reset_hw().

TG3_CL45_D7_EEERES_STAT

#define TG3_CL45_D7_EEERES_STAT   0x803e

Definition at line 2419 of file tg3.h.

TG3_CL45_D7_EEERES_STAT_LP_100TX

#define TG3_CL45_D7_EEERES_STAT_LP_100TX   0x0002

Definition at line 2420 of file tg3.h.

TG3_CL45_D7_EEERES_STAT_LP_1000T

#define TG3_CL45_D7_EEERES_STAT_LP_1000T   0x0004

Definition at line 2421 of file tg3.h.

MII_TG3_FET_PTEST

#define MII_TG3_FET_PTEST   0x17

Definition at line 2425 of file tg3.h.

Referenced by tg3_phy_reset().

MII_TG3_FET_PTEST_FRC_TX_LINK

#define MII_TG3_FET_PTEST_FRC_TX_LINK   0x1000

Definition at line 2426 of file tg3.h.

MII_TG3_FET_PTEST_FRC_TX_LOCK

#define MII_TG3_FET_PTEST_FRC_TX_LOCK   0x0800

Definition at line 2427 of file tg3.h.

MII_TG3_FET_TEST

#define MII_TG3_FET_TEST   0x1f

Definition at line 2429 of file tg3.h.

Referenced by tg3_phy_toggle_automdix().

MII_TG3_FET_SHADOW_EN

#define MII_TG3_FET_SHADOW_EN   0x0080

Definition at line 2430 of file tg3.h.

Referenced by tg3_phy_toggle_automdix().

MII_TG3_FET_SHDW_MISCCTRL

#define MII_TG3_FET_SHDW_MISCCTRL   0x10

Definition at line 2432 of file tg3.h.

Referenced by tg3_phy_toggle_automdix().

MII_TG3_FET_SHDW_MISCCTRL_MDIX

#define MII_TG3_FET_SHDW_MISCCTRL_MDIX   0x4000

Definition at line 2433 of file tg3.h.

Referenced by tg3_phy_toggle_automdix().

MII_TG3_FET_SHDW_AUXMODE4

#define MII_TG3_FET_SHDW_AUXMODE4   0x1a

Definition at line 2435 of file tg3.h.

MII_TG3_FET_SHDW_AUXMODE4_SBPD

#define MII_TG3_FET_SHDW_AUXMODE4_SBPD   0x0008

Definition at line 2436 of file tg3.h.

MII_TG3_FET_SHDW_AUXSTAT2

#define MII_TG3_FET_SHDW_AUXSTAT2   0x1b

Definition at line 2438 of file tg3.h.

MII_TG3_FET_SHDW_AUXSTAT2_APD

#define MII_TG3_FET_SHDW_AUXSTAT2_APD   0x0020

Definition at line 2439 of file tg3.h.

SERDES_TG3_1000X_STATUS

#define SERDES_TG3_1000X_STATUS   0x14

Definition at line 2442 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

SERDES_TG3_SGMII_MODE

#define SERDES_TG3_SGMII_MODE   0x0001

Definition at line 2443 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

SERDES_TG3_LINK_UP

#define SERDES_TG3_LINK_UP   0x0002

Definition at line 2444 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

SERDES_TG3_FULL_DUPLEX

#define SERDES_TG3_FULL_DUPLEX   0x0004

Definition at line 2445 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

SERDES_TG3_SPEED_100

#define SERDES_TG3_SPEED_100   0x0008

Definition at line 2446 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

SERDES_TG3_SPEED_1000

#define SERDES_TG3_SPEED_1000   0x0010

Definition at line 2447 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

TG3_APE_EVENT

#define TG3_APE_EVENT   0x000c

Definition at line 2451 of file tg3.h.

APE_EVENT_1

#define APE_EVENT_1   0x00000001

Definition at line 2452 of file tg3.h.

TG3_APE_LOCK_REQ

#define TG3_APE_LOCK_REQ   0x002c

Definition at line 2453 of file tg3.h.

APE_LOCK_REQ_DRIVER

#define APE_LOCK_REQ_DRIVER   0x00001000

Definition at line 2454 of file tg3.h.

TG3_APE_LOCK_GRANT

#define TG3_APE_LOCK_GRANT   0x004c

Definition at line 2455 of file tg3.h.

APE_LOCK_GRANT_DRIVER

#define APE_LOCK_GRANT_DRIVER   0x00001000

Definition at line 2456 of file tg3.h.

TG3_APE_SEG_SIG

#define TG3_APE_SEG_SIG   0x4000

Definition at line 2457 of file tg3.h.

APE_SEG_SIG_MAGIC

#define APE_SEG_SIG_MAGIC   0x41504521

Definition at line 2458 of file tg3.h.

TG3_APE_FW_STATUS

#define TG3_APE_FW_STATUS   0x400c

Definition at line 2461 of file tg3.h.

APE_FW_STATUS_READY

#define APE_FW_STATUS_READY   0x00000100

Definition at line 2462 of file tg3.h.

TG3_APE_FW_FEATURES

#define TG3_APE_FW_FEATURES   0x4010

Definition at line 2463 of file tg3.h.

TG3_APE_FW_FEATURE_NCSI

#define TG3_APE_FW_FEATURE_NCSI   0x00000002

Definition at line 2464 of file tg3.h.

TG3_APE_FW_VERSION

#define TG3_APE_FW_VERSION   0x4018

Definition at line 2465 of file tg3.h.

APE_FW_VERSION_MAJMSK

#define APE_FW_VERSION_MAJMSK   0xff000000

Definition at line 2466 of file tg3.h.

APE_FW_VERSION_MAJSFT

#define APE_FW_VERSION_MAJSFT   24

Definition at line 2467 of file tg3.h.

APE_FW_VERSION_MINMSK

#define APE_FW_VERSION_MINMSK   0x00ff0000

Definition at line 2468 of file tg3.h.

APE_FW_VERSION_MINSFT

#define APE_FW_VERSION_MINSFT   16

Definition at line 2469 of file tg3.h.

APE_FW_VERSION_REVMSK

#define APE_FW_VERSION_REVMSK   0x0000ff00

Definition at line 2470 of file tg3.h.

APE_FW_VERSION_REVSFT

#define APE_FW_VERSION_REVSFT   8

Definition at line 2471 of file tg3.h.

APE_FW_VERSION_BLDMSK

#define APE_FW_VERSION_BLDMSK   0x000000ff

Definition at line 2472 of file tg3.h.

TG3_APE_HOST_SEG_SIG

#define TG3_APE_HOST_SEG_SIG   0x4200

Definition at line 2473 of file tg3.h.

APE_HOST_SEG_SIG_MAGIC

#define APE_HOST_SEG_SIG_MAGIC   0x484f5354

Definition at line 2474 of file tg3.h.

TG3_APE_HOST_SEG_LEN

#define TG3_APE_HOST_SEG_LEN   0x4204

Definition at line 2475 of file tg3.h.

APE_HOST_SEG_LEN_MAGIC

#define APE_HOST_SEG_LEN_MAGIC   0x00000020

Definition at line 2476 of file tg3.h.

TG3_APE_HOST_INIT_COUNT

#define TG3_APE_HOST_INIT_COUNT   0x4208

Definition at line 2477 of file tg3.h.

TG3_APE_HOST_DRIVER_ID

#define TG3_APE_HOST_DRIVER_ID   0x420c

Definition at line 2478 of file tg3.h.

APE_HOST_DRIVER_ID_LINUX

#define APE_HOST_DRIVER_ID_LINUX   0xf0000000

Definition at line 2479 of file tg3.h.

APE_HOST_DRIVER_ID_MAGIC

#define APE_HOST_DRIVER_ID_MAGIC	(		maj,
			min )

Value:

        (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)

Definition at line 2480 of file tg3.h.

#define  APE_HOST_DRIVER_ID_MAGIC(maj, min)     \
        (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)

TG3_APE_HOST_BEHAVIOR

#define TG3_APE_HOST_BEHAVIOR   0x4210

Definition at line 2482 of file tg3.h.

APE_HOST_BEHAV_NO_PHYLOCK

#define APE_HOST_BEHAV_NO_PHYLOCK   0x00000001

Definition at line 2483 of file tg3.h.

TG3_APE_HOST_HEARTBEAT_INT_MS

#define TG3_APE_HOST_HEARTBEAT_INT_MS   0x4214

Definition at line 2484 of file tg3.h.

APE_HOST_HEARTBEAT_INT_DISABLE

#define APE_HOST_HEARTBEAT_INT_DISABLE   0

Definition at line 2485 of file tg3.h.

APE_HOST_HEARTBEAT_INT_5SEC

#define APE_HOST_HEARTBEAT_INT_5SEC   5000

Definition at line 2486 of file tg3.h.

TG3_APE_HOST_HEARTBEAT_COUNT

#define TG3_APE_HOST_HEARTBEAT_COUNT   0x4218

Definition at line 2487 of file tg3.h.

TG3_APE_HOST_DRVR_STATE

#define TG3_APE_HOST_DRVR_STATE   0x421c

Definition at line 2488 of file tg3.h.

TG3_APE_HOST_DRVR_STATE_START

#define TG3_APE_HOST_DRVR_STATE_START   0x00000001

Definition at line 2489 of file tg3.h.

TG3_APE_HOST_DRVR_STATE_UNLOAD

#define TG3_APE_HOST_DRVR_STATE_UNLOAD   0x00000002

Definition at line 2490 of file tg3.h.

TG3_APE_HOST_DRVR_STATE_WOL

#define TG3_APE_HOST_DRVR_STATE_WOL   0x00000003

Definition at line 2491 of file tg3.h.

TG3_APE_HOST_WOL_SPEED

#define TG3_APE_HOST_WOL_SPEED   0x4224

Definition at line 2492 of file tg3.h.

TG3_APE_HOST_WOL_SPEED_AUTO

#define TG3_APE_HOST_WOL_SPEED_AUTO   0x00008000

Definition at line 2493 of file tg3.h.

TG3_APE_EVENT_STATUS

#define TG3_APE_EVENT_STATUS   0x4300

Definition at line 2495 of file tg3.h.

APE_EVENT_STATUS_DRIVER_EVNT

#define APE_EVENT_STATUS_DRIVER_EVNT   0x00000010

Definition at line 2497 of file tg3.h.

APE_EVENT_STATUS_STATE_CHNGE

#define APE_EVENT_STATUS_STATE_CHNGE   0x00000500

Definition at line 2498 of file tg3.h.

APE_EVENT_STATUS_STATE_START

#define APE_EVENT_STATUS_STATE_START   0x00010000

Definition at line 2499 of file tg3.h.

APE_EVENT_STATUS_STATE_UNLOAD

#define APE_EVENT_STATUS_STATE_UNLOAD   0x00020000

Definition at line 2500 of file tg3.h.

APE_EVENT_STATUS_STATE_WOL

#define APE_EVENT_STATUS_STATE_WOL   0x00030000

Definition at line 2501 of file tg3.h.

APE_EVENT_STATUS_STATE_SUSPEND

#define APE_EVENT_STATUS_STATE_SUSPEND   0x00040000

Definition at line 2502 of file tg3.h.

APE_EVENT_STATUS_EVENT_PENDING

#define APE_EVENT_STATUS_EVENT_PENDING   0x80000000

Definition at line 2503 of file tg3.h.

TG3_APE_PER_LOCK_REQ

#define TG3_APE_PER_LOCK_REQ   0x8400

Definition at line 2505 of file tg3.h.

APE_LOCK_PER_REQ_DRIVER

#define APE_LOCK_PER_REQ_DRIVER   0x00001000

Definition at line 2506 of file tg3.h.

TG3_APE_PER_LOCK_GRANT

#define TG3_APE_PER_LOCK_GRANT   0x8420

Definition at line 2507 of file tg3.h.

APE_PER_LOCK_GRANT_DRIVER

#define APE_PER_LOCK_GRANT_DRIVER   0x00001000

Definition at line 2508 of file tg3.h.

TG3_APE_LOCK_GRC

#define TG3_APE_LOCK_GRC   1

Definition at line 2511 of file tg3.h.

TG3_APE_LOCK_MEM

#define TG3_APE_LOCK_MEM   4

Definition at line 2512 of file tg3.h.

TG3_EEPROM_SB_F1R2_MBA_OFF [2/2]

#define TG3_EEPROM_SB_F1R2_MBA_OFF   0x10

Definition at line 2181 of file tg3.h.

TXD_FLAG_TCPUDP_CSUM

#define TXD_FLAG_TCPUDP_CSUM   0x0001

Definition at line 2558 of file tg3.h.

TXD_FLAG_IP_CSUM

#define TXD_FLAG_IP_CSUM   0x0002

Definition at line 2559 of file tg3.h.

TXD_FLAG_END

#define TXD_FLAG_END   0x0004

Definition at line 2560 of file tg3.h.

Referenced by tg3_transmit().

TXD_FLAG_IP_FRAG

#define TXD_FLAG_IP_FRAG   0x0008

Definition at line 2561 of file tg3.h.

TXD_FLAG_JMB_PKT

#define TXD_FLAG_JMB_PKT   0x0008

Definition at line 2562 of file tg3.h.

TXD_FLAG_IP_FRAG_END

#define TXD_FLAG_IP_FRAG_END   0x0010

Definition at line 2563 of file tg3.h.

TXD_FLAG_VLAN

#define TXD_FLAG_VLAN   0x0040

Definition at line 2564 of file tg3.h.

TXD_FLAG_COAL_NOW

#define TXD_FLAG_COAL_NOW   0x0080

Definition at line 2565 of file tg3.h.

TXD_FLAG_CPU_PRE_DMA

#define TXD_FLAG_CPU_PRE_DMA   0x0100

Definition at line 2566 of file tg3.h.

TXD_FLAG_CPU_POST_DMA

#define TXD_FLAG_CPU_POST_DMA   0x0200

Definition at line 2567 of file tg3.h.

TXD_FLAG_ADD_SRC_ADDR

#define TXD_FLAG_ADD_SRC_ADDR   0x1000

Definition at line 2568 of file tg3.h.

TXD_FLAG_CHOOSE_SRC_ADDR

#define TXD_FLAG_CHOOSE_SRC_ADDR   0x6000

Definition at line 2569 of file tg3.h.

TXD_FLAG_NO_CRC

#define TXD_FLAG_NO_CRC   0x8000

Definition at line 2570 of file tg3.h.

TXD_LEN_SHIFT

#define TXD_LEN_SHIFT   16

Definition at line 2571 of file tg3.h.

Referenced by tg3_set_txd().

TXD_VLAN_TAG_SHIFT

#define TXD_VLAN_TAG_SHIFT   0

Definition at line 2574 of file tg3.h.

TXD_MSS_SHIFT

#define TXD_MSS_SHIFT   16

Definition at line 2575 of file tg3.h.

TXD_ADDR

#define TXD_ADDR   0x00UL /* 64-bit */

Definition at line 2578 of file tg3.h.

TXD_LEN_FLAGS

#define TXD_LEN_FLAGS   0x08UL /* 32-bit (upper 16-bits are len) */

Definition at line 2579 of file tg3.h.

TXD_VLAN_TAG

#define TXD_VLAN_TAG   0x0cUL /* 32-bit (upper 16-bits are tag) */

Definition at line 2580 of file tg3.h.

TXD_SIZE

#define TXD_SIZE   0x10UL

Definition at line 2581 of file tg3.h.

RXD_IDX_MASK

#define RXD_IDX_MASK   0xffff0000

Definition at line 2588 of file tg3.h.

RXD_IDX_SHIFT

#define RXD_IDX_SHIFT   16

Definition at line 2589 of file tg3.h.

RXD_LEN_MASK

#define RXD_LEN_MASK   0x0000ffff

Definition at line 2590 of file tg3.h.

Referenced by tg3_rx_complete().

RXD_LEN_SHIFT

#define RXD_LEN_SHIFT   0

Definition at line 2591 of file tg3.h.

Referenced by tg3_rx_complete(), and tg3_rx_prodring_alloc().

RXD_TYPE_SHIFT

#define RXD_TYPE_SHIFT   16

Definition at line 2594 of file tg3.h.

RXD_FLAGS_SHIFT

#define RXD_FLAGS_SHIFT   0

Definition at line 2595 of file tg3.h.

Referenced by tg3_rx_prodring_alloc().

RXD_FLAG_END

#define RXD_FLAG_END   0x0004

Definition at line 2597 of file tg3.h.

Referenced by tg3_rx_prodring_alloc().

RXD_FLAG_MINI

#define RXD_FLAG_MINI   0x0800

Definition at line 2598 of file tg3.h.

RXD_FLAG_JUMBO

#define RXD_FLAG_JUMBO   0x0020

Definition at line 2599 of file tg3.h.

RXD_FLAG_VLAN

#define RXD_FLAG_VLAN   0x0040

Definition at line 2600 of file tg3.h.

RXD_FLAG_ERROR

#define RXD_FLAG_ERROR   0x0400

Definition at line 2601 of file tg3.h.

RXD_FLAG_IP_CSUM

#define RXD_FLAG_IP_CSUM   0x1000

Definition at line 2602 of file tg3.h.

RXD_FLAG_TCPUDP_CSUM

#define RXD_FLAG_TCPUDP_CSUM   0x2000

Definition at line 2603 of file tg3.h.

RXD_FLAG_IS_TCP

#define RXD_FLAG_IS_TCP   0x4000

Definition at line 2604 of file tg3.h.

RXD_IPCSUM_MASK

#define RXD_IPCSUM_MASK   0xffff0000

Definition at line 2607 of file tg3.h.

RXD_IPCSUM_SHIFT

#define RXD_IPCSUM_SHIFT   16

Definition at line 2608 of file tg3.h.

RXD_TCPCSUM_MASK

#define RXD_TCPCSUM_MASK   0x0000ffff

Definition at line 2609 of file tg3.h.

RXD_TCPCSUM_SHIFT

#define RXD_TCPCSUM_SHIFT   0

Definition at line 2610 of file tg3.h.

RXD_VLAN_MASK

#define RXD_VLAN_MASK   0x0000ffff

Definition at line 2614 of file tg3.h.

RXD_ERR_BAD_CRC

#define RXD_ERR_BAD_CRC   0x00010000

Definition at line 2616 of file tg3.h.

RXD_ERR_COLLISION

#define RXD_ERR_COLLISION   0x00020000

Definition at line 2617 of file tg3.h.

RXD_ERR_LINK_LOST

#define RXD_ERR_LINK_LOST   0x00040000

Definition at line 2618 of file tg3.h.

RXD_ERR_PHY_DECODE

#define RXD_ERR_PHY_DECODE   0x00080000

Definition at line 2619 of file tg3.h.

RXD_ERR_ODD_NIBBLE_RCVD_MII

#define RXD_ERR_ODD_NIBBLE_RCVD_MII   0x00100000

Definition at line 2620 of file tg3.h.

Referenced by tg3_rx_complete().

RXD_ERR_MAC_ABRT

#define RXD_ERR_MAC_ABRT   0x00200000

Definition at line 2621 of file tg3.h.

RXD_ERR_TOO_SMALL

#define RXD_ERR_TOO_SMALL   0x00400000

Definition at line 2622 of file tg3.h.

RXD_ERR_NO_RESOURCES

#define RXD_ERR_NO_RESOURCES   0x00800000

Definition at line 2623 of file tg3.h.

RXD_ERR_HUGE_FRAME

#define RXD_ERR_HUGE_FRAME   0x01000000

Definition at line 2624 of file tg3.h.

RXD_ERR_MASK

#define RXD_ERR_MASK   0xffff0000

Definition at line 2625 of file tg3.h.

Referenced by tg3_rx_complete().

RXD_OPAQUE_INDEX_MASK

#define RXD_OPAQUE_INDEX_MASK   0x0000ffff

Definition at line 2629 of file tg3.h.

Referenced by tg3_rx_complete().

RXD_OPAQUE_INDEX_SHIFT

#define RXD_OPAQUE_INDEX_SHIFT   0

Definition at line 2630 of file tg3.h.

Referenced by tg3_rx_prodring_alloc().

RXD_OPAQUE_RING_STD

#define RXD_OPAQUE_RING_STD   0x00010000

Definition at line 2631 of file tg3.h.

Referenced by tg3_rx_prodring_alloc().

RXD_OPAQUE_RING_JUMBO

#define RXD_OPAQUE_RING_JUMBO   0x00020000

Definition at line 2632 of file tg3.h.

RXD_OPAQUE_RING_MINI

#define RXD_OPAQUE_RING_MINI   0x00040000

Definition at line 2633 of file tg3.h.

RXD_OPAQUE_RING_MASK

#define RXD_OPAQUE_RING_MASK   0x00070000

Definition at line 2634 of file tg3.h.

TG3_HW_STATUS_SIZE

#define TG3_HW_STATUS_SIZE   0x50

Definition at line 2669 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_alloc_consistent(), tg3_free_consistent(), tg3_init_rings(), tg3_reset_hw(), and tg3_rings_reset().

SD_STATUS_UPDATED

#define SD_STATUS_UPDATED   0x00000001

Definition at line 2672 of file tg3.h.

Referenced by tg3_enable_ints(), tg3_poll(), and tg3_setup_fiber_phy().

SD_STATUS_LINK_CHG

#define SD_STATUS_LINK_CHG   0x00000002

Definition at line 2673 of file tg3.h.

Referenced by tg3_poll_link(), and tg3_setup_fiber_phy().

SD_STATUS_ERROR

#define SD_STATUS_ERROR   0x00000004

Definition at line 2674 of file tg3.h.

SPEED_INVALID

#define SPEED_INVALID   0xffff

Definition at line 2835 of file tg3.h.

DUPLEX_INVALID

#define DUPLEX_INVALID   0xff

Definition at line 2836 of file tg3.h.

AUTONEG_INVALID

#define AUTONEG_INVALID   0xff

Definition at line 2837 of file tg3.h.

Referenced by tg3_phy_init_link_config().

TG3_DEF_RX_RING_PENDING

#define TG3_DEF_RX_RING_PENDING   8

Definition at line 2949 of file tg3.h.

Referenced by tg3_alloc_rx_iob(), tg3_refill_prod_ring(), tg3_rx_complete(), tg3_rx_prodring_free(), and tg3_setup_rxbd_thresholds().

TG3_IRQ_MAX_VECS_RSS

#define TG3_IRQ_MAX_VECS_RSS   5

Definition at line 2960 of file tg3.h.

TG3_IRQ_MAX_VECS

#define TG3_IRQ_MAX_VECS   TG3_IRQ_MAX_VECS_RSS

Definition at line 2961 of file tg3.h.

DIV_ROUND_UP

#define DIV_ROUND_UP	(		n,
			d )

Value:

(((n) + (d) - 1) / (d))

Definition at line 3039 of file tg3.h.

BITS_PER_BYTE

#define BITS_PER_BYTE   8

Definition at line 3041 of file tg3.h.

BITS_TO_LONGS

#define BITS_TO_LONGS

(

nr

)

Value:

DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))

Definition at line 3042 of file tg3.h.

DECLARE_BITMAP

#define DECLARE_BITMAP	(		name,
			bits )

Value:

        unsigned long name[BITS_TO_LONGS(bits)]

Definition at line 3044 of file tg3.h.

#define DECLARE_BITMAP(name,bits) \
        unsigned long name[BITS_TO_LONGS(bits)]

SERDES_AN_TIMEOUT_5704S

#define SERDES_AN_TIMEOUT_5704S   2

Definition at line 3150 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SERDES_PARALLEL_DET_TIMEOUT

#define SERDES_PARALLEL_DET_TIMEOUT   1

Definition at line 3151 of file tg3.h.

Referenced by tg3_setup_fiber_hw_autoneg().

SERDES_AN_TIMEOUT_5714S

#define SERDES_AN_TIMEOUT_5714S   1

Definition at line 3152 of file tg3.h.

Referenced by tg3_setup_fiber_mii_phy().

TG3_PHY_ID_MASK

#define TG3_PHY_ID_MASK   0xfffffff0

Definition at line 3185 of file tg3.h.

Referenced by tg3_5700_link_polarity(), tg3_phy_probe(), tg3_phy_reset(), and tg3_setup_copper_phy().

TG3_PHY_ID_BCM5400

#define TG3_PHY_ID_BCM5400   0x60008040

Definition at line 3186 of file tg3.h.

TG3_PHY_ID_BCM5401

#define TG3_PHY_ID_BCM5401   0x60008050

Definition at line 3187 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_reset(), and tg3_setup_copper_phy().

TG3_PHY_ID_BCM5411

#define TG3_PHY_ID_BCM5411   0x60008070

Definition at line 3188 of file tg3.h.

Referenced by tg3_5700_link_polarity(), and tg3_setup_copper_phy().

TG3_PHY_ID_BCM5701

#define TG3_PHY_ID_BCM5701   0x60008110

Definition at line 3189 of file tg3.h.

TG3_PHY_ID_BCM5703

#define TG3_PHY_ID_BCM5703   0x60008160

Definition at line 3190 of file tg3.h.

TG3_PHY_ID_BCM5704

#define TG3_PHY_ID_BCM5704   0x60008190

Definition at line 3191 of file tg3.h.

TG3_PHY_ID_BCM5705

#define TG3_PHY_ID_BCM5705   0x600081a0

Definition at line 3192 of file tg3.h.

TG3_PHY_ID_BCM5750

#define TG3_PHY_ID_BCM5750   0x60008180

Definition at line 3193 of file tg3.h.

TG3_PHY_ID_BCM5752

#define TG3_PHY_ID_BCM5752   0x60008100

Definition at line 3194 of file tg3.h.

TG3_PHY_ID_BCM5714

#define TG3_PHY_ID_BCM5714   0x60008340

Definition at line 3195 of file tg3.h.

TG3_PHY_ID_BCM5780

#define TG3_PHY_ID_BCM5780   0x60008350

Definition at line 3196 of file tg3.h.

TG3_PHY_ID_BCM5755

#define TG3_PHY_ID_BCM5755   0xbc050cc0

Definition at line 3197 of file tg3.h.

TG3_PHY_ID_BCM5787

#define TG3_PHY_ID_BCM5787   0xbc050ce0

Definition at line 3198 of file tg3.h.

TG3_PHY_ID_BCM5756

#define TG3_PHY_ID_BCM5756   0xbc050ed0

Definition at line 3199 of file tg3.h.

TG3_PHY_ID_BCM5784

#define TG3_PHY_ID_BCM5784   0xbc050fa0

Definition at line 3200 of file tg3.h.

TG3_PHY_ID_BCM5761

#define TG3_PHY_ID_BCM5761   0xbc050fd0

Definition at line 3201 of file tg3.h.

TG3_PHY_ID_BCM5718C

#define TG3_PHY_ID_BCM5718C   0x5c0d8a00

Definition at line 3202 of file tg3.h.

TG3_PHY_ID_BCM5718S

#define TG3_PHY_ID_BCM5718S   0xbc050ff0

Definition at line 3203 of file tg3.h.

TG3_PHY_ID_BCM57765

#define TG3_PHY_ID_BCM57765   0x5c0d8a40

Definition at line 3204 of file tg3.h.

TG3_PHY_ID_BCM5719C

#define TG3_PHY_ID_BCM5719C   0x5c0d8a20

Definition at line 3205 of file tg3.h.

TG3_PHY_ID_BCM5720C

#define TG3_PHY_ID_BCM5720C   0x5c0d8b60

Definition at line 3206 of file tg3.h.

TG3_PHY_ID_BCM5906

#define TG3_PHY_ID_BCM5906   0xdc00ac40

Definition at line 3207 of file tg3.h.

TG3_PHY_ID_BCM8002

#define TG3_PHY_ID_BCM8002   0x60010140

Definition at line 3208 of file tg3.h.

Referenced by tg3_phy_probe(), and tg3_setup_fiber_phy().

TG3_PHY_ID_INVALID

#define TG3_PHY_ID_INVALID   0xffffffff

Definition at line 3209 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), and tg3_phy_probe().

PHY_ID_RTL8211C

#define PHY_ID_RTL8211C   0x001cc910

Definition at line 3211 of file tg3.h.

PHY_ID_RTL8201E

#define PHY_ID_RTL8201E   0x00008200

Definition at line 3212 of file tg3.h.

TG3_PHY_ID_REV_MASK

#define TG3_PHY_ID_REV_MASK   0x0000000f

Definition at line 3214 of file tg3.h.

Referenced by tg3_setup_copper_phy().

TG3_PHY_REV_BCM5401_B0

#define TG3_PHY_REV_BCM5401_B0   0x1

Definition at line 3215 of file tg3.h.

Referenced by tg3_setup_copper_phy().

TG3_KNOWN_PHY_ID

#define TG3_KNOWN_PHY_ID

(

X

)

Value:

        ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
         (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
         (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
         (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
         (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
         (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
         (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
         (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
         (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
         (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
         (X) == TG3_PHY_ID_BCM8002)

Definition at line 3220 of file tg3.h.

#define TG3_KNOWN_PHY_ID(X)             \
        ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
         (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
         (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
         (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
         (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
         (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
         (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
         (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
         (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
         (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
         (X) == TG3_PHY_ID_BCM8002)

Referenced by tg3_phy_probe().

TG3_PHYFLG_IS_LOW_POWER

#define TG3_PHYFLG_IS_LOW_POWER   0x00000001

Definition at line 3234 of file tg3.h.

TG3_PHYFLG_IS_CONNECTED

#define TG3_PHYFLG_IS_CONNECTED   0x00000002

Definition at line 3235 of file tg3.h.

TG3_PHYFLG_USE_MI_INTERRUPT

#define TG3_PHYFLG_USE_MI_INTERRUPT   0x00000004

Definition at line 3236 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_copper_phy().

TG3_PHYFLG_PHY_SERDES

#define TG3_PHYFLG_PHY_SERDES   0x00000010

Definition at line 3237 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_phy_probe(), tg3_reset_hw(), and tg3_setup_phy().

TG3_PHYFLG_MII_SERDES

#define TG3_PHYFLG_MII_SERDES   0x00000020

Definition at line 3238 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), tg3_phy_reset(), tg3_reset_hw(), tg3_setup_phy(), tg3_test_and_report_link_chg(), and tg3_ump_link_report().

TG3_PHYFLG_ANY_SERDES

#define TG3_PHYFLG_ANY_SERDES

Value:

                                        (TG3_PHYFLG_PHY_SERDES |   \
                                        TG3_PHYFLG_MII_SERDES)

Definition at line 3239 of file tg3.h.

#define TG3_PHYFLG_ANY_SERDES           (TG3_PHYFLG_PHY_SERDES |        \
                                        TG3_PHYFLG_MII_SERDES)

Referenced by tg3_get_invariants(), tg3_phy_init_link_config(), tg3_phy_probe(), tg3_phy_toggle_automdix(), and tg3_setup_flow_control().

TG3_PHYFLG_IS_FET

#define TG3_PHYFLG_IS_FET   0x00000040

Definition at line 3241 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex(), tg3_get_invariants(), tg3_phy_toggle_automdix(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_writephy().

TG3_PHYFLG_10_100_ONLY

#define TG3_PHYFLG_10_100_ONLY   0x00000080

Definition at line 3242 of file tg3.h.

Referenced by tg3_copper_is_advertising_all(), tg3_get_invariants(), tg3_phy_autoneg_cfg(), tg3_phy_copper_begin(), and tg3_phy_init_link_config().

TG3_PHYFLG_ENABLE_APD

#define TG3_PHYFLG_ENABLE_APD   0x00000100

Definition at line 3243 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg().

TG3_PHYFLG_CAPACITIVE_COUPLING

#define TG3_PHYFLG_CAPACITIVE_COUPLING   0x00000200

Definition at line 3244 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), and tg3_setup_copper_phy().

TG3_PHYFLG_NO_ETH_WIRE_SPEED

#define TG3_PHYFLG_NO_ETH_WIRE_SPEED   0x00000400

Definition at line 3245 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_set_wirespeed().

TG3_PHYFLG_JITTER_BUG

#define TG3_PHYFLG_JITTER_BUG   0x00000800

Definition at line 3246 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_reset().

TG3_PHYFLG_ADJUST_TRIM

#define TG3_PHYFLG_ADJUST_TRIM   0x00001000

Definition at line 3247 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_reset().

TG3_PHYFLG_ADC_BUG

#define TG3_PHYFLG_ADC_BUG   0x00002000

Definition at line 3248 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_reset().

TG3_PHYFLG_5704_A0_BUG

#define TG3_PHYFLG_5704_A0_BUG   0x00004000

Definition at line 3249 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_reset().

TG3_PHYFLG_BER_BUG

#define TG3_PHYFLG_BER_BUG   0x00008000

Definition at line 3250 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_reset().

TG3_PHYFLG_SERDES_PREEMPHASIS

#define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000

Definition at line 3251 of file tg3.h.

Referenced by tg3_get_eeprom_hw_cfg(), and tg3_reset_hw().

TG3_PHYFLG_PARALLEL_DETECT

#define TG3_PHYFLG_PARALLEL_DETECT   0x00020000

Definition at line 3252 of file tg3.h.

Referenced by tg3_reset_hw(), tg3_setup_fiber_hw_autoneg(), tg3_setup_fiber_mii_phy(), and tg3_test_and_report_link_chg().

TG3_PHYFLG_EEE_CAP

#define TG3_PHYFLG_EEE_CAP   0x00040000

Definition at line 3253 of file tg3.h.

Referenced by tg3_link_report(), tg3_phy_autoneg_cfg(), and tg3_phy_probe().

TG3_BPN_SIZE

#define TG3_BPN_SIZE   24

Definition at line 3259 of file tg3.h.

TG3_VER_SIZE

#define TG3_VER_SIZE   32

Definition at line 3261 of file tg3.h.

TG3_NVRAM_SIZE_2KB

#define TG3_NVRAM_SIZE_2KB   0x00000800

Definition at line 3269 of file tg3.h.

TG3_NVRAM_SIZE_64KB

#define TG3_NVRAM_SIZE_64KB   0x00010000

Definition at line 3270 of file tg3.h.

TG3_NVRAM_SIZE_128KB

#define TG3_NVRAM_SIZE_128KB   0x00020000

Definition at line 3271 of file tg3.h.

TG3_NVRAM_SIZE_256KB

#define TG3_NVRAM_SIZE_256KB   0x00040000

Definition at line 3272 of file tg3.h.

TG3_NVRAM_SIZE_512KB

#define TG3_NVRAM_SIZE_512KB   0x00080000

Definition at line 3273 of file tg3.h.

TG3_NVRAM_SIZE_1MB

#define TG3_NVRAM_SIZE_1MB   0x00100000

Definition at line 3274 of file tg3.h.

TG3_NVRAM_SIZE_2MB

#define TG3_NVRAM_SIZE_2MB   0x00200000

Definition at line 3275 of file tg3.h.

JEDEC_ATMEL

#define JEDEC_ATMEL   0x1f

Definition at line 3280 of file tg3.h.

Referenced by tg3_nvram_phys_addr().

JEDEC_ST

#define JEDEC_ST   0x20

Definition at line 3281 of file tg3.h.

JEDEC_SAIFUN

#define JEDEC_SAIFUN   0x4f

Definition at line 3282 of file tg3.h.

JEDEC_SST

#define JEDEC_SST   0xbf

Definition at line 3283 of file tg3.h.

ATMEL_AT24C02_CHIP_SIZE

#define ATMEL_AT24C02_CHIP_SIZE   TG3_NVRAM_SIZE_2KB

Definition at line 3285 of file tg3.h.

ATMEL_AT24C02_PAGE_SIZE

#define ATMEL_AT24C02_PAGE_SIZE   (8)

Definition at line 3286 of file tg3.h.

ATMEL_AT24C64_CHIP_SIZE

#define ATMEL_AT24C64_CHIP_SIZE   TG3_NVRAM_SIZE_64KB

Definition at line 3288 of file tg3.h.

ATMEL_AT24C64_PAGE_SIZE

#define ATMEL_AT24C64_PAGE_SIZE   (32)

Definition at line 3289 of file tg3.h.

ATMEL_AT24C512_CHIP_SIZE

#define ATMEL_AT24C512_CHIP_SIZE   TG3_NVRAM_SIZE_512KB

Definition at line 3291 of file tg3.h.

ATMEL_AT24C512_PAGE_SIZE

#define ATMEL_AT24C512_PAGE_SIZE   (128)

Definition at line 3292 of file tg3.h.

ATMEL_AT45DB0X1B_PAGE_POS

#define ATMEL_AT45DB0X1B_PAGE_POS   9

Definition at line 3294 of file tg3.h.

Referenced by tg3_nvram_phys_addr().

ATMEL_AT45DB0X1B_PAGE_SIZE

#define ATMEL_AT45DB0X1B_PAGE_SIZE   264

Definition at line 3295 of file tg3.h.

ATMEL_AT25F512_PAGE_SIZE

#define ATMEL_AT25F512_PAGE_SIZE   256

Definition at line 3297 of file tg3.h.

ST_M45PEX0_PAGE_SIZE

#define ST_M45PEX0_PAGE_SIZE   256

Definition at line 3299 of file tg3.h.

SAIFUN_SA25F0XX_PAGE_SIZE

#define SAIFUN_SA25F0XX_PAGE_SIZE   256

Definition at line 3301 of file tg3.h.

SST_25VF0X0_PAGE_SIZE

#define SST_25VF0X0_PAGE_SIZE   4098

Definition at line 3303 of file tg3.h.

TG3_TX_RING_SIZE

#define TG3_TX_RING_SIZE   512

Definition at line 3310 of file tg3.h.

Referenced by tg3_alloc_consistent(), tg3_rings_reset(), and tg3_tx_avail().

TG3_DEF_TX_RING_PENDING

#define TG3_DEF_TX_RING_PENDING   (TG3_TX_RING_SIZE - 1)

Definition at line 3311 of file tg3.h.

Referenced by tg3_tx_avail().

TG3_DMA_ALIGNMENT

#define TG3_DMA_ALIGNMENT   16

Definition at line 3313 of file tg3.h.

Referenced by tg3_alloc_consistent(), and tg3_test_dma().

TG3_RX_STD_DMA_SZ

#define TG3_RX_STD_DMA_SZ   (1536 + 64 + 2)

Definition at line 3315 of file tg3.h.

Referenced by tg3_alloc_rx_iob(), and tg3_rx_prodring_alloc().

tw32

#define tw32	(		reg,
			val )

Value:

tg3_write_indirect_reg32(tp, reg, val)

Definition at line 3329 of file tg3.h.

Referenced by __tg3_set_coalesce(), __tg3_set_mac_addr(), __tg3_set_rx_mode(), _tw32_flush(), tg3_abort_hw(), tg3_chip_reset(), tg3_clear_mac_status(), tg3_disable_ints(), tg3_disable_nvram_access(), tg3_do_test_dma(), tg3_enable_ints(), tg3_enable_nvram_access(), tg3_fiber_aneg_smachine(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_init_hw(), tg3_init_one(), tg3_issue_otp_command(), tg3_nvram_exec_cmd(), tg3_nvram_lock(), tg3_nvram_read(), tg3_nvram_read_using_eeprom(), tg3_phy_reset(), tg3_read_otp_phycfg(), tg3_reset_hw(), tg3_rings_reset(), tg3_setup_copper_phy(), tg3_setup_fiber_phy(), tg3_setup_phy(), tg3_setup_rxbd_thresholds(), and tg3_test_dma().

tw32_mailbox

#define tw32_mailbox	(		reg,
			val )

Value:

tg3_write_indirect_mbox(tp, (reg), (val))

#define tw32_mailbox(reg, val) tg3_write_indirect_mbox(((val) & 0xffffffff), tp->regs + (reg))

Definition at line 3331 of file tg3.h.

Referenced by tg3_rings_reset().

tw32_mailbox_f

#define tw32_mailbox_f	(		reg,
			val )

Value:

tw32_mailbox_flush(tp, (reg), (val))

Definition at line 3332 of file tg3.h.

Referenced by tg3_disable_ints(), tg3_enable_ints(), and tg3_rings_reset().

tw32_f

#define tw32_f	(		reg,
			val )

Value:

_tw32_flush(tp, (reg), (val), 0)

Definition at line 3333 of file tg3.h.

Referenced by __tg3_set_rx_mode(), fiber_autoneg(), tg3_abort_hw(), tg3_chip_reset(), tg3_clear_mac_status(), tg3_do_test_dma(), tg3_fiber_aneg_smachine(), tg3_generate_fw_event(), tg3_get_device_address(), tg3_nvram_unlock(), tg3_phy_reset(), tg3_readphy(), tg3_reset_hw(), tg3_setup_copper_phy(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tg3_setup_flow_control(), tg3_stop_block(), and tg3_writephy().

tw32_wait_f

#define tw32_wait_f	(		reg,
			val,
			us )

Value:

_tw32_flush(tp, (reg), (val), (us))

Definition at line 3334 of file tg3.h.

Referenced by tg3_set_power_state_0(), and tg3_switch_clocks().

tw32_tx_mbox

#define tw32_tx_mbox	(		reg,
			val )

Value:

tp->write32_tx_mbox(tp, reg, val)

Definition at line 3336 of file tg3.h.

Referenced by tg3_rings_reset(), and tg3_transmit().

tw32_rx_mbox

#define tw32_rx_mbox	(		reg,
			val )

Value:

tp->write32_rx_mbox(tp, reg, val)

Definition at line 3337 of file tg3.h.

Referenced by tg3_refill_prod_ring(), tg3_reset_hw(), tg3_rings_reset(), and tg3_rx_complete().

tr32

#define tr32

(

reg

)

Value:

tg3_read_indirect_reg32(tp, reg)

Definition at line 3339 of file tg3.h.

Referenced by _tw32_flush(), tg3_abort_hw(), tg3_chip_reset(), tg3_disable_nvram_access(), tg3_do_test_dma(), tg3_enable_nvram_access(), tg3_fiber_aneg_smachine(), tg3_generate_fw_event(), tg3_get_device_address(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_init_bcm8002(), tg3_init_one(), tg3_issue_otp_command(), tg3_mdio_init(), tg3_nvram_exec_cmd(), tg3_nvram_lock(), tg3_nvram_read(), tg3_nvram_read_using_eeprom(), tg3_phy_reset(), tg3_poll_fw(), tg3_read_otp_phycfg(), tg3_readphy(), tg3_reset_hw(), tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tg3_setup_phy(), tg3_stop_block(), tg3_switch_clocks(), tg3_test_dma(), tg3_wait_for_event_ack(), and tg3_writephy().

tr32_mailbox

#define tr32_mailbox

(

reg

)

Value:

tp->read32_mbox(tp, reg)

Definition at line 3340 of file tg3.h.

tg3_flag

#define tg3_flag	(		tp,
			flag )

Value:

        _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)

Definition at line 3365 of file tg3.h.

#define tg3_flag(tp, flag)                              \
        _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)

Referenced by __tg3_set_coalesce(), tg3_adv_1000T_flowctrl_ok(), tg3_chip_reset(), tg3_disable_nvram_access(), tg3_enable_ints(), tg3_enable_nvram_access(), tg3_get_device_address(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_init_bcm8002(), tg3_init_bufmgr_config(), tg3_mdio_init(), tg3_nvram_lock(), tg3_nvram_phys_addr(), tg3_nvram_read(), tg3_nvram_unlock(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_toggle_automdix(), tg3_poll_fw(), tg3_reset_hw(), tg3_restore_pci_state(), tg3_rings_reset(), tg3_set_bdinfo(), tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tg3_setup_flow_control(), tg3_setup_phy(), tg3_setup_rxbd_thresholds(), tg3_stop_block(), tg3_stop_fw(), tg3_switch_clocks(), tg3_test_dma(), and tg3_ump_link_report().

tg3_flag_set

#define tg3_flag_set	(		tp,
			flag )

Value:

        _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)

Definition at line 3367 of file tg3.h.

#define tg3_flag_set(tp, flag)                          \
        _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)

Referenced by tg3_chip_reset(), tg3_get_eeprom_hw_cfg(), tg3_get_invariants(), tg3_phy_probe(), tg3_poll_fw(), and tg3_reset_hw().

tg3_flag_clear

#define tg3_flag_clear	(		tp,
			flag )

Value:

        _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)

Definition at line 3369 of file tg3.h.

#define tg3_flag_clear(tp, flag)                        \
        _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)

Referenced by tg3_chip_reset(), tg3_close(), tg3_get_eeprom_hw_cfg(), and tg3_get_invariants().

ETH_FCS_LEN

#define ETH_FCS_LEN   4

Definition at line 3469 of file tg3.h.

Enumeration Type Documentation

TG3_FLAGS

enum TG3_FLAGS

Enumerator
TG3_FLAG_TAGGED_STATUS
TG3_FLAG_TXD_MBOX_HWBUG
TG3_FLAG_USE_LINKCHG_REG
TG3_FLAG_ERROR_PROCESSED
TG3_FLAG_ENABLE_ASF
TG3_FLAG_ASPM_WORKAROUND
TG3_FLAG_POLL_SERDES
TG3_FLAG_MBOX_WRITE_REORDER
TG3_FLAG_PCIX_TARGET_HWBUG
TG3_FLAG_WOL_SPEED_100MB
TG3_FLAG_WOL_ENABLE
TG3_FLAG_EEPROM_WRITE_PROT
TG3_FLAG_NVRAM
TG3_FLAG_NVRAM_BUFFERED
TG3_FLAG_SUPPORT_MSI
TG3_FLAG_SUPPORT_MSIX
TG3_FLAG_PCIX_MODE
TG3_FLAG_PCI_HIGH_SPEED
TG3_FLAG_PCI_32BIT
TG3_FLAG_SRAM_USE_CONFIG
TG3_FLAG_TX_RECOVERY_PENDING
TG3_FLAG_WOL_CAP
TG3_FLAG_JUMBO_RING_ENABLE
TG3_FLAG_PAUSE_AUTONEG
TG3_FLAG_CPMU_PRESENT
TG3_FLAG_BROKEN_CHECKSUMS
TG3_FLAG_JUMBO_CAPABLE
TG3_FLAG_CHIP_RESETTING
TG3_FLAG_INIT_COMPLETE
TG3_FLAG_RESTART_TIMER
TG3_FLAG_TSO_BUG
TG3_FLAG_IS_5788
TG3_FLAG_MAX_RXPEND_64
TG3_FLAG_TSO_CAPABLE
TG3_FLAG_PCI_EXPRESS
TG3_FLAG_ASF_NEW_HANDSHAKE
TG3_FLAG_HW_AUTONEG
TG3_FLAG_IS_NIC
TG3_FLAG_FLASH
TG3_FLAG_HW_TSO_1
TG3_FLAG_5705_PLUS
TG3_FLAG_5750_PLUS
TG3_FLAG_HW_TSO_3
TG3_FLAG_USING_MSI
TG3_FLAG_USING_MSIX
TG3_FLAG_ICH_WORKAROUND
TG3_FLAG_5780_CLASS
TG3_FLAG_HW_TSO_2
TG3_FLAG_1SHOT_MSI
TG3_FLAG_NO_FWARE_REPORTED
TG3_FLAG_NO_NVRAM_ADDR_TRANS
TG3_FLAG_ENABLE_APE
TG3_FLAG_PROTECTED_NVRAM
TG3_FLAG_MDIOBUS_INITED
TG3_FLAG_LRG_PROD_RING_CAP
TG3_FLAG_RGMII_INBAND_DISABLE
TG3_FLAG_RGMII_EXT_IBND_RX_EN
TG3_FLAG_RGMII_EXT_IBND_TX_EN
TG3_FLAG_CLKREQ_BUG
TG3_FLAG_5755_PLUS
TG3_FLAG_NO_NVRAM
TG3_FLAG_ENABLE_RSS
TG3_FLAG_ENABLE_TSS
TG3_FLAG_4G_DMA_BNDRY_BUG
TG3_FLAG_USE_JUMBO_BDFLAG
TG3_FLAG_L1PLLPD_EN
TG3_FLAG_57765_PLUS
TG3_FLAG_APE_HAS_NCSI
TG3_FLAG_5717_PLUS
TG3_FLAG_NUMBER_OF_FLAGS

Definition at line 2963 of file tg3.h.

               {
        TG3_FLAG_TAGGED_STATUS = 0,
        TG3_FLAG_TXD_MBOX_HWBUG,
        TG3_FLAG_USE_LINKCHG_REG,
        TG3_FLAG_ERROR_PROCESSED,
        TG3_FLAG_ENABLE_ASF,
        TG3_FLAG_ASPM_WORKAROUND,
        TG3_FLAG_POLL_SERDES,
        TG3_FLAG_MBOX_WRITE_REORDER,
        TG3_FLAG_PCIX_TARGET_HWBUG,
        TG3_FLAG_WOL_SPEED_100MB,
        TG3_FLAG_WOL_ENABLE,
        TG3_FLAG_EEPROM_WRITE_PROT,
        TG3_FLAG_NVRAM,
        TG3_FLAG_NVRAM_BUFFERED,
        TG3_FLAG_SUPPORT_MSI,
        TG3_FLAG_SUPPORT_MSIX,
        TG3_FLAG_PCIX_MODE,
        TG3_FLAG_PCI_HIGH_SPEED,
        TG3_FLAG_PCI_32BIT,
        TG3_FLAG_SRAM_USE_CONFIG,
        TG3_FLAG_TX_RECOVERY_PENDING,
        TG3_FLAG_WOL_CAP,
        TG3_FLAG_JUMBO_RING_ENABLE,
        TG3_FLAG_PAUSE_AUTONEG,
        TG3_FLAG_CPMU_PRESENT,
        TG3_FLAG_BROKEN_CHECKSUMS,
        TG3_FLAG_JUMBO_CAPABLE,
        TG3_FLAG_CHIP_RESETTING,
        TG3_FLAG_INIT_COMPLETE,
        TG3_FLAG_RESTART_TIMER,
        TG3_FLAG_TSO_BUG,
        TG3_FLAG_IS_5788,
        TG3_FLAG_MAX_RXPEND_64,
        TG3_FLAG_TSO_CAPABLE,
        TG3_FLAG_PCI_EXPRESS,
        TG3_FLAG_ASF_NEW_HANDSHAKE,
        TG3_FLAG_HW_AUTONEG,
        TG3_FLAG_IS_NIC,
        TG3_FLAG_FLASH,
        TG3_FLAG_HW_TSO_1,
        TG3_FLAG_5705_PLUS,
        TG3_FLAG_5750_PLUS,
        TG3_FLAG_HW_TSO_3,
        TG3_FLAG_USING_MSI,
        TG3_FLAG_USING_MSIX,
        TG3_FLAG_ICH_WORKAROUND,
        TG3_FLAG_5780_CLASS,
        TG3_FLAG_HW_TSO_2,
        TG3_FLAG_1SHOT_MSI,
        TG3_FLAG_NO_FWARE_REPORTED,
        TG3_FLAG_NO_NVRAM_ADDR_TRANS,
        TG3_FLAG_ENABLE_APE,
        TG3_FLAG_PROTECTED_NVRAM,
        TG3_FLAG_MDIOBUS_INITED,
        TG3_FLAG_LRG_PROD_RING_CAP,
        TG3_FLAG_RGMII_INBAND_DISABLE,
        TG3_FLAG_RGMII_EXT_IBND_RX_EN,
        TG3_FLAG_RGMII_EXT_IBND_TX_EN,
        TG3_FLAG_CLKREQ_BUG,
        TG3_FLAG_5755_PLUS,
        TG3_FLAG_NO_NVRAM,
        TG3_FLAG_ENABLE_RSS,
        TG3_FLAG_ENABLE_TSS,
        TG3_FLAG_4G_DMA_BNDRY_BUG,
        TG3_FLAG_USE_JUMBO_BDFLAG,
        TG3_FLAG_L1PLLPD_EN,
        TG3_FLAG_57765_PLUS,
        TG3_FLAG_APE_HAS_NCSI,
        TG3_FLAG_5717_PLUS,
 
        /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
        TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
};

Function Documentation

tw32_mailbox_flush()

void tw32_mailbox_flush ( struct tg3 * tp, u32 off, u32 val )

inlinestatic

if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND)) tp->read32_mbox(tp, off);

Definition at line 3317 of file tg3.h.

{
        tp->write32_mbox(tp, off, val);
///     if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
///             tp->read32_mbox(tp, off);
}

References tp, u32, and val.

tg3_read_indirect_reg32()

u32 tg3_read_indirect_reg32	(	struct tg3 *	tp,
		u32	off )

Definition at line 49 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        u32 val;
 
        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
        pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
        return val;
}

References DBGP, pci_read_config_dword(), pci_write_config_dword(), TG3PCI_REG_BASE_ADDR, TG3PCI_REG_DATA, tp, u32, and val.

tg3_write_indirect_reg32()

void tg3_write_indirect_reg32	(	struct tg3 *	tp,
		u32	off,
		u32	val )

Definition at line 42 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
        pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
}

References DBGP, pci_write_config_dword(), TG3PCI_REG_BASE_ADDR, TG3PCI_REG_DATA, tp, u32, and val.

Referenced by tg3_get_invariants().

tg3_read_indirect_mbox()

u32 tg3_read_indirect_mbox	(	struct tg3 *	tp,
		u32	off )

Definition at line 98 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        u32 val;
 
        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
        pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 
        return val;
}

References DBGP, pci_read_config_dword(), pci_write_config_dword(), TG3PCI_REG_BASE_ADDR, TG3PCI_REG_DATA, tp, u32, and val.

Referenced by tg3_get_invariants().

tg3_write_indirect_mbox()

void tg3_write_indirect_mbox	(	struct tg3 *	tp,
		u32	off,
		u32	val )

Definition at line 71 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
                pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
                                       TG3_64BIT_REG_LOW, val);
                return;
        }
        if (off == TG3_RX_STD_PROD_IDX_REG) {
                pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
                                       TG3_64BIT_REG_LOW, val);
                return;
        }
 
        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
        pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 
        /* In indirect mode when disabling interrupts, we also need
         * to clear the interrupt bit in the GRC local ctrl register.
         */
        if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
            (val == 0x1)) {
                pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
                                       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
        }
}

References DBGP, GRC_LCLCTRL_CLEARINT, MAILBOX_INTERRUPT_0, MAILBOX_RCVRET_CON_IDX_0, pci_write_config_dword(), TG3_64BIT_REG_LOW, TG3_RX_STD_PROD_IDX_REG, TG3PCI_MISC_LOCAL_CTRL, TG3PCI_RCV_RET_RING_CON_IDX, TG3PCI_REG_BASE_ADDR, TG3PCI_REG_DATA, TG3PCI_STD_RING_PROD_IDX, tp, u32, and val.

Referenced by tg3_get_invariants().

_tg3_flag()

int _tg3_flag ( enum TG3_FLAGS flag, unsigned long * bits )

inlinestatic

Definition at line 3344 of file tg3.h.

{
        unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
        unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
        return ( !! ( bits[index] & ( 1UL << bit ) ) );
}

References bit, bits, flag, and index.

_tg3_flag_set()

void _tg3_flag_set ( enum TG3_FLAGS flag, unsigned long * bits )

inlinestatic

Definition at line 3351 of file tg3.h.

{
        unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
        unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
        bits[index] |= ( 1UL << bit );
}

References bit, bits, flag, and index.

_tg3_flag_clear()

void _tg3_flag_clear ( enum TG3_FLAGS flag, unsigned long * bits )

inlinestatic

Definition at line 3358 of file tg3.h.

{
        unsigned int index = ( flag / ( 8 * sizeof ( *bits ) ) );
        unsigned int bit = ( flag % ( 8 * sizeof ( *bits ) ) );
        bits[index] &= ~( 1UL << bit );
}

References bit, bits, flag, and index.

tg3_init_rings()

int tg3_init_rings

(

struct tg3 *

tp

)

tg3_free_rings(tp);

Definition at line 204 of file tg3.c.

{       DBGP("%s\n", __func__);
 
        /* Free up all the SKBs. */
///     tg3_free_rings(tp);
 
        tp->last_tag = 0;
        tp->last_irq_tag = 0;
        tp->hw_status->status = 0;
        tp->hw_status->status_tag = 0;
        memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
 
        tp->tx_prod = 0;
        tp->tx_cons = 0;
        if (tp->tx_ring)
                memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
 
        tp->rx_rcb_ptr = 0;
        if (tp->rx_rcb)
                memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
 
        if (tg3_rx_prodring_alloc(tp, &tp->prodring)) {
                DBGC(tp->dev, "tg3_rx_prodring_alloc() failed\n");
                tg3_rx_prodring_free(&tp->prodring);
                return -ENOMEM;
        }
 
        return 0;
}

References DBGC, DBGP, ENOMEM, memset(), TG3_HW_STATUS_SIZE, tg3_rx_prodring_alloc(), tg3_rx_prodring_free(), TG3_RX_RCB_RING_BYTES, TG3_TX_RING_BYTES, and tp.

Referenced by tg3_reset_hw().

tg3_rx_prodring_fini()

void tg3_rx_prodring_fini

(

struct tg3_rx_prodring_set *

tpr

)

Definition at line 42 of file tg3.c.

{       DBGP("%s\n", __func__);
 
        if (tpr->rx_std) {
                free_phys(tpr->rx_std, TG3_RX_STD_RING_BYTES(tp));
                tpr->rx_std = NULL;
        }
}

References DBGP, free_phys(), NULL, tg3_rx_prodring_set::rx_std, TG3_RX_STD_RING_BYTES, and tp.

Referenced by tg3_free_consistent().

tg3_read_otp_phycfg()

u32 tg3_read_otp_phycfg

(

struct tg3 *

tp

)

int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);

Definition at line 57 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 bhalf_otp, thalf_otp;
 
        tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
 
        if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
                return 0;
 
        tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
 
        if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
                return 0;
 
        thalf_otp = tr32(OTP_READ_DATA);
 
        tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
 
        if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
                return 0;
 
        bhalf_otp = tr32(OTP_READ_DATA);
 
        return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
}

References DBGP, OTP_ADDRESS, OTP_ADDRESS_MAGIC1, OTP_ADDRESS_MAGIC2, OTP_CTRL_OTP_CMD_INIT, OTP_CTRL_OTP_CMD_READ, OTP_MODE, OTP_MODE_OTP_THRU_GRC, OTP_READ_DATA, tg3_issue_otp_command(), tp, tr32, tw32, and u32.

Referenced by tg3_get_invariants().

tg3_mdio_init()

void tg3_mdio_init

(

struct tg3 *

tp

)

Definition at line 14 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        if (tg3_flag(tp, 5717_PLUS)) {
                u32 is_serdes;
 
                tp->phy_addr = PCI_FUNC(tp->pdev->busdevfn) + 1;
 
                if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
                        is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
                else
                        is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
                                    TG3_CPMU_PHY_STRAP_IS_SERDES;
                if (is_serdes)
                        tp->phy_addr += 7;
        } else
                tp->phy_addr = TG3_PHY_MII_ADDR;
}

References CHIPREV_ID_5717_A0, DBGP, PCI_FUNC, SG_DIG_IS_SERDES, SG_DIG_STATUS, TG3_CPMU_PHY_STRAP, TG3_CPMU_PHY_STRAP_IS_SERDES, tg3_flag, TG3_PHY_MII_ADDR, tp, tr32, and u32.

Referenced by tg3_get_invariants().

tg3_phy_probe()

int tg3_phy_probe

(

struct tg3 *

tp

)

Definition at line 896 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 hw_phy_id_1, hw_phy_id_2;
        u32 hw_phy_id, hw_phy_id_masked;
        int err;
 
        /* flow control autonegotiation is default behavior */
        tg3_flag_set(tp, PAUSE_AUTONEG);
        tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 
        /* Reading the PHY ID register can conflict with ASF
         * firmware access to the PHY hardware.
         */
        err = 0;
        if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
                hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
        } else {
                /* Now read the physical PHY_ID from the chip and verify
                 * that it is sane.  If it doesn't look good, we fall back
                 * to either the hard-coded table based PHY_ID and failing
                 * that the value found in the eeprom area.
                 */
                err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
                err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
 
                hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
                hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
                hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
 
                hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
        }
 
        if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
                tp->phy_id = hw_phy_id;
                if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
                        tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                else
                        tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
        } else {
                if (tp->phy_id != TG3_PHY_ID_INVALID) {
                        /* Do nothing, phy ID already set up in
                         * tg3_get_eeprom_hw_cfg().
                         */
                } else {
                        struct subsys_tbl_ent *p;
 
                        /* No eeprom signature?  Try the hardcoded
                         * subsys device table.
                         */
                        p = tg3_lookup_by_subsys(tp);
                        if (!p) {
                                DBGC(&tp->pdev->dev, "lookup by subsys failed\n");
                                return -ENODEV;
                        }
 
                        tp->phy_id = p->phy_id;
                        if (!tp->phy_id ||
                            tp->phy_id == TG3_PHY_ID_BCM8002)
                                tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                }
        }
 
        if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
            ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
              tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
                tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
 
        tg3_phy_init_link_config(tp);
 
        if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
            !tg3_flag(tp, ENABLE_APE) &&
            !tg3_flag(tp, ENABLE_ASF)) {
                u32 bmsr;
                u32 mask;
 
                tg3_readphy(tp, MII_BMSR, &bmsr);
                if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
                    (bmsr & BMSR_LSTATUS))
                        goto skip_phy_reset;
 
                err = tg3_phy_reset(tp);
                if (err)
                        return err;
 
                tg3_phy_set_wirespeed(tp);
 
                mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
                        ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
                        ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
                if (!tg3_copper_is_advertising_all(tp, mask)) {
                        tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
                                            tp->link_config.flowctrl);
 
                        tg3_writephy(tp, MII_BMCR,
                                     BMCR_ANENABLE | BMCR_ANRESTART);
                }
        }
 
skip_phy_reset:
        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
                err = tg3_init_5401phy_dsp(tp);
                if (err)
                        return err;
 
                err = tg3_init_5401phy_dsp(tp);
        }
 
        return err;
}

References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, ASIC_REV_57765, BMCR_ANENABLE, BMCR_ANRESTART, BMSR_LSTATUS, CHIPREV_ID_5717_A0, CHIPREV_ID_57765_A0, DBGC, DBGP, ENODEV, FLOW_CTRL_RX, FLOW_CTRL_TX, GET_ASIC_REV, MII_BMCR, MII_BMSR, MII_PHYSID1, MII_PHYSID2, subsys_tbl_ent::phy_id, tg3_copper_is_advertising_all(), tg3_flag, tg3_flag_set, tg3_init_5401phy_dsp(), TG3_KNOWN_PHY_ID, tg3_lookup_by_subsys(), tg3_phy_autoneg_cfg(), TG3_PHY_ID_BCM5401, TG3_PHY_ID_BCM8002, TG3_PHY_ID_INVALID, TG3_PHY_ID_MASK, tg3_phy_init_link_config(), tg3_phy_reset(), tg3_phy_set_wirespeed(), TG3_PHYFLG_ANY_SERDES, TG3_PHYFLG_EEE_CAP, TG3_PHYFLG_PHY_SERDES, tg3_readphy(), tg3_writephy(), TG3PCI_DEVICE_TIGON3_5718, tp, and u32.

Referenced by tg3_get_invariants().

tg3_phy_reset()

int tg3_phy_reset

(

struct tg3 *

tp

)

Definition at line 622 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 val, cpmuctrl;
        int err;
 
        DBGCP(&tp->pdev->dev, "%s\n", __func__);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                val = tr32(GRC_MISC_CFG);
                tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
                udelay(40);
        }
        err  = tg3_readphy(tp, MII_BMSR, &val);
        err |= tg3_readphy(tp, MII_BMSR, &val);
        if (err != 0)
                return -EBUSY;
 
        netdev_link_down(tp->dev);
        tg3_link_report(tp);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
                err = tg3_phy_reset_5703_4_5(tp);
                if (err)
                        return err;
                goto out;
        }
 
        cpmuctrl = 0;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
            GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
                cpmuctrl = tr32(TG3_CPMU_CTRL);
                if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
                        tw32(TG3_CPMU_CTRL,
                             cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
        }
 
        err = tg3_bmcr_reset(tp);
        if (err)
                return err;
 
        if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
                val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
                tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
 
                tw32(TG3_CPMU_CTRL, cpmuctrl);
        }
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
            GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
                val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
                if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
                    CPMU_LSPD_1000MB_MACCLK_12_5) {
                        val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
                        udelay(40);
                        tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
                }
        }
 
        if (tg3_flag(tp, 5717_PLUS) &&
            (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
                return 0;
 
        tg3_phy_apply_otp(tp);
 
out:
        if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
            !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
                tg3_phydsp_write(tp, 0x201f, 0x2aaa);
                tg3_phydsp_write(tp, 0x000a, 0x0323);
                TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
        }
 
        if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
        }
 
        if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
                if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
                        tg3_phydsp_write(tp, 0x000a, 0x310b);
                        tg3_phydsp_write(tp, 0x201f, 0x9506);
                        tg3_phydsp_write(tp, 0x401f, 0x14e2);
                        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
                }
        } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
                if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
                        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
                        if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
                                tg3_writephy(tp, MII_TG3_TEST1,
                                             MII_TG3_TEST1_TRIM_EN | 0x4);
                        } else
                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
 
                        TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
                }
        }
 
        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
                /* Cannot do read-modify-write on 5401 */
                tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                /* adjust output voltage */
                tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
        }
 
        tg3_phy_toggle_automdix(tp, 1);
        tg3_phy_set_wirespeed(tp);
        return 0;
}

References ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, ASIC_REV_5784, ASIC_REV_5906, CHIPREV_5761_AX, CHIPREV_5784_AX, CPMU_CTRL_GPHY_10MB_RXONLY, CPMU_LSPD_1000MB_MACCLK_12_5, CPMU_LSPD_1000MB_MACCLK_MASK, DBGCP, DBGP, EBUSY, GET_ASIC_REV, GET_CHIP_REV, GRC_MISC_CFG, GRC_MISC_CFG_EPHY_IDDQ, MII_BMSR, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, MII_TG3_DSP_ADDRESS, MII_TG3_DSP_EXP8, MII_TG3_DSP_EXP8_AEDW, MII_TG3_DSP_EXP8_REJ2MHz, MII_TG3_DSP_RW_PORT, MII_TG3_FET_PTEST, MII_TG3_MISC_SHDW, MII_TG3_TEST1, MII_TG3_TEST1_TRIM_EN, netdev_link_down(), out, tg3_bmcr_reset(), TG3_CPMU_CTRL, TG3_CPMU_LSPD_1000MB_CLK, tg3_flag, tg3_link_report(), tg3_phy_apply_otp(), TG3_PHY_AUXCTL_SMDSP_DISABLE, TG3_PHY_AUXCTL_SMDSP_ENABLE, tg3_phy_auxctl_write(), TG3_PHY_ID_BCM5401, TG3_PHY_ID_MASK, tg3_phy_reset_5703_4_5(), tg3_phy_set_wirespeed(), tg3_phy_toggle_automdix(), tg3_phydsp_write(), TG3_PHYFLG_5704_A0_BUG, TG3_PHYFLG_ADC_BUG, TG3_PHYFLG_ADJUST_TRIM, TG3_PHYFLG_BER_BUG, TG3_PHYFLG_JITTER_BUG, TG3_PHYFLG_MII_SERDES, tg3_readphy(), tg3_writephy(), tp, tr32, tw32, tw32_f, u32, udelay(), and val.

Referenced by tg3_phy_probe(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_setup_fiber_mii_phy().

tg3_setup_phy()

int tg3_setup_phy	(	struct tg3 *	tp,
		int	force_reset )

Definition at line 2521 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 val;
        int err;
 
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                err = tg3_setup_fiber_phy(tp, force_reset);
        else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
                err = tg3_setup_fiber_mii_phy(tp, force_reset);
        else
                err = tg3_setup_copper_phy(tp, force_reset);
 
        val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
              (6 << TX_LENGTHS_IPG_SHIFT);
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
                val |= tr32(MAC_TX_LENGTHS) &
                       (TX_LENGTHS_JMB_FRM_LEN_MSK |
                        TX_LENGTHS_CNT_DWN_VAL_MSK);
 
        if (tp->link_config.active_speed == SPEED_1000 &&
            tp->link_config.active_duplex == DUPLEX_HALF)
                tw32(MAC_TX_LENGTHS, val |
                     (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
        else
                tw32(MAC_TX_LENGTHS, val |
                     (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
 
        if (!tg3_flag(tp, 5705_PLUS)) {
                if (netdev_link_ok(tp->dev)) {
                        tw32(HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS);
                } else {
                        tw32(HOSTCC_STAT_COAL_TICKS, 0);
                }
        }
 
        val = tr32(PCIE_PWR_MGMT_THRESH);
        if (!netdev_link_ok(tp->dev))
                val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK);
        else
                val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
        tw32(PCIE_PWR_MGMT_THRESH, val);
 
        return err;
}

References ASIC_REV_5720, DBGP, DEFAULT_STAT_COAL_TICKS, DUPLEX_HALF, GET_ASIC_REV, HOSTCC_STAT_COAL_TICKS, MAC_TX_LENGTHS, netdev_link_ok(), PCIE_PWR_MGMT_L1_THRESH_MSK, PCIE_PWR_MGMT_THRESH, SPEED_1000, tg3_flag, TG3_PHYFLG_MII_SERDES, TG3_PHYFLG_PHY_SERDES, tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), tg3_setup_fiber_phy(), tp, tr32, tw32, TX_LENGTHS_CNT_DWN_VAL_MSK, TX_LENGTHS_IPG_CRS_SHIFT, TX_LENGTHS_IPG_SHIFT, TX_LENGTHS_JMB_FRM_LEN_MSK, TX_LENGTHS_SLOT_TIME_SHIFT, u32, and val.

Referenced by tg3_init_one(), tg3_poll_link(), and tg3_reset_hw().

tg3_readphy()

int tg3_readphy	(	struct tg3 *	tp,
		int	reg,
		u32 *	val )

Definition at line 86 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 frame_val;
        unsigned int loops;
        int ret;
 
        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
                tw32_f(MAC_MI_MODE,
                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
                udelay(80);
        }
 
        *val = 0x0;
 
        frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
                      MI_COM_PHY_ADDR_MASK);
        frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
                      MI_COM_REG_ADDR_MASK);
        frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 
        tw32_f(MAC_MI_COM, frame_val);
 
        loops = PHY_BUSY_LOOPS;
        while (loops != 0) {
                udelay(10);
                frame_val = tr32(MAC_MI_COM);
 
                if ((frame_val & MI_COM_BUSY) == 0) {
                        udelay(5);
                        frame_val = tr32(MAC_MI_COM);
                        break;
                }
                loops -= 1;
        }
 
        ret = -EBUSY;
        if (loops != 0) {
                *val = frame_val & MI_COM_DATA_MASK;
                ret = 0;
        }
 
        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
                tw32_f(MAC_MI_MODE, tp->mi_mode);
                udelay(80);
        }
 
        return ret;
}

References DBGP, EBUSY, MAC_MI_COM, MAC_MI_MODE, MAC_MI_MODE_AUTO_POLL, MI_COM_BUSY, MI_COM_CMD_READ, MI_COM_DATA_MASK, MI_COM_PHY_ADDR_MASK, MI_COM_PHY_ADDR_SHIFT, MI_COM_REG_ADDR_MASK, MI_COM_REG_ADDR_SHIFT, MI_COM_START, PHY_BUSY_LOOPS, reg, tp, tr32, tw32_f, u32, udelay(), and val.

Referenced by tg3_adv_1000T_flowctrl_ok(), tg3_bmcr_reset(), tg3_copper_is_advertising_all(), tg3_phy_auxctl_read(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_toggle_automdix(), tg3_phy_write_and_check_testpat(), tg3_reset_hw(), tg3_setup_copper_phy(), tg3_setup_fiber_mii_phy(), tg3_ump_link_report(), and tg3_wait_macro_done().

tg3_writephy()

int tg3_writephy	(	struct tg3 *	tp,
		int	reg,
		u32	val )

Definition at line 222 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        u32 frame_val;
        unsigned int loops;
        int ret;
 
        if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
            (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
                return 0;
 
        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
                tw32_f(MAC_MI_MODE,
                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
                udelay(80);
        }
 
        frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
                      MI_COM_PHY_ADDR_MASK);
        frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
                      MI_COM_REG_ADDR_MASK);
        frame_val |= (val & MI_COM_DATA_MASK);
        frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 
        tw32_f(MAC_MI_COM, frame_val);
 
        loops = PHY_BUSY_LOOPS;
        while (loops != 0) {
                udelay(10);
                frame_val = tr32(MAC_MI_COM);
                if ((frame_val & MI_COM_BUSY) == 0) {
                        udelay(5);
                        frame_val = tr32(MAC_MI_COM);
                        break;
                }
                loops -= 1;
        }
 
        ret = -EBUSY;
        if (loops != 0)
                ret = 0;
 
        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
                tw32_f(MAC_MI_MODE, tp->mi_mode);
                udelay(80);
        }
 
        return ret;
}

References DBGP, EBUSY, MAC_MI_COM, MAC_MI_MODE, MAC_MI_MODE_AUTO_POLL, MI_COM_BUSY, MI_COM_CMD_WRITE, MI_COM_DATA_MASK, MI_COM_PHY_ADDR_MASK, MI_COM_PHY_ADDR_SHIFT, MI_COM_REG_ADDR_MASK, MI_COM_REG_ADDR_SHIFT, MI_COM_START, MII_TG3_AUX_CTRL, MII_TG3_CTRL, PHY_BUSY_LOOPS, reg, TG3_PHYFLG_IS_FET, tp, tr32, tw32_f, u32, udelay(), and val.

Referenced by tg3_adv_1000T_flowctrl_ok(), tg3_bmcr_reset(), tg3_init_bcm8002(), tg3_phy_autoneg_cfg(), tg3_phy_auxctl_read(), tg3_phy_auxctl_write(), tg3_phy_copper_begin(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_toggle_automdix(), tg3_phy_write_and_check_testpat(), tg3_phydsp_write(), tg3_reset_hw(), tg3_setup_copper_phy(), and tg3_setup_fiber_mii_phy().

_tw32_flush()

void _tw32_flush	(	struct tg3 *	tp,
		u32	off,
		u32	val,
		u32	usec_wait )

Definition at line 114 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        tw32(off, val);
        if (usec_wait)
                udelay(usec_wait);
        tr32(off);
 
        /* Wait again after the read for the posted method to guarantee that
         * the wait time is met.
         */
        if (usec_wait)
                udelay(usec_wait);
}

References DBGP, tp, tr32, tw32, u32, udelay(), and val.

tg3_write_mem()

void tg3_write_mem	(	struct tg3 *	tp,
		u32	off,
		u32	val )

Definition at line 922 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
            (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
                return;
 
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 
        /* Always leave this as zero. */
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
}

References ASIC_REV_5906, DBGP, GET_ASIC_REV, NIC_SRAM_STATS_BLK, NIC_SRAM_TX_BUFFER_DESC, pci_write_config_dword(), TG3PCI_MEM_WIN_BASE_ADDR, TG3PCI_MEM_WIN_DATA, tp, u32, and val.

Referenced by tg3_reset_hw(), tg3_rings_reset(), tg3_set_bdinfo(), tg3_setup_copper_phy(), tg3_stop_fw(), tg3_ump_link_report(), and tg3_write_sig_pre_reset().

tg3_get_invariants()

int tg3_get_invariants

(

struct tg3 *

tp

)

tg3_nvram_init(tp);

Definition at line 394 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        u32 misc_ctrl_reg;
        u32 pci_state_reg, grc_misc_cfg;
        u32 val;
        u16 pci_cmd;
        int err;
 
        /* Force memory write invalidate off.  If we leave it on,
         * then on 5700_BX chips we have to enable a workaround.
         * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
         * to match the cacheline size.  The Broadcom driver have this
         * workaround but turns MWI off all the times so never uses
         * it.  This seems to suggest that the workaround is insufficient.
         */
        pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
        pci_cmd &= ~PCI_COMMAND_INVALIDATE;
        pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
 
        /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
         * has the register indirect write enable bit set before
         * we try to access any of the MMIO registers.  It is also
         * critical that the PCI-X hw workaround situation is decided
         * before that as well.
         */
        pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
                              &misc_ctrl_reg);
 
        tp->pci_chip_rev_id = (misc_ctrl_reg >>
                               MISC_HOST_CTRL_CHIPREV_SHIFT);
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
                u32 prod_id_asic_rev;
 
                if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
                        pci_read_config_dword(tp->pdev,
                                              TG3PCI_GEN2_PRODID_ASICREV,
                                              &prod_id_asic_rev);
                else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
                         tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
                        pci_read_config_dword(tp->pdev,
                                              TG3PCI_GEN15_PRODID_ASICREV,
                                              &prod_id_asic_rev);
                else
                        pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
                                              &prod_id_asic_rev);
 
                tp->pci_chip_rev_id = prod_id_asic_rev;
        }
 
        /* Wrong chip ID in 5752 A0. This code can be removed later
         * as A0 is not in production.
         */
        if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
                tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
 
        /* Initialize misc host control in PCI block. */
        tp->misc_host_ctrl |= (misc_ctrl_reg &
                               MISC_HOST_CTRL_CHIPREV);
        pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
                               tp->misc_host_ctrl);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
                tg3_flag_set(tp, 5717_PLUS);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766 ||
            tg3_flag(tp, 5717_PLUS))
                tg3_flag_set(tp, 57765_PLUS);
 
        /* Intentionally exclude ASIC_REV_5906 */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
            tg3_flag(tp, 57765_PLUS))
                tg3_flag_set(tp, 5755_PLUS);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
            tg3_flag(tp, 5755_PLUS) ||
            tg3_flag(tp, 5780_CLASS))
                tg3_flag_set(tp, 5750_PLUS);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
            tg3_flag(tp, 5750_PLUS))
                tg3_flag_set(tp, 5705_PLUS);
 
        if (tg3_flag(tp, 5717_PLUS))
                tg3_flag_set(tp, LRG_PROD_RING_CAP);
 
        pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
                              &pci_state_reg);
 
        tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
        if (tp->pcie_cap != 0) {
                u16 lnkctl;
 
                tg3_flag_set(tp, PCI_EXPRESS);
 
                pci_read_config_word(tp->pdev,
                                     tp->pcie_cap + PCI_EXP_LNKCTL,
                                     &lnkctl);
                if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
                        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
                            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
                            tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
                            tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
                                tg3_flag_set(tp, CLKREQ_BUG);
                } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
                        tg3_flag_set(tp, L1PLLPD_EN);
                }
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
                tg3_flag_set(tp, PCI_EXPRESS);
        } else if (!tg3_flag(tp, 5705_PLUS) ||
                   tg3_flag(tp, 5780_CLASS)) {
                tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
                if (!tp->pcix_cap) {
                        DBGC(&tp->pdev->dev,
                                "Cannot find PCI-X capability, aborting\n");
                        return -EIO;
                }
 
                if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
                        tg3_flag_set(tp, PCIX_MODE);
        }
 
        /* If we have an AMD 762 or VIA K8T800 chipset, write
         * reordering to the mailbox registers done by the host
         * controller can cause major troubles.  We read back from
         * every mailbox register write to force the writes to be
         * posted to the chip in order.
         */
 
        pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
                             &tp->pci_cacheline_sz);
        pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
                             &tp->pci_lat_timer);
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
            tp->pci_lat_timer < 64) {
                tp->pci_lat_timer = 64;
                pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
                                      tp->pci_lat_timer);
        }
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
                /* 5700 BX chips need to have their TX producer index
                 * mailboxes written twice to workaround a bug.
                 */
                tg3_flag_set(tp, TXD_MBOX_HWBUG);
 
                /* If we are in PCI-X mode, enable register write workaround.
                 *
                 * The workaround is to use indirect register accesses
                 * for all chip writes not to mailbox registers.
                 */
                if (tg3_flag(tp, PCIX_MODE)) {
                        u32 pm_reg;
 
                        tg3_flag_set(tp, PCIX_TARGET_HWBUG);
 
                        /* The chip can have it's power management PCI config
                         * space registers clobbered due to this bug.
                         * So explicitly force the chip into D0 here.
                         */
                        pci_read_config_dword(tp->pdev,
                                              tp->pm_cap + PCI_PM_CTRL,
                                              &pm_reg);
                        pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
                        pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
                        pci_write_config_dword(tp->pdev,
                                               tp->pm_cap + PCI_PM_CTRL,
                                               pm_reg);
 
                        /* Also, force SERR#/PERR# in PCI command. */
                        pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
                        pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
                        pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
                }
        }
 
        if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
                tg3_flag_set(tp, PCI_HIGH_SPEED);
        if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
                tg3_flag_set(tp, PCI_32BIT);
 
        /* Chip-specific fixup from Broadcom driver */
        if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
            (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
                pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
                pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
        }
 
        tp->write32_mbox = tg3_write_indirect_reg32;
        tp->write32_rx_mbox = tg3_write_indirect_mbox;
        tp->write32_tx_mbox = tg3_write_indirect_mbox;
        tp->read32_mbox = tg3_read_indirect_mbox;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                tp->read32_mbox = tg3_read32_mbox_5906;
                tp->write32_mbox = tg3_write32_mbox_5906;
                tp->write32_tx_mbox = tg3_write32_mbox_5906;
                tp->write32_rx_mbox = tg3_write32_mbox_5906;
        }
 
        /* Get eeprom hw config before calling tg3_set_power_state().
         * In particular, the TG3_FLAG_IS_NIC flag must be
         * determined before calling tg3_set_power_state() so that
         * we know whether or not to switch out of Vaux power.
         * When the flag is set, it means that GPIO1 is used for eeprom
         * write protect and also implies that it is a LOM where GPIOs
         * are not used to switch power.
         */
        tg3_get_eeprom_hw_cfg(tp);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
            tg3_flag(tp, 57765_PLUS))
                tg3_flag_set(tp, CPMU_PRESENT);
 
        /* Set up tp->grc_local_ctrl before calling tg3_power_up().
         * GPIO1 driven high will bring 5700's external PHY out of reset.
         * It is also used as eeprom write protect on LOMs.
         */
        tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
            tg3_flag(tp, EEPROM_WRITE_PROT))
                tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
                                       GRC_LCLCTRL_GPIO_OUTPUT1);
        /* Unused GPIO3 must be driven as output on 5752 because there
         * are no pull-up resistors on unused GPIO pins.
         */
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
                tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
 
        if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
                /* Turn off the debug UART. */
                tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
                if (tg3_flag(tp, IS_NIC))
                        /* Keep VMain power. */
                        tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
                                              GRC_LCLCTRL_GPIO_OUTPUT0;
        }
 
        /* Force the chip into D0. */
        tg3_set_power_state_0(tp);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                tp->phy_flags |= TG3_PHYFLG_IS_FET;
 
        /* A few boards don't want Ethernet@WireSpeed phy feature */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
             (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
             (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
            (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
            (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
                tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
            GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
                tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
                tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
 
        if (tg3_flag(tp, 5705_PLUS) &&
            !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
            !tg3_flag(tp, 57765_PLUS)) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
                        if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
                            tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
                                tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
                        if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
                                tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
                } else
                        tp->phy_flags |= TG3_PHYFLG_BER_BUG;
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
            GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
                tp->phy_otp = tg3_read_otp_phycfg(tp);
                if (tp->phy_otp == 0)
                        tp->phy_otp = TG3_OTP_DEFAULT;
        }
 
        if (tg3_flag(tp, CPMU_PRESENT))
                tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
        else
                tp->mi_mode = MAC_MI_MODE_BASE;
 
        tp->coalesce_mode = 0;
        if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
            GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
                tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
 
        /* Set these bits to enable statistics workaround. */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
            tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
            tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
                tp->coalesce_mode |= HOSTCC_MODE_ATTN;
                tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
        }
 
        tg3_mdio_init(tp);
 
        /* Initialize data/descriptor byte/word swapping. */
        val = tr32(GRC_MODE);
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
                val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
                        GRC_MODE_WORD_SWAP_B2HRX_DATA |
                        GRC_MODE_B2HRX_ENABLE |
                        GRC_MODE_HTX2B_ENABLE |
                        GRC_MODE_HOST_STACKUP);
        else
                val &= GRC_MODE_HOST_STACKUP;
 
        tw32(GRC_MODE, val | tp->grc_mode);
 
        tg3_switch_clocks(tp);
 
        /* Clear this out for sanity. */
        tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 
        pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
                              &pci_state_reg);
        if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
            !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
                u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
 
                if (chiprevid == CHIPREV_ID_5701_A0 ||
                    chiprevid == CHIPREV_ID_5701_B0 ||
                    chiprevid == CHIPREV_ID_5701_B2 ||
                    chiprevid == CHIPREV_ID_5701_B5) {
                        void *sram_base;
 
                        /* Write some dummy words into the SRAM status block
                         * area, see if it reads back correctly.  If the return
                         * value is bad, force enable the PCIX workaround.
                         */
                        sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
 
                        writel(0x00000000, sram_base);
                        writel(0x00000000, sram_base + 4);
                        writel(0xffffffff, sram_base + 4);
                        if (readl(sram_base) != 0x00000000)
                                tg3_flag_set(tp, PCIX_TARGET_HWBUG);
                }
        }
 
        udelay(50);
        /* FIXME: do we need nvram access? */
///     tg3_nvram_init(tp);
 
        grc_misc_cfg = tr32(GRC_MISC_CFG);
        grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
            (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
                tg3_flag_set(tp, IS_5788);
 
        if (!tg3_flag(tp, IS_5788) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
                tg3_flag_set(tp, TAGGED_STATUS);
        if (tg3_flag(tp, TAGGED_STATUS)) {
                tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
                                      HOSTCC_MODE_CLRTICK_TXBD);
 
                tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
                pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
                                       tp->misc_host_ctrl);
        }
 
        /* Preserve the APE MAC_MODE bits */
        if (tg3_flag(tp, ENABLE_APE))
                tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
        else
                tp->mac_mode = TG3_DEF_MAC_MODE;
 
        /* these are limited to 10/100 only */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
             (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
             tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
             (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
            (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
             (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
              tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
            (tp->phy_flags & TG3_PHYFLG_IS_FET))
                tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
 
        err = tg3_phy_probe(tp);
        if (err) {
                DBGC(&tp->pdev->dev, "phy probe failed, err: %s\n", strerror(err));
                /* ... but do not return immediately ... */
        }
 
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
                tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
        } else {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
                        tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
                else
                        tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
        }
 
        /* For all SERDES we poll the MAC status register. */
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                tg3_flag_set(tp, POLL_SERDES);
        else
                tg3_flag_clear(tp, POLL_SERDES);
 
        /* Increment the rx prod index on the rx std ring by at most
         * 8 for these chips to workaround hw errata.
         */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
                tp->rx_std_max_post = 8;
 
        return err;
}

References ASIC_REV_5700, ASIC_REV_5703, ASIC_REV_5705, ASIC_REV_5717, ASIC_REV_5719, ASIC_REV_5720, ASIC_REV_5750, ASIC_REV_5752, ASIC_REV_5755, ASIC_REV_5761, ASIC_REV_57765, ASIC_REV_57766, ASIC_REV_57780, ASIC_REV_5784, ASIC_REV_5785, ASIC_REV_5787, ASIC_REV_5906, ASIC_REV_USE_PROD_ID_REG, CHIPREV_5700_AX, CHIPREV_5700_BX, CHIPREV_5703_AX, CHIPREV_5704_AX, CHIPREV_5784_AX, CHIPREV_ID_5701_A0, CHIPREV_ID_5701_B0, CHIPREV_ID_5701_B2, CHIPREV_ID_5701_B5, CHIPREV_ID_5704_A0, CHIPREV_ID_5705_A0, CHIPREV_ID_5705_A1, CHIPREV_ID_5717_A0, CHIPREV_ID_5719_A0, CHIPREV_ID_5720_A0, CHIPREV_ID_5752_A0, CHIPREV_ID_5752_A0_HW, CHIPREV_ID_57780_A0, CHIPREV_ID_57780_A1, DBGC, DBGP, EIO, GET_ASIC_REV, GET_CHIP_REV, GET_CHIP_REV_ID, GRC_LCLCTRL_AUTO_SEEPROM, GRC_LCLCTRL_GPIO_OE0, GRC_LCLCTRL_GPIO_OE1, GRC_LCLCTRL_GPIO_OE3, GRC_LCLCTRL_GPIO_OUTPUT0, GRC_LCLCTRL_GPIO_OUTPUT1, GRC_LCLCTRL_GPIO_UART_SEL, GRC_LCLCTRL_INT_ON_ATTN, GRC_MISC_CFG, GRC_MISC_CFG_BOARD_ID_5788, GRC_MISC_CFG_BOARD_ID_5788M, GRC_MISC_CFG_BOARD_ID_MASK, GRC_MODE, GRC_MODE_B2HRX_ENABLE, GRC_MODE_BYTE_SWAP_B2HRX_DATA, GRC_MODE_HOST_STACKUP, GRC_MODE_HTX2B_ENABLE, GRC_MODE_IRQ_ON_FLOW_ATTN, GRC_MODE_WORD_SWAP_B2HRX_DATA, HOSTCC_MODE_32BYTE, HOSTCC_MODE_ATTN, HOSTCC_MODE_CLRTICK_RXBD, HOSTCC_MODE_CLRTICK_TXBD, MAC_MI_MODE_500KHZ_CONST, MAC_MI_MODE_BASE, MAC_MODE_APE_RX_EN, MAC_MODE_APE_TX_EN, MISC_HOST_CTRL_CHIPREV, MISC_HOST_CTRL_CHIPREV_SHIFT, MISC_HOST_CTRL_TAGGED_STATUS, NIC_SRAM_STATS_BLK, NIC_SRAM_WIN_BASE, PCI_CACHE_LINE_SIZE, PCI_CAP_ID_EXP, PCI_CAP_ID_PCIX, PCI_COMMAND, PCI_COMMAND_INVALIDATE, PCI_COMMAND_PARITY, PCI_COMMAND_SERR, PCI_DEVICE_ID_TIGON3_5705F, PCI_DEVICE_ID_TIGON3_5722, PCI_DEVICE_ID_TIGON3_5751F, PCI_DEVICE_ID_TIGON3_5753F, PCI_DEVICE_ID_TIGON3_5755M, PCI_DEVICE_ID_TIGON3_5756, PCI_DEVICE_ID_TIGON3_5761, PCI_DEVICE_ID_TIGON3_5787F, PCI_DEVICE_ID_TIGON3_5901, PCI_DEVICE_ID_TIGON3_5901_2, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_CLKREQ_EN, pci_find_capability(), PCI_LATENCY_TIMER, PCI_PM_CTRL, PCI_PM_CTRL_PME_ENABLE, PCI_PM_CTRL_STATE_MASK, pci_read_config_byte(), pci_read_config_dword(), pci_read_config_word(), PCI_VENDOR_ID_BROADCOM, pci_write_config_byte(), pci_write_config_dword(), pci_write_config_word(), PCISTATE_BUS_32BIT, PCISTATE_BUS_SPEED_HIGH, PCISTATE_CONV_PCI_MODE, PCISTATE_RETRY_SAME_DMA, readl, strerror(), TG3_DEF_MAC_MODE, tg3_flag, tg3_flag_clear, tg3_flag_set, tg3_get_eeprom_hw_cfg(), tg3_mdio_init(), TG3_OTP_DEFAULT, tg3_phy_probe(), TG3_PHYFLG_10_100_ONLY, TG3_PHYFLG_5704_A0_BUG, TG3_PHYFLG_ADC_BUG, TG3_PHYFLG_ADJUST_TRIM, TG3_PHYFLG_ANY_SERDES, TG3_PHYFLG_BER_BUG, TG3_PHYFLG_IS_FET, TG3_PHYFLG_JITTER_BUG, TG3_PHYFLG_NO_ETH_WIRE_SPEED, TG3_PHYFLG_PHY_SERDES, TG3_PHYFLG_USE_MI_INTERRUPT, tg3_read32_mbox_5906(), tg3_read_indirect_mbox(), tg3_read_otp_phycfg(), tg3_set_power_state_0(), tg3_switch_clocks(), tg3_write32_mbox_5906(), tg3_write_indirect_mbox(), tg3_write_indirect_reg32(), TG3PCI_DEVICE_TIGON3_5717, TG3PCI_DEVICE_TIGON3_5718, TG3PCI_DEVICE_TIGON3_5719, TG3PCI_DEVICE_TIGON3_5720, TG3PCI_DEVICE_TIGON3_5761S, TG3PCI_DEVICE_TIGON3_57761, TG3PCI_DEVICE_TIGON3_57762, TG3PCI_DEVICE_TIGON3_57765, TG3PCI_DEVICE_TIGON3_57766, TG3PCI_DEVICE_TIGON3_57781, TG3PCI_DEVICE_TIGON3_57785, TG3PCI_DEVICE_TIGON3_57790, TG3PCI_DEVICE_TIGON3_57791, TG3PCI_DEVICE_TIGON3_57795, TG3PCI_GEN15_PRODID_ASICREV, TG3PCI_GEN2_PRODID_ASICREV, TG3PCI_MEM_WIN_BASE_ADDR, TG3PCI_MISC_HOST_CTRL, TG3PCI_PCISTATE, TG3PCI_PRODID_ASICREV, tp, tr32, tw32, u16, u32, udelay(), val, and writel.

Referenced by tg3_init_one().

tg3_init_bufmgr_config()

void tg3_init_bufmgr_config

(

struct tg3 *

tp

)

Definition at line 850 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        if (tg3_flag(tp, 57765_PLUS)) {
                tp->bufmgr_config.mbuf_read_dma_low_water =
                        DEFAULT_MB_RDMA_LOW_WATER_5705;
                tp->bufmgr_config.mbuf_mac_rx_low_water =
                        DEFAULT_MB_MACRX_LOW_WATER_57765;
                tp->bufmgr_config.mbuf_high_water =
                        DEFAULT_MB_HIGH_WATER_57765;
 
                tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
                        DEFAULT_MB_RDMA_LOW_WATER_5705;
                tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
                        DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
                tp->bufmgr_config.mbuf_high_water_jumbo =
                        DEFAULT_MB_HIGH_WATER_JUMBO_57765;
        } else if (tg3_flag(tp, 5705_PLUS)) {
                tp->bufmgr_config.mbuf_read_dma_low_water =
                        DEFAULT_MB_RDMA_LOW_WATER_5705;
                tp->bufmgr_config.mbuf_mac_rx_low_water =
                        DEFAULT_MB_MACRX_LOW_WATER_5705;
                tp->bufmgr_config.mbuf_high_water =
                        DEFAULT_MB_HIGH_WATER_5705;
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                        tp->bufmgr_config.mbuf_mac_rx_low_water =
                                DEFAULT_MB_MACRX_LOW_WATER_5906;
                        tp->bufmgr_config.mbuf_high_water =
                                DEFAULT_MB_HIGH_WATER_5906;
                }
 
                tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
                        DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
                tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
                        DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
                tp->bufmgr_config.mbuf_high_water_jumbo =
                        DEFAULT_MB_HIGH_WATER_JUMBO_5780;
        } else {
                tp->bufmgr_config.mbuf_read_dma_low_water =
                        DEFAULT_MB_RDMA_LOW_WATER;
                tp->bufmgr_config.mbuf_mac_rx_low_water =
                        DEFAULT_MB_MACRX_LOW_WATER;
                tp->bufmgr_config.mbuf_high_water =
                        DEFAULT_MB_HIGH_WATER;
 
                tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
                        DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
                tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
                        DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
                tp->bufmgr_config.mbuf_high_water_jumbo =
                        DEFAULT_MB_HIGH_WATER_JUMBO;
        }
 
        tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
        tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
}

References ASIC_REV_5906, DBGP, DEFAULT_DMA_HIGH_WATER, DEFAULT_DMA_LOW_WATER, DEFAULT_MB_HIGH_WATER, DEFAULT_MB_HIGH_WATER_5705, DEFAULT_MB_HIGH_WATER_57765, DEFAULT_MB_HIGH_WATER_5906, DEFAULT_MB_HIGH_WATER_JUMBO, DEFAULT_MB_HIGH_WATER_JUMBO_57765, DEFAULT_MB_HIGH_WATER_JUMBO_5780, DEFAULT_MB_MACRX_LOW_WATER, DEFAULT_MB_MACRX_LOW_WATER_5705, DEFAULT_MB_MACRX_LOW_WATER_57765, DEFAULT_MB_MACRX_LOW_WATER_5906, DEFAULT_MB_MACRX_LOW_WATER_JUMBO, DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765, DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780, DEFAULT_MB_RDMA_LOW_WATER, DEFAULT_MB_RDMA_LOW_WATER_5705, DEFAULT_MB_RDMA_LOW_WATER_JUMBO, DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780, GET_ASIC_REV, tg3_flag, and tp.

Referenced by tg3_init_one().

tg3_get_device_address()

int tg3_get_device_address

(

struct tg3 *

tp

)

Definition at line 1650 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        struct net_device *dev = tp->dev;
        u32 hi, lo, mac_offset;
        int addr_ok = 0;
 
        mac_offset = 0x7c;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
            tg3_flag(tp, 5780_CLASS)) {
                if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
                        mac_offset = 0xcc;
                if (tg3_nvram_lock(tp))
                        tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
                else
                        tg3_nvram_unlock(tp);
        } else if (tg3_flag(tp, 5717_PLUS)) {
                if (PCI_FUNC(tp->pdev->busdevfn) & 1)
                        mac_offset = 0xcc;
                if (PCI_FUNC(tp->pdev->busdevfn) > 1)
                        mac_offset += 0x18c;
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                mac_offset = 0x10;
 
        /* First try to get it from MAC address mailbox. */
        tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
        if ((hi >> 16) == 0x484b) {
                dev->hw_addr[0] = (hi >>  8) & 0xff;
                dev->hw_addr[1] = (hi >>  0) & 0xff;
 
                tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
                dev->hw_addr[2] = (lo >> 24) & 0xff;
                dev->hw_addr[3] = (lo >> 16) & 0xff;
                dev->hw_addr[4] = (lo >>  8) & 0xff;
                dev->hw_addr[5] = (lo >>  0) & 0xff;
 
                /* Some old bootcode may report a 0 MAC address in SRAM */
                addr_ok = is_valid_ether_addr(&dev->hw_addr[0]);
        }
        if (!addr_ok) {
                /* Next, try NVRAM. */
                if (!tg3_flag(tp, NO_NVRAM) &&
                    !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
                    !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
                        memcpy(&dev->hw_addr[0], ((char *)&hi) + 2, 2);
                        memcpy(&dev->hw_addr[2], (char *)&lo, sizeof(lo));
                }
                /* Finally just fetch it out of the MAC control regs. */
                else {
                        hi = tr32(MAC_ADDR_0_HIGH);
                        lo = tr32(MAC_ADDR_0_LOW);
 
                        dev->hw_addr[5] = lo & 0xff;
                        dev->hw_addr[4] = (lo >> 8) & 0xff;
                        dev->hw_addr[3] = (lo >> 16) & 0xff;
                        dev->hw_addr[2] = (lo >> 24) & 0xff;
                        dev->hw_addr[1] = hi & 0xff;
                        dev->hw_addr[0] = (hi >> 8) & 0xff;
                }
        }
 
        if (!is_valid_ether_addr(&dev->hw_addr[0])) {
                return -EINVAL;
        }
 
        return 0;
}

References ASIC_REV_5704, ASIC_REV_5906, DBGP, net_device::dev, DUAL_MAC_CTRL_ID, EINVAL, GET_ASIC_REV, is_valid_ether_addr(), MAC_ADDR_0_HIGH, MAC_ADDR_0_LOW, memcpy(), NIC_SRAM_MAC_ADDR_HIGH_MBOX, NIC_SRAM_MAC_ADDR_LOW_MBOX, NVRAM_CMD, NVRAM_CMD_RESET, PCI_FUNC, tg3_flag, tg3_nvram_lock(), tg3_nvram_read_be32(), tg3_nvram_unlock(), tg3_read_mem(), TG3PCI_DUAL_MAC_CTRL, tp, tr32, tw32_f, and u32.

Referenced by tg3_init_one().

tg3_halt()

int tg3_halt

(

struct tg3 *

tp

)

Definition at line 1481 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        int err;
 
        tg3_stop_fw(tp);
 
        tg3_write_sig_pre_reset(tp);
 
        tg3_abort_hw(tp);
        err = tg3_chip_reset(tp);
 
        __tg3_set_mac_addr(tp, 0);
 
        if (err)
                return err;
 
        return 0;
}

References __tg3_set_mac_addr(), DBGP, tg3_abort_hw(), tg3_chip_reset(), tg3_stop_fw(), tg3_write_sig_pre_reset(), and tp.

Referenced by tg3_close(), and tg3_init_one().

tg3_set_txd()

void tg3_set_txd	(	struct tg3 *	tp,
		int	entry,
		dma_addr_t	mapping,
		int	len,
		u32	flags )

Definition at line 2583 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
 
        txd->addr_hi = ((u64) mapping >> 32);
        txd->addr_lo = ((u64) mapping & 0xffffffff);
        txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
        txd->vlan_tag = 0;
}

References DBGP, dma_addr_t, flags, len, tp, txd, TXD_LEN_SHIFT, and u32.

Referenced by tg3_transmit().

tg3_set_power_state_0()

void tg3_set_power_state_0

(

struct tg3 *

tp

)

Definition at line 130 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        uint16_t power_control;
        int pm = tp->pm_cap;
 
        /* Make sure register accesses (indirect or otherwise)
         * will function correctly.
         */
        pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
 
        pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
 
        power_control |= PCI_PM_CTRL_PME_STATUS;
        power_control &= ~(PCI_PM_CTRL_STATE_MASK);
        power_control |= 0;
        pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
 
        tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
 
        return;
}

References DBGP, GRC_LOCAL_CTRL, PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS, PCI_PM_CTRL_STATE_MASK, pci_read_config_word(), pci_write_config_dword(), pci_write_config_word(), TG3PCI_MISC_HOST_CTRL, tp, and tw32_wait_f.

Referenced by tg3_get_invariants(), and tg3_open().

tg3_alloc_consistent()

int tg3_alloc_consistent

(

struct tg3 *

tp

)

Definition at line 85 of file tg3.c.

{       DBGP("%s\n", __func__);
 
        struct tg3_hw_status *sblk;
        struct tg3_rx_prodring_set *tpr = &tp->prodring;
 
        tp->hw_status = malloc_phys(TG3_HW_STATUS_SIZE, TG3_DMA_ALIGNMENT);
        if (!tp->hw_status) {
                DBGC(tp->dev, "hw_status alloc failed\n");
                goto err_out;
        }
        tp->status_mapping = virt_to_bus(tp->hw_status);
 
        memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
        sblk = tp->hw_status;
 
        tpr->rx_std = malloc_phys(TG3_RX_STD_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
        if (!tpr->rx_std) {
                DBGC(tp->dev, "rx prodring alloc failed\n");
                goto err_out;
        }
        tpr->rx_std_mapping = virt_to_bus(tpr->rx_std);
        memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
 
        tp->tx_buffers = zalloc(sizeof(struct ring_info) * TG3_TX_RING_SIZE);
        if (!tp->tx_buffers)
                goto err_out;
 
        tp->tx_ring = malloc_phys(TG3_TX_RING_BYTES, TG3_DMA_ALIGNMENT);
        if (!tp->tx_ring)
                goto err_out;
        tp->tx_desc_mapping = virt_to_bus(tp->tx_ring);
 
        /*
         * When RSS is enabled, the status block format changes
         * slightly.  The "rx_jumbo_consumer", "reserved",
         * and "rx_mini_consumer" members get mapped to the
         * other three rx return ring producer indexes.
         */
 
        tp->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
 
        tp->rx_rcb = malloc_phys(TG3_RX_RCB_RING_BYTES(tp), TG3_DMA_ALIGNMENT);
        if (!tp->rx_rcb)
                goto err_out;
        tp->rx_rcb_mapping = virt_to_bus(tp->rx_rcb);
 
        memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
 
        return 0;
 
err_out:
        tg3_free_consistent(tp);
        return -ENOMEM;
}

References DBGC, DBGP, ENOMEM, tg3_hw_status::idx, malloc_phys(), memset(), tg3_hw_status::rx_producer, tg3_rx_prodring_set::rx_std, tg3_rx_prodring_set::rx_std_mapping, TG3_DMA_ALIGNMENT, tg3_free_consistent(), TG3_HW_STATUS_SIZE, TG3_RX_RCB_RING_BYTES, TG3_RX_STD_RING_BYTES, TG3_TX_RING_BYTES, TG3_TX_RING_SIZE, tp, virt_to_bus(), and zalloc().

Referenced by tg3_open().

tg3_init_hw()

int tg3_init_hw	(	struct tg3 *	tp,
		int	reset_phy )

Definition at line 2573 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        tg3_switch_clocks(tp);
 
        tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 
        return tg3_reset_hw(tp, reset_phy);
}

References DBGP, tg3_reset_hw(), tg3_switch_clocks(), TG3PCI_MEM_WIN_BASE_ADDR, tp, and tw32.

Referenced by tg3_open().

tg3_poll_link()

void tg3_poll_link

(

struct tg3 *

tp

)

Definition at line 1009 of file tg3_phy.c.

{       DBGP("%s\n", __func__);
 
        if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
                DBGC(tp->dev,"link_changed\n");
                tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
                tg3_setup_phy(tp, 0);
        }
}

References DBGC, DBGP, SD_STATUS_LINK_CHG, tg3_setup_phy(), and tp.

Referenced by tg3_poll().

tg3_wait_for_event_ack()

void tg3_wait_for_event_ack

(

struct tg3 *

tp

)

Definition at line 909 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        int i;
 
        for (i = 0; i < TG3_FW_EVENT_TIMEOUT_USEC / 10; i++) {
                if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
                        break;
 
                udelay(10);
        }
}

References DBGP, GRC_RX_CPU_DRIVER_EVENT, GRC_RX_CPU_EVENT, TG3_FW_EVENT_TIMEOUT_USEC, tp, tr32, and udelay().

Referenced by tg3_stop_fw(), and tg3_ump_link_report().

__tg3_set_mac_addr()

void __tg3_set_mac_addr	(	struct tg3 *	tp,
		int	skip_mac_1 )

Definition at line 1094 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        u32 addr_high, addr_low;
        int i;
 
        addr_high = ((tp->dev->ll_addr[0] << 8) |
                     tp->dev->ll_addr[1]);
        addr_low = ((tp->dev->ll_addr[2] << 24) |
                    (tp->dev->ll_addr[3] << 16) |
                    (tp->dev->ll_addr[4] <<  8) |
                    (tp->dev->ll_addr[5] <<  0));
        for (i = 0; i < 4; i++) {
                if (i == 1 && skip_mac_1)
                        continue;
                tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
                tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
                for (i = 0; i < 12; i++) {
                        tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
                        tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
                }
        }
 
        addr_high = (tp->dev->ll_addr[0] +
                     tp->dev->ll_addr[1] +
                     tp->dev->ll_addr[2] +
                     tp->dev->ll_addr[3] +
                     tp->dev->ll_addr[4] +
                     tp->dev->ll_addr[5]) &
                TX_BACKOFF_SEED_MASK;
        tw32(MAC_TX_BACKOFF_SEED, addr_high);
}

References ASIC_REV_5703, ASIC_REV_5704, DBGP, GET_ASIC_REV, MAC_ADDR_0_HIGH, MAC_ADDR_0_LOW, MAC_EXTADDR_0_HIGH, MAC_EXTADDR_0_LOW, MAC_TX_BACKOFF_SEED, tp, tw32, TX_BACKOFF_SEED_MASK, and u32.

Referenced by tg3_halt(), tg3_open(), and tg3_reset_hw().

tg3_disable_ints()

void tg3_disable_ints

(

struct tg3 *

tp

)

Definition at line 959 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        tw32(TG3PCI_MISC_HOST_CTRL,
             (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 
        tw32_mailbox_f(tp->int_mbox, 0x00000001);
}

References DBGP, MISC_HOST_CTRL_MASK_PCI_INT, TG3PCI_MISC_HOST_CTRL, tp, tw32, and tw32_mailbox_f.

Referenced by tg3_abort_hw(), and tg3_irq().

tg3_enable_ints()

void tg3_enable_ints

(

struct tg3 *

tp

)

Definition at line 968 of file tg3_hw.c.

{       DBGP("%s\n", __func__);
 
        tw32(TG3PCI_MISC_HOST_CTRL,
             (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 
        tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 
        tw32_mailbox_f(tp->int_mbox, tp->last_tag << 24);
 
        /* Force an initial interrupt */
        if (!tg3_flag(tp, TAGGED_STATUS) &&
            (tp->hw_status->status & SD_STATUS_UPDATED))
                tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
        else
                tw32(HOSTCC_MODE, tp->coal_now);
}

References DBGP, GRC_LCLCTRL_SETINT, GRC_LOCAL_CTRL, HOSTCC_MODE, HOSTCC_MODE_ENABLE, MISC_HOST_CTRL_MASK_PCI_INT, SD_STATUS_UPDATED, tg3_flag, TG3PCI_MISC_HOST_CTRL, tp, tw32, and tw32_mailbox_f.

Referenced by tg3_irq().

tg3_generate_fw_event()

void tg3_generate_fw_event ( struct tg3 * tp )

inlinestatic

Definition at line 3403 of file tg3.h.

{
        u32 val;
 
        val = tr32(GRC_RX_CPU_EVENT);
        val |= GRC_RX_CPU_DRIVER_EVENT;
        tw32_f(GRC_RX_CPU_EVENT, val);
}

References GRC_RX_CPU_DRIVER_EVENT, GRC_RX_CPU_EVENT, tp, tr32, tw32_f, u32, and val.

Referenced by tg3_stop_fw(), and tg3_ump_link_report().

mii_resolve_flowctrl_fdx()

u8 mii_resolve_flowctrl_fdx ( u16 lcladv, u16 rmtadv )

inlinestatic

mii_resolve_flowctrl_fdx @lcladv: value of MII ADVERTISE register @rmtadv: value of MII LPA register

Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3

Definition at line 3420 of file tg3.h.

{
        u8 cap = 0;
 
        if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
                cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
        } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
                if (lcladv & ADVERTISE_PAUSE_CAP)
                        cap = FLOW_CTRL_RX;
                else if (rmtadv & ADVERTISE_PAUSE_CAP)
                        cap = FLOW_CTRL_TX;
        }
 
        return cap;
}

References ADVERTISE_PAUSE_ASYM, ADVERTISE_PAUSE_CAP, FLOW_CTRL_RX, FLOW_CTRL_TX, u16, and u8.

Referenced by tg3_setup_flow_control().

mii_adv_to_ethtool_adv_x()

u32 mii_adv_to_ethtool_adv_x ( u32 adv )

inlinestatic

Definition at line 3436 of file tg3.h.

{
        u32 result = 0;
 
        if (adv & ADVERTISE_1000XHALF)
                result |= ADVERTISED_1000baseT_Half;
        if (adv & ADVERTISE_1000XFULL)
                result |= ADVERTISED_1000baseT_Full;
        if (adv & ADVERTISE_1000XPAUSE)
                result |= ADVERTISED_Pause;
        if (adv & ADVERTISE_1000XPSE_ASYM)
                result |= ADVERTISED_Asym_Pause;
 
        return result;
}

References ADVERTISE_1000XFULL, ADVERTISE_1000XHALF, ADVERTISE_1000XPAUSE, ADVERTISE_1000XPSE_ASYM, ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_Asym_Pause, ADVERTISED_Pause, result, and u32.

Referenced by tg3_setup_fiber_by_hand(), tg3_setup_fiber_hw_autoneg(), and tg3_setup_fiber_mii_phy().

ethtool_adv_to_mii_adv_x()

u32 ethtool_adv_to_mii_adv_x ( u32 ethadv )

inlinestatic

Definition at line 3452 of file tg3.h.

{
        u32 result = 0;
 
        if (ethadv & ADVERTISED_1000baseT_Half)
                result |= ADVERTISE_1000XHALF;
        if (ethadv & ADVERTISED_1000baseT_Full)
                result |= ADVERTISE_1000XFULL;
        if (ethadv & ADVERTISED_Pause)
                result |= ADVERTISE_1000XPAUSE;
        if (ethadv & ADVERTISED_Asym_Pause)
                result |= ADVERTISE_1000XPSE_ASYM;
 
        return result;
}

References ADVERTISE_1000XFULL, ADVERTISE_1000XHALF, ADVERTISE_1000XPAUSE, ADVERTISE_1000XPSE_ASYM, ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_Asym_Pause, ADVERTISED_Pause, result, and u32.

Referenced by tg3_setup_fiber_mii_phy().