iPXE
ath5k_reset.c
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00001 /*
00002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
00003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
00004  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
00005  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
00006  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
00007  *
00008  * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
00009  *
00010  * Permission to use, copy, modify, and distribute this software for any
00011  * purpose with or without fee is hereby granted, provided that the above
00012  * copyright notice and this permission notice appear in all copies.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00015  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00016  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00017  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00018  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00019  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00020  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00021  *
00022  */
00023 
00024 FILE_LICENCE ( MIT );
00025 
00026 #define _ATH5K_RESET
00027 
00028 /*****************************\
00029   Reset functions and helpers
00030 \*****************************/
00031 
00032 #include <ipxe/pci.h>           /* To determine if a card is pci-e */
00033 #include <unistd.h>
00034 
00035 #include "ath5k.h"
00036 #include "reg.h"
00037 #include "base.h"
00038 
00039 /* Find last set bit; fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32 */
00040 static int fls(int x)
00041 {
00042         int r = 32;
00043 
00044         if (!x)
00045                 return 0;
00046         if (!(x & 0xffff0000u)) {
00047                 x <<= 16;
00048                 r -= 16;
00049         }
00050         if (!(x & 0xff000000u)) {
00051                 x <<= 8;
00052                 r -= 8;
00053         }
00054         if (!(x & 0xf0000000u)) {
00055                 x <<= 4;
00056                 r -= 4;
00057         }
00058         if (!(x & 0xc0000000u)) {
00059                 x <<= 2;
00060                 r -= 2;
00061         }
00062         if (!(x & 0x80000000u)) {
00063                 x <<= 1;
00064                 r -= 1;
00065         }
00066         return r;
00067 }
00068 
00069 
00070 /**
00071  * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
00072  *
00073  * @ah: the &struct ath5k_hw
00074  * @channel: the currently set channel upon reset
00075  *
00076  * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
00077  * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
00078  *
00079  * Since delta slope is floating point we split it on its exponent and
00080  * mantissa and provide these values on hw.
00081  *
00082  * For more infos i think this patent is related
00083  * http://www.freepatentsonline.com/7184495.html
00084  */
00085 static int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
00086         struct net80211_channel *channel)
00087 {
00088         /* Get exponent and mantissa and set it */
00089         u32 coef_scaled, coef_exp, coef_man,
00090                 ds_coef_exp, ds_coef_man, clock;
00091 
00092         if (!(ah->ah_version == AR5K_AR5212) ||
00093             !(channel->hw_value & CHANNEL_OFDM)) {
00094                 DBG("ath5k: attempt to set OFDM timings on non-OFDM channel\n");
00095                 return -EFAULT;
00096         }
00097 
00098         /* Get coefficient
00099          * ALGO: coef = (5 * clock * carrier_freq) / 2)
00100          * we scale coef by shifting clock value by 24 for
00101          * better precision since we use integers */
00102         /* TODO: Half/quarter rate */
00103         clock =  ath5k_hw_htoclock(1, channel->hw_value & CHANNEL_TURBO);
00104 
00105         coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
00106 
00107         /* Get exponent
00108          * ALGO: coef_exp = 14 - highest set bit position */
00109         coef_exp = fls(coef_scaled) - 1;
00110 
00111         /* Doesn't make sense if it's zero*/
00112         if (!coef_scaled || !coef_exp)
00113                 return -EINVAL;
00114 
00115         /* Note: we've shifted coef_scaled by 24 */
00116         coef_exp = 14 - (coef_exp - 24);
00117 
00118 
00119         /* Get mantissa (significant digits)
00120          * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
00121         coef_man = coef_scaled +
00122                 (1 << (24 - coef_exp - 1));
00123 
00124         /* Calculate delta slope coefficient exponent
00125          * and mantissa (remove scaling) and set them on hw */
00126         ds_coef_man = coef_man >> (24 - coef_exp);
00127         ds_coef_exp = coef_exp - 16;
00128 
00129         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
00130                 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
00131         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
00132                 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
00133 
00134         return 0;
00135 }
00136 
00137 /**
00138  * ath5k_hw_write_rate_duration - fill rate code to duration table
00139  *
00140  * @ah: the &struct ath5k_hw
00141  * @mode: one of enum ath5k_driver_mode
00142  *
00143  * Write the rate code to duration table upon hw reset. This is a helper for
00144  * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
00145  * the hardware, based on current mode, for each rate. The rates which are
00146  * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
00147  * different rate code so we write their value twice (one for long preample
00148  * and one for short).
00149  *
00150  * Note: Band doesn't matter here, if we set the values for OFDM it works
00151  * on both a and g modes. So all we have to do is set values for all g rates
00152  * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
00153  * quarter rate mode, we need to use another set of bitrates (that's why we
00154  * need the mode parameter) but we don't handle these proprietary modes yet.
00155  */
00156 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
00157        unsigned int mode __unused)
00158 {
00159         struct ath5k_softc *sc = ah->ah_sc;
00160         u16 rate;
00161         int i;
00162 
00163         /* Write rate duration table */
00164         for (i = 0; i < sc->hwinfo->nr_rates[NET80211_BAND_2GHZ]; i++) {
00165                 u32 reg;
00166                 u16 tx_time;
00167 
00168                 rate = sc->hwinfo->rates[NET80211_BAND_2GHZ][i];
00169 
00170                 /* Set ACK timeout */
00171                 reg = AR5K_RATE_DUR(ath5k_bitrate_to_hw_rix(rate));
00172 
00173                 /* An ACK frame consists of 10 bytes. If you add the FCS,
00174                  * it's 14 bytes. Note we use the control rate and not the
00175                  * actual rate for this rate. See mac80211 tx.c
00176                  * ieee80211_duration() for a brief description of
00177                  * what rate we should choose to TX ACKs. */
00178                 tx_time = net80211_duration(sc->dev, 14, rate);
00179 
00180                 ath5k_hw_reg_write(ah, tx_time, reg);
00181 
00182                 if (rate != 20 && rate != 55 && rate != 110)
00183                         continue;
00184 
00185                 /*
00186                  * We're not distinguishing short preamble here,
00187                  * This is true, all we'll get is a longer value here
00188                  * which is not necessarilly bad.
00189                  */
00190                 ath5k_hw_reg_write(ah, tx_time,
00191                         reg + (AR5K_SET_SHORT_PREAMBLE << 2));
00192         }
00193 }
00194 
00195 /*
00196  * Reset chipset
00197  */
00198 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
00199 {
00200         int ret;
00201         u32 mask = val ? val : ~0U;
00202 
00203         /* Read-and-clear RX Descriptor Pointer*/
00204         ath5k_hw_reg_read(ah, AR5K_RXDP);
00205 
00206         /*
00207          * Reset the device and wait until success
00208          */
00209         ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
00210 
00211         /* Wait at least 128 PCI clocks */
00212         udelay(15);
00213 
00214         if (ah->ah_version == AR5K_AR5210) {
00215                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
00216                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
00217                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
00218                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
00219         } else {
00220                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
00221                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
00222         }
00223 
00224         ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, 0);
00225 
00226         /*
00227          * Reset configuration register (for hw byte-swap). Note that this
00228          * is only set for big endian. We do the necessary magic in
00229          * AR5K_INIT_CFG.
00230          */
00231         if ((val & AR5K_RESET_CTL_PCU) == 0)
00232                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
00233 
00234         return ret;
00235 }
00236 
00237 /*
00238  * Sleep control
00239  */
00240 int ath5k_hw_wake(struct ath5k_hw *ah)
00241 {
00242         unsigned int i;
00243         u32 staid, data;
00244 
00245         staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
00246         staid &= ~AR5K_STA_ID1_PWR_SV;
00247 
00248         /* Preserve sleep duration */
00249         data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
00250         if (data & 0xffc00000)
00251                 data = 0;
00252         else
00253                 data = data & 0xfffcffff;
00254 
00255         ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
00256         udelay(15);
00257 
00258         for (i = 50; i > 0; i--) {
00259                 /* Check if the chip did wake up */
00260                 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
00261                      AR5K_PCICFG_SPWR_DN) == 0)
00262                         break;
00263 
00264                 /* Wait a bit and retry */
00265                 udelay(200);
00266                 ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
00267         }
00268 
00269         /* Fail if the chip didn't wake up */
00270         if (i <= 0)
00271                 return -EIO;
00272 
00273         ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
00274 
00275         return 0;
00276 }
00277 
00278 /*
00279  * Bring up MAC + PHY Chips and program PLL
00280  * TODO: Half/Quarter rate support
00281  */
00282 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial __unused)
00283 {
00284         struct pci_device *pdev = ah->ah_sc->pdev;
00285         u32 turbo, mode, clock, bus_flags;
00286         int ret;
00287 
00288         turbo = 0;
00289         mode = 0;
00290         clock = 0;
00291 
00292         /* Wakeup the device */
00293         ret = ath5k_hw_wake(ah);
00294         if (ret) {
00295                 DBG("ath5k: failed to wake up the MAC chip\n");
00296                 return ret;
00297         }
00298 
00299         if (ah->ah_version != AR5K_AR5210) {
00300                 /*
00301                  * Get channel mode flags
00302                  */
00303 
00304                 if (ah->ah_radio >= AR5K_RF5112) {
00305                         mode = AR5K_PHY_MODE_RAD_RF5112;
00306                         clock = AR5K_PHY_PLL_RF5112;
00307                 } else {
00308                         mode = AR5K_PHY_MODE_RAD_RF5111;        /*Zero*/
00309                         clock = AR5K_PHY_PLL_RF5111;            /*Zero*/
00310                 }
00311 
00312                 if (flags & CHANNEL_2GHZ) {
00313                         mode |= AR5K_PHY_MODE_FREQ_2GHZ;
00314                         clock |= AR5K_PHY_PLL_44MHZ;
00315 
00316                         if (flags & CHANNEL_CCK) {
00317                                 mode |= AR5K_PHY_MODE_MOD_CCK;
00318                         } else if (flags & CHANNEL_OFDM) {
00319                                 /* XXX Dynamic OFDM/CCK is not supported by the
00320                                  * AR5211 so we set MOD_OFDM for plain g (no
00321                                  * CCK headers) operation. We need to test
00322                                  * this, 5211 might support ofdm-only g after
00323                                  * all, there are also initial register values
00324                                  * in the code for g mode (see initvals.c). */
00325                                 if (ah->ah_version == AR5K_AR5211)
00326                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
00327                                 else
00328                                         mode |= AR5K_PHY_MODE_MOD_DYN;
00329                         } else {
00330                                 DBG("ath5k: invalid radio modulation mode\n");
00331                                 return -EINVAL;
00332                         }
00333                 } else if (flags & CHANNEL_5GHZ) {
00334                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
00335 
00336                         if (ah->ah_radio == AR5K_RF5413)
00337                                 clock = AR5K_PHY_PLL_40MHZ_5413;
00338                         else
00339                                 clock |= AR5K_PHY_PLL_40MHZ;
00340 
00341                         if (flags & CHANNEL_OFDM)
00342                                 mode |= AR5K_PHY_MODE_MOD_OFDM;
00343                         else {
00344                                 DBG("ath5k: invalid radio modulation mode\n");
00345                                 return -EINVAL;
00346                         }
00347                 } else {
00348                         DBG("ath5k: invalid radio frequency mode\n");
00349                         return -EINVAL;
00350                 }
00351 
00352                 if (flags & CHANNEL_TURBO)
00353                         turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
00354         } else { /* Reset the device */
00355 
00356                 /* ...enable Atheros turbo mode if requested */
00357                 if (flags & CHANNEL_TURBO)
00358                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
00359                                         AR5K_PHY_TURBO);
00360         }
00361 
00362         /* reseting PCI on PCI-E cards results card to hang
00363          * and always return 0xffff... so we ingore that flag
00364          * for PCI-E cards */
00365         if (pci_find_capability(pdev, PCI_CAP_ID_EXP))
00366                 bus_flags = 0;
00367         else
00368                 bus_flags = AR5K_RESET_CTL_PCI;
00369 
00370         /* Reset chipset */
00371         if (ah->ah_version == AR5K_AR5210) {
00372                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00373                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
00374                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
00375                 mdelay(2);
00376         } else {
00377                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
00378                         AR5K_RESET_CTL_BASEBAND | bus_flags);
00379         }
00380         if (ret) {
00381                 DBG("ath5k: failed to reset the MAC chip\n");
00382                 return -EIO;
00383         }
00384 
00385         /* ...wakeup again!*/
00386         ret = ath5k_hw_wake(ah);
00387         if (ret) {
00388                 DBG("ath5k: failed to resume the MAC chip\n");
00389                 return ret;
00390         }
00391 
00392         /* ...final warm reset */
00393         if (ath5k_hw_nic_reset(ah, 0)) {
00394                 DBG("ath5k: failed to warm reset the MAC chip\n");
00395                 return -EIO;
00396         }
00397 
00398         if (ah->ah_version != AR5K_AR5210) {
00399 
00400                 /* ...update PLL if needed */
00401                 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
00402                         ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
00403                         udelay(300);
00404                 }
00405 
00406                 /* ...set the PHY operating mode */
00407                 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
00408                 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
00409         }
00410 
00411         return 0;
00412 }
00413 
00414 static int ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
00415                                 struct net80211_channel *channel)
00416 {
00417         u8 refclk_freq;
00418 
00419         if ((ah->ah_radio == AR5K_RF5112) ||
00420         (ah->ah_radio == AR5K_RF5413) ||
00421         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
00422                 refclk_freq = 40;
00423         else
00424                 refclk_freq = 32;
00425 
00426         if ((channel->center_freq % refclk_freq != 0) &&
00427         ((channel->center_freq % refclk_freq < 10) ||
00428         (channel->center_freq % refclk_freq > 22)))
00429                 return 1;
00430         else
00431                 return 0;
00432 }
00433 
00434 /* TODO: Half/Quarter rate */
00435 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
00436                                 struct net80211_channel *channel)
00437 {
00438         if (ah->ah_version == AR5K_AR5212 &&
00439             ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
00440 
00441                 /* Setup ADC control */
00442                 ath5k_hw_reg_write(ah,
00443                                 (AR5K_REG_SM(2,
00444                                 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
00445                                 AR5K_REG_SM(2,
00446                                 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
00447                                 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
00448                                 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
00449                                 AR5K_PHY_ADC_CTL);
00450 
00451 
00452 
00453                 /* Disable barker RSSI threshold */
00454                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
00455                                 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
00456 
00457                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
00458                         AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
00459 
00460                 /* Set the mute mask */
00461                 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
00462         }
00463 
00464         /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
00465         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
00466                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
00467 
00468         /* Enable DCU double buffering */
00469         if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
00470                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
00471                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
00472 
00473         /* Set DAC/ADC delays */
00474         if (ah->ah_version == AR5K_AR5212) {
00475                 u32 scal;
00476                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
00477                         scal = AR5K_PHY_SCAL_32MHZ_2417;
00478                 else if (ath5k_eeprom_is_hb63(ah))
00479                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
00480                 else
00481                         scal = AR5K_PHY_SCAL_32MHZ;
00482                 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
00483         }
00484 
00485         /* Set fast ADC */
00486         if ((ah->ah_radio == AR5K_RF5413) ||
00487         (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
00488                 u32 fast_adc = 1;
00489 
00490                 if (channel->center_freq == 2462 ||
00491                 channel->center_freq == 2467)
00492                         fast_adc = 0;
00493 
00494                 /* Only update if needed */
00495                 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
00496                                 ath5k_hw_reg_write(ah, fast_adc,
00497                                                 AR5K_PHY_FAST_ADC);
00498         }
00499 
00500         /* Fix for first revision of the RF5112 RF chipset */
00501         if (ah->ah_radio == AR5K_RF5112 &&
00502                         ah->ah_radio_5ghz_revision <
00503                         AR5K_SREV_RAD_5112A) {
00504                 u32 data;
00505                 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
00506                                 AR5K_PHY_CCKTXCTL);
00507                 if (channel->hw_value & CHANNEL_5GHZ)
00508                         data = 0xffb81020;
00509                 else
00510                         data = 0xffb80d20;
00511                 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
00512         }
00513 
00514         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
00515                 u32 usec_reg;
00516                 /* 5311 has different tx/rx latency masks
00517                  * from 5211, since we deal 5311 the same
00518                  * as 5211 when setting initvals, shift
00519                  * values here to their proper locations */
00520                 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
00521                 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
00522                                 AR5K_USEC_32 |
00523                                 AR5K_USEC_TX_LATENCY_5211 |
00524                                 AR5K_REG_SM(29,
00525                                 AR5K_USEC_RX_LATENCY_5210)),
00526                                 AR5K_USEC_5211);
00527                 /* Clear QCU/DCU clock gating register */
00528                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
00529                 /* Set DAC/ADC delays */
00530                 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
00531                 /* Enable PCU FIFO corruption ECO */
00532                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
00533                                         AR5K_DIAG_SW_ECO_ENABLE);
00534         }
00535 }
00536 
00537 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
00538                 struct net80211_channel *channel, u8 *ant, u8 ee_mode)
00539 {
00540         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
00541         s16 cck_ofdm_pwr_delta;
00542 
00543         /* Adjust power delta for channel 14 */
00544         if (channel->center_freq == 2484)
00545                 cck_ofdm_pwr_delta =
00546                         ((ee->ee_cck_ofdm_power_delta -
00547                         ee->ee_scaled_cck_delta) * 2) / 10;
00548         else
00549                 cck_ofdm_pwr_delta =
00550                         (ee->ee_cck_ofdm_power_delta * 2) / 10;
00551 
00552         /* Set CCK to OFDM power delta on tx power
00553          * adjustment register */
00554         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
00555                 if (channel->hw_value == CHANNEL_G)
00556                         ath5k_hw_reg_write(ah,
00557                         AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
00558                                 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
00559                         AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
00560                                 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
00561                                 AR5K_PHY_TX_PWR_ADJ);
00562                 else
00563                         ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
00564         } else {
00565                 /* For older revs we scale power on sw during tx power
00566                  * setup */
00567                 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
00568                 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
00569                                                 ee->ee_cck_ofdm_gain_delta;
00570         }
00571 
00572         /* Set antenna idle switch table */
00573         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
00574                         AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
00575                         (ah->ah_antenna[ee_mode][0] |
00576                         AR5K_PHY_ANT_CTL_TXRX_EN));
00577 
00578         /* Set antenna switch table */
00579         ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
00580                 AR5K_PHY_ANT_SWITCH_TABLE_0);
00581         ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
00582                 AR5K_PHY_ANT_SWITCH_TABLE_1);
00583 
00584         /* Noise floor threshold */
00585         ath5k_hw_reg_write(ah,
00586                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
00587                 AR5K_PHY_NFTHRES);
00588 
00589         if ((channel->hw_value & CHANNEL_TURBO) &&
00590         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
00591                 /* Switch settling time (Turbo) */
00592                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
00593                                 AR5K_PHY_SETTLING_SWITCH,
00594                                 ee->ee_switch_settling_turbo[ee_mode]);
00595 
00596                 /* Tx/Rx attenuation (Turbo) */
00597                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
00598                                 AR5K_PHY_GAIN_TXRX_ATTEN,
00599                                 ee->ee_atn_tx_rx_turbo[ee_mode]);
00600 
00601                 /* ADC/PGA desired size (Turbo) */
00602                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00603                                 AR5K_PHY_DESIRED_SIZE_ADC,
00604                                 ee->ee_adc_desired_size_turbo[ee_mode]);
00605 
00606                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00607                                 AR5K_PHY_DESIRED_SIZE_PGA,
00608                                 ee->ee_pga_desired_size_turbo[ee_mode]);
00609 
00610                 /* Tx/Rx margin (Turbo) */
00611                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
00612                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
00613                                 ee->ee_margin_tx_rx_turbo[ee_mode]);
00614 
00615         } else {
00616                 /* Switch settling time */
00617                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
00618                                 AR5K_PHY_SETTLING_SWITCH,
00619                                 ee->ee_switch_settling[ee_mode]);
00620 
00621                 /* Tx/Rx attenuation */
00622                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
00623                                 AR5K_PHY_GAIN_TXRX_ATTEN,
00624                                 ee->ee_atn_tx_rx[ee_mode]);
00625 
00626                 /* ADC/PGA desired size */
00627                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00628                                 AR5K_PHY_DESIRED_SIZE_ADC,
00629                                 ee->ee_adc_desired_size[ee_mode]);
00630 
00631                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
00632                                 AR5K_PHY_DESIRED_SIZE_PGA,
00633                                 ee->ee_pga_desired_size[ee_mode]);
00634 
00635                 /* Tx/Rx margin */
00636                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
00637                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
00638                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
00639                                 ee->ee_margin_tx_rx[ee_mode]);
00640         }
00641 
00642         /* XPA delays */
00643         ath5k_hw_reg_write(ah,
00644                 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
00645                 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
00646                 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
00647                 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
00648 
00649         /* XLNA delay */
00650         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
00651                         AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
00652                         ee->ee_tx_end2xlna_enable[ee_mode]);
00653 
00654         /* Thresh64 (ANI) */
00655         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
00656                         AR5K_PHY_NF_THRESH62,
00657                         ee->ee_thr_62[ee_mode]);
00658 
00659 
00660         /* False detect backoff for channels
00661          * that have spur noise. Write the new
00662          * cyclic power RSSI threshold. */
00663         if (ath5k_hw_chan_has_spur_noise(ah, channel))
00664                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
00665                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
00666                                 AR5K_INIT_CYCRSSI_THR1 +
00667                                 ee->ee_false_detect[ee_mode]);
00668         else
00669                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
00670                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
00671                                 AR5K_INIT_CYCRSSI_THR1);
00672 
00673         /* I/Q correction
00674          * TODO: Per channel i/q infos ? */
00675         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
00676                 AR5K_PHY_IQ_CORR_ENABLE |
00677                 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
00678                 ee->ee_q_cal[ee_mode]);
00679 
00680         /* Heavy clipping -disable for now */
00681         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
00682                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
00683 
00684         return;
00685 }
00686 
00687 /*
00688  * Main reset function
00689  */
00690 int ath5k_hw_reset(struct ath5k_hw *ah,
00691         struct net80211_channel *channel, int change_channel)
00692 {
00693         u32 s_seq[10], s_ant, s_led[3], staid1_flags;
00694         u32 phy_tst1;
00695         u8 mode, freq, ee_mode, ant[2];
00696         int i, ret;
00697 
00698         s_ant = 0;
00699         ee_mode = 0;
00700         staid1_flags = 0;
00701         freq = 0;
00702         mode = 0;
00703 
00704         /*
00705          * Save some registers before a reset
00706          */
00707         /*DCU/Antenna selection not available on 5210*/
00708         if (ah->ah_version != AR5K_AR5210) {
00709 
00710                 switch (channel->hw_value & CHANNEL_MODES) {
00711                 case CHANNEL_A:
00712                         mode = AR5K_MODE_11A;
00713                         freq = AR5K_INI_RFGAIN_5GHZ;
00714                         ee_mode = AR5K_EEPROM_MODE_11A;
00715                         break;
00716                 case CHANNEL_G:
00717                         mode = AR5K_MODE_11G;
00718                         freq = AR5K_INI_RFGAIN_2GHZ;
00719                         ee_mode = AR5K_EEPROM_MODE_11G;
00720                         break;
00721                 case CHANNEL_B:
00722                         mode = AR5K_MODE_11B;
00723                         freq = AR5K_INI_RFGAIN_2GHZ;
00724                         ee_mode = AR5K_EEPROM_MODE_11B;
00725                         break;
00726                 case CHANNEL_T:
00727                         mode = AR5K_MODE_11A_TURBO;
00728                         freq = AR5K_INI_RFGAIN_5GHZ;
00729                         ee_mode = AR5K_EEPROM_MODE_11A;
00730                         break;
00731                 case CHANNEL_TG:
00732                         if (ah->ah_version == AR5K_AR5211) {
00733                                 DBG("ath5k: TurboG not available on 5211\n");
00734                                 return -EINVAL;
00735                         }
00736                         mode = AR5K_MODE_11G_TURBO;
00737                         freq = AR5K_INI_RFGAIN_2GHZ;
00738                         ee_mode = AR5K_EEPROM_MODE_11G;
00739                         break;
00740                 case CHANNEL_XR:
00741                         if (ah->ah_version == AR5K_AR5211) {
00742                                 DBG("ath5k: XR mode not available on 5211\n");
00743                                 return -EINVAL;
00744                         }
00745                         mode = AR5K_MODE_XR;
00746                         freq = AR5K_INI_RFGAIN_5GHZ;
00747                         ee_mode = AR5K_EEPROM_MODE_11A;
00748                         break;
00749                 default:
00750                         DBG("ath5k: invalid channel (%d MHz)\n",
00751                             channel->center_freq);
00752                         return -EINVAL;
00753                 }
00754 
00755                 if (change_channel) {
00756                         /*
00757                          * Save frame sequence count
00758                          * For revs. after Oahu, only save
00759                          * seq num for DCU 0 (Global seq num)
00760                          */
00761                         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
00762 
00763                                 for (i = 0; i < 10; i++)
00764                                         s_seq[i] = ath5k_hw_reg_read(ah,
00765                                                 AR5K_QUEUE_DCU_SEQNUM(i));
00766 
00767                         } else {
00768                                 s_seq[0] = ath5k_hw_reg_read(ah,
00769                                                 AR5K_QUEUE_DCU_SEQNUM(0));
00770                         }
00771                 }
00772 
00773                 /* Save default antenna */
00774                 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
00775 
00776                 if (ah->ah_version == AR5K_AR5212) {
00777                         /* Since we are going to write rf buffer
00778                          * check if we have any pending gain_F
00779                          * optimization settings */
00780                         if (change_channel && ah->ah_rf_banks != NULL)
00781                                 ath5k_hw_gainf_calibrate(ah);
00782                 }
00783         }
00784 
00785         /*GPIOs*/
00786         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
00787                                         AR5K_PCICFG_LEDSTATE;
00788         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
00789         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
00790 
00791         /* AR5K_STA_ID1 flags, only preserve antenna
00792          * settings and ack/cts rate mode */
00793         staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
00794                         (AR5K_STA_ID1_DEFAULT_ANTENNA |
00795                         AR5K_STA_ID1_DESC_ANTENNA |
00796                         AR5K_STA_ID1_RTS_DEF_ANTENNA |
00797                         AR5K_STA_ID1_ACKCTS_6MB |
00798                         AR5K_STA_ID1_BASE_RATE_11B |
00799                         AR5K_STA_ID1_SELFGEN_DEF_ANT);
00800 
00801         /* Wakeup the device */
00802         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0);
00803         if (ret)
00804                 return ret;
00805 
00806         /* PHY access enable */
00807         if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
00808                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
00809         else
00810                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
00811                                                         AR5K_PHY(0));
00812 
00813         /* Write initial settings */
00814         ret = ath5k_hw_write_initvals(ah, mode, change_channel);
00815         if (ret)
00816                 return ret;
00817 
00818         /*
00819          * 5211/5212 Specific
00820          */
00821         if (ah->ah_version != AR5K_AR5210) {
00822 
00823                 /*
00824                  * Write initial RF gain settings
00825                  * This should work for both 5111/5112
00826                  */
00827                 ret = ath5k_hw_rfgain_init(ah, freq);
00828                 if (ret)
00829                         return ret;
00830 
00831                 mdelay(1);
00832 
00833                 /*
00834                  * Tweak initval settings for revised
00835                  * chipsets and add some more config
00836                  * bits
00837                  */
00838                 ath5k_hw_tweak_initval_settings(ah, channel);
00839 
00840                 /*
00841                  * Set TX power (FIXME)
00842                  */
00843                 ret = ath5k_hw_txpower(ah, channel, ee_mode,
00844                                         AR5K_TUNE_DEFAULT_TXPOWER);
00845                 if (ret)
00846                         return ret;
00847 
00848                 /* Write rate duration table only on AR5212 */
00849                 if (ah->ah_version == AR5K_AR5212)
00850                         ath5k_hw_write_rate_duration(ah, mode);
00851 
00852                 /*
00853                  * Write RF buffer
00854                  */
00855                 ret = ath5k_hw_rfregs_init(ah, channel, mode);
00856                 if (ret)
00857                         return ret;
00858 
00859 
00860                 /* Write OFDM timings on 5212*/
00861                 if (ah->ah_version == AR5K_AR5212 &&
00862                         channel->hw_value & CHANNEL_OFDM) {
00863                         ret = ath5k_hw_write_ofdm_timings(ah, channel);
00864                         if (ret)
00865                                 return ret;
00866                 }
00867 
00868                 /*Enable/disable 802.11b mode on 5111
00869                 (enable 2111 frequency converter + CCK)*/
00870                 if (ah->ah_radio == AR5K_RF5111) {
00871                         if (mode == AR5K_MODE_11B)
00872                                 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
00873                                     AR5K_TXCFG_B_MODE);
00874                         else
00875                                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
00876                                     AR5K_TXCFG_B_MODE);
00877                 }
00878 
00879                 /*
00880                  * In case a fixed antenna was set as default
00881                  * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
00882                  * registers.
00883                  */
00884                 if (s_ant != 0) {
00885                         if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
00886                                 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
00887                         else    /* 2 - Aux */
00888                                 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
00889                 } else {
00890                         ant[0] = AR5K_ANT_FIXED_A;
00891                         ant[1] = AR5K_ANT_FIXED_B;
00892                 }
00893 
00894                 /* Commit values from EEPROM */
00895                 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode);
00896 
00897         } else {
00898                 /*
00899                  * For 5210 we do all initialization using
00900                  * initvals, so we don't have to modify
00901                  * any settings (5210 also only supports
00902                  * a/aturbo modes)
00903                  */
00904                 mdelay(1);
00905                 /* Disable phy and wait */
00906                 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
00907                 mdelay(1);
00908         }
00909 
00910         /*
00911          * Restore saved values
00912          */
00913 
00914         /*DCU/Antenna selection not available on 5210*/
00915         if (ah->ah_version != AR5K_AR5210) {
00916 
00917                 if (change_channel) {
00918                         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
00919                                 for (i = 0; i < 10; i++)
00920                                         ath5k_hw_reg_write(ah, s_seq[i],
00921                                                 AR5K_QUEUE_DCU_SEQNUM(i));
00922                         } else {
00923                                 ath5k_hw_reg_write(ah, s_seq[0],
00924                                         AR5K_QUEUE_DCU_SEQNUM(0));
00925                         }
00926                 }
00927 
00928                 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
00929         }
00930 
00931         /* Ledstate */
00932         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
00933 
00934         /* Gpio settings */
00935         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
00936         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
00937 
00938         /* Restore sta_id flags and preserve our mac address*/
00939         ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id),
00940                                                 AR5K_STA_ID0);
00941         ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id),
00942                                                 AR5K_STA_ID1);
00943 
00944 
00945         /*
00946          * Configure PCU
00947          */
00948 
00949         /* Restore bssid and bssid mask */
00950         /* XXX: add ah->aid once mac80211 gives this to us */
00951         ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
00952 
00953         /* Set PCU config */
00954         ath5k_hw_set_opmode(ah);
00955 
00956         /* Clear any pending interrupts
00957          * PISR/SISR Not available on 5210 */
00958         if (ah->ah_version != AR5K_AR5210)
00959                 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
00960 
00961         /* Set RSSI/BRSSI thresholds
00962          *
00963          * Note: If we decide to set this value
00964          * dynamicaly, have in mind that when AR5K_RSSI_THR
00965          * register is read it might return 0x40 if we haven't
00966          * wrote anything to it plus BMISS RSSI threshold is zeroed.
00967          * So doing a save/restore procedure here isn't the right
00968          * choice. Instead store it on ath5k_hw */
00969         ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
00970                                 AR5K_TUNE_BMISS_THRES <<
00971                                 AR5K_RSSI_THR_BMISS_S),
00972                                 AR5K_RSSI_THR);
00973 
00974         /* MIC QoS support */
00975         if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
00976                 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
00977                 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
00978         }
00979 
00980         /* QoS NOACK Policy */
00981         if (ah->ah_version == AR5K_AR5212) {
00982                 ath5k_hw_reg_write(ah,
00983                         AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
00984                         AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
00985                         AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
00986                         AR5K_QOS_NOACK);
00987         }
00988 
00989 
00990         /*
00991          * Configure PHY
00992          */
00993 
00994         /* Set channel on PHY */
00995         ret = ath5k_hw_channel(ah, channel);
00996         if (ret)
00997                 return ret;
00998 
00999         /*
01000          * Enable the PHY and wait until completion
01001          * This includes BaseBand and Synthesizer
01002          * activation.
01003          */
01004         ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
01005 
01006         /*
01007          * On 5211+ read activation -> rx delay
01008          * and use it.
01009          *
01010          * TODO: Half/quarter rate support
01011          */
01012         if (ah->ah_version != AR5K_AR5210) {
01013                 u32 delay;
01014                 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
01015                         AR5K_PHY_RX_DELAY_M;
01016                 delay = (channel->hw_value & CHANNEL_CCK) ?
01017                         ((delay << 2) / 22) : (delay / 10);
01018 
01019                 udelay(100 + (2 * delay));
01020         } else {
01021                 mdelay(1);
01022         }
01023 
01024         /*
01025          * Perform ADC test to see if baseband is ready
01026          * Set tx hold and check adc test register
01027          */
01028         phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
01029         ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
01030         for (i = 0; i <= 20; i++) {
01031                 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
01032                         break;
01033                 udelay(200);
01034         }
01035         ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
01036 
01037         /*
01038          * Start automatic gain control calibration
01039          *
01040          * During AGC calibration RX path is re-routed to
01041          * a power detector so we don't receive anything.
01042          *
01043          * This method is used to calibrate some static offsets
01044          * used together with on-the fly I/Q calibration (the
01045          * one performed via ath5k_hw_phy_calibrate), that doesn't
01046          * interrupt rx path.
01047          *
01048          * While rx path is re-routed to the power detector we also
01049          * start a noise floor calibration, to measure the
01050          * card's noise floor (the noise we measure when we are not
01051          * transmiting or receiving anything).
01052          *
01053          * If we are in a noisy environment AGC calibration may time
01054          * out and/or noise floor calibration might timeout.
01055          */
01056         AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
01057                                 AR5K_PHY_AGCCTL_CAL);
01058 
01059         /* At the same time start I/Q calibration for QAM constellation
01060          * -no need for CCK- */
01061         ah->ah_calibration = 0;
01062         if (!(mode == AR5K_MODE_11B)) {
01063                 ah->ah_calibration = 1;
01064                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
01065                                 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
01066                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
01067                                 AR5K_PHY_IQ_RUN);
01068         }
01069 
01070         /* Wait for gain calibration to finish (we check for I/Q calibration
01071          * during ath5k_phy_calibrate) */
01072         if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
01073                         AR5K_PHY_AGCCTL_CAL, 0, 0)) {
01074                 DBG("ath5k: gain calibration timeout (%d MHz)\n",
01075                     channel->center_freq);
01076         }
01077 
01078         /*
01079          * If we run NF calibration before AGC, it always times out.
01080          * Binary HAL starts NF and AGC calibration at the same time
01081          * and only waits for AGC to finish. Also if AGC or NF cal.
01082          * times out, reset doesn't fail on binary HAL. I believe
01083          * that's wrong because since rx path is routed to a detector,
01084          * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211
01085          * enables noise floor calibration after offset calibration and if noise
01086          * floor calibration fails, reset fails. I believe that's
01087          * a better approach, we just need to find a polling interval
01088          * that suits best, even if reset continues we need to make
01089          * sure that rx path is ready.
01090          */
01091         ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
01092 
01093 
01094         /*
01095          * Configure QCUs/DCUs
01096          */
01097 
01098         /* TODO: HW Compression support for data queues */
01099         /* TODO: Burst prefetch for data queues */
01100 
01101         /*
01102          * Reset queues and start beacon timers at the end of the reset routine
01103          * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
01104          * Note: If we want we can assign multiple qcus on one dcu.
01105          */
01106         ret = ath5k_hw_reset_tx_queue(ah);
01107         if (ret) {
01108                 DBG("ath5k: failed to reset TX queue\n");
01109                 return ret;
01110         }
01111 
01112         /*
01113          * Configure DMA/Interrupts
01114          */
01115 
01116         /*
01117          * Set Rx/Tx DMA Configuration
01118          *
01119          * Set standard DMA size (128). Note that
01120          * a DMA size of 512 causes rx overruns and tx errors
01121          * on pci-e cards (tested on 5424 but since rx overruns
01122          * also occur on 5416/5418 with madwifi we set 128
01123          * for all PCI-E cards to be safe).
01124          *
01125          * XXX: need to check 5210 for this
01126          * TODO: Check out tx triger level, it's always 64 on dumps but I
01127          * guess we can tweak it and see how it goes ;-)
01128          */
01129         if (ah->ah_version != AR5K_AR5210) {
01130                 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
01131                         AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
01132                 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
01133                         AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
01134         }
01135 
01136         /* Pre-enable interrupts on 5211/5212*/
01137         if (ah->ah_version != AR5K_AR5210)
01138                 ath5k_hw_set_imr(ah, ah->ah_imr);
01139 
01140         /*
01141          * Setup RFKill interrupt if rfkill flag is set on eeprom.
01142          * TODO: Use gpio pin and polarity infos from eeprom
01143          * TODO: Handle this in ath5k_intr because it'll result
01144          *       a nasty interrupt storm.
01145          */
01146 #if 0
01147         if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
01148                 ath5k_hw_set_gpio_input(ah, 0);
01149                 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
01150                 if (ah->ah_gpio[0] == 0)
01151                         ath5k_hw_set_gpio_intr(ah, 0, 1);
01152                 else
01153                         ath5k_hw_set_gpio_intr(ah, 0, 0);
01154         }
01155 #endif
01156 
01157         /*
01158          * Disable beacons and reset the register
01159          */
01160         AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
01161                         AR5K_BEACON_RESET_TSF);
01162 
01163         return 0;
01164 }
01165 
01166 #undef _ATH5K_RESET