iPXE
ath5k.c
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00001 /*
00002  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
00003  * Copyright (c) 2004-2005 Atheros Communications, Inc.
00004  * Copyright (c) 2006 Devicescape Software, Inc.
00005  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
00006  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
00007  *
00008  * Modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
00009  * Original from Linux kernel 2.6.30.
00010  *
00011  * All rights reserved.
00012  *
00013  * Redistribution and use in source and binary forms, with or without
00014  * modification, are permitted provided that the following conditions
00015  * are met:
00016  * 1. Redistributions of source code must retain the above copyright
00017  *    notice, this list of conditions and the following disclaimer,
00018  *    without modification.
00019  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
00020  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
00021  *    redistribution must be conditioned upon including a substantially
00022  *    similar Disclaimer requirement for further binary redistribution.
00023  * 3. Neither the names of the above-listed copyright holders nor the names
00024  *    of any contributors may be used to endorse or promote products derived
00025  *    from this software without specific prior written permission.
00026  *
00027  * Alternatively, this software may be distributed under the terms of the
00028  * GNU General Public License ("GPL") version 2 as published by the Free
00029  * Software Foundation.
00030  *
00031  * NO WARRANTY
00032  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00033  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00034  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
00035  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
00036  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
00037  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00038  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00039  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
00040  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00041  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
00042  * THE POSSIBILITY OF SUCH DAMAGES.
00043  *
00044  */
00045 
00046 FILE_LICENCE ( BSD3 );
00047 
00048 #include <stdlib.h>
00049 #include <ipxe/malloc.h>
00050 #include <ipxe/timer.h>
00051 #include <ipxe/netdevice.h>
00052 #include <ipxe/pci.h>
00053 #include <ipxe/pci_io.h>
00054 
00055 #include "base.h"
00056 #include "reg.h"
00057 
00058 #define ATH5K_CALIB_INTERVAL    10 /* Calibrate PHY every 10 seconds */
00059 #define ATH5K_RETRIES           4  /* Number of times to retry packet sends */
00060 #define ATH5K_DESC_ALIGN        16 /* Alignment for TX/RX descriptors */
00061 
00062 /******************\
00063 * Internal defines *
00064 \******************/
00065 
00066 /* Known PCI ids */
00067 static struct pci_device_id ath5k_nics[] = {
00068         PCI_ROM(0x168c, 0x0207, "ath5210e", "Atheros 5210 early", AR5K_AR5210),
00069         PCI_ROM(0x168c, 0x0007, "ath5210", "Atheros 5210", AR5K_AR5210),
00070         PCI_ROM(0x168c, 0x0011, "ath5311", "Atheros 5311 (AHB)", AR5K_AR5211),
00071         PCI_ROM(0x168c, 0x0012, "ath5211", "Atheros 5211", AR5K_AR5211),
00072         PCI_ROM(0x168c, 0x0013, "ath5212", "Atheros 5212", AR5K_AR5212),
00073         PCI_ROM(0xa727, 0x0013, "ath5212c","3com Ath 5212", AR5K_AR5212),
00074         PCI_ROM(0x10b7, 0x0013, "rdag675", "3com 3CRDAG675", AR5K_AR5212),
00075         PCI_ROM(0x168c, 0x1014, "ath5212m", "Ath 5212 miniPCI", AR5K_AR5212),
00076         PCI_ROM(0x168c, 0x0014, "ath5212x14", "Atheros 5212 x14", AR5K_AR5212),
00077         PCI_ROM(0x168c, 0x0015, "ath5212x15", "Atheros 5212 x15", AR5K_AR5212),
00078         PCI_ROM(0x168c, 0x0016, "ath5212x16", "Atheros 5212 x16", AR5K_AR5212),
00079         PCI_ROM(0x168c, 0x0017, "ath5212x17", "Atheros 5212 x17", AR5K_AR5212),
00080         PCI_ROM(0x168c, 0x0018, "ath5212x18", "Atheros 5212 x18", AR5K_AR5212),
00081         PCI_ROM(0x168c, 0x0019, "ath5212x19", "Atheros 5212 x19", AR5K_AR5212),
00082         PCI_ROM(0x168c, 0x001a, "ath2413", "Atheros 2413 Griffin", AR5K_AR5212),
00083         PCI_ROM(0x168c, 0x001b, "ath5413", "Atheros 5413 Eagle", AR5K_AR5212),
00084         PCI_ROM(0x168c, 0x001c, "ath5212e", "Atheros 5212 PCI-E", AR5K_AR5212),
00085         PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212),
00086 };
00087 
00088 #define ATH5K_SPMBL_NO   1
00089 #define ATH5K_SPMBL_YES  2
00090 #define ATH5K_SPMBL_BOTH 3
00091 
00092 static const struct {
00093         u16 bitrate;
00094         u8 short_pmbl;
00095         u8 hw_code;
00096 } ath5k_rates[] = {
00097         { 10, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_1M },
00098         { 20, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_2M },
00099         { 55, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_5_5M },
00100         { 110, ATH5K_SPMBL_NO, ATH5K_RATE_CODE_11M },
00101         { 60, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_6M },
00102         { 90, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_9M },
00103         { 120, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_12M },
00104         { 180, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_18M },
00105         { 240, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_24M },
00106         { 360, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_36M },
00107         { 480, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_48M },
00108         { 540, ATH5K_SPMBL_BOTH, ATH5K_RATE_CODE_54M },
00109         { 20, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE },
00110         { 55, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE },
00111         { 110, ATH5K_SPMBL_YES, ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE },
00112         { 0, 0, 0 },
00113 };
00114 
00115 #define ATH5K_NR_RATES 15
00116 
00117 /*
00118  * Prototypes - PCI stack related functions
00119  */
00120 static int              ath5k_probe(struct pci_device *pdev);
00121 static void             ath5k_remove(struct pci_device *pdev);
00122 
00123 struct pci_driver ath5k_pci_driver __pci_driver = {
00124         .ids            = ath5k_nics,
00125         .id_count       = sizeof(ath5k_nics) / sizeof(ath5k_nics[0]),
00126         .probe          = ath5k_probe,
00127         .remove         = ath5k_remove,
00128 };
00129 
00130 
00131 
00132 /*
00133  * Prototypes - MAC 802.11 stack related functions
00134  */
00135 static int ath5k_tx(struct net80211_device *dev, struct io_buffer *skb);
00136 static int ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan);
00137 static int ath5k_reset_wake(struct ath5k_softc *sc);
00138 static int ath5k_start(struct net80211_device *dev);
00139 static void ath5k_stop(struct net80211_device *dev);
00140 static int ath5k_config(struct net80211_device *dev, int changed);
00141 static void ath5k_poll(struct net80211_device *dev);
00142 static void ath5k_irq(struct net80211_device *dev, int enable);
00143 
00144 static struct net80211_device_operations ath5k_ops = {
00145         .open           = ath5k_start,
00146         .close          = ath5k_stop,
00147         .transmit       = ath5k_tx,
00148         .poll           = ath5k_poll,
00149         .irq            = ath5k_irq,
00150         .config         = ath5k_config,
00151 };
00152 
00153 /*
00154  * Prototypes - Internal functions
00155  */
00156 /* Attach detach */
00157 static int      ath5k_attach(struct net80211_device *dev);
00158 static void     ath5k_detach(struct net80211_device *dev);
00159 /* Channel/mode setup */
00160 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
00161                                 struct net80211_channel *channels,
00162                                 unsigned int mode,
00163                                 unsigned int max);
00164 static int      ath5k_setup_bands(struct net80211_device *dev);
00165 static int      ath5k_chan_set(struct ath5k_softc *sc,
00166                                 struct net80211_channel *chan);
00167 static void     ath5k_setcurmode(struct ath5k_softc *sc,
00168                                 unsigned int mode);
00169 static void     ath5k_mode_setup(struct ath5k_softc *sc);
00170 
00171 /* Descriptor setup */
00172 static int      ath5k_desc_alloc(struct ath5k_softc *sc);
00173 static void     ath5k_desc_free(struct ath5k_softc *sc);
00174 /* Buffers setup */
00175 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
00176 static int      ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf);
00177 
00178 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
00179                                     struct ath5k_buf *bf)
00180 {
00181         if (!bf->iob)
00182                 return;
00183 
00184         net80211_tx_complete(sc->dev, bf->iob, 0, ECANCELED);
00185         bf->iob = NULL;
00186 }
00187 
00188 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc __unused,
00189                                     struct ath5k_buf *bf)
00190 {
00191         free_iob(bf->iob);
00192         bf->iob = NULL;
00193 }
00194 
00195 /* Queues setup */
00196 static int      ath5k_txq_setup(struct ath5k_softc *sc,
00197                                            int qtype, int subtype);
00198 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
00199                                  struct ath5k_txq *txq);
00200 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
00201 static void     ath5k_txq_release(struct ath5k_softc *sc);
00202 /* Rx handling */
00203 static int      ath5k_rx_start(struct ath5k_softc *sc);
00204 static void     ath5k_rx_stop(struct ath5k_softc *sc);
00205 /* Tx handling */
00206 static void     ath5k_tx_processq(struct ath5k_softc *sc,
00207                                   struct ath5k_txq *txq);
00208 
00209 /* Interrupt handling */
00210 static int      ath5k_init(struct ath5k_softc *sc);
00211 static int      ath5k_stop_hw(struct ath5k_softc *sc);
00212 
00213 static void     ath5k_calibrate(struct ath5k_softc *sc);
00214 
00215 /* Filter */
00216 static void     ath5k_configure_filter(struct ath5k_softc *sc);
00217 
00218 /********************\
00219 * PCI Initialization *
00220 \********************/
00221 
00222 #if DBGLVL_MAX
00223 static const char *
00224 ath5k_chip_name(enum ath5k_srev_type type, u16 val)
00225 {
00226         const char *name = "xxxxx";
00227         unsigned int i;
00228 
00229         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
00230                 if (srev_names[i].sr_type != type)
00231                         continue;
00232 
00233                 if ((val & 0xf0) == srev_names[i].sr_val)
00234                         name = srev_names[i].sr_name;
00235 
00236                 if ((val & 0xff) == srev_names[i].sr_val) {
00237                         name = srev_names[i].sr_name;
00238                         break;
00239                 }
00240         }
00241 
00242         return name;
00243 }
00244 #endif
00245 
00246 static int ath5k_probe(struct pci_device *pdev)
00247 {
00248         void *mem;
00249         struct ath5k_softc *sc;
00250         struct net80211_device *dev;
00251         int ret;
00252         u8 csz;
00253 
00254         adjust_pci_device(pdev);
00255 
00256         /*
00257          * Cache line size is used to size and align various
00258          * structures used to communicate with the hardware.
00259          */
00260         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
00261         if (csz == 0) {
00262                 /*
00263                  * We must have this setup properly for rx buffer
00264                  * DMA to work so force a reasonable value here if it
00265                  * comes up zero.
00266                  */
00267                 csz = 16;
00268                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
00269         }
00270         /*
00271          * The default setting of latency timer yields poor results,
00272          * set it to the value used by other systems.  It may be worth
00273          * tweaking this setting more.
00274          */
00275         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
00276 
00277         /*
00278          * Disable the RETRY_TIMEOUT register (0x41) to keep
00279          * PCI Tx retries from interfering with C3 CPU state.
00280          */
00281         pci_write_config_byte(pdev, 0x41, 0);
00282 
00283         mem = ioremap(pdev->membase, 0x10000);
00284         if (!mem) {
00285                 DBG("ath5k: cannot remap PCI memory region\n");
00286                 ret = -EIO;
00287                 goto err;
00288         }
00289 
00290         /*
00291          * Allocate dev (net80211 main struct)
00292          * and dev->priv (driver private data)
00293          */
00294         dev = net80211_alloc(sizeof(*sc));
00295         if (!dev) {
00296                 DBG("ath5k: cannot allocate 802.11 device\n");
00297                 ret = -ENOMEM;
00298                 goto err_map;
00299         }
00300 
00301         /* Initialize driver private data */
00302         sc = dev->priv;
00303         sc->dev = dev;
00304         sc->pdev = pdev;
00305 
00306         sc->hwinfo = zalloc(sizeof(*sc->hwinfo));
00307         if (!sc->hwinfo) {
00308                 DBG("ath5k: cannot allocate 802.11 hardware info structure\n");
00309                 ret = -ENOMEM;
00310                 goto err_free;
00311         }
00312 
00313         sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS;
00314         sc->hwinfo->signal_type = NET80211_SIGNAL_DB;
00315         sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */
00316         sc->hwinfo->channel_change_time = 5000;
00317 
00318         /* Avoid working with the device until setup is complete */
00319         sc->status |= ATH_STAT_INVALID;
00320 
00321         sc->iobase = mem;
00322         sc->cachelsz = csz * 4; /* convert to bytes */
00323 
00324         DBG("ath5k: register base at %p (%08lx)\n", sc->iobase, pdev->membase);
00325         DBG("ath5k: cache line size %d\n", sc->cachelsz);
00326 
00327         /* Set private data */
00328         pci_set_drvdata(pdev, dev);
00329         dev->netdev->dev = (struct device *)pdev;
00330 
00331         /* Initialize device */
00332         ret = ath5k_hw_attach(sc, pdev->id->driver_data, &sc->ah);
00333         if (ret)
00334                 goto err_free_hwinfo;
00335 
00336         /* Finish private driver data initialization */
00337         ret = ath5k_attach(dev);
00338         if (ret)
00339                 goto err_ah;
00340 
00341 #if DBGLVL_MAX
00342         DBG("Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
00343             ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
00344             sc->ah->ah_mac_srev, sc->ah->ah_phy_revision);
00345 
00346         if (!sc->ah->ah_single_chip) {
00347                 /* Single chip radio (!RF5111) */
00348                 if (sc->ah->ah_radio_5ghz_revision &&
00349                     !sc->ah->ah_radio_2ghz_revision) {
00350                         /* No 5GHz support -> report 2GHz radio */
00351                         if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A)) {
00352                                 DBG("RF%s 2GHz radio found (0x%x)\n",
00353                                     ath5k_chip_name(AR5K_VERSION_RAD,
00354                                                     sc->ah->ah_radio_5ghz_revision),
00355                                     sc->ah->ah_radio_5ghz_revision);
00356                         /* No 2GHz support (5110 and some
00357                          * 5Ghz only cards) -> report 5Ghz radio */
00358                         } else if (!(sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B)) {
00359                                 DBG("RF%s 5GHz radio found (0x%x)\n",
00360                                     ath5k_chip_name(AR5K_VERSION_RAD,
00361                                                     sc->ah->ah_radio_5ghz_revision),
00362                                     sc->ah->ah_radio_5ghz_revision);
00363                         /* Multiband radio */
00364                         } else {
00365                                 DBG("RF%s multiband radio found (0x%x)\n",
00366                                     ath5k_chip_name(AR5K_VERSION_RAD,
00367                                                     sc->ah->ah_radio_5ghz_revision),
00368                                     sc->ah->ah_radio_5ghz_revision);
00369                         }
00370                 }
00371                 /* Multi chip radio (RF5111 - RF2111) ->
00372                  * report both 2GHz/5GHz radios */
00373                 else if (sc->ah->ah_radio_5ghz_revision &&
00374                          sc->ah->ah_radio_2ghz_revision) {
00375                         DBG("RF%s 5GHz radio found (0x%x)\n",
00376                             ath5k_chip_name(AR5K_VERSION_RAD,
00377                                             sc->ah->ah_radio_5ghz_revision),
00378                             sc->ah->ah_radio_5ghz_revision);
00379                         DBG("RF%s 2GHz radio found (0x%x)\n",
00380                             ath5k_chip_name(AR5K_VERSION_RAD,
00381                                             sc->ah->ah_radio_2ghz_revision),
00382                             sc->ah->ah_radio_2ghz_revision);
00383                 }
00384         }
00385 #endif
00386 
00387         /* Ready to go */
00388         sc->status &= ~ATH_STAT_INVALID;
00389 
00390         return 0;
00391 err_ah:
00392         ath5k_hw_detach(sc->ah);
00393 err_free_hwinfo:
00394         free(sc->hwinfo);
00395 err_free:
00396         net80211_free(dev);
00397 err_map:
00398         iounmap(mem);
00399 err:
00400         return ret;
00401 }
00402 
00403 static void ath5k_remove(struct pci_device *pdev)
00404 {
00405         struct net80211_device *dev = pci_get_drvdata(pdev);
00406         struct ath5k_softc *sc = dev->priv;
00407 
00408         ath5k_detach(dev);
00409         ath5k_hw_detach(sc->ah);
00410         iounmap(sc->iobase);
00411         free(sc->hwinfo);
00412         net80211_free(dev);
00413 }
00414 
00415 
00416 /***********************\
00417 * Driver Initialization *
00418 \***********************/
00419 
00420 static int
00421 ath5k_attach(struct net80211_device *dev)
00422 {
00423         struct ath5k_softc *sc = dev->priv;
00424         struct ath5k_hw *ah = sc->ah;
00425         int ret;
00426 
00427         /*
00428          * Collect the channel list.  The 802.11 layer
00429          * is resposible for filtering this list based
00430          * on settings like the phy mode and regulatory
00431          * domain restrictions.
00432          */
00433         ret = ath5k_setup_bands(dev);
00434         if (ret) {
00435                 DBG("ath5k: can't get channels\n");
00436                 goto err;
00437         }
00438 
00439         /* NB: setup here so ath5k_rate_update is happy */
00440         if (ah->ah_modes & AR5K_MODE_BIT_11A)
00441                 ath5k_setcurmode(sc, AR5K_MODE_11A);
00442         else
00443                 ath5k_setcurmode(sc, AR5K_MODE_11B);
00444 
00445         /*
00446          * Allocate tx+rx descriptors and populate the lists.
00447          */
00448         ret = ath5k_desc_alloc(sc);
00449         if (ret) {
00450                 DBG("ath5k: can't allocate descriptors\n");
00451                 goto err;
00452         }
00453 
00454         /*
00455          * Allocate hardware transmit queues. Note that hw functions
00456          * handle reseting these queues at the needed time.
00457          */
00458         ret = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
00459         if (ret) {
00460                 DBG("ath5k: can't setup xmit queue\n");
00461                 goto err_desc;
00462         }
00463 
00464         sc->last_calib_ticks = currticks();
00465 
00466         ret = ath5k_eeprom_read_mac(ah, sc->hwinfo->hwaddr);
00467         if (ret) {
00468                 DBG("ath5k: unable to read address from EEPROM: 0x%04x\n",
00469                     sc->pdev->device);
00470                 goto err_queues;
00471         }
00472 
00473         memset(sc->bssidmask, 0xff, ETH_ALEN);
00474         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
00475 
00476         ret = net80211_register(sc->dev, &ath5k_ops, sc->hwinfo);
00477         if (ret) {
00478                 DBG("ath5k: can't register ieee80211 hw\n");
00479                 goto err_queues;
00480         }
00481 
00482         return 0;
00483 err_queues:
00484         ath5k_txq_release(sc);
00485 err_desc:
00486         ath5k_desc_free(sc);
00487 err:
00488         return ret;
00489 }
00490 
00491 static void
00492 ath5k_detach(struct net80211_device *dev)
00493 {
00494         struct ath5k_softc *sc = dev->priv;
00495 
00496         net80211_unregister(dev);
00497         ath5k_desc_free(sc);
00498         ath5k_txq_release(sc);
00499 }
00500 
00501 
00502 
00503 
00504 /********************\
00505 * Channel/mode setup *
00506 \********************/
00507 
00508 /*
00509  * Convert IEEE channel number to MHz frequency.
00510  */
00511 static inline short
00512 ath5k_ieee2mhz(short chan)
00513 {
00514         if (chan < 14)
00515                 return 2407 + 5 * chan;
00516         if (chan == 14)
00517                 return 2484;
00518         if (chan < 27)
00519                 return 2212 + 20 * chan;
00520         return 5000 + 5 * chan;
00521 }
00522 
00523 static unsigned int
00524 ath5k_copy_channels(struct ath5k_hw *ah,
00525                     struct net80211_channel *channels,
00526                     unsigned int mode, unsigned int max)
00527 {
00528         unsigned int i, count, size, chfreq, freq, ch;
00529 
00530         if (!(ah->ah_modes & (1 << mode)))
00531                 return 0;
00532 
00533         switch (mode) {
00534         case AR5K_MODE_11A:
00535         case AR5K_MODE_11A_TURBO:
00536                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
00537                 size = 220;
00538                 chfreq = CHANNEL_5GHZ;
00539                 break;
00540         case AR5K_MODE_11B:
00541         case AR5K_MODE_11G:
00542         case AR5K_MODE_11G_TURBO:
00543                 size = 26;
00544                 chfreq = CHANNEL_2GHZ;
00545                 break;
00546         default:
00547                 return 0;
00548         }
00549 
00550         for (i = 0, count = 0; i < size && max > 0; i++) {
00551                 ch = i + 1 ;
00552                 freq = ath5k_ieee2mhz(ch);
00553 
00554                 /* Check if channel is supported by the chipset */
00555                 if (!ath5k_channel_ok(ah, freq, chfreq))
00556                         continue;
00557 
00558                 /* Write channel info and increment counter */
00559                 channels[count].center_freq = freq;
00560                 channels[count].maxpower = 0; /* use regulatory */
00561                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
00562                         NET80211_BAND_2GHZ : NET80211_BAND_5GHZ;
00563                 switch (mode) {
00564                 case AR5K_MODE_11A:
00565                 case AR5K_MODE_11G:
00566                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
00567                         break;
00568                 case AR5K_MODE_11A_TURBO:
00569                 case AR5K_MODE_11G_TURBO:
00570                         channels[count].hw_value = chfreq |
00571                                 CHANNEL_OFDM | CHANNEL_TURBO;
00572                         break;
00573                 case AR5K_MODE_11B:
00574                         channels[count].hw_value = CHANNEL_B;
00575                 }
00576 
00577                 count++;
00578                 max--;
00579         }
00580 
00581         return count;
00582 }
00583 
00584 static int
00585 ath5k_setup_bands(struct net80211_device *dev)
00586 {
00587         struct ath5k_softc *sc = dev->priv;
00588         struct ath5k_hw *ah = sc->ah;
00589         int max_c, count_c = 0;
00590         int i;
00591         int band;
00592 
00593         max_c = sizeof(sc->hwinfo->channels) / sizeof(sc->hwinfo->channels[0]);
00594 
00595         /* 2GHz band */
00596         if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11G) {
00597                 /* G mode */
00598                 band = NET80211_BAND_2GHZ;
00599                 sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ;
00600                 sc->hwinfo->modes = (NET80211_MODE_G | NET80211_MODE_B);
00601 
00602                 for (i = 0; i < 12; i++)
00603                         sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
00604                 sc->hwinfo->nr_rates[band] = 12;
00605 
00606                 sc->hwinfo->nr_channels =
00607                         ath5k_copy_channels(ah, sc->hwinfo->channels,
00608                                             AR5K_MODE_11G, max_c);
00609                 count_c = sc->hwinfo->nr_channels;
00610                 max_c -= count_c;
00611         } else if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11B) {
00612                 /* B mode */
00613                 band = NET80211_BAND_2GHZ;
00614                 sc->hwinfo->bands = NET80211_BAND_BIT_2GHZ;
00615                 sc->hwinfo->modes = NET80211_MODE_B;
00616 
00617                 for (i = 0; i < 4; i++)
00618                         sc->hwinfo->rates[band][i] = ath5k_rates[i].bitrate;
00619                 sc->hwinfo->nr_rates[band] = 4;
00620 
00621                 sc->hwinfo->nr_channels =
00622                         ath5k_copy_channels(ah, sc->hwinfo->channels,
00623                                             AR5K_MODE_11B, max_c);
00624                 count_c = sc->hwinfo->nr_channels;
00625                 max_c -= count_c;
00626         }
00627 
00628         /* 5GHz band, A mode */
00629         if (sc->ah->ah_capabilities.cap_mode & AR5K_MODE_BIT_11A) {
00630                 band = NET80211_BAND_5GHZ;
00631                 sc->hwinfo->bands |= NET80211_BAND_BIT_5GHZ;
00632                 sc->hwinfo->modes |= NET80211_MODE_A;
00633 
00634                 for (i = 0; i < 8; i++)
00635                         sc->hwinfo->rates[band][i] = ath5k_rates[i+4].bitrate;
00636                 sc->hwinfo->nr_rates[band] = 8;
00637 
00638                 sc->hwinfo->nr_channels =
00639                         ath5k_copy_channels(ah, sc->hwinfo->channels,
00640                                             AR5K_MODE_11B, max_c);
00641                 count_c = sc->hwinfo->nr_channels;
00642                 max_c -= count_c;
00643         }
00644 
00645         return 0;
00646 }
00647 
00648 /*
00649  * Set/change channels.  If the channel is really being changed,
00650  * it's done by reseting the chip.  To accomplish this we must
00651  * first cleanup any pending DMA, then restart stuff after a la
00652  * ath5k_init.
00653  */
00654 static int
00655 ath5k_chan_set(struct ath5k_softc *sc, struct net80211_channel *chan)
00656 {
00657         if (chan->center_freq != sc->curchan->center_freq ||
00658             chan->hw_value != sc->curchan->hw_value) {
00659                 /*
00660                  * To switch channels clear any pending DMA operations;
00661                  * wait long enough for the RX fifo to drain, reset the
00662                  * hardware at the new frequency, and then re-enable
00663                  * the relevant bits of the h/w.
00664                  */
00665                 DBG2("ath5k: resetting for channel change (%d -> %d MHz)\n",
00666                      sc->curchan->center_freq, chan->center_freq);
00667                 return ath5k_reset(sc, chan);
00668         }
00669 
00670         return 0;
00671 }
00672 
00673 static void
00674 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
00675 {
00676         sc->curmode = mode;
00677 
00678         if (mode == AR5K_MODE_11A) {
00679                 sc->curband = NET80211_BAND_5GHZ;
00680         } else {
00681                 sc->curband = NET80211_BAND_2GHZ;
00682         }
00683 }
00684 
00685 static void
00686 ath5k_mode_setup(struct ath5k_softc *sc)
00687 {
00688         struct ath5k_hw *ah = sc->ah;
00689         u32 rfilt;
00690 
00691         /* configure rx filter */
00692         rfilt = sc->filter_flags;
00693         ath5k_hw_set_rx_filter(ah, rfilt);
00694 
00695         if (ath5k_hw_hasbssidmask(ah))
00696                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
00697 
00698         /* configure operational mode */
00699         ath5k_hw_set_opmode(ah);
00700 
00701         ath5k_hw_set_mcast_filter(ah, 0, 0);
00702 }
00703 
00704 static inline int
00705 ath5k_hw_rix_to_bitrate(int hw_rix)
00706 {
00707         int i;
00708 
00709         for (i = 0; i < ATH5K_NR_RATES; i++) {
00710                 if (ath5k_rates[i].hw_code == hw_rix)
00711                         return ath5k_rates[i].bitrate;
00712         }
00713 
00714         DBG("ath5k: invalid rix %02x\n", hw_rix);
00715         return 10;              /* use lowest rate */
00716 }
00717 
00718 int ath5k_bitrate_to_hw_rix(int bitrate)
00719 {
00720         int i;
00721 
00722         for (i = 0; i < ATH5K_NR_RATES; i++) {
00723                 if (ath5k_rates[i].bitrate == bitrate)
00724                         return ath5k_rates[i].hw_code;
00725         }
00726 
00727         DBG("ath5k: invalid bitrate %d\n", bitrate);
00728         return ATH5K_RATE_CODE_1M; /* use lowest rate */
00729 }
00730 
00731 /***************\
00732 * Buffers setup *
00733 \***************/
00734 
00735 static struct io_buffer *
00736 ath5k_rx_iob_alloc(struct ath5k_softc *sc, u32 *iob_addr)
00737 {
00738         struct io_buffer *iob;
00739         unsigned int off;
00740 
00741         /*
00742          * Allocate buffer with headroom_needed space for the
00743          * fake physical layer header at the start.
00744          */
00745         iob = alloc_iob(sc->rxbufsize + sc->cachelsz - 1);
00746 
00747         if (!iob) {
00748                 DBG("ath5k: can't alloc iobuf of size %d\n",
00749                     sc->rxbufsize + sc->cachelsz - 1);
00750                 return NULL;
00751         }
00752 
00753         *iob_addr = virt_to_bus(iob->data);
00754 
00755         /*
00756          * Cache-line-align.  This is important (for the
00757          * 5210 at least) as not doing so causes bogus data
00758          * in rx'd frames.
00759          */
00760         off = *iob_addr % sc->cachelsz;
00761         if (off != 0) {
00762                 iob_reserve(iob, sc->cachelsz - off);
00763                 *iob_addr += sc->cachelsz - off;
00764         }
00765 
00766         return iob;
00767 }
00768 
00769 static int
00770 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
00771 {
00772         struct ath5k_hw *ah = sc->ah;
00773         struct io_buffer *iob = bf->iob;
00774         struct ath5k_desc *ds;
00775 
00776         if (!iob) {
00777                 iob = ath5k_rx_iob_alloc(sc, &bf->iobaddr);
00778                 if (!iob)
00779                         return -ENOMEM;
00780                 bf->iob = iob;
00781         }
00782 
00783         /*
00784          * Setup descriptors.  For receive we always terminate
00785          * the descriptor list with a self-linked entry so we'll
00786          * not get overrun under high load (as can happen with a
00787          * 5212 when ANI processing enables PHY error frames).
00788          *
00789          * To insure the last descriptor is self-linked we create
00790          * each descriptor as self-linked and add it to the end.  As
00791          * each additional descriptor is added the previous self-linked
00792          * entry is ``fixed'' naturally.  This should be safe even
00793          * if DMA is happening.  When processing RX interrupts we
00794          * never remove/process the last, self-linked, entry on the
00795          * descriptor list.  This insures the hardware always has
00796          * someplace to write a new frame.
00797          */
00798         ds = bf->desc;
00799         ds->ds_link = bf->daddr;        /* link to self */
00800         ds->ds_data = bf->iobaddr;
00801         if (ah->ah_setup_rx_desc(ah, ds,
00802                                  iob_tailroom(iob),     /* buffer size */
00803                                  0) != 0) {
00804                 DBG("ath5k: error setting up RX descriptor for %zd bytes\n", iob_tailroom(iob));
00805                 return -EINVAL;
00806         }
00807 
00808         if (sc->rxlink != NULL)
00809                 *sc->rxlink = bf->daddr;
00810         sc->rxlink = &ds->ds_link;
00811         return 0;
00812 }
00813 
00814 static int
00815 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
00816 {
00817         struct ath5k_hw *ah = sc->ah;
00818         struct ath5k_txq *txq = &sc->txq;
00819         struct ath5k_desc *ds = bf->desc;
00820         struct io_buffer *iob = bf->iob;
00821         unsigned int pktlen, flags;
00822         int ret;
00823         u16 duration = 0;
00824         u16 cts_rate = 0;
00825 
00826         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
00827         bf->iobaddr = virt_to_bus(iob->data);
00828         pktlen = iob_len(iob);
00829 
00830         /* FIXME: If we are in g mode and rate is a CCK rate
00831          * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
00832          * from tx power (value is in dB units already) */
00833         if (sc->dev->phy_flags & NET80211_PHY_USE_PROTECTION) {
00834                 struct net80211_device *dev = sc->dev;
00835 
00836                 flags |= AR5K_TXDESC_CTSENA;
00837                 cts_rate = sc->hw_rtscts_rate;
00838                 duration = net80211_cts_duration(dev, pktlen);
00839         }
00840         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
00841                                    IEEE80211_TYP_FRAME_HEADER_LEN,
00842                                    AR5K_PKT_TYPE_NORMAL, sc->power_level * 2,
00843                                    sc->hw_rate, ATH5K_RETRIES,
00844                                    AR5K_TXKEYIX_INVALID, 0, flags,
00845                                    cts_rate, duration);
00846         if (ret)
00847                 return ret;
00848 
00849         ds->ds_link = 0;
00850         ds->ds_data = bf->iobaddr;
00851 
00852         list_add_tail(&bf->list, &txq->q);
00853         if (txq->link == NULL) /* is this first packet? */
00854                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
00855         else /* no, so only link it */
00856                 *txq->link = bf->daddr;
00857 
00858         txq->link = &ds->ds_link;
00859         ath5k_hw_start_tx_dma(ah, txq->qnum);
00860         mb();
00861 
00862         return 0;
00863 }
00864 
00865 /*******************\
00866 * Descriptors setup *
00867 \*******************/
00868 
00869 static int
00870 ath5k_desc_alloc(struct ath5k_softc *sc)
00871 {
00872         struct ath5k_desc *ds;
00873         struct ath5k_buf *bf;
00874         u32 da;
00875         unsigned int i;
00876         int ret;
00877 
00878         /* allocate descriptors */
00879         sc->desc_len = sizeof(struct ath5k_desc) * (ATH_TXBUF + ATH_RXBUF + 1);
00880         sc->desc = malloc_dma(sc->desc_len, ATH5K_DESC_ALIGN);
00881         if (sc->desc == NULL) {
00882                 DBG("ath5k: can't allocate descriptors\n");
00883                 ret = -ENOMEM;
00884                 goto err;
00885         }
00886         memset(sc->desc, 0, sc->desc_len);
00887         sc->desc_daddr = virt_to_bus(sc->desc);
00888 
00889         ds = sc->desc;
00890         da = sc->desc_daddr;
00891 
00892         bf = calloc(ATH_TXBUF + ATH_RXBUF + 1, sizeof(struct ath5k_buf));
00893         if (bf == NULL) {
00894                 DBG("ath5k: can't allocate buffer pointers\n");
00895                 ret = -ENOMEM;
00896                 goto err_free;
00897         }
00898         sc->bufptr = bf;
00899 
00900         INIT_LIST_HEAD(&sc->rxbuf);
00901         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
00902                 bf->desc = ds;
00903                 bf->daddr = da;
00904                 list_add_tail(&bf->list, &sc->rxbuf);
00905         }
00906 
00907         INIT_LIST_HEAD(&sc->txbuf);
00908         sc->txbuf_len = ATH_TXBUF;
00909         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
00910                 bf->desc = ds;
00911                 bf->daddr = da;
00912                 list_add_tail(&bf->list, &sc->txbuf);
00913         }
00914 
00915         return 0;
00916 
00917 err_free:
00918         free_dma(sc->desc, sc->desc_len);
00919 err:
00920         sc->desc = NULL;
00921         return ret;
00922 }
00923 
00924 static void
00925 ath5k_desc_free(struct ath5k_softc *sc)
00926 {
00927         struct ath5k_buf *bf;
00928 
00929         list_for_each_entry(bf, &sc->txbuf, list)
00930                 ath5k_txbuf_free(sc, bf);
00931         list_for_each_entry(bf, &sc->rxbuf, list)
00932                 ath5k_rxbuf_free(sc, bf);
00933 
00934         /* Free memory associated with all descriptors */
00935         free_dma(sc->desc, sc->desc_len);
00936 
00937         free(sc->bufptr);
00938         sc->bufptr = NULL;
00939 }
00940 
00941 
00942 
00943 
00944 
00945 /**************\
00946 * Queues setup *
00947 \**************/
00948 
00949 static int
00950 ath5k_txq_setup(struct ath5k_softc *sc, int qtype, int subtype)
00951 {
00952         struct ath5k_hw *ah = sc->ah;
00953         struct ath5k_txq *txq;
00954         struct ath5k_txq_info qi = {
00955                 .tqi_subtype = subtype,
00956                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
00957                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
00958                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
00959         };
00960         int qnum;
00961 
00962         /*
00963          * Enable interrupts only for EOL and DESC conditions.
00964          * We mark tx descriptors to receive a DESC interrupt
00965          * when a tx queue gets deep; otherwise waiting for the
00966          * EOL to reap descriptors.  Note that this is done to
00967          * reduce interrupt load and this only defers reaping
00968          * descriptors, never transmitting frames.  Aside from
00969          * reducing interrupts this also permits more concurrency.
00970          * The only potential downside is if the tx queue backs
00971          * up in which case the top half of the kernel may backup
00972          * due to a lack of tx descriptors.
00973          */
00974         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
00975                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
00976         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
00977         if (qnum < 0) {
00978                 DBG("ath5k: can't set up a TX queue\n");
00979                 return -EIO;
00980         }
00981 
00982         txq = &sc->txq;
00983         if (!txq->setup) {
00984                 txq->qnum = qnum;
00985                 txq->link = NULL;
00986                 INIT_LIST_HEAD(&txq->q);
00987                 txq->setup = 1;
00988         }
00989         return 0;
00990 }
00991 
00992 static void
00993 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
00994 {
00995         struct ath5k_buf *bf, *bf0;
00996 
00997         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
00998                 ath5k_txbuf_free(sc, bf);
00999 
01000                 list_del(&bf->list);
01001                 list_add_tail(&bf->list, &sc->txbuf);
01002                 sc->txbuf_len++;
01003         }
01004         txq->link = NULL;
01005 }
01006 
01007 /*
01008  * Drain the transmit queues and reclaim resources.
01009  */
01010 static void
01011 ath5k_txq_cleanup(struct ath5k_softc *sc)
01012 {
01013         struct ath5k_hw *ah = sc->ah;
01014 
01015         if (!(sc->status & ATH_STAT_INVALID)) {
01016                 /* don't touch the hardware if marked invalid */
01017                 if (sc->txq.setup) {
01018                         ath5k_hw_stop_tx_dma(ah, sc->txq.qnum);
01019                         DBG("ath5k: txq [%d] %x, link %p\n",
01020                             sc->txq.qnum,
01021                             ath5k_hw_get_txdp(ah, sc->txq.qnum),
01022                             sc->txq.link);
01023                 }
01024         }
01025 
01026         if (sc->txq.setup)
01027                 ath5k_txq_drainq(sc, &sc->txq);
01028 }
01029 
01030 static void
01031 ath5k_txq_release(struct ath5k_softc *sc)
01032 {
01033         if (sc->txq.setup) {
01034                 ath5k_hw_release_tx_queue(sc->ah);
01035                 sc->txq.setup = 0;
01036         }
01037 }
01038 
01039 
01040 
01041 
01042 /*************\
01043 * RX Handling *
01044 \*************/
01045 
01046 /*
01047  * Enable the receive h/w following a reset.
01048  */
01049 static int
01050 ath5k_rx_start(struct ath5k_softc *sc)
01051 {
01052         struct ath5k_hw *ah = sc->ah;
01053         struct ath5k_buf *bf;
01054         int ret;
01055 
01056         sc->rxbufsize = IEEE80211_MAX_LEN;
01057         if (sc->rxbufsize % sc->cachelsz != 0)
01058                 sc->rxbufsize += sc->cachelsz - (sc->rxbufsize % sc->cachelsz);
01059 
01060         sc->rxlink = NULL;
01061 
01062         list_for_each_entry(bf, &sc->rxbuf, list) {
01063                 ret = ath5k_rxbuf_setup(sc, bf);
01064                 if (ret != 0)
01065                         return ret;
01066         }
01067 
01068         bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
01069 
01070         ath5k_hw_set_rxdp(ah, bf->daddr);
01071         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
01072         ath5k_mode_setup(sc);           /* set filters, etc. */
01073         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
01074 
01075         return 0;
01076 }
01077 
01078 /*
01079  * Disable the receive h/w in preparation for a reset.
01080  */
01081 static void
01082 ath5k_rx_stop(struct ath5k_softc *sc)
01083 {
01084         struct ath5k_hw *ah = sc->ah;
01085 
01086         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
01087         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
01088         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
01089 
01090         sc->rxlink = NULL;              /* just in case */
01091 }
01092 
01093 static void
01094 ath5k_handle_rx(struct ath5k_softc *sc)
01095 {
01096         struct ath5k_rx_status rs;
01097         struct io_buffer *iob, *next_iob;
01098         u32 next_iob_addr;
01099         struct ath5k_buf *bf, *bf_last;
01100         struct ath5k_desc *ds;
01101         int ret;
01102 
01103         memset(&rs, 0, sizeof(rs));
01104 
01105         if (list_empty(&sc->rxbuf)) {
01106                 DBG("ath5k: empty rx buf pool\n");
01107                 return;
01108         }
01109 
01110         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
01111 
01112         do {
01113                 bf = list_entry(sc->rxbuf.next, struct ath5k_buf, list);
01114                 assert(bf->iob != NULL);
01115                 iob = bf->iob;
01116                 ds = bf->desc;
01117 
01118                 /*
01119                  * last buffer must not be freed to ensure proper hardware
01120                  * function. When the hardware finishes also a packet next to
01121                  * it, we are sure, it doesn't use it anymore and we can go on.
01122                  */
01123                 if (bf_last == bf)
01124                         bf->flags |= 1;
01125                 if (bf->flags) {
01126                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
01127                                         struct ath5k_buf, list);
01128                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
01129                                         &rs);
01130                         if (ret)
01131                                 break;
01132                         bf->flags &= ~1;
01133                         /* skip the overwritten one (even status is martian) */
01134                         goto next;
01135                 }
01136 
01137                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
01138                 if (ret) {
01139                         if (ret != -EINPROGRESS) {
01140                                 DBG("ath5k: error in processing rx desc: %s\n",
01141                                     strerror(ret));
01142                                 net80211_rx_err(sc->dev, NULL, -ret);
01143                         } else {
01144                                 /* normal return, reached end of
01145                                    available descriptors */
01146                         }
01147                         return;
01148                 }
01149 
01150                 if (rs.rs_more) {
01151                         DBG("ath5k: unsupported fragmented rx\n");
01152                         goto next;
01153                 }
01154 
01155                 if (rs.rs_status) {
01156                         if (rs.rs_status & AR5K_RXERR_PHY) {
01157                                 /* These are uncommon, and may indicate a real problem. */
01158                                 net80211_rx_err(sc->dev, NULL, EIO);
01159                                 goto next;
01160                         }
01161                         if (rs.rs_status & AR5K_RXERR_CRC) {
01162                                 /* These occur *all the time*. */
01163                                 goto next;
01164                         }
01165                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
01166                                 /*
01167                                  * Decrypt error.  If the error occurred
01168                                  * because there was no hardware key, then
01169                                  * let the frame through so the upper layers
01170                                  * can process it.  This is necessary for 5210
01171                                  * parts which have no way to setup a ``clear''
01172                                  * key cache entry.
01173                                  *
01174                                  * XXX do key cache faulting
01175                                  */
01176                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
01177                                     !(rs.rs_status & AR5K_RXERR_CRC))
01178                                         goto accept;
01179                         }
01180 
01181                         /* any other error, unhandled */
01182                         DBG("ath5k: packet rx status %x\n", rs.rs_status);
01183                         goto next;
01184                 }
01185 accept:
01186                 next_iob = ath5k_rx_iob_alloc(sc, &next_iob_addr);
01187 
01188                 /*
01189                  * If we can't replace bf->iob with a new iob under memory
01190                  * pressure, just skip this packet
01191                  */
01192                 if (!next_iob) {
01193                         DBG("ath5k: dropping packet under memory pressure\n");
01194                         goto next;
01195                 }
01196 
01197                 iob_put(iob, rs.rs_datalen);
01198 
01199                 /* The MAC header is padded to have 32-bit boundary if the
01200                  * packet payload is non-zero. However, iPXE only
01201                  * supports standard 802.11 packets with 24-byte
01202                  * header, so no padding correction should be needed.
01203                  */
01204 
01205                 DBG2("ath5k: rx %d bytes, signal %d\n", rs.rs_datalen,
01206                      rs.rs_rssi);
01207 
01208                 net80211_rx(sc->dev, iob, rs.rs_rssi,
01209                             ath5k_hw_rix_to_bitrate(rs.rs_rate));
01210 
01211                 bf->iob = next_iob;
01212                 bf->iobaddr = next_iob_addr;
01213 next:
01214                 list_del(&bf->list);
01215                 list_add_tail(&bf->list, &sc->rxbuf);
01216         } while (ath5k_rxbuf_setup(sc, bf) == 0);
01217 }
01218 
01219 
01220 
01221 
01222 /*************\
01223 * TX Handling *
01224 \*************/
01225 
01226 static void
01227 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
01228 {
01229         struct ath5k_tx_status ts;
01230         struct ath5k_buf *bf, *bf0;
01231         struct ath5k_desc *ds;
01232         struct io_buffer *iob;
01233         int ret;
01234 
01235         memset(&ts, 0, sizeof(ts));
01236 
01237         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
01238                 ds = bf->desc;
01239 
01240                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
01241                 if (ret) {
01242                         if (ret != -EINPROGRESS) {
01243                                 DBG("ath5k: error in processing tx desc: %s\n",
01244                                     strerror(ret));
01245                         } else {
01246                                 /* normal return, reached end of tx completions */
01247                         }
01248                         break;
01249                 }
01250 
01251                 iob = bf->iob;
01252                 bf->iob = NULL;
01253 
01254                 DBG2("ath5k: tx %zd bytes complete, %d retries\n",
01255                      iob_len(iob), ts.ts_retry[0]);
01256 
01257                 net80211_tx_complete(sc->dev, iob, ts.ts_retry[0],
01258                                      ts.ts_status ? EIO : 0);
01259 
01260                 list_del(&bf->list);
01261                 list_add_tail(&bf->list, &sc->txbuf);
01262                 sc->txbuf_len++;
01263         }
01264 
01265         if (list_empty(&txq->q))
01266                 txq->link = NULL;
01267 }
01268 
01269 static void
01270 ath5k_handle_tx(struct ath5k_softc *sc)
01271 {
01272         ath5k_tx_processq(sc, &sc->txq);
01273 }
01274 
01275 
01276 /********************\
01277 * Interrupt handling *
01278 \********************/
01279 
01280 static void
01281 ath5k_irq(struct net80211_device *dev, int enable)
01282 {
01283         struct ath5k_softc *sc = dev->priv;
01284         struct ath5k_hw *ah = sc->ah;
01285 
01286         sc->irq_ena = enable;
01287         ah->ah_ier = enable ? AR5K_IER_ENABLE : AR5K_IER_DISABLE;
01288 
01289         ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER);
01290         ath5k_hw_set_imr(ah, sc->imask);
01291 }
01292 
01293 static int
01294 ath5k_init(struct ath5k_softc *sc)
01295 {
01296         struct ath5k_hw *ah = sc->ah;
01297         int ret, i;
01298 
01299         /*
01300          * Stop anything previously setup.  This is safe
01301          * no matter this is the first time through or not.
01302          */
01303         ath5k_stop_hw(sc);
01304 
01305         /*
01306          * The basic interface to setting the hardware in a good
01307          * state is ``reset''.  On return the hardware is known to
01308          * be powered up and with interrupts disabled.  This must
01309          * be followed by initialization of the appropriate bits
01310          * and then setup of the interrupt mask.
01311          */
01312         sc->curchan = sc->dev->channels + sc->dev->channel;
01313         sc->curband = sc->curchan->band;
01314         sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
01315                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
01316                 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
01317         ret = ath5k_reset(sc, NULL);
01318         if (ret)
01319                 goto done;
01320 
01321         ath5k_rfkill_hw_start(ah);
01322 
01323         /*
01324          * Reset the key cache since some parts do not reset the
01325          * contents on initial power up or resume from suspend.
01326          */
01327         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
01328                 ath5k_hw_reset_key(ah, i);
01329 
01330         /* Set ack to be sent at low bit-rates */
01331         ath5k_hw_set_ack_bitrate_high(ah, 0);
01332 
01333         ret = 0;
01334 done:
01335         mb();
01336         return ret;
01337 }
01338 
01339 static int
01340 ath5k_stop_hw(struct ath5k_softc *sc)
01341 {
01342         struct ath5k_hw *ah = sc->ah;
01343 
01344         /*
01345          * Shutdown the hardware and driver:
01346          *    stop output from above
01347          *    disable interrupts
01348          *    turn off timers
01349          *    turn off the radio
01350          *    clear transmit machinery
01351          *    clear receive machinery
01352          *    drain and release tx queues
01353          *    reclaim beacon resources
01354          *    power down hardware
01355          *
01356          * Note that some of this work is not possible if the
01357          * hardware is gone (invalid).
01358          */
01359 
01360         if (!(sc->status & ATH_STAT_INVALID)) {
01361                 ath5k_hw_set_imr(ah, 0);
01362         }
01363         ath5k_txq_cleanup(sc);
01364         if (!(sc->status & ATH_STAT_INVALID)) {
01365                 ath5k_rx_stop(sc);
01366                 ath5k_hw_phy_disable(ah);
01367         } else
01368                 sc->rxlink = NULL;
01369 
01370         ath5k_rfkill_hw_stop(sc->ah);
01371 
01372         return 0;
01373 }
01374 
01375 static void
01376 ath5k_poll(struct net80211_device *dev)
01377 {
01378         struct ath5k_softc *sc = dev->priv;
01379         struct ath5k_hw *ah = sc->ah;
01380         enum ath5k_int status;
01381         unsigned int counter = 1000;
01382 
01383         if (currticks() - sc->last_calib_ticks >
01384             ATH5K_CALIB_INTERVAL * TICKS_PER_SEC) {
01385                 ath5k_calibrate(sc);
01386                 sc->last_calib_ticks = currticks();
01387         }
01388 
01389         if ((sc->status & ATH_STAT_INVALID) ||
01390             (sc->irq_ena && !ath5k_hw_is_intr_pending(ah)))
01391                 return;
01392 
01393         do {
01394                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
01395                 DBGP("ath5k: status %#x/%#x\n", status, sc->imask);
01396                 if (status & AR5K_INT_FATAL) {
01397                         /*
01398                          * Fatal errors are unrecoverable.
01399                          * Typically these are caused by DMA errors.
01400                          */
01401                         DBG("ath5k: fatal error, resetting\n");
01402                         ath5k_reset_wake(sc);
01403                 } else if (status & AR5K_INT_RXORN) {
01404                         DBG("ath5k: rx overrun, resetting\n");
01405                         ath5k_reset_wake(sc);
01406                 } else {
01407                         if (status & AR5K_INT_RXEOL) {
01408                                 /*
01409                                  * NB: the hardware should re-read the link when
01410                                  *     RXE bit is written, but it doesn't work at
01411                                  *     least on older hardware revs.
01412                                  */
01413                                 DBG("ath5k: rx EOL\n");
01414                                 sc->rxlink = NULL;
01415                         }
01416                         if (status & AR5K_INT_TXURN) {
01417                                 /* bump tx trigger level */
01418                                 DBG("ath5k: tx underrun\n");
01419                                 ath5k_hw_update_tx_triglevel(ah, 1);
01420                         }
01421                         if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
01422                                 ath5k_handle_rx(sc);
01423                         if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
01424                                       | AR5K_INT_TXERR | AR5K_INT_TXEOL))
01425                                 ath5k_handle_tx(sc);
01426                 }
01427         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
01428 
01429         if (!counter)
01430                 DBG("ath5k: too many interrupts, giving up for now\n");
01431 }
01432 
01433 /*
01434  * Periodically recalibrate the PHY to account
01435  * for temperature/environment changes.
01436  */
01437 static void
01438 ath5k_calibrate(struct ath5k_softc *sc)
01439 {
01440         struct ath5k_hw *ah = sc->ah;
01441 
01442         if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
01443                 /*
01444                  * Rfgain is out of bounds, reset the chip
01445                  * to load new gain values.
01446                  */
01447                 DBG("ath5k: resetting for calibration\n");
01448                 ath5k_reset_wake(sc);
01449         }
01450         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
01451                 DBG("ath5k: calibration of channel %d failed\n",
01452                     sc->curchan->channel_nr);
01453 }
01454 
01455 
01456 /********************\
01457 * Net80211 functions *
01458 \********************/
01459 
01460 static int
01461 ath5k_tx(struct net80211_device *dev, struct io_buffer *iob)
01462 {
01463         struct ath5k_softc *sc = dev->priv;
01464         struct ath5k_buf *bf;
01465         int rc;
01466 
01467         /*
01468          * The hardware expects the header padded to 4 byte boundaries.
01469          * iPXE only ever sends 24-byte headers, so no action necessary.
01470          */
01471 
01472         if (list_empty(&sc->txbuf)) {
01473                 DBG("ath5k: dropping packet because no tx bufs available\n");
01474                 return -ENOBUFS;
01475         }
01476 
01477         bf = list_entry(sc->txbuf.next, struct ath5k_buf, list);
01478         list_del(&bf->list);
01479         sc->txbuf_len--;
01480 
01481         bf->iob = iob;
01482 
01483         if ((rc = ath5k_txbuf_setup(sc, bf)) != 0) {
01484                 bf->iob = NULL;
01485                 list_add_tail(&bf->list, &sc->txbuf);
01486                 sc->txbuf_len++;
01487                 return rc;
01488         }
01489         return 0;
01490 }
01491 
01492 /*
01493  * Reset the hardware.  If chan is not NULL, then also pause rx/tx
01494  * and change to the given channel.
01495  */
01496 static int
01497 ath5k_reset(struct ath5k_softc *sc, struct net80211_channel *chan)
01498 {
01499         struct ath5k_hw *ah = sc->ah;
01500         int ret;
01501 
01502         if (chan) {
01503                 ath5k_hw_set_imr(ah, 0);
01504                 ath5k_txq_cleanup(sc);
01505                 ath5k_rx_stop(sc);
01506 
01507                 sc->curchan = chan;
01508                 sc->curband = chan->band;
01509         }
01510 
01511         ret = ath5k_hw_reset(ah, sc->curchan, 1);
01512         if (ret) {
01513                 DBG("ath5k: can't reset hardware: %s\n", strerror(ret));
01514                 return ret;
01515         }
01516 
01517         ret = ath5k_rx_start(sc);
01518         if (ret) {
01519                 DBG("ath5k: can't start rx logic: %s\n", strerror(ret));
01520                 return ret;
01521         }
01522 
01523         /*
01524          * Change channels and update the h/w rate map if we're switching;
01525          * e.g. 11a to 11b/g.
01526          *
01527          * We may be doing a reset in response to an ioctl that changes the
01528          * channel so update any state that might change as a result.
01529          *
01530          * XXX needed?
01531          */
01532 /*      ath5k_chan_change(sc, c); */
01533 
01534         /* Reenable interrupts if necessary */
01535         ath5k_irq(sc->dev, sc->irq_ena);
01536 
01537         return 0;
01538 }
01539 
01540 static int ath5k_reset_wake(struct ath5k_softc *sc)
01541 {
01542         return ath5k_reset(sc, sc->curchan);
01543 }
01544 
01545 static int ath5k_start(struct net80211_device *dev)
01546 {
01547         struct ath5k_softc *sc = dev->priv;
01548         int ret;
01549 
01550         if ((ret = ath5k_init(sc)) != 0)
01551                 return ret;
01552 
01553         sc->assoc = 0;
01554         ath5k_configure_filter(sc);
01555         ath5k_hw_set_lladdr(sc->ah, dev->netdev->ll_addr);
01556 
01557         return 0;
01558 }
01559 
01560 static void ath5k_stop(struct net80211_device *dev)
01561 {
01562         struct ath5k_softc *sc = dev->priv;
01563         u8 mac[ETH_ALEN] = {};
01564 
01565         ath5k_hw_set_lladdr(sc->ah, mac);
01566 
01567         ath5k_stop_hw(sc);
01568 }
01569 
01570 static int
01571 ath5k_config(struct net80211_device *dev, int changed)
01572 {
01573         struct ath5k_softc *sc = dev->priv;
01574         struct ath5k_hw *ah = sc->ah;
01575         struct net80211_channel *chan = &dev->channels[dev->channel];
01576         int ret;
01577 
01578         if (changed & NET80211_CFG_CHANNEL) {
01579                 sc->power_level = chan->maxpower;
01580                 if ((ret = ath5k_chan_set(sc, chan)) != 0)
01581                         return ret;
01582         }
01583 
01584         if ((changed & NET80211_CFG_RATE) ||
01585             (changed & NET80211_CFG_PHY_PARAMS)) {
01586                 int spmbl = ATH5K_SPMBL_NO;
01587                 u16 rate = dev->rates[dev->rate];
01588                 u16 slowrate = dev->rates[dev->rtscts_rate];
01589                 int i;
01590 
01591                 if (dev->phy_flags & NET80211_PHY_USE_SHORT_PREAMBLE)
01592                         spmbl = ATH5K_SPMBL_YES;
01593 
01594                 for (i = 0; i < ATH5K_NR_RATES; i++) {
01595                         if (ath5k_rates[i].bitrate == rate &&
01596                             (ath5k_rates[i].short_pmbl & spmbl))
01597                                 sc->hw_rate = ath5k_rates[i].hw_code;
01598 
01599                         if (ath5k_rates[i].bitrate == slowrate &&
01600                             (ath5k_rates[i].short_pmbl & spmbl))
01601                                 sc->hw_rtscts_rate = ath5k_rates[i].hw_code;
01602                 }
01603         }
01604 
01605         if (changed & NET80211_CFG_ASSOC) {
01606                 sc->assoc = !!(dev->state & NET80211_ASSOCIATED);
01607                 if (sc->assoc) {
01608                         memcpy(ah->ah_bssid, dev->bssid, ETH_ALEN);
01609                 } else {
01610                         memset(ah->ah_bssid, 0xff, ETH_ALEN);
01611                 }
01612                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
01613         }
01614 
01615         return 0;
01616 }
01617 
01618 /*
01619  * o always accept unicast, broadcast, and multicast traffic
01620  * o multicast traffic for all BSSIDs will be enabled if mac80211
01621  *   says it should be
01622  * o maintain current state of phy ofdm or phy cck error reception.
01623  *   If the hardware detects any of these type of errors then
01624  *   ath5k_hw_get_rx_filter() will pass to us the respective
01625  *   hardware filters to be able to receive these type of frames.
01626  * o probe request frames are accepted only when operating in
01627  *   hostap, adhoc, or monitor modes
01628  * o enable promiscuous mode according to the interface state
01629  * o accept beacons:
01630  *   - when operating in adhoc mode so the 802.11 layer creates
01631  *     node table entries for peers,
01632  *   - when operating in station mode for collecting rssi data when
01633  *     the station is otherwise quiet, or
01634  *   - when scanning
01635  */
01636 static void ath5k_configure_filter(struct ath5k_softc *sc)
01637 {
01638         struct ath5k_hw *ah = sc->ah;
01639         u32 mfilt[2], rfilt;
01640 
01641         /* Enable all multicast */
01642         mfilt[0] = ~0;
01643         mfilt[1] = ~0;
01644 
01645         /* Enable data frames and beacons */
01646         rfilt = (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
01647                  AR5K_RX_FILTER_MCAST | AR5K_RX_FILTER_BEACON);
01648 
01649         /* Set filters */
01650         ath5k_hw_set_rx_filter(ah, rfilt);
01651 
01652         /* Set multicast bits */
01653         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
01654 
01655         /* Set the cached hw filter flags, this will alter actually
01656          * be set in HW */
01657         sc->filter_flags = rfilt;
01658 }