iPXE
bnxt_dbg.h
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1 /*
2  * Copyright © 2018 Broadcom. All Rights Reserved.
3  * The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.
4 
5  * This program is free software; you can redistribute it and/or modify it under
6  * the terms of version 2 of the GNU General Public License as published by the
7  * Free Software Foundation.
8 
9  * This program is distributed in the hope that it will be useful.
10  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING
11  * ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
12  * NON-INFRINGEMENT, ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS
13  * ARE HELD TO BE LEGALLY INVALID. See the GNU General Public License for more
14  * details, a copy of which can be found in the file COPYING included with this
15  * package.
16  */
17 
18 //#define DEBUG_DRV
19 //#define DEBUG_KEY
20 //#define DEBUG_PCI
21 //#define DEBUG_MEMORY
22 //#define DEBUG_LINK
23 //#define DEBUG_CHIP
24 //#define DEBUG_FAIL
25 //#define DEBUG_HWRM_CMDS
26 //#define DEBUG_HWRM_DUMP
27 //#define DEBUG_CQ
28 //#define DEBUG_CQ_DUMP
29 //#define DEBUG_TX
30 //#define DEBUG_TX_DUMP
31 //#define DEBUG_RX
32 //#define DEBUG_RX_DUMP
33 
34 #if \
35  defined(DEBUG_DRV) || \
36  defined(DEBUG_PCI) || \
37  defined(DEBUG_CHIP) || \
38  defined(DEBUG_MEMORY) || \
39  defined(DEBUG_LINK) || \
40  defined(DEBUG_FAIL) || \
41  defined(DEBUG_HWRM_CMDS) || \
42  defined(DEBUG_HWRM_DUMP) || \
43  defined(DEBUG_CQ) || \
44  defined(DEBUG_CQ_DUMP) || \
45  defined(DEBUG_TX) || \
46  defined(DEBUG_TX_DUMP) || \
47  defined(DEBUG_RX) || \
48  defined(DEBUG_RX_DUMP)
49 #define DEBUG_DEFAULT
50 #endif
51 #if defined(DEBUG_DEFAULT)
52 #define dbg_prn printf
53 
54 void pause_drv(void)
55 {
56 #if defined(DEBUG_KEY)
57  dbg_prn(" Press a key...");
58  getchar();
59 #endif
60  dbg_prn("\n");
61 }
62 
63 #define MAX_CHAR_SIZE(a) (u32)((1 << (a)) - 1)
64 #define DISP_U8 0x00
65 #define DISP_U16 0x01
66 #define DISP_U32 0x02
67 #define DISP_U64 0x03
68 
69 void dumpmemory1(u8 *buffer, u32 length, u8 flag)
70 {
71  u32 jj = 0;
72  u8 i, c;
73 
74  dbg_prn("\n %p:", buffer);
75  for (jj = 0; jj < 16; jj++) {
76  if (!(jj & MAX_CHAR_SIZE(flag)))
77  dbg_prn(" ");
78  if (jj < length)
79  dbg_prn("%02x", buffer[jj]);
80  else
81  dbg_prn(" ");
82  if ((jj & 0xF) == 0xF) {
83  dbg_prn(" ");
84  for (i = 0; i < 16; i++) {
85  if (i < length) {
86  c = buffer[jj + i - 15];
87  if (c >= 0x20 && c < 0x7F)
88  ;
89  else
90  c = '.';
91  dbg_prn("%c", c);
92  }
93  }
94  }
95  }
96 }
97 
98 void dump_mem(u8 *buffer, u32 length, u8 flag)
99 {
100  u32 length16, remlen, jj;
101 
102  length16 = length & 0xFFFFFFF0;
103  remlen = length & 0xF;
104  for (jj = 0; jj < length16; jj += 16)
105  dumpmemory1((u8 *)&buffer[jj], 16, flag);
106  if (remlen)
107  dumpmemory1((u8 *)&buffer[length16], remlen, flag);
108  if (length16 || remlen)
109  dbg_prn("\n");
110 }
111 #else
112 #define dbg_prn(func)
113 #endif
114 
115 #if defined(DEBUG_PCI)
116 void dbg_pci(struct bnxt *bp, const char *func, u16 cmd_reg)
117 {
118  struct pci_device *pdev = bp->pdev;
119 
120  dbg_prn("- %s()\n", func);
121  dbg_prn(" Bus:Dev:Func : %04X\n", pdev->busdevfn);
122  dbg_prn(" Vendor id : %04X\n", pdev->vendor);
123  dbg_prn(" Device id : %04X (%cF)\n",
124  pdev->device, (bp->vf) ? 'V' : 'P');
125  dbg_prn(" Irq : %d\n", pdev->irq);
126  dbg_prn(" PCI Command Reg : %04X\n", cmd_reg);
127  dbg_prn(" Sub Vendor id : %04X\n", bp->subsystem_vendor);
128  dbg_prn(" Sub Device id : %04X\n", bp->subsystem_device);
129  dbg_prn(" PF Number : %X\n", bp->pf_num);
130  dbg_prn(" BAR (0) : %p %lx\n",
131  bp->bar0, pci_bar_start(pdev, PCI_BASE_ADDRESS_0));
132  dbg_prn(" BAR (1) : %p %lx\n",
133  bp->bar1, pci_bar_start(pdev, PCI_BASE_ADDRESS_2));
134  dbg_prn(" BAR (2) : %p %lx\n",
135  bp->bar2, pci_bar_start(pdev, PCI_BASE_ADDRESS_4));
136  dbg_prn(" ");
137  pause_drv();
138 }
139 #else
140 #define dbg_pci(bp, func, creg)
141 #endif
142 
143 #if defined(DEBUG_MEMORY)
144 void dbg_mem(struct bnxt *bp, const char *func)
145 {
146  dbg_prn("- %s()\n", func);
147  dbg_prn(" bp Addr : %p", bp);
148  dbg_prn(" Len %4d", (u16)sizeof(struct bnxt));
149  dbg_prn(" phy %lx\n", virt_to_bus(bp));
150  dbg_prn(" bp->hwrm_req_addr : %p", bp->hwrm_addr_req);
151  dbg_prn(" Len %4d", (u16)REQ_BUFFER_SIZE);
152  dbg_prn(" phy %lx\n", bp->req_addr_mapping);
153  dbg_prn(" bp->hwrm_resp_addr : %p", bp->hwrm_addr_resp);
154  dbg_prn(" Len %4d", (u16)RESP_BUFFER_SIZE);
155  dbg_prn(" phy %lx\n", bp->resp_addr_mapping);
156  dbg_prn(" bp->dma_addr : %p", bp->hwrm_addr_dma);
157  dbg_prn(" Len %4d", (u16)DMA_BUFFER_SIZE);
158  dbg_prn(" phy %lx\n", bp->dma_addr_mapping);
159  dbg_prn(" bp->tx.bd_virt : %p", bp->tx.bd_virt);
160  dbg_prn(" Len %4d", (u16)TX_RING_BUFFER_SIZE);
161  dbg_prn(" phy %lx\n", virt_to_bus(bp->tx.bd_virt));
162  dbg_prn(" bp->rx.bd_virt : %p", bp->rx.bd_virt);
163  dbg_prn(" Len %4d", (u16)RX_RING_BUFFER_SIZE);
164  dbg_prn(" phy %lx\n", virt_to_bus(bp->rx.bd_virt));
165  dbg_prn(" bp->cq.bd_virt : %p", bp->cq.bd_virt);
166  dbg_prn(" Len %4d", (u16)CQ_RING_BUFFER_SIZE);
167  dbg_prn(" phy %lx\n", virt_to_bus(bp->cq.bd_virt));
168  dbg_prn(" bp->nq.bd_virt : %p", bp->nq.bd_virt);
169  dbg_prn(" Len %4d", (u16)NQ_RING_BUFFER_SIZE);
170  dbg_prn(" phy %lx\n", virt_to_bus(bp->nq.bd_virt));
171  dbg_prn(" ");
172  pause_drv();
173 }
174 #else
175 #define dbg_mem(bp, func) (func = func)
176 #endif
177 
178 #if defined(DEBUG_CHIP)
179 void dbg_fw_ver(struct hwrm_ver_get_output *resp, u32 tmo)
180 {
181  if (resp->hwrm_intf_maj_8b < 1) {
182  dbg_prn(" HWRM interface %d.%d.%d is older than 1.0.0.\n",
183  resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
184  resp->hwrm_intf_upd_8b);
185  dbg_prn(" Update FW with HWRM interface 1.0.0 or newer.\n");
186  }
187  dbg_prn(" FW Version : %d.%d.%d.%d\n",
188  resp->hwrm_fw_maj_8b, resp->hwrm_fw_min_8b,
189  resp->hwrm_fw_bld_8b, resp->hwrm_fw_rsvd_8b);
190  dbg_prn(" cmd timeout : %d\n", tmo);
191  if (resp->hwrm_intf_maj_8b >= 1)
192  dbg_prn(" hwrm_max_req_len : %d\n", resp->max_req_win_len);
193  dbg_prn(" hwrm_max_ext_req : %d\n", resp->max_ext_req_len);
194  dbg_prn(" chip_num : %x\n", resp->chip_num);
195  dbg_prn(" chip_id : %x\n",
196  (u32)(resp->chip_rev << 24) |
197  (u32)(resp->chip_metal << 16) |
198  (u32)(resp->chip_bond_id << 8) |
199  (u32)resp->chip_platform_type);
200  if((resp->dev_caps_cfg & SHORT_CMD_SUPPORTED) &&
202  dbg_prn(" SHORT_CMD_SUPPORTED\n");
203 }
204 
205 void dbg_func_resource_qcaps(struct bnxt *bp)
206 {
207 // Ring Groups
208  dbg_prn(" min_hw_ring_grps : %d\n", bp->min_hw_ring_grps);
209  dbg_prn(" max_hw_ring_grps : %d\n", bp->max_hw_ring_grps);
210 // TX Rings
211  dbg_prn(" min_tx_rings : %d\n", bp->min_tx_rings);
212  dbg_prn(" max_tx_rings : %d\n", bp->max_tx_rings);
213 // RX Rings
214  dbg_prn(" min_rx_rings : %d\n", bp->min_rx_rings);
215  dbg_prn(" max_rx_rings : %d\n", bp->max_rx_rings);
216 // Completion Rings
217  dbg_prn(" min_cq_rings : %d\n", bp->min_cp_rings);
218  dbg_prn(" max_cq_rings : %d\n", bp->max_cp_rings);
219 // Statistic Contexts
220  dbg_prn(" min_stat_ctxs : %d\n", bp->min_stat_ctxs);
221  dbg_prn(" max_stat_ctxs : %d\n", bp->max_stat_ctxs);
222 }
223 
224 void dbg_func_qcaps(struct bnxt *bp)
225 {
226  dbg_prn(" Port Number : %d\n", bp->port_idx);
227  dbg_prn(" fid : 0x%04x\n", bp->fid);
228  dbg_prn(" PF MAC : %02x:%02x:%02x:%02x:%02x:%02x\n",
229  bp->mac_addr[0],
230  bp->mac_addr[1],
231  bp->mac_addr[2],
232  bp->mac_addr[3],
233  bp->mac_addr[4],
234  bp->mac_addr[5]);
235 }
236 
237 void dbg_func_qcfg(struct bnxt *bp)
238 {
239  dbg_prn(" ordinal_value : %d\n", bp->ordinal_value);
240  dbg_prn(" stat_ctx_id : %x\n", bp->stat_ctx_id);
241  if (bp->vf) {
243  dbg_prn(" vlan_id : %d\n", bp->vlan_id);
244  }
245 }
246 
247 void prn_set_speed(u32 speed)
248 {
249  u32 speed1 = ((speed & LINK_SPEED_DRV_MASK) >> LINK_SPEED_DRV_SHIFT);
250 
251  dbg_prn(" Set Link Speed : ");
252  switch (speed & LINK_SPEED_DRV_MASK) {
253  case LINK_SPEED_DRV_1G:
254  dbg_prn("1 GBPS");
255  break;
256  case LINK_SPEED_DRV_10G:
257  dbg_prn("10 GBPS");
258  break;
259  case LINK_SPEED_DRV_25G:
260  dbg_prn("25 GBPS");
261  break;
262  case LINK_SPEED_DRV_40G:
263  dbg_prn("40 GBPS");
264  break;
265  case LINK_SPEED_DRV_50G:
266  dbg_prn("50 GBPS");
267  break;
268  case LINK_SPEED_DRV_100G:
269  dbg_prn("100 GBPS");
270  break;
271  case LINK_SPEED_DRV_200G:
272  dbg_prn("200 GBPS");
273  break;
275  dbg_prn("AUTONEG");
276  break;
277  default:
278  dbg_prn("%x", speed1);
279  break;
280  }
281  dbg_prn("\n");
282 }
283 
284 void dbg_chip_info(struct bnxt *bp)
285 {
286  if (bp->thor)
287  dbg_prn(" NQ Ring Id : %d\n", bp->nq_ring_id);
288  else
289  dbg_prn(" Grp ID : %d\n", bp->ring_grp_id);
290  dbg_prn(" Stat Ctx ID : %d\n", bp->stat_ctx_id);
291  dbg_prn(" CQ Ring Id : %d\n", bp->cq_ring_id);
292  dbg_prn(" Tx Ring Id : %d\n", bp->tx_ring_id);
293  dbg_prn(" Rx ring Id : %d\n", bp->rx_ring_id);
294  dbg_prn(" ");
295  pause_drv();
296 }
297 
298 void dbg_num_rings(struct bnxt *bp)
299 {
300  dbg_prn(" num_cmpl_rings : %d\n", bp->num_cmpl_rings);
301  dbg_prn(" num_tx_rings : %d\n", bp->num_tx_rings);
302  dbg_prn(" num_rx_rings : %d\n", bp->num_rx_rings);
303  dbg_prn(" num_ring_grps : %d\n", bp->num_hw_ring_grps);
304  dbg_prn(" num_stat_ctxs : %d\n", bp->num_stat_ctxs);
305 }
306 
307 void dbg_flags(const char *func, u32 flags)
308 {
309  dbg_prn("- %s()\n", func);
310  dbg_prn(" bp->flags : 0x%04x\n", flags);
311 }
312 
313 void dbg_bnxt_pause(void)
314 {
315  dbg_prn(" ");
316  pause_drv();
317 }
318 #else
319 #define dbg_fw_ver(resp, tmo)
320 #define dbg_func_resource_qcaps(bp)
321 #define dbg_func_qcaps(bp)
322 #define dbg_func_qcfg(bp)
323 #define prn_set_speed(speed)
324 #define dbg_chip_info(bp)
325 #define dbg_num_rings(bp)
326 #define dbg_flags(func, flags)
327 #define dbg_bnxt_pause()
328 #endif
329 
330 #if defined(DEBUG_HWRM_CMDS) || defined(DEBUG_FAIL)
331 void dump_hwrm_req(struct bnxt *bp, const char *func, u32 len, u32 tmo)
332 {
333  dbg_prn("- %s(0x%04x) cmd_len %d cmd_tmo %d",
334  func, (u16)((struct input *)bp->hwrm_addr_req)->req_type,
335  len, tmo);
336 #if defined(DEBUG_HWRM_DUMP)
337  dump_mem((u8 *)bp->hwrm_addr_req, len, DISP_U8);
338 #else
339  dbg_prn("\n");
340 #endif
341 }
342 
343 void debug_resp(struct bnxt *bp, const char *func, u32 resp_len, u16 err)
344 {
345  dbg_prn("- %s(0x%04x) - ",
346  func, (u16)((struct input *)bp->hwrm_addr_req)->req_type);
347  if (err == STATUS_SUCCESS)
348  dbg_prn("Done");
349  else if (err != STATUS_TIMEOUT)
350  dbg_prn("Fail err 0x%04x", err);
351  else
352  dbg_prn("timedout");
353 #if defined(DEBUG_HWRM_DUMP)
354  if (err != STATUS_TIMEOUT) {
355  dump_mem((u8 *)bp->hwrm_addr_resp, resp_len, DISP_U8);
356  sleep(1);
357  } else
358  dbg_prn("\n");
359 #else
360  resp_len = resp_len;
361  dbg_prn("\n");
362 #endif
363 }
364 
365 void dbg_hw_cmd(struct bnxt *bp,
366  const char *func, u16 cmd_len,
367  u16 resp_len, u32 cmd_tmo, u16 err)
368 {
369 #if !defined(DEBUG_HWRM_CMDS)
370  if (err)
371 #endif
372  {
373  dump_hwrm_req(bp, func, cmd_len, cmd_tmo);
374  debug_resp(bp, func, resp_len, err);
375  }
376 }
377 #else
378 #define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err) (func = func)
379 #endif
380 
381 #if defined(DEBUG_HWRM_CMDS)
382 void dbg_short_cmd(u8 *req, const char *func, u32 len)
383 {
384  struct hwrm_short_input *sreq;
385 
386  sreq = (struct hwrm_short_input *)req;
387  dbg_prn("- %s(0x%04x) short_cmd_len %d",
388  func,
389  sreq->req_type,
390  (int)len);
391 #if defined(DEBUG_HWRM_DUMP)
392  dump_mem((u8 *)sreq, len, DISP_U8);
393 #else
394  dbg_prn("\n");
395 #endif
396 }
397 #else
398 #define dbg_short_cmd(sreq, func, len)
399 #endif
400 
401 #if defined(DEBUG_RX)
402 void dump_rx_bd(struct rx_pkt_cmpl *rx_cmp,
403  struct rx_pkt_cmpl_hi *rx_cmp_hi,
404  u32 desc_idx)
405 {
406  dbg_prn(" RX desc_idx %d PktLen %d\n", desc_idx, rx_cmp->len);
407  dbg_prn("- rx_cmp %lx", virt_to_bus(rx_cmp));
408 #if defined(DEBUG_RX_DUMP)
409  dump_mem((u8 *)rx_cmp, (u32)sizeof(struct rx_pkt_cmpl), DISP_U8);
410 #else
411  dbg_prn("\n");
412 #endif
413  dbg_prn("- rx_cmp_hi %lx", virt_to_bus(rx_cmp_hi));
414 #if defined(DEBUG_RX_DUMP)
415  dump_mem((u8 *)rx_cmp_hi, (u32)sizeof(struct rx_pkt_cmpl_hi), DISP_U8);
416 #else
417  dbg_prn("\n");
418 #endif
419 }
420 
421 void dbg_alloc_rx_iob(struct io_buffer *iob, u16 id, u16 cid)
422 {
423  dbg_prn(" Rx alloc_iob (%d) %p bd_virt (%d)\n",
424  id, iob->data, cid);
425 }
426 
427 void dbg_rx_cid(u16 idx, u16 cid)
428 {
429  dbg_prn("- RX old cid %d new cid %d\n", idx, cid);
430 }
431 
432 void dbg_alloc_rx_iob_fail(u16 iob_idx, u16 cons_id)
433 {
434  dbg_prn(" Rx alloc_iob (%d) ", iob_idx);
435  dbg_prn("failed for cons_id %d\n", cons_id);
436 }
437 
438 void dbg_rxp(u8 *iob, u16 rx_len, u8 drop)
439 {
440  dbg_prn("- RX iob %lx Len %d ", virt_to_bus(iob), rx_len);
441  if (drop == 1)
442  dbg_prn("drop ErrPkt ");
443  else if (drop == 2)
444  dbg_prn("drop LoopBack ");
445  else if (drop == 3)
446  dbg_prn("drop VLAN");
447 #if defined(DEBUG_RX_DUMP)
448  dump_mem(iob, (u32)rx_len, DISP_U8);
449 #else
450  dbg_prn("\n");
451 #endif
452 }
453 
454 void dbg_rx_stat(struct bnxt *bp)
455 {
456  dbg_prn("- RX Stat Total %d Good %d Drop err %d LB %d\n",
457  bp->rx.cnt, bp->rx.good,
458  bp->rx.drop_err, bp->rx.drop_lb);
459 }
460 #else
461 #define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
462 #define dbg_alloc_rx_iob(iob, id, cid)
463 #define dbg_rx_cid(idx, cid)
464 #define dbg_alloc_rx_iob_fail(iob_idx, cons_id)
465 #define dbg_rxp(iob, rx_len, drop)
466 #define dbg_rx_stat(bp)
467 #endif
468 
469 #if defined(DEBUG_CQ)
470 static void dump_cq(struct cmpl_base *cmp, u16 cid, u8 toggle)
471 {
472  dbg_prn("- CQ Type ");
473  switch (cmp->type & CMPL_BASE_TYPE_MASK) {
475  dbg_prn("(ae)");
476  break;
478  dbg_prn("(se)");
479  break;
481  dbg_prn("(tx)");
482  break;
484  dbg_prn("(rx)");
485  break;
486  default:
487  dbg_prn("%04x", (u16)(cmp->type & CMPL_BASE_TYPE_MASK));
488  break;
489  }
490  dbg_prn(" cid %d, tog %d", cid, toggle);
491 #if defined(DEBUG_CQ_DUMP)
492  dump_mem((u8 *)cmp, (u32)sizeof(struct cmpl_base), DISP_U8);
493 #else
494  dbg_prn("\n");
495 #endif
496 }
497 
498 static void dump_nq(struct nq_base *nqp, u16 cid)
499 {
500  dbg_prn("- NQ Type %lx cid %d", (nqp->type & NQ_CN_TYPE_MASK), cid);
501 #if defined(DEBUG_CQ_DUMP)
502  dump_mem((u8 *)nqp, (u32)sizeof(struct nq_base), DISP_U8);
503 #else
504  dbg_prn("\n");
505 #endif
506 }
507 #else
508 #define dump_cq(cq, id, toggle)
509 #define dump_nq(nq, id)
510 #endif
511 
512 #if defined(DEBUG_TX)
513 void dbg_tx_avail(struct bnxt *bp, u32 avail, u16 use)
514 {
515  dbg_prn("- Tx BD %d Avail %d Use %d pid %d cid %d\n",
516  bp->tx.ring_cnt,
517  avail, use,
518  bp->tx.prod_id,
519  bp->tx.cons_id);
520 }
521 
522 void dbg_tx_vlan(struct bnxt *bp, char *src, u16 plen, u16 len)
523 {
524  dbg_prn("- Tx VLAN PKT %d MBA %d", bp->vlan_tx, bp->vlan_id);
525  dbg_prn(" PKT %d",
526  BYTE_SWAP_S(*(u16 *)(&src[MAC_HDR_SIZE + 2])));
527  dbg_prn(" Pro %x",
528  BYTE_SWAP_S(*(u16 *)(&src[MAC_HDR_SIZE])));
529  dbg_prn(" old len %d new len %d\n", plen, len);
530 }
531 
532 void dump_tx_stat(struct bnxt *bp)
533 {
534  dbg_prn(" TX stats cnt %d req_cnt %d", bp->tx.cnt, bp->tx.cnt_req);
535  dbg_prn(" prod_id %d cons_id %d\n", bp->tx.prod_id, bp->tx.cons_id);
536 }
537 
538 void dump_tx_pkt(u8 *pkt, u16 len, u16 idx)
539 {
540  dbg_prn(" TX(%d) Addr %lx Size %d", idx, virt_to_bus(pkt), len);
541 #if defined(DEBUG_TX_DUMP)
542  dump_mem(pkt, (u32)len, DISP_U8);
543 #else
544  dbg_prn("\n");
545 #endif
546 }
547 
548 void dump_tx_bd(struct tx_bd_short *tx_bd, u16 len, int idx)
549 {
550  dbg_prn(" Tx(%d) BD Addr %lx Size %d", idx, virt_to_bus(tx_bd), len);
551 #if defined(DEBUG_TX_DUMP)
552  dump_mem((u8 *)tx_bd, (u32)len, DISP_U8);
553 #else
554  dbg_prn("\n");
555 #endif
556 }
557 
558 void dbg_tx_done(u8 *pkt, u16 len, u16 idx)
559 {
560  dbg_prn(" Tx(%d) Done pkt %lx Size %d\n", idx, virt_to_bus(pkt), len);
561 }
562 #else
563 #define dbg_tx_avail(bp, a, u)
564 #define dbg_tx_vlan(bp, src, plen, len)
565 #define dbg_tx_pad(plen, len)
566 #define dump_tx_stat(bp)
567 #define dump_tx_pkt(pkt, len, idx)
568 #define dump_tx_bd(prod_bd, len, idx)
569 #define dbg_tx_done(pkt, len, idx)
570 #endif
571 
572 #if defined(DEBUG_LINK)
573 static void dump_evt(u8 *cmp, u32 type, u16 cid, u8 ring)
574 {
575  u32 size;
576  u8 c;
577 
578  if (ring) {
579  c = 'N';
580  size = sizeof(struct nq_base);
581  } else {
582  c = 'C';
583  size = sizeof(struct cmpl_base);
584  }
585  switch (type) {
587  break;
588  default:
589  return;
590  }
591  dbg_prn("- %cQ Type (ae) cid %d", c, cid);
592  dump_mem(cmp, size, DISP_U8);
593 }
594 
595 void dbg_link_info(struct bnxt *bp)
596 {
597  dbg_prn(" Current Speed : ");
598  switch (bp->current_link_speed) {
600  dbg_prn("200 %s", str_gbps);
601  break;
603  dbg_prn("100 %s", str_gbps);
604  break;
606  dbg_prn("50 %s", str_gbps);
607  break;
609  dbg_prn("40 %s", str_gbps);
610  break;
612  dbg_prn("25 %s", str_gbps);
613  break;
615  dbg_prn("20 %s", str_gbps);
616  break;
618  dbg_prn("10 %s", str_gbps);
619  break;
621  dbg_prn("2.5 %s", str_gbps);
622  break;
624  dbg_prn("2 %s", str_gbps);
625  break;
627  dbg_prn("1 %s", str_gbps);
628  break;
630  dbg_prn("100 %s", str_mbps);
631  break;
633  dbg_prn("10 %s", str_mbps);
634  break;
635  default:
636  dbg_prn("%x", bp->current_link_speed);
637  }
638  dbg_prn("\n");
639  dbg_prn(" media_detect : %x\n", bp->media_detect);
640 }
641 
642 void dbg_link_status(struct bnxt *bp)
643 {
644  dbg_prn(" Port(%d) : Link", bp->port_idx);
645  if (bp->link_status == STATUS_LINK_ACTIVE)
646  dbg_prn("Up");
647  else
648  dbg_prn("Down");
649  dbg_prn("\n");
650 }
651 
652 void dbg_link_state(struct bnxt *bp, u32 tmo)
653 {
655  dbg_link_info(bp);
656  dbg_prn(" Link wait time : %d ms", tmo);
657  pause_drv();
658 }
659 #else
660 #define dump_evt(cq, ty, id, ring)
661 #define dbg_link_status(bp)
662 #define dbg_link_info(bp)
663 #define dbg_link_state(bp, tmo)
664 #endif
#define dump_evt(cq, ty, id, ring)
Definition: bnxt_dbg.h:660
#define dbg_tx_avail(bp, a, u)
Definition: bnxt_dbg.h:563
uint16_t u16
Definition: stdint.h:21
#define str_mbps
Definition: bnxt.h:214
u16 length
Definition: sky2.h:9
uint8_t irq
Interrupt number.
Definition: pci.h:233
#define STATUS_SUCCESS
Definition: bnxt.h:55
#define MAC_HDR_SIZE
Definition: bnxt.h:189
#define dbg_flags(func, flags)
Definition: bnxt_dbg.h:326
#define SHORT_CMD_SUPPORTED
Definition: bnxt.h:1064
#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err)
Definition: bnxt_dbg.h:378
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
Definition: bnxt_hsi.h:3274
#define dbg_alloc_rx_iob(iob, id, cid)
Definition: bnxt_dbg.h:462
#define dbg_func_resource_qcaps(bp)
Definition: bnxt_dbg.h:320
#define RESP_BUFFER_SIZE
Definition: bnxt.h:157
#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
Definition: bnxt_hsi.h:3273
#define dbg_short_cmd(sreq, func, len)
Definition: bnxt_dbg.h:398
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
Definition: bnxt_hsi.h:3275
#define dbg_rxp(iob, rx_len, drop)
Definition: bnxt_dbg.h:465
#define LINK_SPEED_DRV_AUTONEG
Definition: bnxt.h:223
#define NQ_RING_BUFFER_SIZE
Definition: bnxt.h:173
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
Definition: bnxt_hsi.h:3280
uint32_t type
Operating system type.
Definition: ena.h:12
#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
Definition: bnxt_hsi.h:3272
uint16_t size
Buffer size.
Definition: dwmac.h:14
#define dbg_tx_vlan(bp, src, plen, len)
Definition: bnxt_dbg.h:564
__le16 req_type
Definition: bnxt_hsi.h:86
Definition: bnxt_hsi.h:68
uint16_t bp
Definition: registers.h:23
#define PCI_BASE_ADDRESS_0
Definition: pci.h:62
__le16 max_ext_req_len
Definition: bnxt_hsi.h:467
#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB
Definition: bnxt_hsi.h:3281
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
#define NQ_CN_TYPE_MASK
Definition: bnxt.h:570
#define dbg_pci(bp, func, creg)
Definition: bnxt_dbg.h:140
#define dump_nq(nq, id)
Definition: bnxt_dbg.h:509
#define STATUS_LINK_ACTIVE
Definition: bnxt.h:59
u16 type
Definition: bnxt.h:562
#define LINK_SPEED_DRV_40G
Definition: bnxt.h:231
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
uint16_t device
Device ID.
Definition: pci.h:229
#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
Definition: bnxt_hsi.h:3277
#define REQ_BUFFER_SIZE
Definition: bnxt.h:156
#define SHORT_CMD_REQUIRED
Definition: bnxt.h:1065
#define RX_RING_BUFFER_SIZE
Definition: bnxt.h:151
#define dbg_mem(bp, func)
Definition: bnxt_dbg.h:175
static const void * src
Definition: string.h:47
#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
Definition: bnxt.h:534
#define BYTE_SWAP_S(w)
Definition: bnxt.h:192
Definition: bnx2.h:150
#define dbg_func_qcaps(bp)
Definition: bnxt_dbg.h:321
#define PCI_BASE_ADDRESS_2
Definition: pci.h:64
ring len
Length.
Definition: dwmac.h:231
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
#define STATUS_TIMEOUT
Definition: bnxt.h:79
#define CMPL_BASE_TYPE_RX_L2
Definition: bnxt.h:525
#define dbg_bnxt_pause()
Definition: bnxt_dbg.h:327
#define TX_RING_BUFFER_SIZE
Definition: bnxt.h:150
#define str_gbps
Definition: bnxt.h:215
int getchar(void)
Read a single character from any console.
Definition: console.c:85
uint8_t flags
Flags.
Definition: ena.h:18
#define dbg_rx_cid(idx, cid)
Definition: bnxt_dbg.h:463
#define dbg_rx_stat(bp)
Definition: bnxt_dbg.h:466
#define dbg_alloc_rx_iob_fail(iob_idx, cons_id)
Definition: bnxt_dbg.h:464
#define CMPL_BASE_TYPE_TX_L2
Definition: bnxt.h:524
#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
Definition: bnxt_hsi.h:3276
A PCI device.
Definition: pci.h:210
#define LINK_SPEED_DRV_MASK
Definition: bnxt.h:221
#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
Definition: bnxt_hsi.h:3283
u16 type
Definition: bnxt.h:521
#define dump_tx_pkt(pkt, len, idx)
Definition: bnxt_dbg.h:567
#define CQ_RING_BUFFER_SIZE
Definition: bnxt.h:153
#define dump_tx_stat(bp)
Definition: bnxt_dbg.h:566
#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
Definition: bnxt_hsi.h:3278
uint16_t vendor
Vendor ID.
Definition: pci.h:227
#define dbg_chip_info(bp)
Definition: bnxt_dbg.h:324
#define LINK_SPEED_DRV_10G
Definition: bnxt.h:227
#define dump_cq(cq, id, toggle)
Definition: bnxt_dbg.h:508
#define CMPL_BASE_TYPE_STAT_EJECT
Definition: bnxt.h:530
#define dbg_tx_done(pkt, len, idx)
Definition: bnxt_dbg.h:569
uint32_t busdevfn
Segment, bus, device, and function (bus:dev.fn) number.
Definition: pci.h:237
#define prn_set_speed(speed)
Definition: bnxt_dbg.h:323
#define dbg_link_info(bp)
Definition: bnxt_dbg.h:662
#define dbg_fw_ver(resp, tmo)
Definition: bnxt_dbg.h:319
#define LINK_SPEED_DRV_SHIFT
Definition: bnxt.h:222
#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
Definition: bnxt_hsi.h:3279
#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
Definition: bnxt_dbg.h:461
void * data
Start of data.
Definition: iobuf.h:52
#define LINK_SPEED_DRV_50G
Definition: bnxt.h:233
#define LINK_SPEED_DRV_200G
Definition: bnxt.h:237
#define DMA_BUFFER_SIZE
Definition: bnxt.h:158
#define LINK_SPEED_DRV_100G
Definition: bnxt.h:235
#define dbg_link_status(bp)
Definition: bnxt_dbg.h:661
#define dump_tx_bd(prod_bd, len, idx)
Definition: bnxt_dbg.h:568
#define dbg_num_rings(bp)
Definition: bnxt_dbg.h:325
#define LINK_SPEED_DRV_1G
Definition: bnxt.h:225
#define dbg_link_state(bp, tmo)
Definition: bnxt_dbg.h:663
uint32_t flag
Flag number.
Definition: aqc1xx.h:37
#define dbg_func_qcfg(bp)
Definition: bnxt_dbg.h:322
#define PCI_BASE_ADDRESS_4
Definition: pci.h:66
Definition: bnxt.h:561
u16 len
Definition: bnxt.h:636
#define dbg_prn(func)
Definition: bnxt_dbg.h:112
unsigned int sleep(unsigned int secs)
Sleep (interruptibly) for a fixed number of seconds.
Definition: timer.c:133
__le16 max_req_win_len
Definition: bnxt_hsi.h:439
#define CMPL_BASE_TYPE_MASK
Definition: bnxt.h:522
uint8_t u8
Definition: stdint.h:19
#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
Definition: bnxt_hsi.h:3271
uint32_t u32
Definition: stdint.h:23
Definition: bnxt.h:951
A persistent I/O buffer.
Definition: iobuf.h:37
#define LINK_SPEED_DRV_25G
Definition: bnxt.h:229