iPXE
Macros | Functions
vxge_traffic.c File Reference
#include <ipxe/netdevice.h>
#include <errno.h>
#include "vxge_traffic.h"
#include "vxge_config.h"
#include "vxge_main.h"

Go to the source code of this file.

Macros

#define ETH_FCS_LEN   4
 vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed descriptors and process the same. More...
 

Functions

 FILE_LICENCE (GPL2_ONLY)
 
enum vxge_hw_status vxge_hw_vpath_intr_enable (struct __vxge_hw_virtualpath *vpath)
 
enum vxge_hw_status vxge_hw_vpath_intr_disable (struct __vxge_hw_virtualpath *vpath)
 
void vxge_hw_device_mask_all (struct __vxge_hw_device *hldev)
 vxge_hw_device_mask_all - Mask all device interrupts. More...
 
void vxge_hw_device_unmask_all (struct __vxge_hw_device *hldev)
 vxge_hw_device_unmask_all - Unmask all device interrupts. More...
 
void vxge_hw_device_intr_enable (struct __vxge_hw_device *hldev)
 vxge_hw_device_intr_enable - Enable interrupts. More...
 
void vxge_hw_device_intr_disable (struct __vxge_hw_device *hldev)
 vxge_hw_device_intr_disable - Disable Titan interrupts. More...
 
void vxge_hw_ring_rxd_post (struct __vxge_hw_ring *ring __unused, struct vxge_hw_ring_rxd_1 *rxdp)
 vxge_hw_ring_rxd_post - Post descriptor on the ring. More...
 
static void __vxge_hw_non_offload_db_post (struct __vxge_hw_fifo *fifo, u64 txdl_ptr, u32 num_txds)
 __vxge_hw_non_offload_db_post - Post non offload doorbell More...
 
struct vxge_hw_fifo_txdvxge_hw_fifo_free_txdl_get (struct __vxge_hw_fifo *fifo)
 vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo More...
 
void vxge_hw_fifo_txdl_buffer_set (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp, struct io_buffer *iob)
 vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor. More...
 
void vxge_hw_fifo_txdl_post (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp)
 vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel. More...
 
static enum vxge_hw_status __vxge_hw_vpath_alarm_process (struct __vxge_hw_virtualpath *vpath)
 
void vxge_hw_device_clear_tx_rx (struct __vxge_hw_device *hldev)
 vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the condition that has caused the Tx and RX interrupt. More...
 
enum vxge_hw_status vxge_hw_device_begin_irq (struct __vxge_hw_device *hldev)
 vxge_hw_device_begin_irq - Begin IRQ processing. More...
 
void vxge_hw_vpath_doorbell_rx (struct __vxge_hw_ring *ring)
 vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted. More...
 
enum vxge_hw_status vxge_hw_vpath_poll_rx (struct __vxge_hw_ring *ring)
 
enum vxge_hw_status vxge_hw_vpath_poll_tx (struct __vxge_hw_fifo *fifo)
 vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same. More...
 

Macro Definition Documentation

◆ ETH_FCS_LEN

#define ETH_FCS_LEN   4

vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed descriptors and process the same.

@ring: Handle to the ring object used for receive

The function polls the Rx for the completed descriptors.

Definition at line 640 of file vxge_traffic.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_ONLY  )

◆ vxge_hw_vpath_intr_enable()

enum vxge_hw_status vxge_hw_vpath_intr_enable ( struct __vxge_hw_virtualpath vpath)

Definition at line 34 of file vxge_traffic.c.

35 {
36  struct vxge_hw_vpath_reg *vp_reg;
38 
39  if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
41  goto exit;
42  }
43 
44  vp_reg = vpath->vp_reg;
45 
47 
49  &vp_reg->general_errors_reg);
50 
52  &vp_reg->pci_config_errors_reg);
53 
55  &vp_reg->mrpcim_to_vpath_alarm_reg);
56 
58  &vp_reg->srpcim_to_vpath_alarm_reg);
59 
61  &vp_reg->vpath_ppif_int_status);
62 
64  &vp_reg->srpcim_msg_to_vpath_reg);
65 
67  &vp_reg->vpath_pcipif_int_status);
68 
70  &vp_reg->prc_alarm_reg);
71 
73  &vp_reg->wrdma_alarm_status);
74 
76  &vp_reg->asic_ntwk_vp_err_reg);
77 
79  &vp_reg->xgmac_vp_int_status);
80 
82 
83  /* Mask unwanted interrupts */
85  &vp_reg->vpath_pcipif_int_mask);
86 
88  &vp_reg->srpcim_msg_to_vpath_mask);
89 
92 
95 
97  &vp_reg->pci_config_errors_mask);
98 
99  /* Unmask the individual interrupts */
104  &vp_reg->general_errors_mask);
105 
113  &vp_reg->kdfcctl_errors_mask);
114 
116 
119  &vp_reg->prc_alarm_mask);
120 
123 
124  if (vpath->hldev->first_vp_id != vpath->vp_id)
126  &vp_reg->asic_ntwk_vp_err_mask);
127  else
131  0, 32), &vp_reg->asic_ntwk_vp_err_mask);
132 
134 exit:
135  return status;
136 
137 }
u64 mrpcim_to_vpath_alarm_mask
Definition: vxge_reg.h:4545
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
u64 asic_ntwk_vp_err_mask
Definition: vxge_reg.h:4252
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR
Definition: vxge_reg.h:499
u64 srpcim_to_vpath_alarm_reg
Definition: vxge_reg.h:4547
u64 vpath_pcipif_int_mask
Definition: vxge_reg.h:4470
#define VXGE_HW_INTR_MASK_ALL
Definition: vxge_traffic.h:29
#define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW
Definition: vxge_reg.h:507
u64 srpcim_to_vpath_alarm_mask
Definition: vxge_reg.h:4550
uint8_t status
Status.
Definition: ena.h:16
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR
Definition: vxge_reg.h:492
#define VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR
Definition: vxge_reg.h:508
#define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK
Definition: vxge_reg.h:229
u64 asic_ntwk_vp_err_reg
Definition: vxge_reg.h:4242
#define VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW
Definition: vxge_reg.h:506
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON
Definition: vxge_reg.h:495
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON
Definition: vxge_reg.h:496
#define vxge_bVALn(bits, loc, n)
Definition: vxge_reg.h:35
u64 vpath_ppif_int_status
Definition: vxge_reg.h:4498
#define VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP
Definition: vxge_reg.h:29
u64 mrpcim_to_vpath_alarm_reg
Definition: vxge_reg.h:4542
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR
Definition: vxge_reg.h:498
u64 srpcim_msg_to_vpath_mask
Definition: vxge_reg.h:4476
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:397
#define VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR
Definition: vxge_reg.h:493
u64 vpath_general_int_mask
Definition: vxge_reg.h:4493
u64 srpcim_msg_to_vpath_reg
Definition: vxge_reg.h:4473
vxge_hw_status
Definition: vxge_config.h:70
struct __vxge_hw_device * hldev
Definition: vxge_config.h:396
u64 vpath_pcipif_int_status
Definition: vxge_reg.h:4464
u64 vpath_general_int_status
Definition: vxge_reg.h:4488
#define VXGE_HW_VP_NOT_OPEN
Definition: vxge_config.h:393
u64 pci_config_errors_reg
Definition: vxge_reg.h:4536
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
u64 pci_config_errors_mask
Definition: vxge_reg.h:4540
uint32_t u32
Definition: stdint.h:23
#define VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ
Definition: vxge_reg.h:509
#define VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT
Definition: vxge_reg.h:227

References __vxge_hw_pio_mem_write32_upper(), vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::asic_ntwk_vp_err_reg, __vxge_hw_device::first_vp_id, vxge_hw_vpath_reg::general_errors_mask, vxge_hw_vpath_reg::general_errors_reg, __vxge_hw_virtualpath::hldev, vxge_hw_vpath_reg::kdfcctl_errors_mask, vxge_hw_vpath_reg::kdfcctl_errors_reg, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_reg, vxge_hw_vpath_reg::pci_config_errors_mask, vxge_hw_vpath_reg::pci_config_errors_reg, vxge_hw_vpath_reg::prc_alarm_mask, vxge_hw_vpath_reg::prc_alarm_reg, readq(), vxge_hw_vpath_reg::srpcim_msg_to_vpath_mask, vxge_hw_vpath_reg::srpcim_msg_to_vpath_reg, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_reg, status, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_mask, vxge_hw_vpath_reg::vpath_general_int_status, vxge_hw_vpath_reg::vpath_pcipif_int_mask, vxge_hw_vpath_reg::vpath_pcipif_int_status, vxge_hw_vpath_reg::vpath_ppif_int_mask, vxge_hw_vpath_reg::vpath_ppif_int_status, vxge_bVALn, VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT, VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW, VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW, VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ, VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR, VXGE_HW_INTR_MASK_ALL, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON, VXGE_HW_OK, VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, VXGE_HW_VP_NOT_OPEN, vxge_hw_vpath_reg::wrdma_alarm_mask, vxge_hw_vpath_reg::wrdma_alarm_status, writeq(), vxge_hw_vpath_reg::xgmac_vp_int_mask, and vxge_hw_vpath_reg::xgmac_vp_int_status.

Referenced by vxge_hw_device_intr_enable().

◆ vxge_hw_vpath_intr_disable()

enum vxge_hw_status vxge_hw_vpath_intr_disable ( struct __vxge_hw_virtualpath vpath)

Definition at line 149 of file vxge_traffic.c.

150 {
152  struct vxge_hw_vpath_reg __iomem *vp_reg;
153 
154  if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
156  goto exit;
157  }
158  vp_reg = vpath->vp_reg;
159 
161  &vp_reg->vpath_general_int_mask);
162 
164 
166  &vp_reg->general_errors_mask);
167 
169  &vp_reg->pci_config_errors_mask);
170 
172  &vp_reg->mrpcim_to_vpath_alarm_mask);
173 
175  &vp_reg->srpcim_to_vpath_alarm_mask);
176 
178  &vp_reg->vpath_ppif_int_mask);
179 
181  &vp_reg->srpcim_msg_to_vpath_mask);
182 
184  &vp_reg->vpath_pcipif_int_mask);
185 
187  &vp_reg->wrdma_alarm_mask);
188 
190  &vp_reg->prc_alarm_mask);
191 
193  &vp_reg->xgmac_vp_int_mask);
194 
196  &vp_reg->asic_ntwk_vp_err_mask);
197 
198 exit:
199  return status;
200 }
u64 mrpcim_to_vpath_alarm_mask
Definition: vxge_reg.h:4545
u64 asic_ntwk_vp_err_mask
Definition: vxge_reg.h:4252
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
u64 vpath_pcipif_int_mask
Definition: vxge_reg.h:4470
#define VXGE_HW_INTR_MASK_ALL
Definition: vxge_traffic.h:29
u64 srpcim_to_vpath_alarm_mask
Definition: vxge_reg.h:4550
uint8_t status
Status.
Definition: ena.h:16
#define __iomem
Definition: igbvf_osdep.h:45
u64 srpcim_msg_to_vpath_mask
Definition: vxge_reg.h:4476
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:397
u64 vpath_general_int_mask
Definition: vxge_reg.h:4493
vxge_hw_status
Definition: vxge_config.h:70
#define VXGE_HW_VP_NOT_OPEN
Definition: vxge_config.h:393
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
u64 pci_config_errors_mask
Definition: vxge_reg.h:4540
uint32_t u32
Definition: stdint.h:23

References __iomem, __vxge_hw_pio_mem_write32_upper(), vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::general_errors_mask, vxge_hw_vpath_reg::kdfcctl_errors_mask, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::pci_config_errors_mask, vxge_hw_vpath_reg::prc_alarm_mask, vxge_hw_vpath_reg::srpcim_msg_to_vpath_mask, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_mask, status, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_mask, vxge_hw_vpath_reg::vpath_pcipif_int_mask, vxge_hw_vpath_reg::vpath_ppif_int_mask, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_INTR_MASK_ALL, VXGE_HW_OK, VXGE_HW_VP_NOT_OPEN, vxge_hw_vpath_reg::wrdma_alarm_mask, writeq(), and vxge_hw_vpath_reg::xgmac_vp_int_mask.

Referenced by vxge_hw_device_intr_disable().

◆ vxge_hw_device_mask_all()

void vxge_hw_device_mask_all ( struct __vxge_hw_device hldev)

vxge_hw_device_mask_all - Mask all device interrupts.

@hldev: HW device handle.

Mask all device interrupts.

See also: vxge_hw_device_unmask_all()

Definition at line 210 of file vxge_traffic.c.

211 {
212  u64 val64;
213 
216 
218  &hldev->common_reg->titan_mask_all_int);
219 
220  return;
221 }
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
uint64_t u64
Definition: stdint.h:25
#define vxge_bVALn(bits, loc, n)
Definition: vxge_reg.h:35
#define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC
Definition: vxge_reg.h:122
#define VXGE_HW_TITAN_MASK_ALL_INT_ALARM
Definition: vxge_reg.h:121
uint32_t u32
Definition: stdint.h:23

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, vxge_bVALn, VXGE_HW_TITAN_MASK_ALL_INT_ALARM, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_hw_device_intr_disable(), vxge_hw_device_intr_enable(), and vxge_irq().

◆ vxge_hw_device_unmask_all()

void vxge_hw_device_unmask_all ( struct __vxge_hw_device hldev)

vxge_hw_device_unmask_all - Unmask all device interrupts.

@hldev: HW device handle.

Unmask all device interrupts.

See also: vxge_hw_device_mask_all()

Definition at line 231 of file vxge_traffic.c.

232 {
234 
236  &hldev->common_reg->titan_mask_all_int);
237 
238  return;
239 }
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
uint64_t u64
Definition: stdint.h:25
#define vxge_bVALn(bits, loc, n)
Definition: vxge_reg.h:35
#define VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC
Definition: vxge_reg.h:122
uint32_t u32
Definition: stdint.h:23

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, vxge_bVALn, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_close(), and vxge_irq().

◆ vxge_hw_device_intr_enable()

void vxge_hw_device_intr_enable ( struct __vxge_hw_device hldev)

vxge_hw_device_intr_enable - Enable interrupts.

@hldev: HW device handle.

Enable Titan interrupts. The function is to be executed the last in Titan initialization sequence.

See also: vxge_hw_device_intr_disable()

Definition at line 250 of file vxge_traffic.c.

251 {
252  u64 val64;
253  u32 val32;
254 
256 
258 
259  val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
261 
262  if (val64 != 0) {
263  writeq(val64, &hldev->common_reg->tim_int_status0);
264 
265  writeq(~val64, &hldev->common_reg->tim_int_mask0);
266  }
267 
268  val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
270 
271  if (val32 != 0) {
273  &hldev->common_reg->tim_int_status1);
274 
276  &hldev->common_reg->tim_int_mask1);
277  }
278 
279  val64 = readq(&hldev->common_reg->titan_general_int_status);
280 
281  /* We have not enabled the top level interrupt yet.
282  * This will be controlled from vxge_irq() entry api.
283  */
284  return;
285 }
u64 tim_int_mask0[4]
Definition: vxge_config.h:511
enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_traffic.c:34
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
struct __vxge_hw_virtualpath virtual_path
Definition: vxge_config.h:507
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
#define VXGE_HW_VPATH_INTR_RX
Definition: vxge_traffic.h:131
uint64_t u64
Definition: stdint.h:25
u32 tim_int_mask1[4]
Definition: vxge_config.h:512
#define VXGE_HW_VPATH_INTR_TX
Definition: vxge_traffic.h:130
u64 titan_general_int_status
Definition: vxge_reg.h:803
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
uint32_t u32
Definition: stdint.h:23
void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
vxge_hw_device_mask_all - Mask all device interrupts.
Definition: vxge_traffic.c:210

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, readq(), __vxge_hw_device::tim_int_mask0, vxge_hw_common_reg::tim_int_mask0, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, vxge_hw_common_reg::titan_general_int_status, __vxge_hw_device::virtual_path, vxge_hw_device_mask_all(), vxge_hw_vpath_intr_enable(), VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq().

Referenced by vxge_open().

◆ vxge_hw_device_intr_disable()

void vxge_hw_device_intr_disable ( struct __vxge_hw_device hldev)

vxge_hw_device_intr_disable - Disable Titan interrupts.

@hldev: HW device handle.

Disable Titan interrupts.

See also: vxge_hw_device_intr_enable()

Definition at line 295 of file vxge_traffic.c.

296 {
298 
299  /* mask all the tim interrupts */
302  &hldev->common_reg->tim_int_mask1);
303 
305 
306  return;
307 }
struct __vxge_hw_virtualpath virtual_path
Definition: vxge_config.h:507
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
#define VXGE_HW_INTR_MASK_ALL
Definition: vxge_traffic.h:29
#define VXGE_HW_DEFAULT_32
Definition: vxge_traffic.h:36
enum vxge_hw_status vxge_hw_vpath_intr_disable(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_traffic.c:149
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
vxge_hw_device_mask_all - Mask all device interrupts.
Definition: vxge_traffic.c:210

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::virtual_path, VXGE_HW_DEFAULT_32, vxge_hw_device_mask_all(), VXGE_HW_INTR_MASK_ALL, vxge_hw_vpath_intr_disable(), and writeq().

Referenced by vxge_close().

◆ vxge_hw_ring_rxd_post()

void vxge_hw_ring_rxd_post ( struct __vxge_hw_ring *ring  __unused,
struct vxge_hw_ring_rxd_1 rxdp 
)

vxge_hw_ring_rxd_post - Post descriptor on the ring.

@ring: Handle to the ring object used for receive @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().

Post descriptor on the ring. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).

Definition at line 318 of file vxge_traffic.c.

320 {
322 }
#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER
Definition: vxge_config.h:159
Definition: sis900.h:32

References rxdp, and VXGE_HW_RING_RXD_LIST_OWN_ADAPTER.

Referenced by vxge_hw_ring_replenish(), and vxge_hw_vpath_poll_rx().

◆ __vxge_hw_non_offload_db_post()

static void __vxge_hw_non_offload_db_post ( struct __vxge_hw_fifo fifo,
u64  txdl_ptr,
u32  num_txds 
)
static

__vxge_hw_non_offload_db_post - Post non offload doorbell

@fifo: fifohandle @txdl_ptr: The starting location of the TxDL in host memory @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)

This function posts a non-offload doorbell to doorbell FIFO

Definition at line 334 of file vxge_traffic.c.

336 {
339  &fifo->nofl_db->control_0);
340 
341  wmb();
342 
343  writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
344 
345  wmb();
346 }
#define VXGE_HW_NODBW_TYPE(val)
Definition: vxge_config.h:294
wmb()
struct __vxge_hw_non_offload_db_wrapper * nofl_db
Definition: vxge_config.h:324
#define VXGE_HW_NODBW_TYPE_NODBW
Definition: vxge_config.h:295
#define VXGE_HW_NODBW_LAST_TXD_NUMBER(val)
Definition: vxge_config.h:298
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.

References __vxge_hw_non_offload_db_wrapper::control_0, __vxge_hw_fifo::nofl_db, __vxge_hw_non_offload_db_wrapper::txdl_ptr, VXGE_HW_NODBW_LAST_TXD_NUMBER, VXGE_HW_NODBW_TYPE, VXGE_HW_NODBW_TYPE_NODBW, wmb(), and writeq().

Referenced by vxge_hw_fifo_txdl_post().

◆ vxge_hw_fifo_free_txdl_get()

struct vxge_hw_fifo_txd* vxge_hw_fifo_free_txdl_get ( struct __vxge_hw_fifo fifo)

vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo

@fifo: tx channel handle

Definition at line 354 of file vxge_traffic.c.

355 {
356  struct vxge_hw_fifo_txd *txdp;
357 
358  txdp = fifo->txdl + fifo->sw_offset;
359  if (txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) {
360  vxge_debug(VXGE_ERR, "%s:%d, error: txd(%d) owned by hw\n",
361  __func__, __LINE__, fifo->sw_offset);
362  return NULL;
363  }
364 
365  return txdp;
366 }
struct vxge_hw_fifo_txd - Transmit Descriptor
Definition: vxge_config.h:212
#define vxge_debug(mask, fmt...)
Definition: vxge_config.h:762
#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER
Definition: vxge_config.h:214
Definition: sis900.h:30
struct vxge_hw_fifo_txd * txdl
Definition: vxge_config.h:328
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define VXGE_ERR
Definition: vxge_config.h:54

References NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, txdp, vxge_debug, VXGE_ERR, and VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER.

Referenced by vxge_xmit().

◆ vxge_hw_fifo_txdl_buffer_set()

void vxge_hw_fifo_txdl_buffer_set ( struct __vxge_hw_fifo fifo,
struct vxge_hw_fifo_txd txdp,
struct io_buffer iob 
)

vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.

@fifo: Handle to the fifo object used for non offload send @txdlh: Descriptor handle. @iob: data buffer.

Definition at line 374 of file vxge_traffic.c.

377 {
378  txdp->control_0 = VXGE_HW_FIFO_TXD_GATHER_CODE(
380  txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(iob_len(iob));
381 
382  txdp->control_1 = VXGE_HW_FIFO_TXD_INT_NUMBER(fifo->tx_intr_num);
384 
385  txdp->host_control = (intptr_t)iob;
386  txdp->buffer_pointer = virt_to_bus(iob->data);
387 }
#define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST
Definition: vxge_config.h:239
unsigned long intptr_t
Definition: stdint.h:21
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val)
Definition: vxge_config.h:226
#define VXGE_HW_FIFO_TXD_GATHER_CODE(val)
Definition: vxge_config.h:220
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
Definition: sis900.h:30
void * data
Start of data.
Definition: iobuf.h:44
#define VXGE_HW_FIFO_TXD_INT_NUMBER(val)
Definition: vxge_config.h:237

References io_buffer::data, iob_len(), __vxge_hw_fifo::tx_intr_num, txdp, virt_to_bus(), VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST, VXGE_HW_FIFO_TXD_BUFFER_SIZE, VXGE_HW_FIFO_TXD_GATHER_CODE, VXGE_HW_FIFO_TXD_INT_NUMBER, and VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST.

Referenced by vxge_xmit().

◆ vxge_hw_fifo_txdl_post()

void vxge_hw_fifo_txdl_post ( struct __vxge_hw_fifo fifo,
struct vxge_hw_fifo_txd txdp 
)

vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.

@fifo: Handle to the fifo object used for non offload send @txdp: Tx Descriptor

Post descriptor on the 'fifo' type channel for transmission. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).

Definition at line 399 of file vxge_traffic.c.

401 {
403 
405 
407 }
static void vxge_hw_fifo_txd_offset_up(u16 *offset)
Definition: vxge_config.h:576
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER
Definition: vxge_config.h:214
uint64_t u64
Definition: stdint.h:25
static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo, u64 txdl_ptr, u32 num_txds)
__vxge_hw_non_offload_db_post - Post non offload doorbell
Definition: vxge_traffic.c:334
Definition: sis900.h:30

References __vxge_hw_non_offload_db_post(), __vxge_hw_fifo::sw_offset, txdp, virt_to_bus(), VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, and vxge_hw_fifo_txd_offset_up().

Referenced by vxge_xmit().

◆ __vxge_hw_vpath_alarm_process()

static enum vxge_hw_status __vxge_hw_vpath_alarm_process ( struct __vxge_hw_virtualpath vpath)
static

Definition at line 417 of file vxge_traffic.c.

419 {
420  u64 val64;
421  u64 alarm_status;
423  struct __vxge_hw_device *hldev = NULL;
424  struct vxge_hw_vpath_reg *vp_reg;
425 
426  hldev = vpath->hldev;
427  vp_reg = vpath->vp_reg;
428  alarm_status = readq(&vp_reg->vpath_general_int_status);
429 
430  if (alarm_status == VXGE_HW_ALL_FOXES) {
431 
432  vxge_debug(VXGE_ERR, "%s: %s:%d, slot freeze error\n",
433  hldev->ndev->name, __func__, __LINE__);
435  goto out;
436  }
437 
438  if (alarm_status & ~(
443 
444  vxge_debug(VXGE_ERR, "%s: %s:%d, Unknown vpath alarm\n",
445  hldev->ndev->name, __func__, __LINE__);
447  goto out;
448  }
449 
450  if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
451 
452  val64 = readq(&vp_reg->xgmac_vp_int_status);
453 
454  if (val64 &
456 
457  val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
458 
459  if (((val64 &
461  (!(val64 &
463  ((val64 &
465  && (!(val64 &
467  ))) {
469  &vp_reg->asic_ntwk_vp_err_mask);
470 
471  netdev_link_down(hldev->ndev);
472  vxge_debug(VXGE_INTR, "%s: %s:%d link down\n",
473  hldev->ndev->name, __func__, __LINE__);
474  }
475 
476  if (((val64 &
478  (!(val64 &
480  ((val64 &
482  && (!(val64 &
484  ))) {
486  &vp_reg->asic_ntwk_vp_err_mask);
487 
488  netdev_link_up(hldev->ndev);
489  vxge_debug(VXGE_INTR, "%s: %s:%d link up\n",
490  hldev->ndev->name, __func__, __LINE__);
491  }
492 
494  &vp_reg->asic_ntwk_vp_err_reg);
495  }
496  } else {
497  vxge_debug(VXGE_INFO, "%s: %s:%d unhandled alarm %llx\n",
498  hldev->ndev->name, __func__, __LINE__,
499  alarm_status);
500  }
501 out:
502  return status;
503 }
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
#define VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT
Definition: vxge_reg.h:470
u64 asic_ntwk_vp_err_mask
Definition: vxge_reg.h:4252
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
#define VXGE_HW_INTR_MASK_ALL
Definition: vxge_traffic.h:29
#define VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT
Definition: vxge_reg.h:468
#define VXGE_INFO
Definition: vxge_config.h:50
#define vxge_debug(mask, fmt...)
Definition: vxge_config.h:762
uint8_t status
Status.
Definition: ena.h:16
#define VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT
Definition: vxge_reg.h:217
#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT
Definition: vxge_reg.h:221
u64 asic_ntwk_vp_err_reg
Definition: vxge_reg.h:4242
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:768
uint64_t u64
Definition: stdint.h:25
__be32 out[4]
Definition: CIB_PRM.h:36
#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR
Definition: vxge_reg.h:223
#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR
Definition: vxge_reg.h:225
struct __vxge_hw_device - Hal device object @magic: Magic Number @bar0: BAR0 virtual address.
Definition: vxge_config.h:477
#define VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK
Definition: vxge_reg.h:222
char name[NETDEV_NAME_LEN]
Name of this network device.
Definition: netdevice.h:358
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:397
#define VXGE_HW_ALL_FOXES
Definition: vxge_traffic.h:28
vxge_hw_status
Definition: vxge_config.h:70
#define VXGE_INTR
Definition: vxge_config.h:51
struct __vxge_hw_device * hldev
Definition: vxge_config.h:396
u64 vpath_general_int_status
Definition: vxge_reg.h:4488
#define VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT
Definition: vxge_reg.h:469
struct net_device * ndev
Definition: vxge_config.h:483
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
#define VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT
Definition: vxge_reg.h:467
#define VXGE_ERR
Definition: vxge_config.h:54

References vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::asic_ntwk_vp_err_reg, __vxge_hw_virtualpath::hldev, net_device::name, __vxge_hw_device::ndev, netdev_link_down(), netdev_link_up(), NULL, out, readq(), status, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_status, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR, VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_FAIL, VXGE_HW_INTR_MASK_ALL, VXGE_HW_OK, VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT, VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT, VXGE_INFO, VXGE_INTR, writeq(), and vxge_hw_vpath_reg::xgmac_vp_int_status.

Referenced by vxge_hw_device_begin_irq().

◆ vxge_hw_device_clear_tx_rx()

void vxge_hw_device_clear_tx_rx ( struct __vxge_hw_device hldev)

vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the condition that has caused the Tx and RX interrupt.

@hldev: HW device.

Acknowledge (that is, clear) the condition that has caused the Tx and Rx interrupt. See also: vxge_hw_device_begin_irq(), vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().

Definition at line 515 of file vxge_traffic.c.

516 {
517 
518  if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
519  (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
522  &hldev->common_reg->tim_int_status0);
523  }
524 
525  if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
526  (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
530  &hldev->common_reg->tim_int_status1);
531  }
532 
533  return;
534 }
u64 tim_int_mask0[4]
Definition: vxge_config.h:511
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
static void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr)
Definition: vxge_config.h:703
#define VXGE_HW_VPATH_INTR_RX
Definition: vxge_traffic.h:131
u32 tim_int_mask1[4]
Definition: vxge_config.h:512
#define VXGE_HW_VPATH_INTR_TX
Definition: vxge_traffic.h:130
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq().

Referenced by vxge_hw_device_begin_irq().

◆ vxge_hw_device_begin_irq()

enum vxge_hw_status vxge_hw_device_begin_irq ( struct __vxge_hw_device hldev)

vxge_hw_device_begin_irq - Begin IRQ processing.

@hldev: HW device handle.

The function performs two actions, It first checks whether (shared IRQ) the interrupt was raised by the device. Next, it masks the device interrupts.

Note: vxge_hw_device_begin_irq() does not flush MMIO writes through the bridge. Therefore, two back-to-back interrupts are potentially possible.

Returns: 0, if the interrupt is not "ours" (note that in this case the device remain enabled). Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter status.

Definition at line 554 of file vxge_traffic.c.

555 {
556  u64 val64;
558  u64 vpath_mask;
559  enum vxge_hw_status ret = VXGE_HW_OK;
560 
561  val64 = readq(&hldev->common_reg->titan_general_int_status);
562 
563  if (!val64) {
564  ret = VXGE_HW_ERR_WRONG_IRQ;
565  goto exit;
566  }
567 
568  if (val64 == VXGE_HW_ALL_FOXES) {
569 
571 
573 
574  vxge_debug(VXGE_ERR, "%s: %s:%d critical error "
575  "occurred\n", hldev->ndev->name,
576  __func__, __LINE__);
578  goto exit;
579  }
580  }
581 
582  vpath_mask = hldev->vpaths_deployed >>
585  vpath_mask))
587 
590 
591 exit:
592  return ret;
593 }
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
struct __vxge_hw_virtualpath virtual_path
Definition: vxge_config.h:507
u64 adapter_status
Definition: vxge_reg.h:137
struct vxge_hw_common_reg * common_reg
Definition: vxge_config.h:497
#define vxge_debug(mask, fmt...)
Definition: vxge_config.h:762
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT
Definition: vxge_reg.h:115
#define VXGE_HW_MAX_VIRTUAL_PATHS
Definition: vxge_traffic.h:30
uint64_t u64
Definition: stdint.h:25
#define VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(val)
Definition: vxge_reg.h:116
char name[NETDEV_NAME_LEN]
Name of this network device.
Definition: netdevice.h:358
#define VXGE_HW_ALL_FOXES
Definition: vxge_traffic.h:28
vxge_hw_status
Definition: vxge_config.h:70
static enum vxge_hw_status __vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath)
Definition: vxge_traffic.c:417
u64 titan_general_int_status
Definition: vxge_reg.h:803
struct net_device * ndev
Definition: vxge_config.h:483
#define VXGE_ERR
Definition: vxge_config.h:54
void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the condition that has caused the Tx and RX...
Definition: vxge_traffic.c:515

References __vxge_hw_vpath_alarm_process(), adapter_status, vxge_hw_common_reg::adapter_status, __vxge_hw_device::common_reg, net_device::name, __vxge_hw_device::ndev, readq(), vxge_hw_common_reg::titan_general_int_status, __vxge_hw_device::virtual_path, __vxge_hw_device::vpaths_deployed, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, vxge_hw_device_clear_tx_rx(), VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_ERR_WRONG_IRQ, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT, and VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT.

Referenced by vxge_poll().

◆ vxge_hw_vpath_doorbell_rx()

void vxge_hw_vpath_doorbell_rx ( struct __vxge_hw_ring ring)

vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.

@ring: Handle to the ring object used for receive

The function writes the number of qwords of rxds posted during replishment. Since the function is called frequently, a flush is not required to post the write transaction. At the very least, the previous write will be flushed once the subsequent write is made.

Returns: None.

Definition at line 607 of file vxge_traffic.c.

608 {
609  u32 rxds_qw_per_block = VXGE_HW_MAX_RXDS_PER_BLOCK_1 *
611 
613 
615 
616  if (ring->total_db_cnt >= rxds_qw_per_block) {
617  /* For each block add 4 more qwords */
619 
620  /* Reset total count */
621  ring->total_db_cnt -= rxds_qw_per_block;
622  }
623 
624  if (ring->doorbell_cnt >= ring->rxd_qword_limit) {
625  wmb();
627  ring->doorbell_cnt),
628  &ring->vp_reg->prc_rxd_doorbell);
629  ring->doorbell_cnt = 0;
630  }
631 }
wmb()
struct vxge_hw_vpath_reg * vp_reg
Definition: vxge_config.h:361
#define VXGE_HW_RING_RXD_QWORDS_MODE_1
Definition: vxge_config.h:364
#define VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val)
Definition: vxge_reg.h:77
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
uint32_t u32
Definition: stdint.h:23
#define VXGE_HW_MAX_RXDS_PER_BLOCK_1
Definition: vxge_config.h:341

References __vxge_hw_ring::doorbell_cnt, vxge_hw_vpath_reg::prc_rxd_doorbell, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::total_db_cnt, __vxge_hw_ring::vp_reg, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT, VXGE_HW_RING_RXD_QWORDS_MODE_1, wmb(), and writeq().

Referenced by vxge_hw_vpath_poll_rx().

◆ vxge_hw_vpath_poll_rx()

enum vxge_hw_status vxge_hw_vpath_poll_rx ( struct __vxge_hw_ring ring)

Definition at line 641 of file vxge_traffic.c.

642 {
643  struct __vxge_hw_device *hldev;
645  struct vxge_hw_ring_rxd_1 *rxd;
646  unsigned int len;
647  enum vxge_hw_ring_tcode tcode;
648  struct io_buffer *rx_iob, *iobuf = NULL;
649  u16 poll_count = 0;
650 
651  hldev = ring->vpathh->hldev;
652 
653  do {
654  rxd = &ring->rxdl->rxd[ring->rxd_offset];
655  tcode = VXGE_HW_RING_RXD_T_CODE_GET(rxd->control_0);
656 
657  /* if tcode is VXGE_HW_RING_T_CODE_FRM_DROP, it is
658  * possible the ownership bit still set to adapter
659  */
660  if ((rxd->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)
661  && (tcode == VXGE_HW_RING_T_CODE_OK)) {
662 
664  goto err0;
665  }
666 
667  vxge_debug(VXGE_INFO, "%s: rx frame received at offset %d\n",
668  hldev->ndev->name, ring->rxd_offset);
669 
670  iobuf = (struct io_buffer *)(intptr_t)rxd->host_control;
671 
672  if (tcode != VXGE_HW_RING_T_CODE_OK) {
673  netdev_rx_err(hldev->ndev, NULL, -EINVAL);
674  vxge_debug(VXGE_ERR, "%s:%d, rx error tcode %d\n",
675  __func__, __LINE__, tcode);
677  goto err1;
678  }
679 
681  len -= ETH_FCS_LEN;
682 
683  rx_iob = alloc_iob(len);
684  if (!rx_iob) {
685  netdev_rx_err(hldev->ndev, NULL, -ENOMEM);
686  vxge_debug(VXGE_ERR, "%s:%d, alloc_iob error\n",
687  __func__, __LINE__);
689  goto err1;
690  }
691 
692  memcpy(iob_put(rx_iob, len), iobuf->data, len);
693  /* Add this packet to the receive queue. */
694  netdev_rx(hldev->ndev, rx_iob);
695 
696 err1:
697  /* repost the rxd */
698  rxd->control_0 = rxd->control_1 = 0;
700  VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
701  vxge_hw_ring_rxd_post(ring, rxd);
702 
703  /* repost the qword count for doorbell */
705 
706  /* increment the descriptor offset */
708 
709  } while (++poll_count < ring->rx_poll_weight);
710 err0:
711  return status;
712 }
uint16_t u16
Definition: stdint.h:21
#define EINVAL
Invalid argument.
Definition: errno.h:428
#define iob_put(iobuf, len)
Definition: iobuf.h:116
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:501
#define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1)
Definition: vxge_config.h:194
struct __vxge_hw_virtualpath * vpathh
Definition: vxge_config.h:379
#define ETH_FCS_LEN
vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed descriptors and process the same.
Definition: vxge_traffic.c:640
void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring __unused, struct vxge_hw_ring_rxd_1 *rxdp)
vxge_hw_ring_rxd_post - Post descriptor on the ring.
Definition: vxge_traffic.c:318
static void vxge_hw_ring_rxd_offset_up(u16 *offset)
Definition: vxge_config.h:570
#define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0)
Definition: vxge_config.h:167
unsigned long intptr_t
Definition: stdint.h:21
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
#define VXGE_INFO
Definition: vxge_config.h:50
#define vxge_debug(mask, fmt...)
Definition: vxge_config.h:762
#define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER
Definition: vxge_config.h:159
struct vxgedev * vdev
Definition: vxge_config.h:484
uint8_t status
Status.
Definition: ena.h:16
#define ENOMEM
Not enough space.
Definition: errno.h:534
void * memcpy(void *dest, const void *src, size_t len) __nonnull
struct __vxge_hw_ring_block * rxdl
Definition: vxge_config.h:370
#define VXGE_LL_MAX_FRAME_SIZE(dev)
Definition: vxge_main.h:147
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
struct __vxge_hw_device - Hal device object @magic: Magic Number @bar0: BAR0 virtual address.
Definition: vxge_config.h:477
char name[NETDEV_NAME_LEN]
Name of this network device.
Definition: netdevice.h:358
uint32_t len
Length.
Definition: ena.h:14
void * data
Start of data.
Definition: iobuf.h:44
static void vxge_hw_ring_rxd_1b_set(struct vxge_hw_ring_rxd_1 *rxdp, struct io_buffer *iob, u32 size)
vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor.
Definition: vxge_config.h:597
vxge_hw_ring_tcode
enum vxge_hw_ring_tcode - Transfer codes returned by adapter @VXGE_HW_RING_T_CODE_OK: Transfer ok.
Definition: vxge_traffic.h:172
vxge_hw_status
Definition: vxge_config.h:70
struct __vxge_hw_device * hldev
Definition: vxge_config.h:396
struct vxge_hw_ring_rxd_1 rxd[VXGE_HW_MAX_RXDS_PER_BLOCK_1]
Definition: vxge_config.h:342
struct net_device * ndev
Definition: vxge_config.h:483
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring
Definition: vxge_config.h:154
#define VXGE_ERR
Definition: vxge_config.h:54
#define rxd
Definition: davicom.c:145
void vxge_hw_vpath_doorbell_rx(struct __vxge_hw_ring *ring)
vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.
Definition: vxge_traffic.c:607
A persistent I/O buffer.
Definition: iobuf.h:32

References alloc_iob(), io_buffer::data, EINVAL, ENOMEM, ETH_FCS_LEN, __vxge_hw_virtualpath::hldev, iob_put, len, memcpy(), net_device::name, __vxge_hw_device::ndev, netdev_rx(), netdev_rx_err(), NULL, rxd, __vxge_hw_ring_block::rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, status, __vxge_hw_device::vdev, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FAIL, VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS, VXGE_HW_OK, VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET, vxge_hw_ring_rxd_1b_set(), VXGE_HW_RING_RXD_LIST_OWN_ADAPTER, vxge_hw_ring_rxd_offset_up(), vxge_hw_ring_rxd_post(), VXGE_HW_RING_RXD_T_CODE_GET, VXGE_HW_RING_T_CODE_OK, vxge_hw_vpath_doorbell_rx(), VXGE_INFO, and VXGE_LL_MAX_FRAME_SIZE.

Referenced by vxge_poll().

◆ vxge_hw_vpath_poll_tx()

enum vxge_hw_status vxge_hw_vpath_poll_tx ( struct __vxge_hw_fifo fifo)

vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.

@fifo: Handle to the fifo object used for non offload send

The function polls the Tx for the completed descriptors and calls the driver via supplied completion callback.

Definition at line 722 of file vxge_traffic.c.

723 {
725  struct vxge_hw_fifo_txd *txdp;
726 
727  txdp = fifo->txdl + fifo->hw_offset;
728  if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)
729  && (txdp->host_control)) {
730 
731  vxge_xmit_compl(fifo, txdp,
732  VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0));
733 
735  }
736 
737  return status;
738 }
struct vxge_hw_fifo_txd - Transmit Descriptor
Definition: vxge_config.h:212
static void vxge_hw_fifo_txd_offset_up(u16 *offset)
Definition: vxge_config.h:576
uint8_t status
Status.
Definition: ena.h:16
#define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER
Definition: vxge_config.h:214
Definition: sis900.h:30
#define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0)
Definition: vxge_config.h:216
vxge_hw_status
Definition: vxge_config.h:70
struct vxge_hw_fifo_txd * txdl
Definition: vxge_config.h:328
enum vxge_hw_status vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw, struct vxge_hw_fifo_txd *txdp, enum vxge_hw_fifo_tcode tcode)
Definition: vxge_main.c:65

References __vxge_hw_fifo::hw_offset, status, __vxge_hw_fifo::txdl, txdp, VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, vxge_hw_fifo_txd_offset_up(), VXGE_HW_FIFO_TXD_T_CODE_GET, VXGE_HW_OK, and vxge_xmit_compl().

Referenced by vxge_poll().