iPXE
ath9k_ar9003_mac.c
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00001 /*
00002  * Copyright (c) 2010-2011 Atheros Communications Inc.
00003  *
00004  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
00005  * Original from Linux kernel 3.0.1
00006  *
00007  * Permission to use, copy, modify, and/or distribute this software for any
00008  * purpose with or without fee is hereby granted, provided that the above
00009  * copyright notice and this permission notice appear in all copies.
00010  *
00011  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
00012  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
00013  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
00014  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
00015  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
00016  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
00017  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
00018  */
00019 #include <ipxe/io.h>
00020 
00021 #include "hw.h"
00022 #include "ar9003_mac.h"
00023 
00024 static void ar9003_hw_rx_enable(struct ath_hw *hw)
00025 {
00026         REG_WRITE(hw, AR_CR, 0);
00027 }
00028 
00029 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
00030 {
00031         int checksum;
00032 
00033         checksum = ads->info + ads->link
00034                 + ads->data0 + ads->ctl3
00035                 + ads->data1 + ads->ctl5
00036                 + ads->data2 + ads->ctl7
00037                 + ads->data3 + ads->ctl9;
00038 
00039         return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
00040 }
00041 
00042 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
00043 {
00044         struct ar9003_txc *ads = ds;
00045 
00046         ads->link = ds_link;
00047         ads->ctl10 &= ~AR_TxPtrChkSum;
00048         ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
00049 }
00050 
00051 static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
00052 {
00053         struct ar9003_txc *ads = ds;
00054 
00055         *ds_link = &ads->link;
00056 }
00057 
00058 static int ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
00059 {
00060         u32 isr = 0;
00061         u32 mask2 = 0;
00062         struct ath9k_hw_capabilities *pCap = &ah->caps;
00063         u32 sync_cause = 0;
00064 
00065         if (ah->ah_ier & AR_IER_ENABLE) {
00066                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
00067                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
00068                                         == AR_RTC_STATUS_ON)
00069                                 isr = REG_READ(ah, AR_ISR);
00070                 }
00071 
00072                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
00073 
00074                 *masked = 0;
00075 
00076                 if (!isr && !sync_cause)
00077                         return 0;
00078         } else {
00079                 *masked = 0;
00080                 isr = REG_READ(ah, AR_ISR);
00081         }
00082 
00083         if (isr) {
00084                 if (isr & AR_ISR_BCNMISC) {
00085                         u32 isr2;
00086                         isr2 = REG_READ(ah, AR_ISR_S2);
00087 
00088                         mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
00089                                   MAP_ISR_S2_TIM);
00090                         mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
00091                                   MAP_ISR_S2_DTIM);
00092                         mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
00093                                   MAP_ISR_S2_DTIMSYNC);
00094                         mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
00095                                   MAP_ISR_S2_CABEND);
00096                         mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
00097                                   MAP_ISR_S2_GTT);
00098                         mask2 |= ((isr2 & AR_ISR_S2_CST) <<
00099                                   MAP_ISR_S2_CST);
00100                         mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
00101                                   MAP_ISR_S2_TSFOOR);
00102                         mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
00103                                   MAP_ISR_S2_BB_WATCHDOG);
00104 
00105                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
00106                                 REG_WRITE(ah, AR_ISR_S2, isr2);
00107                                 isr &= ~AR_ISR_BCNMISC;
00108                         }
00109                 }
00110 
00111                 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
00112                         isr = REG_READ(ah, AR_ISR_RAC);
00113 
00114                 if (isr == 0xffffffff) {
00115                         *masked = 0;
00116                         return 0;
00117                 }
00118 
00119                 *masked = isr & ATH9K_INT_COMMON;
00120 
00121                 if (ah->config.rx_intr_mitigation)
00122                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
00123                                 *masked |= ATH9K_INT_RXLP;
00124 
00125                 if (ah->config.tx_intr_mitigation)
00126                         if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
00127                                 *masked |= ATH9K_INT_TX;
00128 
00129                 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
00130                         *masked |= ATH9K_INT_RXLP;
00131 
00132                 if (isr & AR_ISR_HP_RXOK)
00133                         *masked |= ATH9K_INT_RXHP;
00134 
00135                 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
00136                         *masked |= ATH9K_INT_TX;
00137 
00138                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
00139                                 u32 s0, s1;
00140                                 s0 = REG_READ(ah, AR_ISR_S0);
00141                                 REG_WRITE(ah, AR_ISR_S0, s0);
00142                                 s1 = REG_READ(ah, AR_ISR_S1);
00143                                 REG_WRITE(ah, AR_ISR_S1, s1);
00144 
00145                                 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
00146                                          AR_ISR_TXEOL);
00147                         }
00148                 }
00149 
00150                 if (isr & AR_ISR_GENTMR) {
00151                         u32 s5;
00152 
00153                         if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
00154                                 s5 = REG_READ(ah, AR_ISR_S5_S);
00155                         else
00156                                 s5 = REG_READ(ah, AR_ISR_S5);
00157 
00158                         ah->intr_gen_timer_trigger =
00159                                 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
00160 
00161                         ah->intr_gen_timer_thresh =
00162                                 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
00163 
00164                         if (ah->intr_gen_timer_trigger)
00165                                 *masked |= ATH9K_INT_GENTIMER;
00166 
00167                         if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
00168                                 REG_WRITE(ah, AR_ISR_S5, s5);
00169                                 isr &= ~AR_ISR_GENTMR;
00170                         }
00171 
00172                 }
00173 
00174                 *masked |= mask2;
00175 
00176                 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
00177                         REG_WRITE(ah, AR_ISR, isr);
00178 
00179                         (void) REG_READ(ah, AR_ISR);
00180                 }
00181         }
00182 
00183         if (sync_cause) {
00184                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
00185                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
00186                         REG_WRITE(ah, AR_RC, 0);
00187                         *masked |= ATH9K_INT_FATAL;
00188                 }
00189 
00190                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
00191                         DBG("ath9k: "
00192                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
00193 
00194                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
00195                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
00196 
00197         }
00198         return 1;
00199 }
00200 
00201 static void ar9003_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen,
00202                                   int is_firstseg, int is_lastseg,
00203                                   const void *ds0, u32 buf_addr,
00204                                   unsigned int qcu)
00205 {
00206         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00207         unsigned int descid = 0;
00208 
00209         ads->info = (ATHEROS_VENDOR_ID << AR_DescId_S) |
00210                                      (1 << AR_TxRxDesc_S) |
00211                                      (1 << AR_CtrlStat_S) |
00212                                      (qcu << AR_TxQcuNum_S) | 0x17;
00213 
00214         ads->data0 = buf_addr;
00215         ads->data1 = 0;
00216         ads->data2 = 0;
00217         ads->data3 = 0;
00218 
00219         ads->ctl3 = (seglen << AR_BufLen_S);
00220         ads->ctl3 &= AR_BufLen;
00221 
00222         /* Fill in pointer checksum and descriptor id */
00223         ads->ctl10 = ar9003_calc_ptr_chksum(ads);
00224         ads->ctl10 |= (descid << AR_TxDescId_S);
00225 
00226         if (is_firstseg) {
00227                 ads->ctl12 |= (is_lastseg ? 0 : AR_TxMore);
00228         } else if (is_lastseg) {
00229                 ads->ctl11 = 0;
00230                 ads->ctl12 = 0;
00231                 ads->ctl13 = AR9003TXC_CONST(ds0)->ctl13;
00232                 ads->ctl14 = AR9003TXC_CONST(ds0)->ctl14;
00233         } else {
00234                 /* XXX Intermediate descriptor in a multi-descriptor frame.*/
00235                 ads->ctl11 = 0;
00236                 ads->ctl12 = AR_TxMore;
00237                 ads->ctl13 = 0;
00238                 ads->ctl14 = 0;
00239         }
00240 }
00241 
00242 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds __unused,
00243                                  struct ath_tx_status *ts)
00244 {
00245         struct ar9003_txs *ads;
00246         u32 status;
00247 
00248         ads = &ah->ts_ring[ah->ts_tail];
00249 
00250         status = *(volatile typeof(ads->status8) *)&(ads->status8);
00251         if ((status & AR_TxDone) == 0)
00252                 return -EINPROGRESS;
00253 
00254         ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
00255 
00256         if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
00257             (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
00258                 DBG("ath9k: "
00259                         "Tx Descriptor error %x\n", ads->ds_info);
00260                 memset(ads, 0, sizeof(*ads));
00261                 return -EIO;
00262         }
00263 
00264         if (status & AR_TxOpExceeded)
00265                 ts->ts_status |= ATH9K_TXERR_XTXOP;
00266         ts->ts_rateindex = MS(status, AR_FinalTxIdx);
00267         ts->ts_seqnum = MS(status, AR_SeqNum);
00268         ts->tid = MS(status, AR_TxTid);
00269 
00270         ts->qid = MS(ads->ds_info, AR_TxQcuNum);
00271         ts->desc_id = MS(ads->status1, AR_TxDescId);
00272         ts->ts_tstamp = ads->status4;
00273         ts->ts_status = 0;
00274         ts->ts_flags  = 0;
00275 
00276         status = *(volatile typeof(ads->status2) *)&(ads->status2);
00277         ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
00278         ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
00279         ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
00280         if (status & AR_TxBaStatus) {
00281                 ts->ts_flags |= ATH9K_TX_BA;
00282                 ts->ba_low = ads->status5;
00283                 ts->ba_high = ads->status6;
00284         }
00285 
00286         status = *(volatile typeof(ads->status3) *)&(ads->status3);
00287         if (status & AR_ExcessiveRetries)
00288                 ts->ts_status |= ATH9K_TXERR_XRETRY;
00289         if (status & AR_Filtered)
00290                 ts->ts_status |= ATH9K_TXERR_FILT;
00291         if (status & AR_FIFOUnderrun) {
00292                 ts->ts_status |= ATH9K_TXERR_FIFO;
00293                 ath9k_hw_updatetxtriglevel(ah, 1);
00294         }
00295         if (status & AR_TxTimerExpired)
00296                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
00297         if (status & AR_DescCfgErr)
00298                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
00299         if (status & AR_TxDataUnderrun) {
00300                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
00301                 ath9k_hw_updatetxtriglevel(ah, 1);
00302         }
00303         if (status & AR_TxDelimUnderrun) {
00304                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
00305                 ath9k_hw_updatetxtriglevel(ah, 1);
00306         }
00307         ts->ts_shortretry = MS(status, AR_RTSFailCnt);
00308         ts->ts_longretry = MS(status, AR_DataFailCnt);
00309         ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
00310 
00311         status = *(volatile typeof(ads->status7) *)&(ads->status7);
00312         ts->ts_rssi = MS(status, AR_TxRSSICombined);
00313         ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
00314         ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
00315         ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
00316 
00317         memset(ads, 0, sizeof(*ads));
00318 
00319         return 0;
00320 }
00321 
00322 static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
00323                 u32 pktlen, enum ath9k_pkt_type type, u32 txpower,
00324                 u32 keyIx, enum ath9k_key_type keyType, u32 flags)
00325 {
00326         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00327 
00328         if (txpower > ah->txpower_limit)
00329                 txpower = ah->txpower_limit;
00330 
00331         if (txpower > 63)
00332                 txpower = 63;
00333 
00334         ads->ctl11 = (pktlen & AR_FrameLen)
00335                 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
00336                 | SM(txpower, AR_XmitPower)
00337                 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
00338                 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
00339                 | (flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0);
00340 
00341         ads->ctl12 =
00342                 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
00343                 | SM(type, AR_FrameType)
00344                 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
00345                 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
00346                 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
00347 
00348         ads->ctl17 = SM(keyType, AR_EncrType) |
00349                      (flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
00350         ads->ctl18 = 0;
00351         ads->ctl19 = AR_Not_Sounding;
00352 
00353         ads->ctl20 = 0;
00354         ads->ctl21 = 0;
00355         ads->ctl22 = 0;
00356 }
00357 
00358 static void ar9003_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
00359 {
00360         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00361 
00362         if (val)
00363                 ads->ctl11 |= AR_ClrDestMask;
00364         else
00365                 ads->ctl11 &= ~AR_ClrDestMask;
00366 }
00367 
00368 static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds,
00369                                           void *lastds,
00370                                           u32 durUpdateEn, u32 rtsctsRate,
00371                                           u32 rtsctsDuration __unused,
00372                                           struct ath9k_11n_rate_series series[],
00373                                           u32 nseries __unused, u32 flags)
00374 {
00375         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00376         struct ar9003_txc *last_ads = (struct ar9003_txc *) lastds;
00377         uint32_t ctl11;
00378 
00379         if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
00380                 ctl11 = ads->ctl11;
00381 
00382                 if (flags & ATH9K_TXDESC_RTSENA) {
00383                         ctl11 &= ~AR_CTSEnable;
00384                         ctl11 |= AR_RTSEnable;
00385                 } else {
00386                         ctl11 &= ~AR_RTSEnable;
00387                         ctl11 |= AR_CTSEnable;
00388                 }
00389 
00390                 ads->ctl11 = ctl11;
00391         } else {
00392                 ads->ctl11 = (ads->ctl11 & ~(AR_RTSEnable | AR_CTSEnable));
00393         }
00394 
00395         ads->ctl13 = set11nTries(series, 0)
00396                 |  set11nTries(series, 1)
00397                 |  set11nTries(series, 2)
00398                 |  set11nTries(series, 3)
00399                 |  (durUpdateEn ? AR_DurUpdateEna : 0)
00400                 |  SM(0, AR_BurstDur);
00401 
00402         ads->ctl14 = set11nRate(series, 0)
00403                 |  set11nRate(series, 1)
00404                 |  set11nRate(series, 2)
00405                 |  set11nRate(series, 3);
00406 
00407         ads->ctl15 = set11nPktDurRTSCTS(series, 0)
00408                 |  set11nPktDurRTSCTS(series, 1);
00409 
00410         ads->ctl16 = set11nPktDurRTSCTS(series, 2)
00411                 |  set11nPktDurRTSCTS(series, 3);
00412 
00413         ads->ctl18 = set11nRateFlags(series, 0)
00414                 |  set11nRateFlags(series, 1)
00415                 |  set11nRateFlags(series, 2)
00416                 |  set11nRateFlags(series, 3)
00417                 | SM(rtsctsRate, AR_RTSCTSRate);
00418         ads->ctl19 = AR_Not_Sounding;
00419 
00420         last_ads->ctl13 = ads->ctl13;
00421         last_ads->ctl14 = ads->ctl14;
00422 }
00423 
00424 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
00425                                         u32 aggrLen)
00426 {
00427 #define FIRST_DESC_NDELIMS 60
00428         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00429 
00430         ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
00431 
00432         if (ah->ent_mode & AR_ENT_OTP_MPSD) {
00433                 u32 ctl17, ndelim;
00434                 /*
00435                  * Add delimiter when using RTS/CTS with aggregation
00436                  * and non enterprise AR9003 card
00437                  */
00438                 ctl17 = ads->ctl17;
00439                 ndelim = MS(ctl17, AR_PadDelim);
00440 
00441                 if (ndelim < FIRST_DESC_NDELIMS) {
00442                         aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
00443                         ndelim = FIRST_DESC_NDELIMS;
00444                 }
00445 
00446                 ctl17 &= ~AR_AggrLen;
00447                 ctl17 |= SM(aggrLen, AR_AggrLen);
00448 
00449                 ctl17 &= ~AR_PadDelim;
00450                 ctl17 |= SM(ndelim, AR_PadDelim);
00451 
00452                 ads->ctl17 = ctl17;
00453         } else {
00454                 ads->ctl17 &= ~AR_AggrLen;
00455                 ads->ctl17 |= SM(aggrLen, AR_AggrLen);
00456         }
00457 }
00458 
00459 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds,
00460                                          u32 numDelims)
00461 {
00462         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00463         unsigned int ctl17;
00464 
00465         ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
00466 
00467         /*
00468          * We use a stack variable to manipulate ctl6 to reduce uncached
00469          * read modify, modfiy, write.
00470          */
00471         ctl17 = ads->ctl17;
00472         ctl17 &= ~AR_PadDelim;
00473         ctl17 |= SM(numDelims, AR_PadDelim);
00474         ads->ctl17 = ctl17;
00475 }
00476 
00477 static void ar9003_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
00478 {
00479         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00480 
00481         ads->ctl12 |= AR_IsAggr;
00482         ads->ctl12 &= ~AR_MoreAggr;
00483         ads->ctl17 &= ~AR_PadDelim;
00484 }
00485 
00486 static void ar9003_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
00487 {
00488         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
00489 
00490         ads->ctl12 &= (~AR_IsAggr & ~AR_MoreAggr);
00491 }
00492 
00493 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah __unused, void *ds, u8 chains)
00494 {
00495         struct ar9003_txc *ads = ds;
00496 
00497         ads->ctl12 |= SM(chains, AR_PAPRDChainMask);
00498 }
00499 
00500 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
00501 {
00502         struct ath_hw_ops *ops = ath9k_hw_ops(hw);
00503 
00504         ops->rx_enable = ar9003_hw_rx_enable;
00505         ops->set_desc_link = ar9003_hw_set_desc_link;
00506         ops->get_desc_link = ar9003_hw_get_desc_link;
00507         ops->get_isr = ar9003_hw_get_isr;
00508         ops->fill_txdesc = ar9003_hw_fill_txdesc;
00509         ops->proc_txdesc = ar9003_hw_proc_txdesc;
00510         ops->set11n_txdesc = ar9003_hw_set11n_txdesc;
00511         ops->set11n_ratescenario = ar9003_hw_set11n_ratescenario;
00512         ops->set11n_aggr_first = ar9003_hw_set11n_aggr_first;
00513         ops->set11n_aggr_middle = ar9003_hw_set11n_aggr_middle;
00514         ops->set11n_aggr_last = ar9003_hw_set11n_aggr_last;
00515         ops->clr11n_aggr = ar9003_hw_clr11n_aggr;
00516         ops->set_clrdmask = ar9003_hw_set_clrdmask;
00517 }
00518 
00519 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
00520 {
00521         REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
00522 }
00523 
00524 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
00525                             enum ath9k_rx_qtype qtype)
00526 {
00527         if (qtype == ATH9K_RX_QUEUE_HP)
00528                 REG_WRITE(ah, AR_HP_RXDP, rxdp);
00529         else
00530                 REG_WRITE(ah, AR_LP_RXDP, rxdp);
00531 }
00532 
00533 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah __unused, struct ath_rx_status *rxs,
00534                                  void *buf_addr)
00535 {
00536         struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
00537         unsigned int phyerr;
00538 
00539         /* TODO: byte swap on big endian for ar9300_10 */
00540 
00541         if ((rxsp->status11 & AR_RxDone) == 0)
00542                 return -EINPROGRESS;
00543 
00544         if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
00545                 return -EINVAL;
00546 
00547         if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
00548                 return -EINPROGRESS;
00549 
00550         if (!rxs)
00551                 return 0;
00552 
00553         rxs->rs_status = 0;
00554         rxs->rs_flags =  0;
00555 
00556         rxs->rs_datalen = rxsp->status2 & AR_DataLen;
00557         rxs->rs_tstamp =  rxsp->status3;
00558 
00559         /* XXX: Keycache */
00560         rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
00561         rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
00562         rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
00563         rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
00564         rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
00565         rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
00566         rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
00567 
00568         if (rxsp->status11 & AR_RxKeyIdxValid)
00569                 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
00570         else
00571                 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
00572 
00573         rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
00574         rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
00575 
00576         rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
00577         rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
00578         rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
00579         rxs->rs_flags  = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
00580         rxs->rs_flags  |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
00581 
00582         rxs->evm0 = rxsp->status6;
00583         rxs->evm1 = rxsp->status7;
00584         rxs->evm2 = rxsp->status8;
00585         rxs->evm3 = rxsp->status9;
00586         rxs->evm4 = (rxsp->status10 & 0xffff);
00587 
00588         if (rxsp->status11 & AR_PreDelimCRCErr)
00589                 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
00590 
00591         if (rxsp->status11 & AR_PostDelimCRCErr)
00592                 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
00593 
00594         if (rxsp->status11 & AR_DecryptBusyErr)
00595                 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
00596 
00597         if ((rxsp->status11 & AR_RxFrameOK) == 0) {
00598                 /*
00599                  * AR_CRCErr will bet set to true if we're on the last
00600                  * subframe and the AR_PostDelimCRCErr is caught.
00601                  * In a way this also gives us a guarantee that when
00602                  * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
00603                  * possibly be reviewing the last subframe. AR_CRCErr
00604                  * is the CRC of the actual data.
00605                  */
00606                 if (rxsp->status11 & AR_CRCErr)
00607                         rxs->rs_status |= ATH9K_RXERR_CRC;
00608                 else if (rxsp->status11 & AR_PHYErr) {
00609                         phyerr = MS(rxsp->status11, AR_PHYErrCode);
00610                         /*
00611                          * If we reach a point here where AR_PostDelimCRCErr is
00612                          * true it implies we're *not* on the last subframe. In
00613                          * in that case that we know already that the CRC of
00614                          * the frame was OK, and MAC would send an ACK for that
00615                          * subframe, even if we did get a phy error of type
00616                          * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
00617                          * to frame that are prior to the last subframe.
00618                          * The AR_PostDelimCRCErr is the CRC for the MPDU
00619                          * delimiter, which contains the 4 reserved bits,
00620                          * the MPDU length (12 bits), and follows the MPDU
00621                          * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
00622                          */
00623                         if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
00624                             (rxsp->status11 & AR_PostDelimCRCErr)) {
00625                                 rxs->rs_phyerr = 0;
00626                         } else {
00627                                 rxs->rs_status |= ATH9K_RXERR_PHY;
00628                                 rxs->rs_phyerr = phyerr;
00629                         }
00630 
00631                 } else if (rxsp->status11 & AR_DecryptCRCErr)
00632                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
00633                 else if (rxsp->status11 & AR_MichaelErr)
00634                         rxs->rs_status |= ATH9K_RXERR_MIC;
00635                 else if (rxsp->status11 & AR_KeyMiss)
00636                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
00637         }
00638 
00639         return 0;
00640 }
00641 
00642 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
00643 {
00644         ah->ts_tail = 0;
00645 
00646         memset((void *) ah->ts_ring, 0,
00647                 ah->ts_size * sizeof(struct ar9003_txs));
00648 
00649         DBG2("ath9k: "
00650                 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
00651                 ah->ts_paddr_start, ah->ts_paddr_end,
00652                 ah->ts_ring, ah->ts_size);
00653 
00654         REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
00655         REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
00656 }
00657 
00658 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
00659                                u32 ts_paddr_start,
00660                                u8 size)
00661 {
00662 
00663         ah->ts_paddr_start = ts_paddr_start;
00664         ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
00665         ah->ts_size = size;
00666         ah->ts_ring = (struct ar9003_txs *) ts_start;
00667 
00668         ath9k_hw_reset_txstatus_ring(ah);
00669 }