iPXE
natsemi.c
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1 /*
2  * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  */
19 
20 FILE_LICENCE ( GPL2_OR_LATER );
21 
22 #include <stdint.h>
23 #include <string.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <byteswap.h>
27 #include <ipxe/netdevice.h>
28 #include <ipxe/ethernet.h>
29 #include <ipxe/if_ether.h>
30 #include <ipxe/iobuf.h>
31 #include <ipxe/malloc.h>
32 #include <ipxe/pci.h>
33 #include <ipxe/nvs.h>
34 #include <ipxe/bitbash.h>
35 #include <ipxe/spi_bit.h>
36 #include <ipxe/threewire.h>
37 #include "natsemi.h"
38 
39 /** @file
40  *
41  * National Semiconductor "MacPhyter" network card driver
42  *
43  * Based on the following datasheets:
44  *
45  * http://www.ti.com/lit/ds/symlink/dp83820.pdf
46  * http://www.datasheets.org.uk/indexdl/Datasheet-03/DSA0041338.pdf
47  *
48  */
49 
50 /******************************************************************************
51  *
52  * EEPROM interface
53  *
54  ******************************************************************************
55  */
56 
57 /** Pin mapping for SPI bit-bashing interface */
58 static const uint8_t natsemi_eeprom_bits[] = {
63 };
64 
65 /**
66  * Read input bit
67  *
68  * @v basher Bit-bashing interface
69  * @v bit_id Bit number
70  * @ret zero Input is a logic 0
71  * @ret non-zero Input is a logic 1
72  */
73 static int natsemi_spi_read_bit ( struct bit_basher *basher,
74  unsigned int bit_id ) {
75  struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
76  spibit.basher );
77  uint32_t mask = natsemi_eeprom_bits[bit_id];
78  uint32_t reg;
79 
81  reg = readl ( natsemi->regs + NATSEMI_MEAR );
83  return ( reg & mask );
84 }
85 
86 /**
87  * Set/clear output bit
88  *
89  * @v basher Bit-bashing interface
90  * @v bit_id Bit number
91  * @v data Value to write
92  */
93 static void natsemi_spi_write_bit ( struct bit_basher *basher,
94  unsigned int bit_id, unsigned long data ) {
95  struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
96  spibit.basher );
97  uint32_t mask = natsemi_eeprom_bits[bit_id];
98  uint32_t reg;
99 
101  reg = readl ( natsemi->regs + NATSEMI_MEAR );
102  reg &= ~mask;
103  reg |= ( data & mask );
104  writel ( reg, natsemi->regs + NATSEMI_MEAR );
105  DBG_ENABLE ( DBGLVL_IO );
106 }
107 
108 /** SPI bit-bashing interface */
111  .write = natsemi_spi_write_bit,
112 };
113 
114 /**
115  * Initialise EEPROM
116  *
117  * @v natsemi National Semiconductor device
118  */
119 static void natsemi_init_eeprom ( struct natsemi_nic *natsemi ) {
120 
121  /* Initialise SPI bit-bashing interface */
122  natsemi->spibit.basher.op = &natsemi_basher_ops;
123  natsemi->spibit.bus.mode = SPI_MODE_THREEWIRE;
124  natsemi->spibit.endianness =
125  ( ( natsemi->flags & NATSEMI_EEPROM_LITTLE_ENDIAN ) ?
127  init_spi_bit_basher ( &natsemi->spibit );
128 
129  /* Initialise EEPROM device */
130  init_at93c06 ( &natsemi->eeprom, 16 );
131  natsemi->eeprom.bus = &natsemi->spibit.bus;
132 }
133 
134 /**
135  * Get hardware address from sane EEPROM data
136  *
137  * @v natsemi National Semiconductor device
138  * @v eeprom EEPROM data
139  * @v hw_addr Hardware address to fill in
140  */
141 static void natsemi_hwaddr_sane ( struct natsemi_nic *natsemi,
142  const uint16_t *eeprom, uint16_t *hw_addr ) {
143  int i;
144 
145  /* Copy MAC address from EEPROM data */
146  for ( i = ( ( ETH_ALEN / 2 ) - 1 ) ; i >= 0 ; i-- )
147  *(hw_addr++) = eeprom[ NATSEMI_EEPROM_MAC_SANE + i ];
148 
149  DBGC ( natsemi, "NATSEMI %p has sane EEPROM layout\n", natsemi );
150 }
151 
152 /**
153  * Get hardware address from insane EEPROM data
154  *
155  * @v natsemi National Semiconductor device
156  * @v eeprom EEPROM data
157  * @v hw_addr Hardware address to fill in
158  */
159 static void natsemi_hwaddr_insane ( struct natsemi_nic *natsemi,
160  const uint16_t *eeprom,
161  uint16_t *hw_addr ) {
162  unsigned int i;
163  unsigned int offset;
164  uint16_t word;
165 
166  /* Copy MAC address from EEPROM data */
167  for ( i = 0 ; i < ( ETH_ALEN / 2 ) ; i++ ) {
169  word = ( ( le16_to_cpu ( eeprom[ offset ] ) >> 15 ) |
170  ( le16_to_cpu ( eeprom[ offset + 1 ] << 1 ) ) );
171  hw_addr[i] = cpu_to_le16 ( word );
172  }
173 
174  DBGC ( natsemi, "NATSEMI %p has insane EEPROM layout\n", natsemi );
175 }
176 
177 /**
178  * Get hardware address from EEPROM
179  *
180  * @v natsemi National Semiconductor device
181  * @v hw_addr Hardware address to fill in
182  * @ret rc Return status code
183  */
184 static int natsemi_hwaddr ( struct natsemi_nic *natsemi, void *hw_addr ) {
186  void ( * extract ) ( struct natsemi_nic *natsemi,
187  const uint16_t *eeprom, uint16_t *hw_addr );
188  int rc;
189 
190  /* Read EEPROM contents */
191  if ( ( rc = nvs_read ( &natsemi->eeprom.nvs, 0, buf,
192  sizeof ( buf ) ) ) != 0 ) {
193  DBGC ( natsemi, "NATSEMI %p could not read EEPROM: %s\n",
194  natsemi, strerror ( rc ) );
195  return rc;
196  }
197  DBGC2 ( natsemi, "NATSEMI %p EEPROM contents:\n", natsemi );
198  DBGC2_HDA ( natsemi, 0, buf, sizeof ( buf ) );
199 
200  /* Extract MAC address from EEPROM contents */
201  extract = ( ( natsemi->flags & NATSEMI_EEPROM_INSANE ) ?
203  extract ( natsemi, buf, hw_addr );
204 
205  return 0;
206 }
207 
208 /******************************************************************************
209  *
210  * Device reset
211  *
212  ******************************************************************************
213  */
214 
215 /**
216  * Reset controller chip
217  *
218  * @v natsemi National Semiconductor device
219  * @ret rc Return status code
220  */
221 static int natsemi_soft_reset ( struct natsemi_nic *natsemi ) {
222  unsigned int i;
223 
224  /* Initiate reset */
225  writel ( NATSEMI_CR_RST, natsemi->regs + NATSEMI_CR );
226 
227  /* Wait for reset to complete */
228  for ( i = 0 ; i < NATSEMI_RESET_MAX_WAIT_MS ; i++ ) {
229 
230  /* If reset is not complete, delay 1ms and retry */
231  if ( readl ( natsemi->regs + NATSEMI_CR ) & NATSEMI_CR_RST ) {
232  mdelay ( 1 );
233  continue;
234  }
235 
236  return 0;
237  }
238 
239  DBGC ( natsemi, "NATSEMI %p timed out waiting for reset\n", natsemi );
240  return -ETIMEDOUT;
241 }
242 
243 /**
244  * Reload configuration from EEPROM
245  *
246  * @v natsemi National Semiconductor device
247  * @ret rc Return status code
248  */
249 static int natsemi_reload_config ( struct natsemi_nic *natsemi ) {
250  unsigned int i;
251 
252  /* Initiate reload */
254 
255  /* Wait for reload to complete */
256  for ( i = 0 ; i < NATSEMI_EELOAD_MAX_WAIT_MS ; i++ ) {
257 
258  /* If reload is not complete, delay 1ms and retry */
259  if ( readl ( natsemi->regs + NATSEMI_PTSCR ) &
261  mdelay ( 1 );
262  continue;
263  }
264 
265  return 0;
266  }
267 
268  DBGC ( natsemi, "NATSEMI %p timed out waiting for configuration "
269  "reload\n", natsemi );
270  return -ETIMEDOUT;
271 }
272 
273 /**
274  * Reset hardware
275  *
276  * @v natsemi National Semiconductor device
277  * @ret rc Return status code
278  */
279 static int natsemi_reset ( struct natsemi_nic *natsemi ) {
280  uint32_t cfg;
281  int rc;
282 
283  /* Perform soft reset */
284  if ( ( rc = natsemi_soft_reset ( natsemi ) ) != 0 )
285  return rc;
286 
287  /* Reload configuration from EEPROM */
288  if ( ( rc = natsemi_reload_config ( natsemi ) ) != 0 )
289  return rc;
290 
291  /* Configure 64-bit operation, if applicable */
292  cfg = readl ( natsemi->regs + NATSEMI_CFG );
293  if ( natsemi->flags & NATSEMI_64BIT ) {
295  if ( ! ( cfg & NATSEMI_CFG_PCI64_DET ) )
297  }
298  writel ( cfg, natsemi->regs + NATSEMI_CFG );
299 
300  /* Invalidate link status cache to force an update */
301  natsemi->cfg = ~cfg;
302 
303  DBGC ( natsemi, "NATSEMI %p using configuration %08x\n",
304  natsemi, cfg );
305  return 0;
306 }
307 
308 /******************************************************************************
309  *
310  * Link state
311  *
312  ******************************************************************************
313  */
314 
315 /**
316  * Check link state
317  *
318  * @v netdev Network device
319  */
320 static void natsemi_check_link ( struct net_device *netdev ) {
321  struct natsemi_nic *natsemi = netdev->priv;
322  uint32_t cfg;
323 
324  /* Read link status */
325  cfg = readl ( natsemi->regs + NATSEMI_CFG );
326 
327  /* Do nothing unless link status has changed */
328  if ( cfg == natsemi->cfg )
329  return;
330 
331  /* Set gigabit mode (if applicable) */
332  if ( natsemi->flags & NATSEMI_1000 ) {
334  if ( ! ( cfg & NATSEMI_CFG_SPDSTS1 ) )
336  writel ( cfg, natsemi->regs + NATSEMI_CFG );
337  }
338 
339  /* Update link status */
340  natsemi->cfg = cfg;
341  DBGC ( natsemi, "NATSEMI %p link status is %08x\n", natsemi, cfg );
342 
343  /* Update network device */
344  if ( cfg & NATSEMI_CFG_LNKSTS ) {
346  } else {
348  }
349 }
350 
351 /******************************************************************************
352  *
353  * Network device interface
354  *
355  ******************************************************************************
356  */
357 
358 /**
359  * Set perfect match filter address
360  *
361  * @v natsemi National Semiconductor device
362  * @v mac MAC address
363  */
364 static void natsemi_pmatch ( struct natsemi_nic *natsemi, const void *mac ) {
365  const uint16_t *pmatch = mac;
366  uint32_t rfcr;
367  unsigned int rfaddr;
368  unsigned int i;
369 
370  for ( i = 0 ; i < ETH_ALEN ; i += sizeof ( *pmatch ) ) {
371 
372  /* Select receive filter register address */
373  rfaddr = ( NATSEMI_RFADDR_PMATCH_BASE + i );
374  rfcr = readl ( natsemi->regs + NATSEMI_RFCR );
376  rfcr |= NATSEMI_RFCR_RFADDR ( rfaddr );
377  writel ( rfcr, natsemi->regs + NATSEMI_RFCR );
378 
379  /* Write receive filter data */
380  writel ( ( le16_to_cpu ( *(pmatch++) ) | NATSEMI_RFDR_BMASK ),
381  natsemi->regs + NATSEMI_RFDR );
382  }
383 }
384 
385 /**
386  * Create descriptor ring
387  *
388  * @v natsemi National Semiconductor device
389  * @v ring Descriptor ring
390  * @ret rc Return status code
391  */
392 static int natsemi_create_ring ( struct natsemi_nic *natsemi,
393  struct natsemi_ring *ring ) {
394  size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
395  union natsemi_descriptor *desc;
396  union natsemi_descriptor *linked_desc;
399  size_t offset;
400  unsigned int i;
401  int rc;
402 
403  /* Calculate descriptor offset */
404  offset = ( ( natsemi->flags & NATSEMI_64BIT ) ? 0 :
405  offsetof ( typeof ( desc[i].d32pad ), d32 ) );
406 
407  /* Allocate descriptor ring. Align ring on its own size to
408  * ensure that it can't possibly cross the boundary of 32-bit
409  * address space.
410  */
411  ring->desc = malloc_dma ( len, len );
412  if ( ! ring->desc ) {
413  rc = -ENOMEM;
414  goto err_alloc;
415  }
416  address = ( virt_to_bus ( ring->desc ) + offset );
417 
418  /* Check address is usable by card */
419  if ( ! natsemi_address_ok ( natsemi, address ) ) {
420  DBGC ( natsemi, "NATSEMI %p cannot support 64-bit ring "
421  "address\n", natsemi );
422  rc = -ENOTSUP;
423  goto err_64bit;
424  }
425 
426  /* Initialise descriptor ring */
427  memset ( ring->desc, 0, len );
428  for ( i = 0 ; i < ring->count ; i++ ) {
429  linked_desc = &ring->desc [ ( i + 1 ) % ring->count ];
430  link = ( virt_to_bus ( linked_desc ) + offset );
431  if ( natsemi->flags & NATSEMI_64BIT ) {
432  ring->desc[i].d64.link = cpu_to_le64 ( link );
433  } else {
434  ring->desc[i].d32pad.d32.link = cpu_to_le32 ( link );
435  }
436  }
437 
438  /* Program ring address */
439  writel ( ( address & 0xffffffffUL ), natsemi->regs + ring->reg );
440  if ( natsemi->flags & NATSEMI_64BIT ) {
441  if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
442  writel ( ( ( ( uint64_t ) address ) >> 32 ),
443  natsemi->regs + ring->reg + 4 );
444  } else {
445  writel ( 0, natsemi->regs + ring->reg + 4 );
446  }
447  }
448 
449  DBGC ( natsemi, "NATSEMI %p ring %02x is at [%08llx,%08llx)\n",
450  natsemi, ring->reg,
451  ( ( unsigned long long ) virt_to_bus ( ring->desc ) ),
452  ( ( unsigned long long ) virt_to_bus ( ring->desc ) + len ) );
453 
454  return 0;
455 
456  err_64bit:
457  free_dma ( ring->desc, len );
458  ring->desc = NULL;
459  err_alloc:
460  return rc;
461 }
462 
463 /**
464  * Destroy descriptor ring
465  *
466  * @v natsemi National Semiconductor device
467  * @v ring Descriptor ring
468  */
469 static void natsemi_destroy_ring ( struct natsemi_nic *natsemi,
470  struct natsemi_ring *ring ) {
471  size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
472 
473  /* Clear ring address */
474  writel ( 0, natsemi->regs + ring->reg );
475  if ( natsemi->flags & NATSEMI_64BIT )
476  writel ( 0, natsemi->regs + ring->reg + 4 );
477 
478  /* Free descriptor ring */
479  free_dma ( ring->desc, len );
480  ring->desc = NULL;
481  ring->prod = 0;
482  ring->cons = 0;
483 }
484 
485 /**
486  * Refill receive descriptor ring
487  *
488  * @v netdev Network device
489  */
490 static void natsemi_refill_rx ( struct net_device *netdev ) {
491  struct natsemi_nic *natsemi = netdev->priv;
492  union natsemi_descriptor *rx;
493  struct io_buffer *iobuf;
494  unsigned int rx_idx;
496 
497  while ( ( natsemi->rx.prod - natsemi->rx.cons ) < NATSEMI_NUM_RX_DESC ){
498 
499  /* Allocate I/O buffer */
500  iobuf = alloc_iob ( NATSEMI_RX_MAX_LEN );
501  if ( ! iobuf ) {
502  /* Wait for next refill */
503  return;
504  }
505 
506  /* Check address is usable by card */
507  address = virt_to_bus ( iobuf->data );
508  if ( ! natsemi_address_ok ( natsemi, address ) ) {
509  DBGC ( natsemi, "NATSEMI %p cannot support 64-bit RX "
510  "buffer address\n", natsemi );
511  netdev_rx_err ( netdev, iobuf, -ENOTSUP );
512  return;
513  }
514 
515  /* Get next receive descriptor */
516  rx_idx = ( natsemi->rx.prod++ % NATSEMI_NUM_RX_DESC );
517  rx = &natsemi->rx.desc[rx_idx];
518 
519  /* Populate receive descriptor */
520  if ( natsemi->flags & NATSEMI_64BIT ) {
521  rx->d64.bufptr = cpu_to_le64 ( address );
522  } else {
523  rx->d32pad.d32.bufptr = cpu_to_le32 ( address );
524  }
525  wmb();
526  rx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_INTR |
528  wmb();
529 
530  /* Record I/O buffer */
531  assert ( natsemi->rx_iobuf[rx_idx] == NULL );
532  natsemi->rx_iobuf[rx_idx] = iobuf;
533 
534  /* Notify card that there are descriptors available */
535  writel ( NATSEMI_CR_RXE, natsemi->regs + NATSEMI_CR );
536 
537  DBGC2 ( natsemi, "NATSEMI %p RX %d is [%llx,%llx)\n", natsemi,
538  rx_idx, ( ( unsigned long long ) address ),
539  ( ( unsigned long long ) address + NATSEMI_RX_MAX_LEN));
540  }
541 }
542 
543 /**
544  * Open network device
545  *
546  * @v netdev Network device
547  * @ret rc Return status code
548  */
549 static int natsemi_open ( struct net_device *netdev ) {
550  struct natsemi_nic *natsemi = netdev->priv;
551  int rc;
552 
553  /* Set MAC address */
554  natsemi_pmatch ( natsemi, netdev->ll_addr );
555 
556  /* Create transmit descriptor ring */
557  if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->tx ) ) != 0 )
558  goto err_create_tx;
559 
560  /* Set transmit configuration */
564  ( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
566 
567  /* Create receive descriptor ring */
568  if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->rx ) ) != 0 )
569  goto err_create_rx;
570 
571  /* Set receive configuration */
574  ( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
576 
577  /* Set receive filter configuration */
579  NATSEMI_RFCR_AAU ), natsemi->regs + NATSEMI_RFCR );
580 
581  /* Fill receive ring */
583 
584  /* Unmask transmit and receive interrupts. (Interrupts will
585  * not be generated unless enabled via the IER.)
586  */
588  natsemi->regs + NATSEMI_IMR );
589 
590  /* Update link state */
592 
593  return 0;
594 
595  natsemi_destroy_ring ( natsemi, &natsemi->rx );
596  err_create_rx:
597  natsemi_destroy_ring ( natsemi, &natsemi->tx );
598  err_create_tx:
599  return rc;
600 }
601 
602 /**
603  * Close network device
604  *
605  * @v netdev Network device
606  */
607 static void natsemi_close ( struct net_device *netdev ) {
608  struct natsemi_nic *natsemi = netdev->priv;
609  unsigned int i;
610 
611  /* Mask transmit and receive interrupts */
612  writel ( 0, natsemi->regs + NATSEMI_IMR );
613 
614  /* Reset and disable transmitter and receiver */
616  natsemi->regs + NATSEMI_CR );
617 
618  /* Discard any unused receive buffers */
619  for ( i = 0 ; i < NATSEMI_NUM_RX_DESC ; i++ ) {
620  if ( natsemi->rx_iobuf[i] )
621  free_iob ( natsemi->rx_iobuf[i] );
622  natsemi->rx_iobuf[i] = NULL;
623  }
624 
625  /* Destroy receive descriptor ring */
626  natsemi_destroy_ring ( natsemi, &natsemi->rx );
627 
628  /* Destroy transmit descriptor ring */
629  natsemi_destroy_ring ( natsemi, &natsemi->tx );
630 }
631 
632 /**
633  * Transmit packet
634  *
635  * @v netdev Network device
636  * @v iobuf I/O buffer
637  * @ret rc Return status code
638  */
639 static int natsemi_transmit ( struct net_device *netdev,
640  struct io_buffer *iobuf ) {
641  struct natsemi_nic *natsemi = netdev->priv;
642  union natsemi_descriptor *tx;
643  unsigned int tx_idx;
645 
646  /* Check address is usable by card */
647  address = virt_to_bus ( iobuf->data );
648  if ( ! natsemi_address_ok ( natsemi, address ) ) {
649  DBGC ( natsemi, "NATSEMI %p cannot support 64-bit TX buffer "
650  "address\n", natsemi );
651  return -ENOTSUP;
652  }
653 
654  /* Get next transmit descriptor */
655  if ( ( natsemi->tx.prod - natsemi->tx.cons ) >= NATSEMI_NUM_TX_DESC ) {
656  DBGC ( natsemi, "NATSEMI %p out of transmit descriptors\n",
657  natsemi );
658  return -ENOBUFS;
659  }
660  tx_idx = ( natsemi->tx.prod++ % NATSEMI_NUM_TX_DESC );
661  tx = &natsemi->tx.desc[tx_idx];
662 
663  /* Populate transmit descriptor */
664  if ( natsemi->flags & NATSEMI_64BIT ) {
665  tx->d64.bufptr = cpu_to_le64 ( address );
666  } else {
667  tx->d32pad.d32.bufptr = cpu_to_le32 ( address );
668  }
669  wmb();
670  tx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_OWN | NATSEMI_DESC_INTR |
671  iob_len ( iobuf ) );
672  wmb();
673 
674  /* Notify card that there are packets ready to transmit */
675  writel ( NATSEMI_CR_TXE, natsemi->regs + NATSEMI_CR );
676 
677  DBGC2 ( natsemi, "NATSEMI %p TX %d is [%llx,%llx)\n", natsemi, tx_idx,
678  ( ( unsigned long long ) address ),
679  ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
680 
681  return 0;
682 }
683 
684 /**
685  * Poll for completed packets
686  *
687  * @v netdev Network device
688  */
689 static void natsemi_poll_tx ( struct net_device *netdev ) {
690  struct natsemi_nic *natsemi = netdev->priv;
691  union natsemi_descriptor *tx;
692  unsigned int tx_idx;
693 
694  /* Check for completed packets */
695  while ( natsemi->tx.cons != natsemi->tx.prod ) {
696 
697  /* Get next transmit descriptor */
698  tx_idx = ( natsemi->tx.cons % NATSEMI_NUM_TX_DESC );
699  tx = &natsemi->tx.desc[tx_idx];
700 
701  /* Stop if descriptor is still in use */
702  if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OWN ) )
703  return;
704 
705  /* Complete TX descriptor */
706  if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
707  DBGC2 ( natsemi, "NATSEMI %p TX %d complete\n",
708  natsemi, tx_idx );
710  } else {
711  DBGC ( natsemi, "NATSEMI %p TX %d completion error "
712  "(%08x)\n", natsemi, tx_idx,
713  le32_to_cpu ( tx->common.cmdsts ) );
715  }
716  natsemi->tx.cons++;
717  }
718 }
719 
720 /**
721  * Poll for received packets
722  *
723  * @v netdev Network device
724  */
725 static void natsemi_poll_rx ( struct net_device *netdev ) {
726  struct natsemi_nic *natsemi = netdev->priv;
727  union natsemi_descriptor *rx;
728  struct io_buffer *iobuf;
729  unsigned int rx_idx;
730  size_t len;
731 
732  /* Check for received packets */
733  while ( natsemi->rx.cons != natsemi->rx.prod ) {
734 
735  /* Get next receive descriptor */
736  rx_idx = ( natsemi->rx.cons % NATSEMI_NUM_RX_DESC );
737  rx = &natsemi->rx.desc[rx_idx];
738 
739  /* Stop if descriptor is still in use */
740  if ( ! ( rx->common.cmdsts & NATSEMI_DESC_OWN ) )
741  return;
742 
743  /* Populate I/O buffer */
744  iobuf = natsemi->rx_iobuf[rx_idx];
745  natsemi->rx_iobuf[rx_idx] = NULL;
746  len = ( le32_to_cpu ( rx->common.cmdsts ) &
748  iob_put ( iobuf, len - 4 /* strip CRC */ );
749 
750  /* Hand off to network stack */
751  if ( rx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
752  DBGC2 ( natsemi, "NATSEMI %p RX %d complete (length "
753  "%zd)\n", natsemi, rx_idx, len );
754  netdev_rx ( netdev, iobuf );
755  } else {
756  DBGC ( natsemi, "NATSEMI %p RX %d error (length %zd, "
757  "status %08x)\n", natsemi, rx_idx, len,
758  le32_to_cpu ( rx->common.cmdsts ) );
759  netdev_rx_err ( netdev, iobuf, -EIO );
760  }
761  natsemi->rx.cons++;
762  }
763 }
764 
765 /**
766  * Poll for completed and received packets
767  *
768  * @v netdev Network device
769  */
770 static void natsemi_poll ( struct net_device *netdev ) {
771  struct natsemi_nic *natsemi = netdev->priv;
772  uint32_t isr;
773 
774  /* Poll for link state. The PHY interrupt seems not to
775  * function as expected, and polling for the link state is
776  * only a single register read.
777  */
779 
780  /* Check for and acknowledge interrupts */
781  isr = readl ( natsemi->regs + NATSEMI_ISR );
782  if ( ! isr )
783  return;
784 
785  /* Poll for TX completions, if applicable */
786  if ( isr & NATSEMI_IRQ_TXDESC )
788 
789  /* Poll for RX completionsm, if applicable */
790  if ( isr & NATSEMI_IRQ_RXDESC )
792 
793  /* Refill RX ring */
795 }
796 
797 /**
798  * Enable or disable interrupts
799  *
800  * @v netdev Network device
801  * @v enable Interrupts should be enabled
802  */
803 static void natsemi_irq ( struct net_device *netdev, int enable ) {
804  struct natsemi_nic *natsemi = netdev->priv;
805 
806  /* Enable or disable interrupts */
807  writel ( ( enable ? NATSEMI_IER_IE : 0 ), natsemi->regs + NATSEMI_IER );
808 }
809 
810 /** National Semiconductor network device operations */
812  .open = natsemi_open,
813  .close = natsemi_close,
814  .transmit = natsemi_transmit,
815  .poll = natsemi_poll,
816  .irq = natsemi_irq,
817 };
818 
819 /******************************************************************************
820  *
821  * PCI interface
822  *
823  ******************************************************************************
824  */
825 
826 /**
827  * Probe PCI device
828  *
829  * @v pci PCI device
830  * @ret rc Return status code
831  */
832 static int natsemi_probe ( struct pci_device *pci ) {
833  struct net_device *netdev;
834  struct natsemi_nic *natsemi;
835  int rc;
836 
837  /* Allocate and initialise net device */
838  netdev = alloc_etherdev ( sizeof ( *natsemi ) );
839  if ( ! netdev ) {
840  rc = -ENOMEM;
841  goto err_alloc;
842  }
844  natsemi = netdev->priv;
845  pci_set_drvdata ( pci, netdev );
846  netdev->dev = &pci->dev;
847  memset ( natsemi, 0, sizeof ( *natsemi ) );
848  natsemi->flags = pci->id->driver_data;
849  natsemi_init_ring ( &natsemi->tx, NATSEMI_NUM_TX_DESC, NATSEMI_TXDP );
850  natsemi_init_ring ( &natsemi->rx, NATSEMI_NUM_RX_DESC, NATSEMI_RXDP );
851 
852  /* Fix up PCI device */
853  adjust_pci_device ( pci );
854 
855  /* Map registers */
856  natsemi->regs = ioremap ( pci->membase, NATSEMI_BAR_SIZE );
857  if ( ! natsemi->regs ) {
858  rc = -ENODEV;
859  goto err_ioremap;
860  }
861 
862  /* Reset the NIC */
863  if ( ( rc = natsemi_reset ( natsemi ) ) != 0 )
864  goto err_reset;
865 
866  /* Initialise EEPROM */
867  natsemi_init_eeprom ( natsemi );
868 
869  /* Read initial MAC address */
870  if ( ( rc = natsemi_hwaddr ( natsemi, netdev->hw_addr ) ) != 0 )
871  goto err_hwaddr;
872 
873  /* Register network device */
874  if ( ( rc = register_netdev ( netdev ) ) != 0 )
875  goto err_register_netdev;
876 
877  /* Set initial link state */
879 
880  return 0;
881 
883  err_register_netdev:
884  err_hwaddr:
885  natsemi_reset ( natsemi );
886  err_reset:
887  iounmap ( natsemi->regs );
888  err_ioremap:
890  netdev_put ( netdev );
891  err_alloc:
892  return rc;
893 }
894 
895 /**
896  * Remove PCI device
897  *
898  * @v pci PCI device
899  */
900 static void natsemi_remove ( struct pci_device *pci ) {
901  struct net_device *netdev = pci_get_drvdata ( pci );
902  struct natsemi_nic *natsemi = netdev->priv;
903 
904  /* Unregister network device */
906 
907  /* Reset card */
908  natsemi_reset ( natsemi );
909 
910  /* Free network device */
911  iounmap ( natsemi->regs );
913  netdev_put ( netdev );
914 }
915 
916 /** Flags for DP83815 */
917 #define DP83815_FLAGS ( NATSEMI_EEPROM_LITTLE_ENDIAN | NATSEMI_EEPROM_INSANE )
918 
919 /** Flags for DP83820 */
920 #define DP83820_FLAGS ( NATSEMI_64BIT | NATSEMI_1000 )
921 
922 /** National Semiconductor PCI device IDs */
923 static struct pci_device_id natsemi_nics[] = {
924  PCI_ROM ( 0x100b, 0x0020, "dp83815", "DP83815", DP83815_FLAGS ),
925  PCI_ROM ( 0x100b, 0x0022, "dp83820", "DP83820", DP83820_FLAGS ),
926 };
927 
928 /** National Semiconductor PCI driver */
929 struct pci_driver natsemi_driver __pci_driver = {
930  .ids = natsemi_nics,
931  .id_count = ( sizeof ( natsemi_nics ) / sizeof ( natsemi_nics[0] ) ),
932  .probe = natsemi_probe,
934 };
struct natsemi_descriptor_32 d32
Descriptor.
Definition: natsemi.h:22
#define NATSEMI_ISR
Interrupt Status Register.
Definition: natsemi.h:127
unsigned int prod
Producer index.
Definition: natsemi.h:258
#define NATSEMI_CR_TXE
Transmit enable.
Definition: natsemi.h:88
#define NATSEMI_MEAR_EECLK
EEPROM serial clock.
Definition: natsemi.h:106
struct bit_basher basher
Bit-bashing interface.
Definition: spi_bit.h:20
unsigned long membase
Memory base.
Definition: pci.h:194
#define NATSEMI_CFG
Configuration and Media Status Register.
Definition: natsemi.h:94
#define NATSEMI_RXDP
Receive Descriptor Pointer.
Definition: natsemi.h:186
struct natsemi_ring rx
Receive descriptor ring.
Definition: natsemi.h:296
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
wmb()
#define iob_put(iobuf, len)
Definition: iobuf.h:116
#define NATSEMI_CFG_MODE_1000
1000 Mb/s mode control
Definition: natsemi.h:97
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:501
static struct bit_basher_operations natsemi_basher_ops
SPI bit-bashing interface.
Definition: natsemi.c:109
Card supports 64-bit operation.
Definition: natsemi.h:248
struct natsemi_ring tx
Transmit descriptor ring.
Definition: natsemi.h:294
A PCI driver.
Definition: pci.h:224
#define DBGLVL_IO
Definition: compiler.h:322
#define NATSEMI_TXCFG_MXDMA_DEFAULT
Max DMA burst size (encoded value)
Definition: natsemi.h:165
Packet OK.
Definition: natsemi.h:79
#define DP83820_FLAGS
Flags for DP83820.
Definition: natsemi.c:920
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
#define NATSEMI_MEAR
EEPROM Access Register.
Definition: natsemi.h:104
Error codes.
#define NATSEMI_IMR
Interrupt Mask Register.
Definition: natsemi.h:132
Bit-bashing operations.
Definition: bitbash.h:15
unsigned int cons
Consumer index.
Definition: natsemi.h:260
SPI bit-bashing interface.
static struct pci_device_id natsemi_nics[]
National Semiconductor PCI device IDs.
Definition: natsemi.c:923
#define DP83815_FLAGS
Flags for DP83815.
Definition: natsemi.c:917
unsigned long driver_data
Arbitrary driver data.
Definition: pci.h:159
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:758
I/O buffers.
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
#define DBG_ENABLE(level)
Definition: compiler.h:313
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:226
uint64_t address
Base address.
Definition: ena.h:24
FILE_LICENCE(GPL2_OR_LATER)
#define NATSEMI_RXCFG_ARP
Accept runt packets.
Definition: natsemi.h:202
#define NATSEMI_TXCFG_ATP
Automatic padding.
Definition: natsemi.h:154
static int natsemi_create_ring(struct natsemi_nic *natsemi, struct natsemi_ring *ring)
Create descriptor ring.
Definition: natsemi.c:392
National Semiconductor "MacPhyter" network card driver.
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define DBGC(...)
Definition: compiler.h:505
#define NATSEMI_EEPROM_SIZE
Size of EEPROM (in bytes)
Definition: natsemi.h:111
static void natsemi_hwaddr_sane(struct natsemi_nic *natsemi, const uint16_t *eeprom, uint16_t *hw_addr)
Get hardware address from sane EEPROM data.
Definition: natsemi.c:141
static int natsemi_reload_config(struct natsemi_nic *natsemi)
Reload configuration from EEPROM.
Definition: natsemi.c:249
#define NATSEMI_RFCR
Receive Filter/Match Control Register.
Definition: natsemi.h:225
unsigned long long uint64_t
Definition: stdint.h:13
#define DBG_DISABLE(level)
Definition: compiler.h:312
#define NATSEMI_CFG_SPDSTS1
Speed status bit 1.
Definition: natsemi.h:96
#define NATSEMI_EELOAD_MAX_WAIT_MS
Maximum time to wait for a configuration reload, in milliseconds.
Definition: natsemi.h:124
#define NATSEMI_NUM_TX_DESC
Number of transmit descriptors.
Definition: natsemi.h:145
#define NATSEMI_RFDR_BMASK
Byte mask.
Definition: natsemi.h:238
Non-volatile storage.
#define cpu_to_le64(value)
Definition: byteswap.h:108
void netdev_tx_complete_next_err(struct net_device *netdev, int rc)
Complete network transmission.
Definition: netdevice.c:434
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
uint32_t cfg
Link status (cache)
Definition: natsemi.h:301
#define NATSEMI_TXCFG_FLTH_DEFAULT
Fill threshold (in units of 32 bytes)
Definition: natsemi.h:172
#define NATSEMI_RXCFG_DRTH_DEFAULT
Drain threshold (in units of 8 bytes)
Definition: natsemi.h:222
#define offsetof(type, field)
Get offset of a field within a structure.
Definition: stddef.h:24
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define NATSEMI_CR_RXR
Receiver reset.
Definition: natsemi.h:85
static struct net_device_operations natsemi_operations
National Semiconductor network device operations.
Definition: natsemi.c:811
Master In Slave Out.
Definition: spi_bit.h:39
#define NATSEMI_TXCFG_DRTH_DEFAULT
Drain threshold (in units of 32 bytes)
Definition: natsemi.h:183
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct bit_basher_operations * op
Bit-bashing operations.
Definition: bitbash.h:57
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
struct device dev
Generic device.
Definition: pci.h:189
struct spi_device eeprom
EEPROM.
Definition: natsemi.h:291
static void natsemi_hwaddr_insane(struct natsemi_nic *natsemi, const uint16_t *eeprom, uint16_t *hw_addr)
Get hardware address from insane EEPROM data.
Definition: natsemi.c:159
unsigned int mode
SPI interface mode.
Definition: spi.h:136
#define ENOTSUP
Operation not supported.
Definition: errno.h:589
Dynamic memory allocation.
#define NATSEMI_IRQ_TXDESC
TX descriptor.
Definition: natsemi.h:128
#define NATSEMI_IER_IE
Interrupt enable.
Definition: natsemi.h:136
#define NATSEMI_TXCFG_64
Transmit configuration register (64-bit)
Definition: natsemi.h:151
eeprom
Definition: 3c90x.h:232
#define NATSEMI_PTSCR_EELOAD_EN
Enable EEPROM load.
Definition: natsemi.h:121
#define NATSEMI_TXCFG_CSI
Carrier sense ignore.
Definition: natsemi.h:152
#define NATSEMI_RFCR_RFEN
RX filter enable.
Definition: natsemi.h:226
A packet descriptor.
Definition: natsemi.h:48
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:498
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:338
#define NATSEMI_TXDP
Transmit Descriptor Pointer.
Definition: natsemi.h:139
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define NATSEMI_IER
Interrupt Enable Register.
Definition: natsemi.h:135
static void natsemi_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: natsemi.c:725
union natsemi_descriptor * desc
Descriptors.
Definition: natsemi.h:256
Three-wire serial interface.
#define NATSEMI_MEAR_EEDO
EEPROM data out.
Definition: natsemi.h:107
static void natsemi_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: natsemi.c:770
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define NATSEMI_MEAR_EESEL
EEPROM chip select.
Definition: natsemi.h:105
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:555
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
Ethernet protocol.
static void natsemi_remove(struct pci_device *pci)
Remove PCI device.
Definition: natsemi.c:900
#define NATSEMI_RFDR
Receive Filter/Match Data Register.
Definition: natsemi.h:237
Definition: sis900.h:36
void * priv
Driver private data.
Definition: netdevice.h:425
#define NATSEMI_RXCFG_32
Receive configuration register (32-bit)
Definition: natsemi.h:198
static void natsemi_irq(struct net_device *netdev, int enable)
Enable or disable interrupts.
Definition: natsemi.c:803
void init_spi_bit_basher(struct spi_bit_basher *spibit)
Initialise SPI bit-bashing interface.
Definition: spi_bit.c:235
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:768
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
Bit-bashing interfaces.
unsigned int count
Number of descriptors.
Definition: natsemi.h:263
Master Out Slave In.
Definition: spi_bit.h:37
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
static struct net_device * netdev
Definition: gdbudp.c:52
uint64_t link
Link to next descriptor.
Definition: natsemi.h:32
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:68
#define NATSEMI_RFCR_RFADDR_MASK
Definition: natsemi.h:231
unsigned int flags
Flags.
Definition: natsemi.h:285
Definition: sis900.h:26
static int natsemi_hwaddr(struct natsemi_nic *natsemi, void *hw_addr)
Get hardware address from EEPROM.
Definition: natsemi.c:184
unsigned int reg
Descriptor start address register.
Definition: natsemi.h:265
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:844
uint32_t link
Link to next descriptor.
Definition: natsemi.h:22
static int natsemi_spi_read_bit(struct bit_basher *basher, unsigned int bit_id)
Read input bit.
Definition: natsemi.c:73
uint32_t rx
Maximum number of receive queues.
Definition: intelvf.h:16
#define cpu_to_le32(value)
Definition: byteswap.h:107
static void natsemi_refill_rx(struct net_device *netdev)
Refill receive descriptor ring.
Definition: natsemi.c:490
#define NATSEMI_EEPROM_MAC_INSANE
Word offset of MAC address within insane EEPROM layout.
Definition: natsemi.h:117
#define DBGC2_HDA(...)
Definition: compiler.h:523
int(* read)(struct bit_basher *basher, unsigned int bit_id)
Read input bit.
Definition: bitbash.h:51
A bit-bashing interface.
Definition: bitbash.h:55
#define NATSEMI_CR_TXR
Transmit reset.
Definition: natsemi.h:86
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
struct spi_bit_basher spibit
SPI bit-bashing interface.
Definition: natsemi.h:289
#define NATSEMI_RFCR_AAU
Accept all unicast.
Definition: natsemi.h:229
#define NATSEMI_RXCFG_ATX
Accept transmit packets.
Definition: natsemi.h:203
uint32_t tx
Maximum number of transmit queues.
Definition: intelvf.h:14
static unsigned int unsigned int reg
Definition: intel.h:245
#define NATSEMI_CR
Command Register.
Definition: natsemi.h:83
PCI bus.
A PCI device.
Definition: pci.h:187
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:667
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
#define NATSEMI_PTSCR
PCI Test Control Register.
Definition: natsemi.h:120
Serial clock.
Definition: spi_bit.h:35
static int natsemi_probe(struct pci_device *pci)
Probe PCI device.
Definition: natsemi.c:832
A network device.
Definition: netdevice.h:348
EEPROM layout is insane.
Definition: natsemi.h:246
static void natsemi_check_link(struct net_device *netdev)
Check link state.
Definition: natsemi.c:320
#define ENODEV
No such device.
Definition: errno.h:509
#define SPI_BIT_SS(slave)
Determine bit index for a particular slave.
Definition: spi_bit.h:50
#define NATSEMI_TXCFG_ECRETRY
Excess collision retry.
Definition: natsemi.h:155
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:511
A National Semiconductor descriptor ring.
Definition: natsemi.h:254
unsigned char uint8_t
Definition: stdint.h:10
static void natsemi_destroy_ring(struct natsemi_nic *natsemi, struct natsemi_ring *ring)
Destroy descriptor ring.
Definition: natsemi.c:469
#define NATSEMI_RXCFG_ALP
Accept long packets.
Definition: natsemi.h:204
struct natsemi_descriptor_64 d64
64-bit descriptor
Definition: natsemi.h:59
#define ETH_ALEN
Definition: if_ether.h:8
#define NATSEMI_MEAR_EEDI
EEPROM data in.
Definition: natsemi.h:108
struct natsemi_descriptor_32 d32
Descriptor.
Definition: natsemi.h:65
A PCI device ID list entry.
Definition: pci.h:151
#define le16_to_cpu(value)
Definition: byteswap.h:112
unsigned int uint32_t
Definition: stdint.h:12
static void natsemi_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: natsemi.c:689
static const uint8_t natsemi_eeprom_bits[]
Pin mapping for SPI bit-bashing interface.
Definition: natsemi.c:58
Card supports 1000Mbps link.
Definition: natsemi.h:250
struct spi_bus bus
SPI bus.
Definition: spi_bit.h:18
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static int natsemi_open(struct net_device *netdev)
Open network device.
Definition: natsemi.c:549
Network device operations.
Definition: netdevice.h:213
void * regs
Registers.
Definition: natsemi.h:287
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
static int natsemi_reset(struct natsemi_nic *natsemi)
Reset hardware.
Definition: natsemi.c:279
#define NATSEMI_RFCR_AAB
Accept all broadcast.
Definition: natsemi.h:227
Network device management.
#define SPI_BIT_BIG_ENDIAN
SPI bit basher treats data as big-endian.
Definition: spi_bit.h:56
unsigned long physaddr_t
Definition: stdint.h:20
struct nvs_device nvs
NVS device.
Definition: spi.h:88
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:348
#define NATSEMI_BAR_SIZE
BAR size.
Definition: natsemi.h:17
struct pci_driver natsemi_driver __pci_driver
National Semiconductor PCI driver.
Definition: natsemi.c:929
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
Definition: sis900.h:23
EEPROM is little-endian.
Definition: natsemi.h:244
Descriptor is owned by NIC.
Definition: natsemi.h:75
#define NATSEMI_TXCFG_HBI
Heartbeat ignore.
Definition: natsemi.h:153
#define NATSEMI_CR_RST
Reset.
Definition: natsemi.h:84
#define NATSEMI_RX_MAX_LEN
Receive buffer length.
Definition: natsemi.h:195
uint32_t len
Length.
Definition: ena.h:14
static void natsemi_pmatch(struct natsemi_nic *natsemi, const void *mac)
Set perfect match filter address.
Definition: natsemi.c:364
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
#define NATSEMI_TXCFG_32
Transmit configuration register (32-bit)
Definition: natsemi.h:148
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:237
static int natsemi_soft_reset(struct natsemi_nic *natsemi)
Reset controller chip.
Definition: natsemi.c:221
static void natsemi_init_eeprom(struct natsemi_nic *natsemi)
Initialise EEPROM.
Definition: natsemi.c:119
void * data
Start of data.
Definition: iobuf.h:44
#define EIO
Input/output error.
Definition: errno.h:433
struct spi_bus * bus
SPI bus to which device is attached.
Definition: spi.h:90
static void natsemi_spi_write_bit(struct bit_basher *basher, unsigned int bit_id, unsigned long data)
Set/clear output bit.
Definition: natsemi.c:93
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
#define SPI_BIT_LITTLE_ENDIAN
SPI bit basher treats data as little-endian.
Definition: spi_bit.h:59
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
struct pci_device_id * id
Driver device ID.
Definition: pci.h:220
#define NATSEMI_CFG_EXTSTS_EN
Extended status enable.
Definition: natsemi.h:101
#define cpu_to_le16(value)
Definition: byteswap.h:106
unsigned short word
Definition: smc9000.h:39
#define NATSEMI_CR_RXE
Receiver enable.
Definition: natsemi.h:87
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define NATSEMI_RXCFG_64
Receive configuration register (64-bit)
Definition: natsemi.h:201
static int natsemi_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: natsemi.c:639
#define NATSEMI_CFG_PCI64_DET
PCI 64-bit bus detected.
Definition: natsemi.h:98
#define NATSEMI_CFG_M64ADDR
64-bit address enable
Definition: natsemi.h:100
int nvs_read(struct nvs_device *nvs, unsigned int address, void *data, size_t len)
Read from non-volatile storage device.
Definition: nvs.c:75
#define NATSEMI_RFADDR_PMATCH_BASE
Perfect match filter address base.
Definition: natsemi.h:234
static void natsemi_close(struct net_device *netdev)
Close network device.
Definition: natsemi.c:607
#define NATSEMI_IRQ_RXDESC
RX descriptor.
Definition: natsemi.h:129
#define NATSEMI_RXCFG_MXDMA_DEFAULT
Max DMA burst size (encoded value)
Definition: natsemi.h:213
#define SPI_MODE_THREEWIRE
Threewire-compatible mode.
Definition: spi.h:199
#define NATSEMI_RESET_MAX_WAIT_MS
Maximum time to wait for a reset, in milliseconds.
Definition: natsemi.h:91
#define NATSEMI_EEPROM_MAC_SANE
Word offset of MAC address within sane EEPROM layout.
Definition: natsemi.h:114
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:381
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
Request descriptor interrupt.
Definition: natsemi.h:77
#define NATSEMI_RFCR_AAM
Accept all multicast.
Definition: natsemi.h:228
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
#define NATSEMI_DESC_SIZE_MASK
Descriptor buffer size mask.
Definition: natsemi.h:70
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:375
struct io_buffer * rx_iobuf[NATSEMI_NUM_RX_DESC]
Receive I/O buffers.
Definition: natsemi.h:298
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
String functions.
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define NATSEMI_CFG_LNKSTS
Link status.
Definition: natsemi.h:95
#define NATSEMI_RFCR_RFADDR(addr)
Extended address.
Definition: natsemi.h:230
A National Semiconductor network card.
Definition: natsemi.h:283
#define NATSEMI_CFG_DATA64_EN
64-bit data enable
Definition: natsemi.h:99
#define NATSEMI_NUM_RX_DESC
Number of receive descriptors.
Definition: natsemi.h:192
void * memset(void *dest, int character, size_t len) __nonnull
A persistent I/O buffer.
Definition: iobuf.h:32
int endianness
Endianness of data.
Definition: spi_bit.h:29