iPXE
qib7322.c
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1/*
2 * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17 * 02110-1301, USA.
18 *
19 * You can also choose to distribute this program under the terms of
20 * the Unmodified Binary Distribution Licence (as given in the file
21 * COPYING.UBDL), provided that you have satisfied its requirements.
22 */
23
24FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25
26#include <stdint.h>
27#include <stdlib.h>
28#include <string.h>
29#include <errno.h>
30#include <unistd.h>
31#include <assert.h>
32#include <ipxe/io.h>
33#include <ipxe/pci.h>
34#include <ipxe/infiniband.h>
35#include <ipxe/i2c.h>
36#include <ipxe/bitbash.h>
37#include <ipxe/malloc.h>
38#include <ipxe/iobuf.h>
39#include <ipxe/pcibackup.h>
40#include "qib7322.h"
41
42/**
43 * @file
44 *
45 * QLogic QIB7322 Infiniband HCA
46 *
47 */
48
49/** A QIB7322 send buffer set */
50struct qib7322_send_buffers {
51 /** Offset within register space of the first send buffer */
52 unsigned long base;
53 /** Send buffer size */
54 unsigned int size;
55 /** Index of first send buffer */
56 unsigned int start;
57 /** Number of send buffers
58 *
59 * Must be a power of two.
60 */
61 unsigned int count;
62 /** Send buffer availability producer counter */
63 unsigned int prod;
64 /** Send buffer availability consumer counter */
65 unsigned int cons;
66 /** Send buffer availability */
67 uint16_t avail[0];
68};
69
70/** A QIB7322 send work queue */
71struct qib7322_send_work_queue {
72 /** Send buffer set */
73 struct qib7322_send_buffers *send_bufs;
74 /** Send buffer usage */
75 uint16_t *used;
76 /** Producer index */
77 unsigned int prod;
78 /** Consumer index */
79 unsigned int cons;
80};
81
82/** A QIB7322 receive work queue */
83struct qib7322_recv_work_queue {
84 /** Receive header ring */
85 void *header;
86 /** Receive header producer offset (written by hardware) */
87 struct QIB_7322_scalar header_prod;
88 /** Receive header consumer offset */
89 unsigned int header_cons;
90 /** Offset within register space of the eager array */
91 unsigned long eager_array;
92 /** Number of entries in eager array */
93 unsigned int eager_entries;
94 /** Eager array producer index */
95 unsigned int eager_prod;
96 /** Eager array consumer index */
97 unsigned int eager_cons;
98};
99
100/** A QIB7322 HCA */
101struct qib7322 {
102 /** Registers */
103 void *regs;
104
105 /** In-use contexts */
106 uint8_t used_ctx[QIB7322_NUM_CONTEXTS];
107 /** Send work queues */
108 struct qib7322_send_work_queue send_wq[QIB7322_NUM_CONTEXTS];
109 /** Receive work queues */
110 struct qib7322_recv_work_queue recv_wq[QIB7322_NUM_CONTEXTS];
111
112 /** Send buffer availability (reported by hardware) */
113 struct QIB_7322_SendBufAvail *sendbufavail;
114 /** Small send buffers */
115 struct qib7322_send_buffers *send_bufs_small;
116 /** VL15 port 0 send buffers */
117 struct qib7322_send_buffers *send_bufs_vl15_port0;
118 /** VL15 port 1 send buffers */
119 struct qib7322_send_buffers *send_bufs_vl15_port1;
120
121 /** I2C bit-bashing interface */
122 struct i2c_bit_basher i2c;
123 /** I2C serial EEPROM */
124 struct i2c_device eeprom;
125
126 /** Base GUID */
127 union ib_guid guid;
128 /** Infiniband devices */
129 struct ib_device *ibdev[QIB7322_MAX_PORTS];
130};
131
132/***************************************************************************
133 *
134 * QIB7322 register access
135 *
136 ***************************************************************************
137 *
138 * This card requires atomic 64-bit accesses. Strange things happen
139 * if you try to use 32-bit accesses; sometimes they work, sometimes
140 * they don't, sometimes you get random data.
141 */
142
143/**
144 * Read QIB7322 qword register
145 *
146 * @v qib7322 QIB7322 device
147 * @v qword Register buffer to read into
148 * @v offset Register offset
149 */
150static void qib7322_readq ( struct qib7322 *qib7322, uint64_t *qword,
151 unsigned long offset ) {
152 *qword = readq ( qib7322->regs + offset );
153}
154#define qib7322_readq( _qib7322, _ptr, _offset ) \
155 qib7322_readq ( (_qib7322), (_ptr)->u.qwords, (_offset) )
156#define qib7322_readq_array8b( _qib7322, _ptr, _offset, _idx ) \
157 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
158#define qib7322_readq_array64k( _qib7322, _ptr, _offset, _idx ) \
159 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ) )
160#define qib7322_readq_port( _qib7322, _ptr, _offset, _port ) \
161 qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ) )
162
163/**
164 * Write QIB7322 qword register
165 *
166 * @v qib7322 QIB7322 device
167 * @v qword Register buffer to write
168 * @v offset Register offset
169 */
170static void qib7322_writeq ( struct qib7322 *qib7322, const uint64_t *qword,
171 unsigned long offset ) {
172 writeq ( *qword, ( qib7322->regs + offset ) );
173}
174#define qib7322_writeq( _qib7322, _ptr, _offset ) \
175 qib7322_writeq ( (_qib7322), (_ptr)->u.qwords, (_offset) )
176#define qib7322_writeq_array8b( _qib7322, _ptr, _offset, _idx ) \
177 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
178#define qib7322_writeq_array64k( _qib7322, _ptr, _offset, _idx ) \
179 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ))
180#define qib7322_writeq_port( _qib7322, _ptr, _offset, _port ) \
181 qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ))
182
183/**
184 * Write QIB7322 dword register
185 *
186 * @v qib7322 QIB7322 device
187 * @v dword Value to write
188 * @v offset Register offset
189 */
190static void qib7322_writel ( struct qib7322 *qib7322, uint32_t dword,
191 unsigned long offset ) {
192 writel ( dword, ( qib7322->regs + offset ) );
193}
194
195/***************************************************************************
196 *
197 * Link state management
198 *
199 ***************************************************************************
200 */
201
202/**
203 * Textual representation of link state
204 *
205 * @v link_state Link state
206 * @ret link_text Link state text
207 */
208static const char * qib7322_link_state_text ( unsigned int link_state ) {
209 switch ( link_state ) {
210 case QIB7322_LINK_STATE_DOWN: return "DOWN";
211 case QIB7322_LINK_STATE_INIT: return "INIT";
212 case QIB7322_LINK_STATE_ARM: return "ARM";
213 case QIB7322_LINK_STATE_ACTIVE: return "ACTIVE";
214 case QIB7322_LINK_STATE_ACT_DEFER: return "ACT_DEFER";
215 default: return "UNKNOWN";
216 }
217}
218
219/**
220 * Handle link state change
221 *
222 * @v qib7322 QIB7322 device
223 */
224static void qib7322_link_state_changed ( struct ib_device *ibdev ) {
225 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
226 struct QIB_7322_IBCStatusA_0 ibcstatusa;
227 struct QIB_7322_EXTCtrl extctrl;
228 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
229 unsigned int link_training_state;
230 unsigned int link_state;
231 unsigned int link_width;
232 unsigned int link_speed;
233 unsigned int link_speed_qdr;
234 unsigned int green;
235 unsigned int yellow;
236
237 /* Read link state */
238 qib7322_readq_port ( qib7322, &ibcstatusa,
239 QIB_7322_IBCStatusA_0_offset, port );
240 link_training_state = BIT_GET ( &ibcstatusa, LinkTrainingState );
241 link_state = BIT_GET ( &ibcstatusa, LinkState );
242 link_width = BIT_GET ( &ibcstatusa, LinkWidthActive );
243 link_speed = BIT_GET ( &ibcstatusa, LinkSpeedActive );
244 link_speed_qdr = BIT_GET ( &ibcstatusa, LinkSpeedQDR );
245 DBGC ( qib7322, "QIB7322 %p port %d training state %#x link state %s "
246 "(%s %s)\n", qib7322, port, link_training_state,
247 qib7322_link_state_text ( link_state ),
248 ( link_speed_qdr ? "QDR" : ( link_speed ? "DDR" : "SDR" ) ),
249 ( link_width ? "x4" : "x1" ) );
250
251 /* Set LEDs according to link state */
252 qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
253 green = ( ( link_state >= QIB7322_LINK_STATE_INIT ) ? 1 : 0 );
254 yellow = ( ( link_state >= QIB7322_LINK_STATE_ACTIVE ) ? 1 : 0 );
255 if ( port == 0 ) {
256 BIT_SET ( &extctrl, LEDPort0GreenOn, green );
257 BIT_SET ( &extctrl, LEDPort0YellowOn, yellow );
258 } else {
259 BIT_SET ( &extctrl, LEDPort1GreenOn, green );
260 BIT_SET ( &extctrl, LEDPort1YellowOn, yellow );
261 }
262 qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
263
264 /* Notify Infiniband core of link state change */
265 ibdev->port_state = ( link_state + 1 );
266 ibdev->link_width_active =
267 ( link_width ? IB_LINK_WIDTH_4X : IB_LINK_WIDTH_1X );
268 ibdev->link_speed_active =
269 ( link_speed ? IB_LINK_SPEED_DDR : IB_LINK_SPEED_SDR );
270 ib_link_state_changed ( ibdev );
271}
272
273/**
274 * Wait for link state change to take effect
275 *
276 * @v ibdev Infiniband device
277 * @v new_link_state Expected link state
278 * @ret rc Return status code
279 */
280static int qib7322_link_state_check ( struct ib_device *ibdev,
281 unsigned int new_link_state ) {
282 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
283 struct QIB_7322_IBCStatusA_0 ibcstatusa;
284 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
285 unsigned int link_state;
286 unsigned int i;
287
288 for ( i = 0 ; i < QIB7322_LINK_STATE_MAX_WAIT_US ; i++ ) {
289 qib7322_readq_port ( qib7322, &ibcstatusa,
290 QIB_7322_IBCStatusA_0_offset, port );
291 link_state = BIT_GET ( &ibcstatusa, LinkState );
292 if ( link_state == new_link_state )
293 return 0;
294 udelay ( 1 );
295 }
296
297 DBGC ( qib7322, "QIB7322 %p port %d timed out waiting for link state "
298 "%s\n", qib7322, port, qib7322_link_state_text ( link_state ) );
299 return -ETIMEDOUT;
300}
301
302/**
303 * Set port information
304 *
305 * @v ibdev Infiniband device
306 * @v mad Set port information MAD
307 */
308static int qib7322_set_port_info ( struct ib_device *ibdev,
309 union ib_mad *mad ) {
310 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
311 struct ib_port_info *port_info = &mad->smp.smp_data.port_info;
312 struct QIB_7322_IBCCtrlA_0 ibcctrla;
313 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
314 unsigned int port_state;
315 unsigned int link_state;
316
317 /* Set new link state */
318 port_state = ( port_info->link_speed_supported__port_state & 0xf );
319 if ( port_state ) {
320 link_state = ( port_state - 1 );
321 DBGC ( qib7322, "QIB7322 %p set link state to %s (%x)\n",
322 qib7322, qib7322_link_state_text ( link_state ),
323 link_state );
324 qib7322_readq_port ( qib7322, &ibcctrla,
325 QIB_7322_IBCCtrlA_0_offset, port );
326 BIT_SET ( &ibcctrla, LinkCmd, link_state );
327 qib7322_writeq_port ( qib7322, &ibcctrla,
328 QIB_7322_IBCCtrlA_0_offset, port );
329
330 /* Wait for link state change to take effect. Ignore
331 * errors; the current link state will be returned via
332 * the GetResponse MAD.
333 */
334 qib7322_link_state_check ( ibdev, link_state );
335 }
336
337 /* Detect and report link state change */
338 qib7322_link_state_changed ( ibdev );
339
340 return 0;
341}
342
343/**
344 * Set partition key table
345 *
346 * @v ibdev Infiniband device
347 * @v mad Set partition key table MAD
348 */
349static int qib7322_set_pkey_table ( struct ib_device *ibdev __unused,
350 union ib_mad *mad __unused ) {
351 /* Nothing to do */
352 return 0;
353}
354
355/***************************************************************************
356 *
357 * Context allocation
358 *
359 ***************************************************************************
360 */
361
362/**
363 * Allocate a context and set queue pair number
364 *
365 * @v ibdev Infiniband device
366 * @v qp Queue pair
367 * @ret rc Return status code
368 */
369static int qib7322_alloc_ctx ( struct ib_device *ibdev,
370 struct ib_queue_pair *qp ) {
371 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
372 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
373 unsigned int ctx;
374
375 for ( ctx = port ; ctx < QIB7322_NUM_CONTEXTS ; ctx += 2 ) {
376
377 if ( ! qib7322->used_ctx[ctx] ) {
378 qib7322->used_ctx[ctx] = 1;
379 qp->qpn = ( ctx & ~0x01 );
380 DBGC2 ( qib7322, "QIB7322 %p port %d QPN %ld is CTX "
381 "%d\n", qib7322, port, qp->qpn, ctx );
382 return 0;
383 }
384 }
385
386 DBGC ( qib7322, "QIB7322 %p port %d out of available contexts\n",
387 qib7322, port );
388 return -ENOENT;
389}
390
391/**
392 * Get queue pair context number
393 *
394 * @v ibdev Infiniband device
395 * @v qp Queue pair
396 * @ret ctx Context index
397 */
398static unsigned int qib7322_ctx ( struct ib_device *ibdev,
399 struct ib_queue_pair *qp ) {
400 return ( qp->qpn + ( ibdev->port - QIB7322_PORT_BASE ) );
401}
402
403/**
404 * Free a context
405 *
406 * @v qib7322 QIB7322 device
407 * @v ctx Context index
408 */
409static void qib7322_free_ctx ( struct ib_device *ibdev,
410 struct ib_queue_pair *qp ) {
411 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
412 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
413 unsigned int ctx = qib7322_ctx ( ibdev, qp );
414
415 qib7322->used_ctx[ctx] = 0;
416 DBGC2 ( qib7322, "QIB7322 %p port %d CTX %d freed\n",
417 qib7322, port, ctx );
418}
419
420/***************************************************************************
421 *
422 * Send datapath
423 *
424 ***************************************************************************
425 */
426
427/** Send buffer toggle bit
428 *
429 * We encode send buffers as 15 bits of send buffer index plus a
430 * single bit which should match the "check" bit in the SendBufAvail
431 * array.
432 */
433#define QIB7322_SEND_BUF_TOGGLE 0x8000
434
435/**
436 * Create send buffer set
437 *
438 * @v qib7322 QIB7322 device
439 * @v base Send buffer base offset
440 * @v size Send buffer size
441 * @v start Index of first send buffer
442 * @v count Number of send buffers
443 * @ret send_bufs Send buffer set
444 */
445static struct qib7322_send_buffers *
446qib7322_create_send_bufs ( struct qib7322 *qib7322, unsigned long base,
447 unsigned int size, unsigned int start,
448 unsigned int count ) {
449 struct qib7322_send_buffers *send_bufs;
450 unsigned int i;
451
452 /* Allocate send buffer set */
453 send_bufs = zalloc ( sizeof ( *send_bufs ) +
454 ( count * sizeof ( send_bufs->avail[0] ) ) );
455 if ( ! send_bufs )
456 return NULL;
457
458 /* Populate send buffer set */
459 send_bufs->base = base;
460 send_bufs->size = size;
461 send_bufs->start = start;
462 send_bufs->count = count;
463 for ( i = 0 ; i < count ; i++ )
464 send_bufs->avail[i] = ( start + i );
465
466 DBGC2 ( qib7322, "QIB7322 %p send buffer set %p [%d,%d] at %lx\n",
467 qib7322, send_bufs, start, ( start + count - 1 ),
468 send_bufs->base );
469
470 return send_bufs;
471}
472
473/**
474 * Destroy send buffer set
475 *
476 * @v qib7322 QIB7322 device
477 * @v send_bufs Send buffer set
478 */
479static void
480qib7322_destroy_send_bufs ( struct qib7322 *qib7322 __unused,
481 struct qib7322_send_buffers *send_bufs ) {
482 free ( send_bufs );
483}
484
485/**
486 * Allocate a send buffer
487 *
488 * @v qib7322 QIB7322 device
489 * @v send_bufs Send buffer set
490 * @ret send_buf Send buffer, or negative error
491 */
492static int qib7322_alloc_send_buf ( struct qib7322 *qib7322,
493 struct qib7322_send_buffers *send_bufs ) {
494 unsigned int used;
495 unsigned int mask;
496 unsigned int send_buf;
497
498 used = ( send_bufs->cons - send_bufs->prod );
499 if ( used >= send_bufs->count ) {
500 DBGC ( qib7322, "QIB7322 %p send buffer set %p out of "
501 "buffers\n", qib7322, send_bufs );
502 return -ENOBUFS;
503 }
504
505 mask = ( send_bufs->count - 1 );
506 send_buf = send_bufs->avail[ send_bufs->cons++ & mask ];
507 send_buf ^= QIB7322_SEND_BUF_TOGGLE;
508 return send_buf;
509}
510
511/**
512 * Free a send buffer
513 *
514 * @v qib7322 QIB7322 device
515 * @v send_bufs Send buffer set
516 * @v send_buf Send buffer
517 */
518static void qib7322_free_send_buf ( struct qib7322 *qib7322 __unused,
519 struct qib7322_send_buffers *send_bufs,
520 unsigned int send_buf ) {
521 unsigned int mask;
522
523 mask = ( send_bufs->count - 1 );
524 send_bufs->avail[ send_bufs->prod++ & mask ] = send_buf;
525}
526
527/**
528 * Check to see if send buffer is in use
529 *
530 * @v qib7322 QIB7322 device
531 * @v send_buf Send buffer
532 * @ret in_use Send buffer is in use
533 */
534static int qib7322_send_buf_in_use ( struct qib7322 *qib7322,
535 unsigned int send_buf ) {
536 unsigned int send_idx;
537 unsigned int send_check;
538 unsigned int inusecheck;
539 unsigned int inuse;
540 unsigned int check;
541
542 send_idx = ( send_buf & ~QIB7322_SEND_BUF_TOGGLE );
543 send_check = ( !! ( send_buf & QIB7322_SEND_BUF_TOGGLE ) );
544 inusecheck = BIT_GET ( qib7322->sendbufavail, InUseCheck[send_idx] );
545 inuse = ( !! ( inusecheck & 0x02 ) );
546 check = ( !! ( inusecheck & 0x01 ) );
547 return ( inuse || ( check != send_check ) );
548}
549
550/**
551 * Calculate starting offset for send buffer
552 *
553 * @v qib7322 QIB7322 device
554 * @v send_buf Send buffer
555 * @ret offset Starting offset
556 */
557static unsigned long
558qib7322_send_buffer_offset ( struct qib7322 *qib7322 __unused,
559 struct qib7322_send_buffers *send_bufs,
560 unsigned int send_buf ) {
561 unsigned int index;
562
563 index = ( ( send_buf & ~QIB7322_SEND_BUF_TOGGLE ) - send_bufs->start );
564 return ( send_bufs->base + ( index * send_bufs->size ) );
565}
566
567/**
568 * Create send work queue
569 *
570 * @v ibdev Infiniband device
571 * @v qp Queue pair
572 */
573static int qib7322_create_send_wq ( struct ib_device *ibdev,
574 struct ib_queue_pair *qp ) {
575 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
576 struct ib_work_queue *wq = &qp->send;
577 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
578 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
579
580 /* Select send buffer set */
581 if ( qp->type == IB_QPT_SMI ) {
582 if ( port == 0 ) {
583 qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port0;
584 } else {
585 qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port1;
586 }
587 } else {
588 qib7322_wq->send_bufs = qib7322->send_bufs_small;
589 }
590
591 /* Allocate space for send buffer usage list */
592 qib7322_wq->used = zalloc ( qp->send.num_wqes *
593 sizeof ( qib7322_wq->used[0] ) );
594 if ( ! qib7322_wq->used )
595 return -ENOMEM;
596
597 /* Reset work queue */
598 qib7322_wq->prod = 0;
599 qib7322_wq->cons = 0;
600
601 return 0;
602}
603
604/**
605 * Destroy send work queue
606 *
607 * @v ibdev Infiniband device
608 * @v qp Queue pair
609 */
610static void qib7322_destroy_send_wq ( struct ib_device *ibdev __unused,
611 struct ib_queue_pair *qp ) {
612 struct ib_work_queue *wq = &qp->send;
613 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
614
615 free ( qib7322_wq->used );
616}
617
618/**
619 * Initialise send datapath
620 *
621 * @v qib7322 QIB7322 device
622 * @ret rc Return status code
623 */
624static int qib7322_init_send ( struct qib7322 *qib7322 ) {
625 struct QIB_7322_SendBufBase sendbufbase;
626 struct QIB_7322_SendBufAvailAddr sendbufavailaddr;
627 struct QIB_7322_SendCtrl sendctrl;
628 struct QIB_7322_SendCtrl_0 sendctrlp;
629 unsigned long baseaddr_smallpio;
630 unsigned long baseaddr_largepio;
631 unsigned long baseaddr_vl15_port0;
632 unsigned long baseaddr_vl15_port1;
633 int rc;
634
635 /* Create send buffer sets */
636 qib7322_readq ( qib7322, &sendbufbase, QIB_7322_SendBufBase_offset );
637 baseaddr_smallpio = BIT_GET ( &sendbufbase, BaseAddr_SmallPIO );
638 baseaddr_largepio = BIT_GET ( &sendbufbase, BaseAddr_LargePIO );
639 baseaddr_vl15_port0 = ( baseaddr_largepio +
640 ( QIB7322_LARGE_SEND_BUF_SIZE *
641 QIB7322_LARGE_SEND_BUF_COUNT ) );
642 baseaddr_vl15_port1 = ( baseaddr_vl15_port0 +
643 QIB7322_VL15_PORT0_SEND_BUF_SIZE );
644 qib7322->send_bufs_small =
645 qib7322_create_send_bufs ( qib7322, baseaddr_smallpio,
646 QIB7322_SMALL_SEND_BUF_SIZE,
647 QIB7322_SMALL_SEND_BUF_START,
648 QIB7322_SMALL_SEND_BUF_USED );
649 if ( ! qib7322->send_bufs_small ) {
650 rc = -ENOMEM;
651 goto err_create_send_bufs_small;
652 }
653 qib7322->send_bufs_vl15_port0 =
654 qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port0,
655 QIB7322_VL15_PORT0_SEND_BUF_SIZE,
656 QIB7322_VL15_PORT0_SEND_BUF_START,
657 QIB7322_VL15_PORT0_SEND_BUF_COUNT );
658 if ( ! qib7322->send_bufs_vl15_port0 ) {
659 rc = -ENOMEM;
660 goto err_create_send_bufs_vl15_port0;
661 }
662 qib7322->send_bufs_vl15_port1 =
663 qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port1,
664 QIB7322_VL15_PORT1_SEND_BUF_SIZE,
665 QIB7322_VL15_PORT1_SEND_BUF_START,
666 QIB7322_VL15_PORT1_SEND_BUF_COUNT );
667 if ( ! qib7322->send_bufs_vl15_port1 ) {
668 rc = -ENOMEM;
669 goto err_create_send_bufs_vl15_port1;
670 }
671
672 /* Allocate space for the SendBufAvail array */
673 qib7322->sendbufavail = malloc_phys ( sizeof ( *qib7322->sendbufavail ),
674 QIB7322_SENDBUFAVAIL_ALIGN );
675 if ( ! qib7322->sendbufavail ) {
676 rc = -ENOMEM;
677 goto err_alloc_sendbufavail;
678 }
679 memset ( qib7322->sendbufavail, 0, sizeof ( *qib7322->sendbufavail ) );
680
681 /* Program SendBufAvailAddr into the hardware */
682 memset ( &sendbufavailaddr, 0, sizeof ( sendbufavailaddr ) );
683 BIT_FILL_1 ( &sendbufavailaddr, SendBufAvailAddr,
684 ( virt_to_bus ( qib7322->sendbufavail ) >> 6 ) );
685 qib7322_writeq ( qib7322, &sendbufavailaddr,
686 QIB_7322_SendBufAvailAddr_offset );
687
688 /* Enable sending */
689 memset ( &sendctrlp, 0, sizeof ( sendctrlp ) );
690 BIT_FILL_1 ( &sendctrlp, SendEnable, 1 );
691 qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_0_offset );
692 qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_1_offset );
693
694 /* Enable DMA of SendBufAvail */
695 memset ( &sendctrl, 0, sizeof ( sendctrl ) );
696 BIT_FILL_1 ( &sendctrl, SendBufAvailUpd, 1 );
697 qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
698
699 return 0;
700
701 free_phys ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
702 err_alloc_sendbufavail:
703 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
704 err_create_send_bufs_vl15_port1:
705 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
706 err_create_send_bufs_vl15_port0:
707 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
708 err_create_send_bufs_small:
709 return rc;
710}
711
712/**
713 * Shut down send datapath
714 *
715 * @v qib7322 QIB7322 device
716 */
717static void qib7322_fini_send ( struct qib7322 *qib7322 ) {
718 struct QIB_7322_SendCtrl sendctrl;
719
720 /* Disable sending and DMA of SendBufAvail */
721 memset ( &sendctrl, 0, sizeof ( sendctrl ) );
722 qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
723 mb();
724
725 /* Ensure hardware has seen this disable */
726 qib7322_readq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
727
728 free_phys ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
729 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
730 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
731 qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
732}
733
734/***************************************************************************
735 *
736 * Receive datapath
737 *
738 ***************************************************************************
739 */
740
741/**
742 * Create receive work queue
743 *
744 * @v ibdev Infiniband device
745 * @v qp Queue pair
746 * @ret rc Return status code
747 */
748static int qib7322_create_recv_wq ( struct ib_device *ibdev,
749 struct ib_queue_pair *qp ) {
750 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
751 struct ib_work_queue *wq = &qp->recv;
752 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
753 struct QIB_7322_RcvHdrAddr0 rcvhdraddr;
754 struct QIB_7322_RcvHdrTailAddr0 rcvhdrtailaddr;
755 struct QIB_7322_RcvHdrHead0 rcvhdrhead;
756 struct QIB_7322_scalar rcvegrindexhead;
757 struct QIB_7322_RcvCtrl rcvctrl;
758 struct QIB_7322_RcvCtrl_P rcvctrlp;
759 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
760 unsigned int ctx = qib7322_ctx ( ibdev, qp );
761 int rc;
762
763 /* Reset context information */
764 memset ( &qib7322_wq->header_prod, 0,
765 sizeof ( qib7322_wq->header_prod ) );
766 qib7322_wq->header_cons = 0;
767 qib7322_wq->eager_prod = 0;
768 qib7322_wq->eager_cons = 0;
769
770 /* Allocate receive header buffer */
771 qib7322_wq->header = malloc_phys ( QIB7322_RECV_HEADERS_SIZE,
772 QIB7322_RECV_HEADERS_ALIGN );
773 if ( ! qib7322_wq->header ) {
774 rc = -ENOMEM;
775 goto err_alloc_header;
776 }
777
778 /* Enable context in hardware */
779 memset ( &rcvhdraddr, 0, sizeof ( rcvhdraddr ) );
780 BIT_FILL_1 ( &rcvhdraddr, RcvHdrAddr,
781 ( virt_to_bus ( qib7322_wq->header ) >> 2 ) );
782 qib7322_writeq_array8b ( qib7322, &rcvhdraddr,
783 QIB_7322_RcvHdrAddr0_offset, ctx );
784 memset ( &rcvhdrtailaddr, 0, sizeof ( rcvhdrtailaddr ) );
785 BIT_FILL_1 ( &rcvhdrtailaddr, RcvHdrTailAddr,
786 ( virt_to_bus ( &qib7322_wq->header_prod ) >> 2 ) );
787 qib7322_writeq_array8b ( qib7322, &rcvhdrtailaddr,
788 QIB_7322_RcvHdrTailAddr0_offset, ctx );
789 memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
790 BIT_FILL_1 ( &rcvhdrhead, counter, 1 );
791 qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
792 QIB_7322_RcvHdrHead0_offset, ctx );
793 memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
794 BIT_FILL_1 ( &rcvegrindexhead, Value, 1 );
795 qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
796 QIB_7322_RcvEgrIndexHead0_offset, ctx );
797 qib7322_readq_port ( qib7322, &rcvctrlp,
798 QIB_7322_RcvCtrl_0_offset, port );
799 BIT_SET ( &rcvctrlp, ContextEnable[ctx], 1 );
800 qib7322_writeq_port ( qib7322, &rcvctrlp,
801 QIB_7322_RcvCtrl_0_offset, port );
802 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
803 BIT_SET ( &rcvctrl, IntrAvail[ctx], 1 );
804 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
805
806 DBGC ( qib7322, "QIB7322 %p port %d QPN %ld CTX %d hdrs [%lx,%lx) prod "
807 "%lx\n", qib7322, port, qp->qpn, ctx,
808 virt_to_bus ( qib7322_wq->header ),
809 ( virt_to_bus ( qib7322_wq->header )
810 + QIB7322_RECV_HEADERS_SIZE ),
811 virt_to_bus ( &qib7322_wq->header_prod ) );
812 return 0;
813
814 free_phys ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
815 err_alloc_header:
816 return rc;
817}
818
819/**
820 * Destroy receive work queue
821 *
822 * @v ibdev Infiniband device
823 * @v qp Queue pair
824 */
825static void qib7322_destroy_recv_wq ( struct ib_device *ibdev,
826 struct ib_queue_pair *qp ) {
827 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
828 struct ib_work_queue *wq = &qp->recv;
829 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
830 struct QIB_7322_RcvCtrl rcvctrl;
831 struct QIB_7322_RcvCtrl_P rcvctrlp;
832 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
833 unsigned int ctx = qib7322_ctx ( ibdev, qp );
834
835 /* Disable context in hardware */
836 qib7322_readq_port ( qib7322, &rcvctrlp,
837 QIB_7322_RcvCtrl_0_offset, port );
838 BIT_SET ( &rcvctrlp, ContextEnable[ctx], 0 );
839 qib7322_writeq_port ( qib7322, &rcvctrlp,
840 QIB_7322_RcvCtrl_0_offset, port );
841 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
842 BIT_SET ( &rcvctrl, IntrAvail[ctx], 0 );
843 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
844
845 /* Make sure the hardware has seen that the context is disabled */
846 qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
847 mb();
848
849 /* Free headers ring */
850 free_phys ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
851}
852
853/**
854 * Initialise receive datapath
855 *
856 * @v qib7322 QIB7322 device
857 * @ret rc Return status code
858 */
859static int qib7322_init_recv ( struct qib7322 *qib7322 ) {
860 struct QIB_7322_RcvCtrl rcvctrl;
861 struct QIB_7322_RcvCtrl_0 rcvctrlp;
862 struct QIB_7322_RcvQPMapTableA_0 rcvqpmaptablea0;
863 struct QIB_7322_RcvQPMapTableB_0 rcvqpmaptableb0;
864 struct QIB_7322_RcvQPMapTableA_1 rcvqpmaptablea1;
865 struct QIB_7322_RcvQPMapTableB_1 rcvqpmaptableb1;
866 struct QIB_7322_RcvQPMulticastContext_0 rcvqpmcastctx0;
867 struct QIB_7322_RcvQPMulticastContext_1 rcvqpmcastctx1;
868 struct QIB_7322_scalar rcvegrbase;
869 struct QIB_7322_scalar rcvhdrentsize;
870 struct QIB_7322_scalar rcvhdrcnt;
871 struct QIB_7322_RcvBTHQP_0 rcvbthqp;
872 struct QIB_7322_RxCreditVL0_0 rxcreditvl;
873 unsigned int contextcfg;
874 unsigned long egrbase;
875 unsigned int eager_array_size_kernel;
876 unsigned int eager_array_size_user;
877 unsigned int ctx;
878
879 /* Select configuration based on number of contexts */
880 switch ( QIB7322_NUM_CONTEXTS ) {
881 case 6:
882 contextcfg = QIB7322_CONTEXTCFG_6CTX;
883 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL;
884 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_6CTX_USER;
885 break;
886 case 10:
887 contextcfg = QIB7322_CONTEXTCFG_10CTX;
888 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL;
889 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_10CTX_USER;
890 break;
891 case 18:
892 contextcfg = QIB7322_CONTEXTCFG_18CTX;
893 eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL;
894 eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_18CTX_USER;
895 break;
896 default:
897 build_assert ( 0 );
898 return -EINVAL;
899 }
900
901 /* Configure number of contexts */
902 memset ( &rcvctrl, 0, sizeof ( rcvctrl ) );
903 BIT_FILL_2 ( &rcvctrl,
904 TailUpd, 1,
905 ContextCfg, contextcfg );
906 qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
907
908 /* Map QPNs to contexts */
909 memset ( &rcvctrlp, 0, sizeof ( rcvctrlp ) );
910 BIT_FILL_3 ( &rcvctrlp,
911 RcvIBPortEnable, 1,
912 RcvQPMapEnable, 1,
913 RcvPartitionKeyDisable, 1 );
914 qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_0_offset );
915 qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_1_offset );
916 memset ( &rcvqpmaptablea0, 0, sizeof ( rcvqpmaptablea0 ) );
917 BIT_FILL_6 ( &rcvqpmaptablea0,
918 RcvQPMapContext0, 0,
919 RcvQPMapContext1, 2,
920 RcvQPMapContext2, 4,
921 RcvQPMapContext3, 6,
922 RcvQPMapContext4, 8,
923 RcvQPMapContext5, 10 );
924 qib7322_writeq ( qib7322, &rcvqpmaptablea0,
925 QIB_7322_RcvQPMapTableA_0_offset );
926 memset ( &rcvqpmaptableb0, 0, sizeof ( rcvqpmaptableb0 ) );
927 BIT_FILL_3 ( &rcvqpmaptableb0,
928 RcvQPMapContext6, 12,
929 RcvQPMapContext7, 14,
930 RcvQPMapContext8, 16 );
931 qib7322_writeq ( qib7322, &rcvqpmaptableb0,
932 QIB_7322_RcvQPMapTableB_0_offset );
933 memset ( &rcvqpmaptablea1, 0, sizeof ( rcvqpmaptablea1 ) );
934 BIT_FILL_6 ( &rcvqpmaptablea1,
935 RcvQPMapContext0, 1,
936 RcvQPMapContext1, 3,
937 RcvQPMapContext2, 5,
938 RcvQPMapContext3, 7,
939 RcvQPMapContext4, 9,
940 RcvQPMapContext5, 11 );
941 qib7322_writeq ( qib7322, &rcvqpmaptablea1,
942 QIB_7322_RcvQPMapTableA_1_offset );
943 memset ( &rcvqpmaptableb1, 0, sizeof ( rcvqpmaptableb1 ) );
944 BIT_FILL_3 ( &rcvqpmaptableb1,
945 RcvQPMapContext6, 13,
946 RcvQPMapContext7, 15,
947 RcvQPMapContext8, 17 );
948 qib7322_writeq ( qib7322, &rcvqpmaptableb1,
949 QIB_7322_RcvQPMapTableB_1_offset );
950
951 /* Map multicast QPNs to contexts */
952 memset ( &rcvqpmcastctx0, 0, sizeof ( rcvqpmcastctx0 ) );
953 BIT_FILL_1 ( &rcvqpmcastctx0, RcvQpMcContext, 0 );
954 qib7322_writeq ( qib7322, &rcvqpmcastctx0,
955 QIB_7322_RcvQPMulticastContext_0_offset );
956 memset ( &rcvqpmcastctx1, 0, sizeof ( rcvqpmcastctx1 ) );
957 BIT_FILL_1 ( &rcvqpmcastctx1, RcvQpMcContext, 1 );
958 qib7322_writeq ( qib7322, &rcvqpmcastctx1,
959 QIB_7322_RcvQPMulticastContext_1_offset );
960
961 /* Configure receive header buffer sizes */
962 memset ( &rcvhdrcnt, 0, sizeof ( rcvhdrcnt ) );
963 BIT_FILL_1 ( &rcvhdrcnt, Value, QIB7322_RECV_HEADER_COUNT );
964 qib7322_writeq ( qib7322, &rcvhdrcnt, QIB_7322_RcvHdrCnt_offset );
965 memset ( &rcvhdrentsize, 0, sizeof ( rcvhdrentsize ) );
966 BIT_FILL_1 ( &rcvhdrentsize, Value, ( QIB7322_RECV_HEADER_SIZE >> 2 ) );
967 qib7322_writeq ( qib7322, &rcvhdrentsize,
968 QIB_7322_RcvHdrEntSize_offset );
969
970 /* Calculate eager array start addresses for each context */
971 qib7322_readq ( qib7322, &rcvegrbase, QIB_7322_RcvEgrBase_offset );
972 egrbase = BIT_GET ( &rcvegrbase, Value );
973 for ( ctx = 0 ; ctx < QIB7322_MAX_PORTS ; ctx++ ) {
974 qib7322->recv_wq[ctx].eager_array = egrbase;
975 qib7322->recv_wq[ctx].eager_entries = eager_array_size_kernel;
976 egrbase += ( eager_array_size_kernel *
977 sizeof ( struct QIB_7322_RcvEgr ) );
978 }
979 for ( ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
980 qib7322->recv_wq[ctx].eager_array = egrbase;
981 qib7322->recv_wq[ctx].eager_entries = eager_array_size_user;
982 egrbase += ( eager_array_size_user *
983 sizeof ( struct QIB_7322_RcvEgr ) );
984 }
985 for ( ctx = 0 ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
986 DBGC ( qib7322, "QIB7322 %p CTX %d eager array at %lx (%d "
987 "entries)\n", qib7322, ctx,
988 qib7322->recv_wq[ctx].eager_array,
989 qib7322->recv_wq[ctx].eager_entries );
990 }
991
992 /* Set the BTH QP for Infinipath packets to an unused value */
993 memset ( &rcvbthqp, 0, sizeof ( rcvbthqp ) );
994 BIT_FILL_1 ( &rcvbthqp, RcvBTHQP, QIB7322_QP_IDETH );
995 qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_0_offset );
996 qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_1_offset );
997
998 /* Assign initial credits */
999 memset ( &rxcreditvl, 0, sizeof ( rxcreditvl ) );
1000 BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL0 );
1001 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1002 QIB_7322_RxCreditVL0_0_offset, 0 );
1003 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1004 QIB_7322_RxCreditVL0_1_offset, 0 );
1005 BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL15 );
1006 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1007 QIB_7322_RxCreditVL0_0_offset, 15 );
1008 qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1009 QIB_7322_RxCreditVL0_1_offset, 15 );
1010
1011 return 0;
1012}
1013
1014/**
1015 * Shut down receive datapath
1016 *
1017 * @v qib7322 QIB7322 device
1018 */
1019static void qib7322_fini_recv ( struct qib7322 *qib7322 __unused ) {
1020 /* Nothing to do; all contexts were already disabled when the
1021 * queue pairs were destroyed
1022 */
1023}
1024
1025/***************************************************************************
1026 *
1027 * Completion queue operations
1028 *
1029 ***************************************************************************
1030 */
1031
1032/**
1033 * Create completion queue
1034 *
1035 * @v ibdev Infiniband device
1036 * @v cq Completion queue
1037 * @ret rc Return status code
1038 */
1039static int qib7322_create_cq ( struct ib_device *ibdev,
1040 struct ib_completion_queue *cq ) {
1041 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1042 static int cqn;
1043
1044 /* The hardware has no concept of completion queues. We
1045 * simply use the association between CQs and WQs (already
1046 * handled by the IB core) to decide which WQs to poll.
1047 *
1048 * We do set a CQN, just to avoid confusing debug messages
1049 * from the IB core.
1050 */
1051 cq->cqn = ++cqn;
1052 DBGC ( qib7322, "QIB7322 %p CQN %ld created\n", qib7322, cq->cqn );
1053
1054 return 0;
1055}
1056
1057/**
1058 * Destroy completion queue
1059 *
1060 * @v ibdev Infiniband device
1061 * @v cq Completion queue
1062 */
1063static void qib7322_destroy_cq ( struct ib_device *ibdev,
1064 struct ib_completion_queue *cq ) {
1065 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1066
1067 /* Nothing to do */
1068 DBGC ( qib7322, "QIB7322 %p CQN %ld destroyed\n", qib7322, cq->cqn );
1069}
1070
1071/***************************************************************************
1072 *
1073 * Queue pair operations
1074 *
1075 ***************************************************************************
1076 */
1077
1078/**
1079 * Create queue pair
1080 *
1081 * @v ibdev Infiniband device
1082 * @v qp Queue pair
1083 * @ret rc Return status code
1084 */
1085static int qib7322_create_qp ( struct ib_device *ibdev,
1086 struct ib_queue_pair *qp ) {
1087 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1088 unsigned int ctx;
1089 int rc;
1090
1091 /* Allocate a context and QPN */
1092 if ( ( rc = qib7322_alloc_ctx ( ibdev, qp ) ) != 0 )
1093 goto err_alloc_ctx;
1094 ctx = qib7322_ctx ( ibdev, qp );
1095
1096 /* Set work-queue private data pointers */
1097 ib_wq_set_drvdata ( &qp->send, &qib7322->send_wq[ctx] );
1098 ib_wq_set_drvdata ( &qp->recv, &qib7322->recv_wq[ctx] );
1099
1100 /* Create receive work queue */
1101 if ( ( rc = qib7322_create_recv_wq ( ibdev, qp ) ) != 0 )
1102 goto err_create_recv_wq;
1103
1104 /* Create send work queue */
1105 if ( ( rc = qib7322_create_send_wq ( ibdev, qp ) ) != 0 )
1106 goto err_create_send_wq;
1107
1108 return 0;
1109
1110 qib7322_destroy_send_wq ( ibdev, qp );
1111 err_create_send_wq:
1112 qib7322_destroy_recv_wq ( ibdev, qp );
1113 err_create_recv_wq:
1114 qib7322_free_ctx ( ibdev, qp );
1115 err_alloc_ctx:
1116 return rc;
1117}
1118
1119/**
1120 * Modify queue pair
1121 *
1122 * @v ibdev Infiniband device
1123 * @v qp Queue pair
1124 * @ret rc Return status code
1125 */
1126static int qib7322_modify_qp ( struct ib_device *ibdev,
1127 struct ib_queue_pair *qp ) {
1128 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1129
1130 /* Nothing to do; the hardware doesn't have a notion of queue
1131 * keys
1132 */
1133 DBGC2 ( qib7322, "QIB7322 %p QPN %ld modified\n", qib7322, qp->qpn );
1134 return 0;
1135}
1136
1137/**
1138 * Destroy queue pair
1139 *
1140 * @v ibdev Infiniband device
1141 * @v qp Queue pair
1142 */
1143static void qib7322_destroy_qp ( struct ib_device *ibdev,
1144 struct ib_queue_pair *qp ) {
1145
1146 qib7322_destroy_send_wq ( ibdev, qp );
1147 qib7322_destroy_recv_wq ( ibdev, qp );
1148 qib7322_free_ctx ( ibdev, qp );
1149}
1150
1151/***************************************************************************
1152 *
1153 * Work request operations
1154 *
1155 ***************************************************************************
1156 */
1157
1158/**
1159 * Post send work queue entry
1160 *
1161 * @v ibdev Infiniband device
1162 * @v qp Queue pair
1163 * @v dest Destination address vector
1164 * @v iobuf I/O buffer
1165 * @ret rc Return status code
1166 */
1167static int qib7322_post_send ( struct ib_device *ibdev,
1168 struct ib_queue_pair *qp,
1169 struct ib_address_vector *dest,
1170 struct io_buffer *iobuf ) {
1171 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1172 struct ib_work_queue *wq = &qp->send;
1173 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1174 struct QIB_7322_SendPbc sendpbc;
1175 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1176 uint8_t header_buf[IB_MAX_HEADER_SIZE];
1177 struct io_buffer headers;
1178 int send_buf;
1179 unsigned long start_offset;
1180 unsigned long offset;
1181 size_t len;
1182 ssize_t frag_len;
1183 uint32_t *data;
1184
1185 /* Allocate send buffer and calculate offset */
1186 send_buf = qib7322_alloc_send_buf ( qib7322, qib7322_wq->send_bufs );
1187 if ( send_buf < 0 )
1188 return send_buf;
1189 start_offset = offset =
1190 qib7322_send_buffer_offset ( qib7322, qib7322_wq->send_bufs,
1191 send_buf );
1192
1193 /* Store I/O buffer and send buffer index */
1194 assert ( wq->iobufs[qib7322_wq->prod] == NULL );
1195 wq->iobufs[qib7322_wq->prod] = iobuf;
1196 qib7322_wq->used[qib7322_wq->prod] = send_buf;
1197
1198 /* Construct headers */
1199 iob_populate ( &headers, header_buf, 0, sizeof ( header_buf ) );
1200 iob_reserve ( &headers, sizeof ( header_buf ) );
1201 ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), dest );
1202
1203 /* Calculate packet length */
1204 len = ( ( sizeof ( sendpbc ) + iob_len ( &headers ) +
1205 iob_len ( iobuf ) + 3 ) & ~3 );
1206
1207 /* Construct send per-buffer control word */
1208 memset ( &sendpbc, 0, sizeof ( sendpbc ) );
1209 BIT_FILL_3 ( &sendpbc,
1210 LengthP1_toibc, ( ( len >> 2 ) - 1 ),
1211 Port, port,
1212 VL15, ( ( qp->type == IB_QPT_SMI ) ? 1 : 0 ) );
1213
1214 /* Write SendPbc */
1215 DBG_DISABLE ( DBGLVL_IO );
1216 qib7322_writeq ( qib7322, &sendpbc, offset );
1217 offset += sizeof ( sendpbc );
1218
1219 /* Write headers */
1220 for ( data = headers.data, frag_len = iob_len ( &headers ) ;
1221 frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1222 qib7322_writel ( qib7322, *data, offset );
1223 }
1224
1225 /* Write data */
1226 for ( data = iobuf->data, frag_len = iob_len ( iobuf ) ;
1227 frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1228 qib7322_writel ( qib7322, *data, offset );
1229 }
1230 DBG_ENABLE ( DBGLVL_IO );
1231
1232 assert ( ( start_offset + len ) == offset );
1233 DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) posted [%lx,%lx)\n",
1234 qib7322, qp->qpn, send_buf, qib7322_wq->prod,
1235 start_offset, offset );
1236
1237 /* Increment producer counter */
1238 qib7322_wq->prod = ( ( qib7322_wq->prod + 1 ) & ( wq->num_wqes - 1 ) );
1239
1240 return 0;
1241}
1242
1243/**
1244 * Complete send work queue entry
1245 *
1246 * @v ibdev Infiniband device
1247 * @v qp Queue pair
1248 * @v wqe_idx Work queue entry index
1249 */
1250static void qib7322_complete_send ( struct ib_device *ibdev,
1251 struct ib_queue_pair *qp,
1252 unsigned int wqe_idx ) {
1253 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1254 struct ib_work_queue *wq = &qp->send;
1255 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1256 struct io_buffer *iobuf;
1257 unsigned int send_buf;
1258
1259 /* Parse completion */
1260 send_buf = qib7322_wq->used[wqe_idx];
1261 DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) complete\n",
1262 qib7322, qp->qpn, send_buf, wqe_idx );
1263
1264 /* Complete work queue entry */
1265 iobuf = wq->iobufs[wqe_idx];
1266 assert ( iobuf != NULL );
1267 ib_complete_send ( ibdev, qp, iobuf, 0 );
1268 wq->iobufs[wqe_idx] = NULL;
1269
1270 /* Free send buffer */
1271 qib7322_free_send_buf ( qib7322, qib7322_wq->send_bufs, send_buf );
1272}
1273
1274/**
1275 * Poll send work queue
1276 *
1277 * @v ibdev Infiniband device
1278 * @v qp Queue pair
1279 */
1280static void qib7322_poll_send_wq ( struct ib_device *ibdev,
1281 struct ib_queue_pair *qp ) {
1282 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1283 struct ib_work_queue *wq = &qp->send;
1284 struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1285 unsigned int send_buf;
1286
1287 /* Look for completions */
1288 while ( wq->fill ) {
1289
1290 /* Check to see if send buffer has completed */
1291 send_buf = qib7322_wq->used[qib7322_wq->cons];
1292 if ( qib7322_send_buf_in_use ( qib7322, send_buf ) )
1293 break;
1294
1295 /* Complete this buffer */
1296 qib7322_complete_send ( ibdev, qp, qib7322_wq->cons );
1297
1298 /* Increment consumer counter */
1299 qib7322_wq->cons = ( ( qib7322_wq->cons + 1 ) &
1300 ( wq->num_wqes - 1 ) );
1301 }
1302}
1303
1304/**
1305 * Post receive work queue entry
1306 *
1307 * @v ibdev Infiniband device
1308 * @v qp Queue pair
1309 * @v iobuf I/O buffer
1310 * @ret rc Return status code
1311 */
1312static int qib7322_post_recv ( struct ib_device *ibdev,
1313 struct ib_queue_pair *qp,
1314 struct io_buffer *iobuf ) {
1315 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1316 struct ib_work_queue *wq = &qp->recv;
1317 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1318 struct QIB_7322_RcvEgr rcvegr;
1319 struct QIB_7322_scalar rcvegrindexhead;
1320 unsigned int ctx = qib7322_ctx ( ibdev, qp );
1321 physaddr_t addr;
1322 size_t len;
1323 unsigned int wqe_idx;
1324 unsigned int bufsize;
1325
1326 /* Sanity checks */
1327 addr = virt_to_bus ( iobuf->data );
1328 len = iob_tailroom ( iobuf );
1329 if ( addr & ( QIB7322_EAGER_BUFFER_ALIGN - 1 ) ) {
1330 DBGC ( qib7322, "QIB7322 %p QPN %ld misaligned RX buffer "
1331 "(%08lx)\n", qib7322, qp->qpn, addr );
1332 return -EINVAL;
1333 }
1334 if ( len != QIB7322_RECV_PAYLOAD_SIZE ) {
1335 DBGC ( qib7322, "QIB7322 %p QPN %ld wrong RX buffer size "
1336 "(%zd)\n", qib7322, qp->qpn, len );
1337 return -EINVAL;
1338 }
1339
1340 /* Calculate eager producer index and WQE index */
1341 wqe_idx = ( qib7322_wq->eager_prod & ( wq->num_wqes - 1 ) );
1342 assert ( wq->iobufs[wqe_idx] == NULL );
1343
1344 /* Store I/O buffer */
1345 wq->iobufs[wqe_idx] = iobuf;
1346
1347 /* Calculate buffer size */
1348 switch ( QIB7322_RECV_PAYLOAD_SIZE ) {
1349 case 2048: bufsize = QIB7322_EAGER_BUFFER_2K; break;
1350 case 4096: bufsize = QIB7322_EAGER_BUFFER_4K; break;
1351 case 8192: bufsize = QIB7322_EAGER_BUFFER_8K; break;
1352 case 16384: bufsize = QIB7322_EAGER_BUFFER_16K; break;
1353 case 32768: bufsize = QIB7322_EAGER_BUFFER_32K; break;
1354 case 65536: bufsize = QIB7322_EAGER_BUFFER_64K; break;
1355 default: build_assert ( 0 );
1356 bufsize = QIB7322_EAGER_BUFFER_NONE;
1357 }
1358
1359 /* Post eager buffer */
1360 memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1361 BIT_FILL_2 ( &rcvegr,
1362 Addr, ( addr >> 11 ),
1363 BufSize, bufsize );
1364 qib7322_writeq_array8b ( qib7322, &rcvegr, qib7322_wq->eager_array,
1365 qib7322_wq->eager_prod );
1366 DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x(%04x) posted "
1367 "[%lx,%lx)\n", qib7322, qp->qpn, qib7322_wq->eager_prod,
1368 wqe_idx, addr, ( addr + len ) );
1369
1370 /* Increment producer index */
1371 qib7322_wq->eager_prod = ( ( qib7322_wq->eager_prod + 1 ) &
1372 ( qib7322_wq->eager_entries - 1 ) );
1373
1374 /* Update head index */
1375 memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
1376 BIT_FILL_1 ( &rcvegrindexhead,
1377 Value, ( ( qib7322_wq->eager_prod + 1 ) &
1378 ( qib7322_wq->eager_entries - 1 ) ) );
1379 qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
1380 QIB_7322_RcvEgrIndexHead0_offset, ctx );
1381
1382 return 0;
1383}
1384
1385/**
1386 * Complete receive work queue entry
1387 *
1388 * @v ibdev Infiniband device
1389 * @v qp Queue pair
1390 * @v header_offs Header offset
1391 */
1392static void qib7322_complete_recv ( struct ib_device *ibdev,
1393 struct ib_queue_pair *qp,
1394 unsigned int header_offs ) {
1395 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1396 struct ib_work_queue *wq = &qp->recv;
1397 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1398 struct QIB_7322_RcvHdrFlags *rcvhdrflags;
1399 struct QIB_7322_RcvEgr rcvegr;
1400 struct io_buffer headers;
1401 struct io_buffer *iobuf;
1402 struct ib_queue_pair *intended_qp;
1403 struct ib_address_vector dest;
1404 struct ib_address_vector source;
1405 unsigned int rcvtype;
1406 unsigned int pktlen;
1407 unsigned int egrindex;
1408 unsigned int useegrbfr;
1409 unsigned int iberr, mkerr, tiderr, khdrerr, mtuerr;
1410 unsigned int lenerr, parityerr, vcrcerr, icrcerr;
1411 unsigned int err;
1412 unsigned int hdrqoffset;
1413 unsigned int header_len;
1414 unsigned int padded_payload_len;
1415 unsigned int wqe_idx;
1416 size_t payload_len;
1417 int qp0;
1418 int rc;
1419
1420 /* RcvHdrFlags are at the end of the header entry */
1421 rcvhdrflags = ( qib7322_wq->header + header_offs +
1422 QIB7322_RECV_HEADER_SIZE - sizeof ( *rcvhdrflags ) );
1423 rcvtype = BIT_GET ( rcvhdrflags, RcvType );
1424 pktlen = ( BIT_GET ( rcvhdrflags, PktLen ) << 2 );
1425 egrindex = BIT_GET ( rcvhdrflags, EgrIndex );
1426 useegrbfr = BIT_GET ( rcvhdrflags, UseEgrBfr );
1427 hdrqoffset = ( BIT_GET ( rcvhdrflags, HdrqOffset ) << 2 );
1428 iberr = BIT_GET ( rcvhdrflags, IBErr );
1429 mkerr = BIT_GET ( rcvhdrflags, MKErr );
1430 tiderr = BIT_GET ( rcvhdrflags, TIDErr );
1431 khdrerr = BIT_GET ( rcvhdrflags, KHdrErr );
1432 mtuerr = BIT_GET ( rcvhdrflags, MTUErr );
1433 lenerr = BIT_GET ( rcvhdrflags, LenErr );
1434 parityerr = BIT_GET ( rcvhdrflags, ParityErr );
1435 vcrcerr = BIT_GET ( rcvhdrflags, VCRCErr );
1436 icrcerr = BIT_GET ( rcvhdrflags, ICRCErr );
1437 header_len = ( QIB7322_RECV_HEADER_SIZE - hdrqoffset -
1438 sizeof ( *rcvhdrflags ) );
1439 padded_payload_len = ( pktlen - header_len - 4 /* ICRC */ );
1440 err = ( iberr | mkerr | tiderr | khdrerr | mtuerr |
1441 lenerr | parityerr | vcrcerr | icrcerr );
1442 /* IB header is placed immediately before RcvHdrFlags */
1443 iob_populate ( &headers, ( ( ( void * ) rcvhdrflags ) - header_len ),
1444 header_len, header_len );
1445
1446 /* Dump diagnostic information */
1447 DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x%s hdr %d type %d len "
1448 "%d(%d+%d+4)%s%s%s%s%s%s%s%s%s%s%s\n", qib7322, qp->qpn,
1449 egrindex, ( useegrbfr ? "" : "(unused)" ),
1450 ( header_offs / QIB7322_RECV_HEADER_SIZE ),
1451 rcvtype, pktlen, header_len, padded_payload_len,
1452 ( err ? " [Err" : "" ), ( iberr ? " IB" : "" ),
1453 ( mkerr ? " MK" : "" ), ( tiderr ? " TID" : "" ),
1454 ( khdrerr ? " KHdr" : "" ), ( mtuerr ? " MTU" : "" ),
1455 ( lenerr ? " Len" : "" ), ( parityerr ? " Parity" : ""),
1456 ( vcrcerr ? " VCRC" : "" ), ( icrcerr ? " ICRC" : "" ),
1457 ( err ? "]" : "" ) );
1458 DBGCP_HDA ( qib7322, hdrqoffset, headers.data,
1459 ( header_len + sizeof ( *rcvhdrflags ) ) );
1460
1461 /* Parse header to generate address vector */
1462 qp0 = ( qp->qpn == 0 );
1463 intended_qp = NULL;
1464 if ( ( rc = ib_pull ( ibdev, &headers, ( qp0 ? &intended_qp : NULL ),
1465 &payload_len, &dest, &source ) ) != 0 ) {
1466 DBGC ( qib7322, "QIB7322 %p could not parse headers: %s\n",
1467 qib7322, strerror ( rc ) );
1468 err = 1;
1469 }
1470 if ( ! intended_qp )
1471 intended_qp = qp;
1472
1473 /* Complete this buffer and any skipped buffers. Note that
1474 * when the hardware runs out of buffers, it will repeatedly
1475 * report the same buffer (the tail) as a TID error, and that
1476 * it also has a habit of sometimes skipping over several
1477 * buffers at once.
1478 */
1479 while ( 1 ) {
1480
1481 /* If we have caught up to the producer counter, stop.
1482 * This will happen when the hardware first runs out
1483 * of buffers and starts reporting TID errors against
1484 * the eager buffer it wants to use next.
1485 */
1486 if ( qib7322_wq->eager_cons == qib7322_wq->eager_prod )
1487 break;
1488
1489 /* If we have caught up to where we should be after
1490 * completing this egrindex, stop. We phrase the test
1491 * this way to avoid completing the entire ring when
1492 * we receive the same egrindex twice in a row.
1493 */
1494 if ( ( qib7322_wq->eager_cons ==
1495 ( ( egrindex + 1 ) & ( qib7322_wq->eager_entries - 1 ))))
1496 break;
1497
1498 /* Identify work queue entry and corresponding I/O
1499 * buffer.
1500 */
1501 wqe_idx = ( qib7322_wq->eager_cons & ( wq->num_wqes - 1 ) );
1502 iobuf = wq->iobufs[wqe_idx];
1503 assert ( iobuf != NULL );
1504 wq->iobufs[wqe_idx] = NULL;
1505
1506 /* Complete the eager buffer */
1507 if ( qib7322_wq->eager_cons == egrindex ) {
1508 /* Completing the eager buffer described in
1509 * this header entry.
1510 */
1511 if ( payload_len <= iob_tailroom ( iobuf ) ) {
1512 iob_put ( iobuf, payload_len );
1513 rc = ( err ?
1514 -EIO : ( useegrbfr ? 0 : -ECANCELED ) );
1515 } else {
1516 DBGC ( qib7322, "QIB7322 %p bad payload len "
1517 "%zd\n", qib7322, payload_len );
1518 rc = -EPROTO;
1519 }
1520 /* Redirect to target QP if necessary */
1521 if ( qp != intended_qp ) {
1522 DBGC2 ( qib7322, "QIB7322 %p redirecting QPN "
1523 "%ld => %ld\n",
1524 qib7322, qp->qpn, intended_qp->qpn );
1525 /* Compensate for incorrect fill levels */
1526 qp->recv.fill--;
1527 intended_qp->recv.fill++;
1528 }
1529 ib_complete_recv ( ibdev, intended_qp, &dest, &source,
1530 iobuf, rc );
1531 } else {
1532 /* Completing on a skipped-over eager buffer */
1533 ib_complete_recv ( ibdev, qp, &dest, &source, iobuf,
1534 -ECANCELED );
1535 }
1536
1537 /* Clear eager buffer */
1538 memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1539 qib7322_writeq_array8b ( qib7322, &rcvegr,
1540 qib7322_wq->eager_array,
1541 qib7322_wq->eager_cons );
1542
1543 /* Increment consumer index */
1544 qib7322_wq->eager_cons = ( ( qib7322_wq->eager_cons + 1 ) &
1545 ( qib7322_wq->eager_entries - 1 ) );
1546 }
1547}
1548
1549/**
1550 * Poll receive work queue
1551 *
1552 * @v ibdev Infiniband device
1553 * @v qp Queue pair
1554 */
1555static void qib7322_poll_recv_wq ( struct ib_device *ibdev,
1556 struct ib_queue_pair *qp ) {
1557 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1558 struct ib_work_queue *wq = &qp->recv;
1559 struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1560 struct QIB_7322_RcvHdrHead0 rcvhdrhead;
1561 unsigned int ctx = qib7322_ctx ( ibdev, qp );
1562 unsigned int header_prod;
1563
1564 /* Check for received packets */
1565 header_prod = ( BIT_GET ( &qib7322_wq->header_prod, Value ) << 2 );
1566 if ( header_prod == qib7322_wq->header_cons )
1567 return;
1568
1569 /* Process all received packets */
1570 while ( qib7322_wq->header_cons != header_prod ) {
1571
1572 /* Complete the receive */
1573 qib7322_complete_recv ( ibdev, qp, qib7322_wq->header_cons );
1574
1575 /* Increment the consumer offset */
1576 qib7322_wq->header_cons += QIB7322_RECV_HEADER_SIZE;
1577 qib7322_wq->header_cons %= QIB7322_RECV_HEADERS_SIZE;
1578
1579 /* QIB7322 has only one send buffer per port for VL15,
1580 * which almost always leads to send buffer exhaustion
1581 * and dropped MADs. Mitigate this by refusing to
1582 * process more than one VL15 MAD per poll, which will
1583 * enforce interleaved TX/RX polls.
1584 */
1585 if ( qp->type == IB_QPT_SMI )
1586 break;
1587 }
1588
1589 /* Update consumer offset */
1590 memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
1591 BIT_FILL_2 ( &rcvhdrhead,
1592 RcvHeadPointer, ( qib7322_wq->header_cons >> 2 ),
1593 counter, 1 );
1594 qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
1595 QIB_7322_RcvHdrHead0_offset, ctx );
1596}
1597
1598/**
1599 * Poll completion queue
1600 *
1601 * @v ibdev Infiniband device
1602 * @v cq Completion queue
1603 */
1604static void qib7322_poll_cq ( struct ib_device *ibdev,
1605 struct ib_completion_queue *cq ) {
1606 struct ib_work_queue *wq;
1607
1608 /* Poll associated send and receive queues */
1609 list_for_each_entry ( wq, &cq->work_queues, list ) {
1610 if ( wq->is_send ) {
1611 qib7322_poll_send_wq ( ibdev, wq->qp );
1612 } else {
1613 qib7322_poll_recv_wq ( ibdev, wq->qp );
1614 }
1615 }
1616}
1617
1618/***************************************************************************
1619 *
1620 * Event queues
1621 *
1622 ***************************************************************************
1623 */
1624
1625/**
1626 * Poll event queue
1627 *
1628 * @v ibdev Infiniband device
1629 */
1630static void qib7322_poll_eq ( struct ib_device *ibdev ) {
1631 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1632 struct QIB_7322_ErrStatus_0 errstatus;
1633 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1634
1635 /* Check for and clear status bits */
1636 DBG_DISABLE ( DBGLVL_IO );
1637 qib7322_readq_port ( qib7322, &errstatus,
1638 QIB_7322_ErrStatus_0_offset, port );
1639 if ( errstatus.u.qwords[0] ) {
1640 DBGC ( qib7322, "QIB7322 %p port %d status %08x%08x\n", qib7322,
1641 port, errstatus.u.dwords[1], errstatus.u.dwords[0] );
1642 qib7322_writeq_port ( qib7322, &errstatus,
1643 QIB_7322_ErrClear_0_offset, port );
1644 }
1645 DBG_ENABLE ( DBGLVL_IO );
1646
1647 /* Check for link status changes */
1648 if ( BIT_GET ( &errstatus, IBStatusChanged ) )
1649 qib7322_link_state_changed ( ibdev );
1650}
1651
1652/***************************************************************************
1653 *
1654 * Infiniband link-layer operations
1655 *
1656 ***************************************************************************
1657 */
1658
1659/**
1660 * Determine supported link speeds
1661 *
1662 * @v qib7322 QIB7322 device
1663 * @ret supported Supported link speeds
1664 */
1665static unsigned int qib7322_link_speed_supported ( struct qib7322 *qib7322,
1666 unsigned int port ) {
1667 struct QIB_7322_feature_mask features;
1668 struct QIB_7322_Revision revision;
1669 unsigned int supported;
1670 unsigned int boardid;
1671
1672 /* Read the active feature mask */
1673 qib7322_readq ( qib7322, &features,
1674 QIB_7322_active_feature_mask_offset );
1675 switch ( port ) {
1676 case 0 :
1677 supported = BIT_GET ( &features, Port0_Link_Speed_Supported );
1678 break;
1679 case 1 :
1680 supported = BIT_GET ( &features, Port1_Link_Speed_Supported );
1681 break;
1682 default:
1683 DBGC ( qib7322, "QIB7322 %p port %d is invalid\n",
1684 qib7322, port );
1685 supported = 0;
1686 break;
1687 }
1688
1689 /* Apply hacks for specific board IDs */
1690 qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
1691 boardid = BIT_GET ( &revision, BoardID );
1692 switch ( boardid ) {
1693 case QIB7322_BOARD_QMH7342 :
1694 DBGC2 ( qib7322, "QIB7322 %p is a QMH7342; forcing QDR-only\n",
1695 qib7322 );
1696 supported = IB_LINK_SPEED_QDR;
1697 break;
1698 default:
1699 /* Do nothing */
1700 break;
1701 }
1702
1703 DBGC2 ( qib7322, "QIB7322 %p port %d %s%s%s%s\n", qib7322, port,
1704 ( supported ? "supports" : "disabled" ),
1705 ( ( supported & IB_LINK_SPEED_SDR ) ? " SDR" : "" ),
1706 ( ( supported & IB_LINK_SPEED_DDR ) ? " DDR" : "" ),
1707 ( ( supported & IB_LINK_SPEED_QDR ) ? " QDR" : "" ) );
1708 return supported;
1709}
1710
1711/**
1712 * Initialise Infiniband link
1713 *
1714 * @v ibdev Infiniband device
1715 * @ret rc Return status code
1716 */
1717static int qib7322_open ( struct ib_device *ibdev ) {
1718 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1719 struct QIB_7322_IBCCtrlA_0 ibcctrla;
1720 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1721
1722 /* Enable link */
1723 qib7322_readq_port ( qib7322, &ibcctrla,
1724 QIB_7322_IBCCtrlA_0_offset, port );
1725 BIT_SET ( &ibcctrla, IBLinkEn, 1 );
1726 qib7322_writeq_port ( qib7322, &ibcctrla,
1727 QIB_7322_IBCCtrlA_0_offset, port );
1728
1729 return 0;
1730}
1731
1732/**
1733 * Close Infiniband link
1734 *
1735 * @v ibdev Infiniband device
1736 */
1737static void qib7322_close ( struct ib_device *ibdev ) {
1738 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1739 struct QIB_7322_IBCCtrlA_0 ibcctrla;
1740 unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1741
1742 /* Disable link */
1743 qib7322_readq_port ( qib7322, &ibcctrla,
1744 QIB_7322_IBCCtrlA_0_offset, port );
1745 BIT_SET ( &ibcctrla, IBLinkEn, 0 );
1746 qib7322_writeq_port ( qib7322, &ibcctrla,
1747 QIB_7322_IBCCtrlA_0_offset, port );
1748}
1749
1750/***************************************************************************
1751 *
1752 * Multicast group operations
1753 *
1754 ***************************************************************************
1755 */
1756
1757/**
1758 * Attach to multicast group
1759 *
1760 * @v ibdev Infiniband device
1761 * @v qp Queue pair
1762 * @v gid Multicast GID
1763 * @ret rc Return status code
1764 */
1765static int qib7322_mcast_attach ( struct ib_device *ibdev,
1766 struct ib_queue_pair *qp,
1767 union ib_gid *gid ) {
1768 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1769
1770 ( void ) qib7322;
1771 ( void ) qp;
1772 ( void ) gid;
1773 return 0;
1774}
1775
1776/**
1777 * Detach from multicast group
1778 *
1779 * @v ibdev Infiniband device
1780 * @v qp Queue pair
1781 * @v gid Multicast GID
1782 */
1783static void qib7322_mcast_detach ( struct ib_device *ibdev,
1784 struct ib_queue_pair *qp,
1785 union ib_gid *gid ) {
1786 struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1787
1788 ( void ) qib7322;
1789 ( void ) qp;
1790 ( void ) gid;
1791 }
1792
1793/** QIB7322 Infiniband operations */
1794static struct ib_device_operations qib7322_ib_operations = {
1795 .create_cq = qib7322_create_cq,
1796 .destroy_cq = qib7322_destroy_cq,
1797 .create_qp = qib7322_create_qp,
1798 .modify_qp = qib7322_modify_qp,
1799 .destroy_qp = qib7322_destroy_qp,
1800 .post_send = qib7322_post_send,
1801 .post_recv = qib7322_post_recv,
1802 .poll_cq = qib7322_poll_cq,
1803 .poll_eq = qib7322_poll_eq,
1804 .open = qib7322_open,
1805 .close = qib7322_close,
1806 .mcast_attach = qib7322_mcast_attach,
1807 .mcast_detach = qib7322_mcast_detach,
1808 .set_port_info = qib7322_set_port_info,
1809 .set_pkey_table = qib7322_set_pkey_table,
1810};
1811
1812/***************************************************************************
1813 *
1814 * I2C bus operations
1815 *
1816 ***************************************************************************
1817 */
1818
1819/** QIB7322 I2C bit to GPIO mappings */
1820static unsigned int qib7322_i2c_bits[] = {
1821 [I2C_BIT_SCL] = ( 1 << QIB7322_GPIO_SCL ),
1822 [I2C_BIT_SDA] = ( 1 << QIB7322_GPIO_SDA ),
1823};
1824
1825/**
1826 * Read QIB7322 I2C line status
1827 *
1828 * @v basher Bit-bashing interface
1829 * @v bit_id Bit number
1830 * @ret zero Input is a logic 0
1831 * @ret non-zero Input is a logic 1
1832 */
1833static int qib7322_i2c_read_bit ( struct bit_basher *basher,
1834 unsigned int bit_id ) {
1835 struct qib7322 *qib7322 =
1836 container_of ( basher, struct qib7322, i2c.basher );
1837 struct QIB_7322_EXTStatus extstatus;
1838 unsigned int status;
1839
1840 DBG_DISABLE ( DBGLVL_IO );
1841
1842 qib7322_readq ( qib7322, &extstatus, QIB_7322_EXTStatus_offset );
1843 status = ( BIT_GET ( &extstatus, GPIOIn ) & qib7322_i2c_bits[bit_id] );
1844
1845 DBG_ENABLE ( DBGLVL_IO );
1846
1847 return status;
1848}
1849
1850/**
1851 * Write QIB7322 I2C line status
1852 *
1853 * @v basher Bit-bashing interface
1854 * @v bit_id Bit number
1855 * @v data Value to write
1856 */
1857static void qib7322_i2c_write_bit ( struct bit_basher *basher,
1858 unsigned int bit_id, unsigned long data ) {
1859 struct qib7322 *qib7322 =
1860 container_of ( basher, struct qib7322, i2c.basher );
1861 struct QIB_7322_EXTCtrl extctrl;
1862 struct QIB_7322_GPIO gpioout;
1863 unsigned int bit = qib7322_i2c_bits[bit_id];
1864 unsigned int outputs = 0;
1865 unsigned int output_enables = 0;
1866
1867 DBG_DISABLE ( DBGLVL_IO );
1868
1869 /* Read current GPIO mask and outputs */
1870 qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1871 qib7322_readq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1872
1873 /* Update outputs and output enables. I2C lines are tied
1874 * high, so we always set the output to 0 and use the output
1875 * enable to control the line.
1876 */
1877 output_enables = BIT_GET ( &extctrl, GPIOOe );
1878 output_enables = ( ( output_enables & ~bit ) | ( ~data & bit ) );
1879 outputs = BIT_GET ( &gpioout, GPIO );
1880 outputs = ( outputs & ~bit );
1881 BIT_SET ( &extctrl, GPIOOe, output_enables );
1882 BIT_SET ( &gpioout, GPIO, outputs );
1883
1884 /* Write the output enable first; that way we avoid logic
1885 * hazards.
1886 */
1887 qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1888 qib7322_writeq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1889 mb();
1890
1891 DBG_ENABLE ( DBGLVL_IO );
1892}
1893
1894/** QIB7322 I2C bit-bashing interface operations */
1899
1900/**
1901 * Initialise QIB7322 I2C subsystem
1902 *
1903 * @v qib7322 QIB7322 device
1904 * @ret rc Return status code
1905 */
1906static int qib7322_init_i2c ( struct qib7322 *qib7322 ) {
1907 static int try_eeprom_address[] = { 0x51, 0x50 };
1908 unsigned int i;
1909 int rc;
1910
1911 /* Initialise bus */
1912 if ( ( rc = init_i2c_bit_basher ( &qib7322->i2c,
1913 &qib7322_i2c_basher_ops ) ) != 0 ) {
1914 DBGC ( qib7322, "QIB7322 %p could not initialise I2C bus: %s\n",
1915 qib7322, strerror ( rc ) );
1916 return rc;
1917 }
1918
1919 /* Probe for devices */
1920 for ( i = 0 ; i < ( sizeof ( try_eeprom_address ) /
1921 sizeof ( try_eeprom_address[0] ) ) ; i++ ) {
1922 init_i2c_eeprom ( &qib7322->eeprom, try_eeprom_address[i] );
1923 if ( ( rc = i2c_check_presence ( &qib7322->i2c.i2c,
1924 &qib7322->eeprom ) ) == 0 ) {
1925 DBGC2 ( qib7322, "QIB7322 %p found EEPROM at %02x\n",
1926 qib7322, try_eeprom_address[i] );
1927 return 0;
1928 }
1929 }
1930
1931 DBGC ( qib7322, "QIB7322 %p could not find EEPROM\n", qib7322 );
1932 return -ENODEV;
1933}
1934
1935/**
1936 * Read EEPROM parameters
1937 *
1938 * @v qib7322 QIB7322 device
1939 * @ret rc Return status code
1940 */
1941static int qib7322_read_eeprom ( struct qib7322 *qib7322 ) {
1942 struct i2c_interface *i2c = &qib7322->i2c.i2c;
1943 union ib_guid *guid = &qib7322->guid;
1944 int rc;
1945
1946 /* Read GUID */
1947 if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1948 QIB7322_EEPROM_GUID_OFFSET, guid->bytes,
1949 sizeof ( *guid ) ) ) != 0 ) {
1950 DBGC ( qib7322, "QIB7322 %p could not read GUID: %s\n",
1951 qib7322, strerror ( rc ) );
1952 return rc;
1953 }
1954 DBGC2 ( qib7322, "QIB7322 %p has GUID " IB_GUID_FMT "\n",
1955 qib7322, IB_GUID_ARGS ( guid ) );
1956
1957 /* Read serial number (debug only) */
1958 if ( DBG_LOG ) {
1959 uint8_t serial[QIB7322_EEPROM_SERIAL_SIZE + 1];
1960
1961 serial[ sizeof ( serial ) - 1 ] = '\0';
1962 if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1963 QIB7322_EEPROM_SERIAL_OFFSET, serial,
1964 ( sizeof ( serial ) - 1 ) ) ) != 0 ) {
1965 DBGC ( qib7322, "QIB7322 %p could not read serial: "
1966 "%s\n", qib7322, strerror ( rc ) );
1967 return rc;
1968 }
1969 DBGC2 ( qib7322, "QIB7322 %p has serial number \"%s\"\n",
1970 qib7322, serial );
1971 }
1972
1973 return 0;
1974}
1975
1976/***************************************************************************
1977 *
1978 * Advanced High-performance Bus (AHB) access
1979 *
1980 ***************************************************************************
1981 */
1982
1983/**
1984 * Wait for AHB transaction to complete
1985 *
1986 * @v qib7322 QIB7322 device
1987 * @ret rc Return status code
1988 */
1989static int qib7322_ahb_wait ( struct qib7322 *qib7322 ) {
1990 struct QIB_7322_ahb_transaction_reg transaction;
1991 unsigned int i;
1992
1993 /* Wait for Ready bit to be asserted */
1994 for ( i = 0 ; i < QIB7322_AHB_MAX_WAIT_US ; i++ ) {
1995 qib7322_readq ( qib7322, &transaction,
1996 QIB_7322_ahb_transaction_reg_offset );
1997 if ( BIT_GET ( &transaction, ahb_rdy ) )
1998 return 0;
1999 udelay ( 1 );
2000 }
2001
2002 DBGC ( qib7322, "QIB7322 %p timed out waiting for AHB transaction\n",
2003 qib7322 );
2004 return -ETIMEDOUT;
2005}
2006
2007/**
2008 * Request ownership of the AHB
2009 *
2010 * @v qib7322 QIB7322 device
2011 * @v location AHB location
2012 * @ret rc Return status code
2013 */
2014static int qib7322_ahb_request ( struct qib7322 *qib7322,
2015 unsigned int location ) {
2016 struct QIB_7322_ahb_access_ctrl access;
2017 int rc;
2018
2019 /* Request ownership */
2020 memset ( &access, 0, sizeof ( access ) );
2021 BIT_FILL_2 ( &access,
2022 sw_ahb_sel, 1,
2023 sw_sel_ahb_trgt, QIB7322_AHB_LOC_TARGET ( location ) );
2024 qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2025
2026 /* Wait for ownership to be granted */
2027 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 ) {
2028 DBGC ( qib7322, "QIB7322 %p could not obtain AHB ownership: "
2029 "%s\n", qib7322, strerror ( rc ) );
2030 return rc;
2031 }
2032
2033 return 0;
2034}
2035
2036/**
2037 * Release ownership of the AHB
2038 *
2039 * @v qib7322 QIB7322 device
2040 */
2041static void qib7322_ahb_release ( struct qib7322 *qib7322 ) {
2042 struct QIB_7322_ahb_access_ctrl access;
2043
2044 memset ( &access, 0, sizeof ( access ) );
2045 qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2046}
2047
2048/**
2049 * Read data via AHB
2050 *
2051 * @v qib7322 QIB7322 device
2052 * @v location AHB location
2053 * @v data Data to read
2054 * @ret rc Return status code
2055 *
2056 * You must have already acquired ownership of the AHB.
2057 */
2058static int qib7322_ahb_read ( struct qib7322 *qib7322, unsigned int location,
2059 uint32_t *data ) {
2060 struct QIB_7322_ahb_transaction_reg xact;
2061 int rc;
2062
2063 /* Avoid returning uninitialised data on error */
2064 *data = 0;
2065
2066 /* Initiate transaction */
2067 memset ( &xact, 0, sizeof ( xact ) );
2068 BIT_FILL_2 ( &xact,
2069 ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2070 write_not_read, 0 );
2071 qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2072
2073 /* Wait for transaction to complete */
2074 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2075 return rc;
2076
2077 /* Read transaction data */
2078 qib7322_readq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2079 *data = BIT_GET ( &xact, ahb_data );
2080 return 0;
2081}
2082
2083/**
2084 * Write data via AHB
2085 *
2086 * @v qib7322 QIB7322 device
2087 * @v location AHB location
2088 * @v data Data to write
2089 * @ret rc Return status code
2090 *
2091 * You must have already acquired ownership of the AHB.
2092 */
2093static int qib7322_ahb_write ( struct qib7322 *qib7322, unsigned int location,
2094 uint32_t data ) {
2095 struct QIB_7322_ahb_transaction_reg xact;
2096 int rc;
2097
2098 /* Initiate transaction */
2099 memset ( &xact, 0, sizeof ( xact ) );
2100 BIT_FILL_3 ( &xact,
2101 ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2102 write_not_read, 1,
2103 ahb_data, data );
2104 qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2105
2106 /* Wait for transaction to complete */
2107 if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2108 return rc;
2109
2110 return 0;
2111}
2112
2113/**
2114 * Read/modify/write AHB register
2115 *
2116 * @v qib7322 QIB7322 device
2117 * @v location AHB location
2118 * @v value Value to set
2119 * @v mask Mask to apply to old value
2120 * @ret rc Return status code
2121 */
2122static int qib7322_ahb_mod_reg ( struct qib7322 *qib7322, unsigned int location,
2123 uint32_t value, uint32_t mask ) {
2124 uint32_t old_value;
2125 uint32_t new_value;
2126 int rc;
2127
2128 DBG_DISABLE ( DBGLVL_IO );
2129
2130 /* Sanity check */
2131 assert ( ( value & mask ) == value );
2132
2133 /* Acquire bus ownership */
2134 if ( ( rc = qib7322_ahb_request ( qib7322, location ) ) != 0 )
2135 goto out;
2136
2137 /* Read existing value */
2138 if ( ( rc = qib7322_ahb_read ( qib7322, location, &old_value ) ) != 0 )
2139 goto out_release;
2140
2141 /* Update value */
2142 new_value = ( ( old_value & ~mask ) | value );
2143 DBGCP ( qib7322, "QIB7322 %p AHB %x %#08x => %#08x\n",
2144 qib7322, location, old_value, new_value );
2145 if ( ( rc = qib7322_ahb_write ( qib7322, location, new_value ) ) != 0 )
2146 goto out_release;
2147
2148 out_release:
2149 /* Release bus */
2150 qib7322_ahb_release ( qib7322 );
2151 out:
2152 DBG_ENABLE ( DBGLVL_IO );
2153 return rc;
2154}
2155
2156/**
2157 * Read/modify/write AHB register across all ports and channels
2158 *
2159 * @v qib7322 QIB7322 device
2160 * @v reg AHB register
2161 * @v value Value to set
2162 * @v mask Mask to apply to old value
2163 * @ret rc Return status code
2164 */
2165static int qib7322_ahb_mod_reg_all ( struct qib7322 *qib7322, unsigned int reg,
2166 uint32_t value, uint32_t mask ) {
2167 unsigned int port;
2168 unsigned int channel;
2169 unsigned int location;
2170 int rc;
2171
2172 for ( port = 0 ; port < QIB7322_MAX_PORTS ; port++ ) {
2173 for ( channel = 0 ; channel < QIB7322_MAX_WIDTH ; channel++ ) {
2174 location = QIB7322_AHB_LOCATION ( port, channel, reg );
2175 if ( ( rc = qib7322_ahb_mod_reg ( qib7322, location,
2176 value, mask ) ) != 0 )
2177 return rc;
2178 }
2179 }
2180 return 0;
2181}
2182
2183/***************************************************************************
2184 *
2185 * Infiniband SerDes initialisation
2186 *
2187 ***************************************************************************
2188 */
2189
2190/**
2191 * Initialise the IB SerDes
2192 *
2193 * @v qib7322 QIB7322 device
2194 * @ret rc Return status code
2195 */
2196static int qib7322_init_ib_serdes ( struct qib7322 *qib7322 ) {
2197 struct QIB_7322_IBCCtrlA_0 ibcctrla;
2198 struct QIB_7322_IBCCtrlB_0 ibcctrlb;
2199 struct QIB_7322_IBPCSConfig_0 ibpcsconfig;
2200
2201 /* Configure sensible defaults for IBC */
2202 memset ( &ibcctrla, 0, sizeof ( ibcctrla ) );
2203 BIT_FILL_5 ( &ibcctrla, /* Tuning values taken from Linux driver */
2204 FlowCtrlPeriod, 0x03,
2205 FlowCtrlWaterMark, 0x05,
2206 MaxPktLen, ( ( QIB7322_RECV_HEADER_SIZE +
2207 QIB7322_RECV_PAYLOAD_SIZE +
2208 4 /* ICRC */ ) >> 2 ),
2209 PhyerrThreshold, 0xf,
2210 OverrunThreshold, 0xf );
2211 qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_0_offset );
2212 qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_1_offset );
2213
2214 /* Force SDR only to avoid needing all the DDR tuning,
2215 * Mellanox compatibility hacks etc. SDR is plenty for
2216 * boot-time operation.
2217 */
2218 qib7322_readq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2219 BIT_SET ( &ibcctrlb, IB_ENHANCED_MODE, 0 );
2220 BIT_SET ( &ibcctrlb, SD_SPEED_SDR, 1 );
2221 BIT_SET ( &ibcctrlb, SD_SPEED_DDR, 0 );
2222 BIT_SET ( &ibcctrlb, SD_SPEED_QDR, 0 );
2223 BIT_SET ( &ibcctrlb, IB_NUM_CHANNELS, 1 ); /* 4X only */
2224 BIT_SET ( &ibcctrlb, IB_LANE_REV_SUPPORTED, 0 );
2225 BIT_SET ( &ibcctrlb, HRTBT_ENB, 0 );
2226 BIT_SET ( &ibcctrlb, HRTBT_AUTO, 0 );
2227 qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2228 qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_1_offset );
2229
2230 /* Tune SerDes */
2231 qib7322_ahb_mod_reg_all ( qib7322, 2, 0, 0x00000e00UL );
2232
2233 /* Bring XGXS out of reset */
2234 memset ( &ibpcsconfig, 0, sizeof ( ibpcsconfig ) );
2235 qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_0_offset );
2236 qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_1_offset );
2237
2238 return 0;
2239}
2240
2241/***************************************************************************
2242 *
2243 * PCI layer interface
2244 *
2245 ***************************************************************************
2246 */
2247
2248/**
2249 * Reset QIB7322
2250 *
2251 * @v qib7322 QIB7322 device
2252 * @v pci PCI device
2253 * @ret rc Return status code
2254 */
2255static void qib7322_reset ( struct qib7322 *qib7322, struct pci_device *pci ) {
2256 struct QIB_7322_Control control;
2257 struct pci_config_backup backup;
2258
2259 /* Back up PCI configuration space */
2260 pci_backup ( pci, &backup, PCI_CONFIG_BACKUP_ALL, NULL );
2261
2262 /* Assert reset */
2263 memset ( &control, 0, sizeof ( control ) );
2264 BIT_FILL_1 ( &control, SyncReset, 1 );
2265 qib7322_writeq ( qib7322, &control, QIB_7322_Control_offset );
2266
2267 /* Wait for reset to complete */
2268 mdelay ( 1000 );
2269
2270 /* Restore PCI configuration space */
2271 pci_restore ( pci, &backup, PCI_CONFIG_BACKUP_ALL, NULL );
2272}
2273
2274/**
2275 * Probe PCI device
2276 *
2277 * @v pci PCI device
2278 * @v id PCI ID
2279 * @ret rc Return status code
2280 */
2281static int qib7322_probe ( struct pci_device *pci ) {
2282 struct qib7322 *qib7322;
2283 struct QIB_7322_Revision revision;
2284 struct ib_device *ibdev;
2285 unsigned int link_speed_supported;
2286 int i;
2287 int rc;
2288
2289 /* Allocate QIB7322 device */
2290 qib7322 = zalloc ( sizeof ( *qib7322 ) );
2291 if ( ! qib7322 ) {
2292 rc = -ENOMEM;
2293 goto err_alloc_qib7322;
2294 }
2295 pci_set_drvdata ( pci, qib7322 );
2296
2297 /* Fix up PCI device */
2298 adjust_pci_device ( pci );
2299
2300 /* Map PCI BARs */
2301 qib7322->regs = pci_ioremap ( pci, pci->membase, QIB7322_BAR0_SIZE );
2302 DBGC2 ( qib7322, "QIB7322 %p has BAR at %08lx\n",
2303 qib7322, pci->membase );
2304
2305 /* Reset device */
2306 qib7322_reset ( qib7322, pci );
2307
2308 /* Print some general data */
2309 qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
2310 DBGC2 ( qib7322, "QIB7322 %p board %02lx v%ld.%ld.%ld.%ld\n", qib7322,
2311 BIT_GET ( &revision, BoardID ),
2312 BIT_GET ( &revision, R_SW ),
2313 BIT_GET ( &revision, R_Arch ),
2314 BIT_GET ( &revision, R_ChipRevMajor ),
2315 BIT_GET ( &revision, R_ChipRevMinor ) );
2316
2317 /* Initialise I2C subsystem */
2318 if ( ( rc = qib7322_init_i2c ( qib7322 ) ) != 0 )
2319 goto err_init_i2c;
2320
2321 /* Read EEPROM parameters */
2322 if ( ( rc = qib7322_read_eeprom ( qib7322 ) ) != 0 )
2323 goto err_read_eeprom;
2324
2325 /* Initialise send datapath */
2326 if ( ( rc = qib7322_init_send ( qib7322 ) ) != 0 )
2327 goto err_init_send;
2328
2329 /* Initialise receive datapath */
2330 if ( ( rc = qib7322_init_recv ( qib7322 ) ) != 0 )
2331 goto err_init_recv;
2332
2333 /* Initialise the IB SerDes */
2334 if ( ( rc = qib7322_init_ib_serdes ( qib7322 ) ) != 0 )
2335 goto err_init_ib_serdes;
2336
2337 /* Allocate Infiniband devices */
2338 for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2339 link_speed_supported =
2340 qib7322_link_speed_supported ( qib7322, i );
2341 if ( ! link_speed_supported )
2342 continue;
2343 ibdev = alloc_ibdev ( 0 );
2344 if ( ! ibdev ) {
2345 rc = -ENOMEM;
2346 goto err_alloc_ibdev;
2347 }
2348 qib7322->ibdev[i] = ibdev;
2349 ibdev->dev = &pci->dev;
2350 ibdev->op = &qib7322_ib_operations;
2351 ibdev->port = ( QIB7322_PORT_BASE + i );
2352 ibdev->ports = QIB7322_MAX_PORTS;
2353 ibdev->link_width_enabled = ibdev->link_width_supported =
2354 IB_LINK_WIDTH_4X; /* 1x does not work */
2355 ibdev->link_speed_enabled = ibdev->link_speed_supported =
2356 IB_LINK_SPEED_SDR; /* to avoid need for link tuning */
2357 memcpy ( &ibdev->node_guid, &qib7322->guid,
2358 sizeof ( ibdev->node_guid ) );
2359 memcpy ( &ibdev->gid.s.guid, &qib7322->guid,
2360 sizeof ( ibdev->gid.s.guid ) );
2361 assert ( ( ibdev->gid.s.guid.bytes[7] & i ) == 0 );
2362 ibdev->gid.s.guid.bytes[7] |= i;
2363 ib_set_drvdata ( ibdev, qib7322 );
2364 }
2365
2366 /* Register Infiniband devices */
2367 for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2368 if ( ! qib7322->ibdev[i] )
2369 continue;
2370 if ( ( rc = register_ibdev ( qib7322->ibdev[i] ) ) != 0 ) {
2371 DBGC ( qib7322, "QIB7322 %p port %d could not register "
2372 "IB device: %s\n", qib7322, i, strerror ( rc ) );
2373 goto err_register_ibdev;
2374 }
2375 }
2376
2377 return 0;
2378
2379 i = QIB7322_MAX_PORTS;
2380 err_register_ibdev:
2381 for ( i-- ; i >= 0 ; i-- ) {
2382 if ( qib7322->ibdev[i] )
2383 unregister_ibdev ( qib7322->ibdev[i] );
2384 }
2385 i = QIB7322_MAX_PORTS;
2386 err_alloc_ibdev:
2387 for ( i-- ; i >= 0 ; i-- )
2388 ibdev_put ( qib7322->ibdev[i] );
2389 err_init_ib_serdes:
2390 qib7322_fini_send ( qib7322 );
2391 err_init_send:
2392 qib7322_fini_recv ( qib7322 );
2393 err_init_recv:
2394 err_read_eeprom:
2395 err_init_i2c:
2396 iounmap ( qib7322->regs );
2397 free ( qib7322 );
2398 err_alloc_qib7322:
2399 return rc;
2400}
2401
2402/**
2403 * Remove PCI device
2404 *
2405 * @v pci PCI device
2406 */
2407static void qib7322_remove ( struct pci_device *pci ) {
2408 struct qib7322 *qib7322 = pci_get_drvdata ( pci );
2409 int i;
2410
2411 for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- ) {
2412 if ( qib7322->ibdev[i] )
2413 unregister_ibdev ( qib7322->ibdev[i] );
2414 }
2415 for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- )
2416 ibdev_put ( qib7322->ibdev[i] );
2417 qib7322_fini_send ( qib7322 );
2418 qib7322_fini_recv ( qib7322 );
2419 iounmap ( qib7322->regs );
2420 free ( qib7322 );
2421}
2422
2423static struct pci_device_id qib7322_nics[] = {
2424 PCI_ROM ( 0x1077, 0x7322, "iba7322", "IBA7322 QDR InfiniBand HCA", 0 ),
2425};
2426
2427struct pci_driver qib7322_driver __pci_driver = {
2428 .ids = qib7322_nics,
2429 .id_count = ( sizeof ( qib7322_nics ) / sizeof ( qib7322_nics[0] ) ),
2430 .probe = qib7322_probe,
2431 .remove = qib7322_remove,
2432};
NULL
#define NULL
NULL pointer (VOID *)
Definition Base.h:322
cqn
__be32 cqn
Definition CIB_PRM.h:1
gid
u8 gid[16]
Definition CIB_PRM.h:3
ctx
struct golan_eq_context ctx
Definition CIB_PRM.h:0
port
u8 port
Port number.
Definition CIB_PRM.h:3
port_state
u8 port_state
Definition CIB_PRM.h:10
out
__be32 out[4]
Definition CIB_PRM.h:8
rc
struct arbelprm_rc_send_wqe rc
Definition arbel.h:3
value
pseudo_bit_t value[0x00020]
Definition arbel.h:2
mad
union ib_mad mad
Definition arbel.h:1
headers
uint8_t headers[IB_MAX_HEADER_SIZE]
Definition arbel.h:3
qp
struct arbelprm_qp_db_record qp
Definition arbel.h:2
uint16_t
unsigned short uint16_t
Definition stdint.h:11
uint32_t
unsigned int uint32_t
Definition stdint.h:12
physaddr_t
unsigned long physaddr_t
Definition stdint.h:20
uint64_t
unsigned long long uint64_t
Definition stdint.h:13
uint8_t
unsigned char uint8_t
Definition stdint.h:10
ssize_t
signed long ssize_t
Definition stdint.h:7
index
long index
Definition bigint.h:65
dest
if(len >=6 *4) __asm__ __volatile__("movsl" if(len >=5 *4) __asm__ __volatile__("movsl" if(len >=4 *4) __asm__ __volatile__("movsl" if(len >=3 *4) __asm__ __volatile__("movsl" if(len >=2 *4) __asm__ __volatile__("movsl" if(len >=1 *4) __asm__ __volatile__("movsl" if((len % 4) >=2) __asm__ __volatile__("movsw" if((len % 2) >=1) __asm__ __volatile__("movsb" retur dest)
Definition string.h:151
assert.h
Assertions.
build_assert
#define build_assert(condition)
Assert a condition at build time (after dead code elimination)
Definition assert.h:77
assert
#define assert(condition)
Assert a condition at run-time.
Definition assert.h:50
bitbash.h
Bit-bashing interfaces.
offset
uint16_t offset
Offset to command line.
Definition bzimage.h:3
len
ring len
Length.
Definition dwmac.h:226
addr
uint32_t addr
Buffer address.
Definition dwmac.h:9
serial
uint64_t serial
Serial number.
Definition edd.h:1
guid
uint64_t guid
GUID.
Definition edd.h:1
features
uint32_t features
Supported features.
Definition ena.h:5
data
uint8_t data[48]
Additional event data.
Definition ena.h:11
supported
uint16_t supported
Bitmask of supported option values.
Definition ena.h:1
status
uint8_t status
Status.
Definition ena.h:5
errno.h
Error codes.
xact
uint32_t xact
Requester transaction ID.
Definition eth_slow.h:7
__unused
#define __unused
Declare a variable or data structure as unused.
Definition compiler.h:573
DBGCP_HDA
#define DBGCP_HDA(...)
Definition compiler.h:540
DBGC2
#define DBGC2(...)
Definition compiler.h:522
DBGLVL_IO
#define DBGLVL_IO
Definition compiler.h:322
DBG_DISABLE
#define DBG_DISABLE(level)
Definition compiler.h:312
DBGCP
#define DBGCP(...)
Definition compiler.h:539
DBG_ENABLE
#define DBG_ENABLE(level)
Definition compiler.h:313
DBGC
#define DBGC(...)
Definition compiler.h:505
DBG_LOG
#define DBG_LOG
Definition compiler.h:317
bufsize
uint8_t bufsize
Size of the packet, in bytes.
Definition int13.h:1
start
uint32_t start
Starting offset.
Definition netvsc.h:1
size
uint16_t size
Buffer size.
Definition dwmac.h:3
count
static unsigned int count
Number of entries.
Definition dwmac.h:220
FILE_LICENCE
#define FILE_LICENCE(_licence)
Declare a particular licence as applying to a file.
Definition compiler.h:896
ENOENT
#define ENOENT
No such file or directory.
Definition errno.h:515
EINVAL
#define EINVAL
Invalid argument.
Definition errno.h:429
ETIMEDOUT
#define ETIMEDOUT
Connection timed out.
Definition errno.h:670
EPROTO
#define EPROTO
Protocol error.
Definition errno.h:625
ENOMEM
#define ENOMEM
Not enough space.
Definition errno.h:535
EIO
#define EIO
Input/output error.
Definition errno.h:434
ECANCELED
#define ECANCELED
Operation canceled.
Definition errno.h:344
ENOBUFS
#define ENOBUFS
No buffer space available.
Definition errno.h:499
ENODEV
#define ENODEV
No such device.
Definition errno.h:510
i2c.h
I2C interface.
i2c_check_presence
static int i2c_check_presence(struct i2c_interface *i2c, struct i2c_device *i2cdev)
Check presence of I2C device.
Definition i2c.h:135
I2C_BIT_SDA
@ I2C_BIT_SDA
Serial data.
Definition i2c.h:116
I2C_BIT_SCL
@ I2C_BIT_SCL
Serial clock.
Definition i2c.h:114
init_i2c_eeprom
static __always_inline void init_i2c_eeprom(struct i2c_device *i2cdev, unsigned int dev_addr)
Initialise generic I2C EEPROM device.
Definition i2c.h:149
init_i2c_bit_basher
int init_i2c_bit_basher(struct i2c_bit_basher *i2cbit, struct bit_basher_operations *bash_op)
Initialise I2C bit-bashing interface.
Definition i2c_bit.c:387
IB_LINK_SPEED_DDR
#define IB_LINK_SPEED_DDR
Definition ib_mad.h:146
IB_LINK_SPEED_SDR
#define IB_LINK_SPEED_SDR
Definition ib_mad.h:145
IB_LINK_SPEED_QDR
#define IB_LINK_SPEED_QDR
Definition ib_mad.h:147
IB_LINK_WIDTH_1X
#define IB_LINK_WIDTH_1X
Definition ib_mad.h:140
port_info
struct ib_port_info port_info
Definition ib_mad.h:3
revision
uint32_t revision
Entry point revision.
Definition ib_mad.h:9
IB_LINK_WIDTH_4X
#define IB_LINK_WIDTH_4X
Definition ib_mad.h:141
ib_pull
int ib_pull(struct ib_device *ibdev, struct io_buffer *iobuf, struct ib_queue_pair **qp, size_t *payload_len, struct ib_address_vector *dest, struct ib_address_vector *source)
Remove IB headers.
Definition ib_packet.c:133
ib_push
int ib_push(struct ib_device *ibdev, struct io_buffer *iobuf, struct ib_queue_pair *qp, size_t payload_len, const struct ib_address_vector *dest)
Add IB headers.
Definition ib_packet.c:52
IB_GUID_FMT
#define IB_GUID_FMT
Infiniband Globally Unique Identifier debug message format.
Definition ib_packet.h:27
IB_MAX_HEADER_SIZE
#define IB_MAX_HEADER_SIZE
Maximum size required for IB headers.
Definition ib_packet.h:157
IB_GUID_ARGS
#define IB_GUID_ARGS(guid)
Infiniband Globally Unique Identifier debug message arguments.
Definition ib_packet.h:30
bit
static unsigned int unsigned int bit
Definition bigint.h:392
io.h
iPXE I/O API
mb
void mb(void)
Memory barrier.
readq
#define readq(io_addr)
Definition io.h:234
virt_to_bus
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition io.h:184
writeq
#define writeq(data, io_addr)
Definition io.h:273
iounmap
void iounmap(volatile const void *io_addr)
Unmap I/O address.
pci_ioremap
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
string.h
String functions.
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
memset
void * memset(void *dest, int character, size_t len) __nonnull
ib_link_state_changed
void ib_link_state_changed(struct ib_device *ibdev)
Notify of Infiniband link state change.
Definition infiniband.c:637
ib_complete_recv
void ib_complete_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, struct ib_address_vector *dest, struct ib_address_vector *source, struct io_buffer *iobuf, int rc)
Complete receive work queue entry.
Definition infiniband.c:536
register_ibdev
int register_ibdev(struct ib_device *ibdev)
Register Infiniband device.
Definition infiniband.c:944
unregister_ibdev
void unregister_ibdev(struct ib_device *ibdev)
Unregister Infiniband device.
Definition infiniband.c:985
ib_complete_send
void ib_complete_send(struct ib_device *ibdev, struct ib_queue_pair *qp, struct io_buffer *iobuf, int rc)
Complete send work queue entry.
Definition infiniband.c:515
alloc_ibdev
struct ib_device * alloc_ibdev(size_t priv_size)
Allocate Infiniband device.
Definition infiniband.c:917
infiniband.h
Infiniband protocol.
ib_get_drvdata
static __always_inline void * ib_get_drvdata(struct ib_device *ibdev)
Get Infiniband device driver-private data.
Definition infiniband.h:709
IB_QPT_SMI
@ IB_QPT_SMI
Definition infiniband.h:140
ib_set_drvdata
static __always_inline void ib_set_drvdata(struct ib_device *ibdev, void *priv)
Set Infiniband device driver-private data.
Definition infiniband.h:698
ib_wq_get_drvdata
static __always_inline void * ib_wq_get_drvdata(struct ib_work_queue *wq)
Get Infiniband work queue driver-private data.
Definition infiniband.h:621
ib_wq_set_drvdata
static __always_inline void ib_wq_set_drvdata(struct ib_work_queue *wq, void *priv)
Set Infiniband work queue driver-private data.
Definition infiniband.h:610
ibdev_put
static __always_inline void ibdev_put(struct ib_device *ibdev)
Drop reference to Infiniband device.
Definition infiniband.h:599
iobuf.h
I/O buffers.
iob_populate
static void iob_populate(struct io_buffer *iobuf, void *data, size_t len, size_t max_len)
Create a temporary I/O buffer.
Definition iobuf.h:195
iob_put
#define iob_put(iobuf, len)
Definition iobuf.h:125
iob_len
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition iobuf.h:160
iob_reserve
#define iob_reserve(iobuf, len)
Definition iobuf.h:72
iob_tailroom
static size_t iob_tailroom(struct io_buffer *iobuf)
Calculate available space at end of an I/O buffer.
Definition iobuf.h:180
base
uint32_t base
Base.
Definition librm.h:3
list_for_each_entry
#define list_for_each_entry(pos, head, member)
Iterate over entries in a list.
Definition list.h:432
zalloc
void * zalloc(size_t size)
Allocate cleared memory.
Definition malloc.c:662
malloc_phys
void * malloc_phys(size_t size, size_t phys_align)
Allocate memory with specified physical alignment.
Definition malloc.c:707
free_phys
void free_phys(void *ptr, size_t size)
Free memory allocated with malloc_phys()
Definition malloc.c:723
malloc.h
Dynamic memory allocation.
control
uint32_t control
Control.
Definition myson.h:3
reg
static unsigned int unsigned int reg
Definition myson.h:162
channel
uint32_t channel
RNDIS channel.
Definition netvsc.h:3
adjust_pci_device
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition pci.c:241
pci.h
PCI bus.
__pci_driver
#define __pci_driver
Declare a PCI driver.
Definition pci.h:278
pci_set_drvdata
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition pci.h:366
PCI_ROM
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition pci.h:308
pci_get_drvdata
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition pci.h:376
pci_restore
void pci_restore(struct pci_device *pci, struct pci_config_backup *backup, unsigned int limit, const uint8_t *exclude)
Restore PCI configuration space.
Definition pcibackup.c:88
pci_backup
void pci_backup(struct pci_device *pci, struct pci_config_backup *backup, unsigned int limit, const uint8_t *exclude)
Back up PCI configuration space.
Definition pcibackup.c:68
pcibackup.h
PCI configuration space backup and restoration.
PCI_CONFIG_BACKUP_ALL
#define PCI_CONFIG_BACKUP_ALL
Limit of PCI configuration space.
Definition pcibackup.h:16
BIT_GET
#define BIT_GET(_ptr, _field)
Extract value of named field (for fields up to the size of a long)
Definition pseudobit.h:235
BIT_FILL_5
#define BIT_FILL_5(_ptr, _field1,...)
Definition pseudobit.h:205
BIT_FILL_3
#define BIT_FILL_3(_ptr, _field1,...)
Definition pseudobit.h:195
BIT_SET
#define BIT_SET(_ptr, _field, _value)
Definition pseudobit.h:238
BIT_FILL_2
#define BIT_FILL_2(_ptr, _field1,...)
Definition pseudobit.h:190
BIT_FILL_6
#define BIT_FILL_6(_ptr, _field1,...)
Definition pseudobit.h:210
BIT_FILL_1
#define BIT_FILL_1(_ptr, _field1,...)
Definition pseudobit.h:185
qib7322_destroy_recv_wq
static void qib7322_destroy_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Destroy receive work queue.
Definition qib7322.c:825
qib7322_writeq_array64k
#define qib7322_writeq_array64k(_qib7322, _ptr, _offset, _idx)
Definition qib7322.c:178
qib7322_read_eeprom
static int qib7322_read_eeprom(struct qib7322 *qib7322)
Read EEPROM parameters.
Definition qib7322.c:1941
qib7322_link_state_text
static const char * qib7322_link_state_text(unsigned int link_state)
Textual representation of link state.
Definition qib7322.c:208
qib7322_link_state_check
static int qib7322_link_state_check(struct ib_device *ibdev, unsigned int new_link_state)
Wait for link state change to take effect.
Definition qib7322.c:280
qib7322_ahb_write
static int qib7322_ahb_write(struct qib7322 *qib7322, unsigned int location, uint32_t data)
Write data via AHB.
Definition qib7322.c:2093
qib7322_open
static int qib7322_open(struct ib_device *ibdev)
Initialise Infiniband link.
Definition qib7322.c:1717
qib7322_modify_qp
static int qib7322_modify_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Modify queue pair.
Definition qib7322.c:1126
qib7322_i2c_write_bit
static void qib7322_i2c_write_bit(struct bit_basher *basher, unsigned int bit_id, unsigned long data)
Write QIB7322 I2C line status.
Definition qib7322.c:1857
qib7322_init_i2c
static int qib7322_init_i2c(struct qib7322 *qib7322)
Initialise QIB7322 I2C subsystem.
Definition qib7322.c:1906
qib7322_alloc_ctx
static int qib7322_alloc_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Allocate a context and set queue pair number.
Definition qib7322.c:369
qib7322_i2c_basher_ops
static struct bit_basher_operations qib7322_i2c_basher_ops
QIB7322 I2C bit-bashing interface operations.
Definition qib7322.c:1895
qib7322_init_ib_serdes
static int qib7322_init_ib_serdes(struct qib7322 *qib7322)
Initialise the IB SerDes.
Definition qib7322.c:2196
qib7322_init_recv
static int qib7322_init_recv(struct qib7322 *qib7322)
Initialise receive datapath.
Definition qib7322.c:859
qib7322_set_port_info
static int qib7322_set_port_info(struct ib_device *ibdev, union ib_mad *mad)
Set port information.
Definition qib7322.c:308
qib7322_close
static void qib7322_close(struct ib_device *ibdev)
Close Infiniband link.
Definition qib7322.c:1737
qib7322_send_buffer_offset
static unsigned long qib7322_send_buffer_offset(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs, unsigned int send_buf)
Calculate starting offset for send buffer.
Definition qib7322.c:558
qib7322_poll_eq
static void qib7322_poll_eq(struct ib_device *ibdev)
Poll event queue.
Definition qib7322.c:1630
qib7322_post_send
static int qib7322_post_send(struct ib_device *ibdev, struct ib_queue_pair *qp, struct ib_address_vector *dest, struct io_buffer *iobuf)
Post send work queue entry.
Definition qib7322.c:1167
qib7322_writeq_port
#define qib7322_writeq_port(_qib7322, _ptr, _offset, _port)
Definition qib7322.c:180
qib7322_ahb_wait
static int qib7322_ahb_wait(struct qib7322 *qib7322)
Wait for AHB transaction to complete.
Definition qib7322.c:1989
qib7322_link_state_changed
static void qib7322_link_state_changed(struct ib_device *ibdev)
Handle link state change.
Definition qib7322.c:224
qib7322_fini_send
static void qib7322_fini_send(struct qib7322 *qib7322)
Shut down send datapath.
Definition qib7322.c:717
qib7322_probe
static int qib7322_probe(struct pci_device *pci)
Probe PCI device.
Definition qib7322.c:2281
qib7322_ahb_release
static void qib7322_ahb_release(struct qib7322 *qib7322)
Release ownership of the AHB.
Definition qib7322.c:2041
qib7322_free_send_buf
static void qib7322_free_send_buf(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs, unsigned int send_buf)
Free a send buffer.
Definition qib7322.c:518
qib7322_init_send
static int qib7322_init_send(struct qib7322 *qib7322)
Initialise send datapath.
Definition qib7322.c:624
qib7322_create_qp
static int qib7322_create_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create queue pair.
Definition qib7322.c:1085
qib7322_create_send_bufs
static struct qib7322_send_buffers * qib7322_create_send_bufs(struct qib7322 *qib7322, unsigned long base, unsigned int size, unsigned int start, unsigned int count)
Create send buffer set.
Definition qib7322.c:446
qib7322_ctx
static unsigned int qib7322_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Get queue pair context number.
Definition qib7322.c:398
qib7322_post_recv
static int qib7322_post_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, struct io_buffer *iobuf)
Post receive work queue entry.
Definition qib7322.c:1312
qib7322_complete_recv
static void qib7322_complete_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, unsigned int header_offs)
Complete receive work queue entry.
Definition qib7322.c:1392
qib7322_destroy_send_bufs
static void qib7322_destroy_send_bufs(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs)
Destroy send buffer set.
Definition qib7322.c:480
qib7322_create_send_wq
static int qib7322_create_send_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create send work queue.
Definition qib7322.c:573
qib7322_create_recv_wq
static int qib7322_create_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create receive work queue.
Definition qib7322.c:748
qib7322_link_speed_supported
static unsigned int qib7322_link_speed_supported(struct qib7322 *qib7322, unsigned int port)
Determine supported link speeds.
Definition qib7322.c:1665
qib7322_readq_port
#define qib7322_readq_port(_qib7322, _ptr, _offset, _port)
Definition qib7322.c:160
qib7322_destroy_send_wq
static void qib7322_destroy_send_wq(struct ib_device *ibdev __unused, struct ib_queue_pair *qp)
Destroy send work queue.
Definition qib7322.c:610
qib7322_ahb_mod_reg_all
static int qib7322_ahb_mod_reg_all(struct qib7322 *qib7322, unsigned int reg, uint32_t value, uint32_t mask)
Read/modify/write AHB register across all ports and channels.
Definition qib7322.c:2165
qib7322_ahb_request
static int qib7322_ahb_request(struct qib7322 *qib7322, unsigned int location)
Request ownership of the AHB.
Definition qib7322.c:2014
QIB7322_SEND_BUF_TOGGLE
#define QIB7322_SEND_BUF_TOGGLE
Send buffer toggle bit.
Definition qib7322.c:433
qib7322_send_buf_in_use
static int qib7322_send_buf_in_use(struct qib7322 *qib7322, unsigned int send_buf)
Check to see if send buffer is in use.
Definition qib7322.c:534
qib7322_complete_send
static void qib7322_complete_send(struct ib_device *ibdev, struct ib_queue_pair *qp, unsigned int wqe_idx)
Complete send work queue entry.
Definition qib7322.c:1250
qib7322_mcast_detach
static void qib7322_mcast_detach(struct ib_device *ibdev, struct ib_queue_pair *qp, union ib_gid *gid)
Detach from multicast group.
Definition qib7322.c:1783
qib7322_writel
static void qib7322_writel(struct qib7322 *qib7322, uint32_t dword, unsigned long offset)
Write QIB7322 dword register.
Definition qib7322.c:190
qib7322_set_pkey_table
static int qib7322_set_pkey_table(struct ib_device *ibdev __unused, union ib_mad *mad __unused)
Set partition key table.
Definition qib7322.c:349
qib7322_poll_send_wq
static void qib7322_poll_send_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Poll send work queue.
Definition qib7322.c:1280
qib7322_create_cq
static int qib7322_create_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Create completion queue.
Definition qib7322.c:1039
qib7322_mcast_attach
static int qib7322_mcast_attach(struct ib_device *ibdev, struct ib_queue_pair *qp, union ib_gid *gid)
Attach to multicast group.
Definition qib7322.c:1765
qib7322_reset
static void qib7322_reset(struct qib7322 *qib7322, struct pci_device *pci)
Reset QIB7322.
Definition qib7322.c:2255
qib7322_ahb_mod_reg
static int qib7322_ahb_mod_reg(struct qib7322 *qib7322, unsigned int location, uint32_t value, uint32_t mask)
Read/modify/write AHB register.
Definition qib7322.c:2122
qib7322_writeq_array8b
#define qib7322_writeq_array8b(_qib7322, _ptr, _offset, _idx)
Definition qib7322.c:176
qib7322_poll_recv_wq
static void qib7322_poll_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Poll receive work queue.
Definition qib7322.c:1555
qib7322_remove
static void qib7322_remove(struct pci_device *pci)
Remove PCI device.
Definition qib7322.c:2407
qib7322_i2c_read_bit
static int qib7322_i2c_read_bit(struct bit_basher *basher, unsigned int bit_id)
Read QIB7322 I2C line status.
Definition qib7322.c:1833
qib7322_ib_operations
static struct ib_device_operations qib7322_ib_operations
QIB7322 Infiniband operations.
Definition qib7322.c:1794
qib7322_readq
#define qib7322_readq(_qib7322, _ptr, _offset)
Definition qib7322.c:154
qib7322_ahb_read
static int qib7322_ahb_read(struct qib7322 *qib7322, unsigned int location, uint32_t *data)
Read data via AHB.
Definition qib7322.c:2058
qib7322_destroy_cq
static void qib7322_destroy_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Destroy completion queue.
Definition qib7322.c:1063
qib7322_free_ctx
static void qib7322_free_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Free a context.
Definition qib7322.c:409
qib7322_i2c_bits
static unsigned int qib7322_i2c_bits[]
QIB7322 I2C bit to GPIO mappings.
Definition qib7322.c:1820
qib7322_writeq
#define qib7322_writeq(_qib7322, _ptr, _offset)
Definition qib7322.c:174
qib7322_alloc_send_buf
static int qib7322_alloc_send_buf(struct qib7322 *qib7322, struct qib7322_send_buffers *send_bufs)
Allocate a send buffer.
Definition qib7322.c:492
qib7322_destroy_qp
static void qib7322_destroy_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Destroy queue pair.
Definition qib7322.c:1143
qib7322_fini_recv
static void qib7322_fini_recv(struct qib7322 *qib7322 __unused)
Shut down receive datapath.
Definition qib7322.c:1019
qib7322_poll_cq
static void qib7322_poll_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Poll completion queue.
Definition qib7322.c:1604
qib7322_nics
static struct pci_device_id qib7322_nics[]
Definition qib7322.c:2423
qib7322.h
QLogic QIB7322 Infiniband HCA.
QIB7322_LARGE_SEND_BUF_COUNT
#define QIB7322_LARGE_SEND_BUF_COUNT
QIB7322 large send buffer count.
Definition qib7322.h:220
QIB7322_VL15_PORT1_SEND_BUF_SIZE
#define QIB7322_VL15_PORT1_SEND_BUF_SIZE
QIB7322 VL15 port 0 send buffer size.
Definition qib7322.h:238
QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL
Definition qib7322.h:264
QIB7322_SMALL_SEND_BUF_START
#define QIB7322_SMALL_SEND_BUF_START
QIB7322 small send buffer starting index.
Definition qib7322.h:208
QIB7322_LINK_STATE_MAX_WAIT_US
#define QIB7322_LINK_STATE_MAX_WAIT_US
Maximum time to wait for link state changes, in us.
Definition qib7322.h:367
QIB7322_RECV_HEADERS_SIZE
#define QIB7322_RECV_HEADERS_SIZE
Total size of an RX header ring.
Definition qib7322.h:296
QIB7322_AHB_MAX_WAIT_US
#define QIB7322_AHB_MAX_WAIT_US
Maximum time for wait for AHB, in us.
Definition qib7322.h:337
QIB7322_SMALL_SEND_BUF_SIZE
#define QIB7322_SMALL_SEND_BUF_SIZE
QIB7322 small send buffer size.
Definition qib7322.h:205
QIB7322_VL15_PORT1_SEND_BUF_COUNT
#define QIB7322_VL15_PORT1_SEND_BUF_COUNT
QIB7322 VL15 port 0 send buffer count.
Definition qib7322.h:235
QIB7322_QP_IDETH
#define QIB7322_QP_IDETH
QPN used for Infinipath Packets.
Definition qib7322.h:334
QIB7322_LARGE_SEND_BUF_SIZE
#define QIB7322_LARGE_SEND_BUF_SIZE
QIB7322 large send buffer size.
Definition qib7322.h:214
QIB7322_VL15_PORT0_SEND_BUF_COUNT
#define QIB7322_VL15_PORT0_SEND_BUF_COUNT
QIB7322 VL15 port 0 send buffer count.
Definition qib7322.h:226
QIB7322_BAR0_SIZE
#define QIB7322_BAR0_SIZE
QIB7322 memory BAR size.
Definition qib7322.h:163
QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL
Definition qib7322.h:266
QIB7322_GPIO_SCL
#define QIB7322_GPIO_SCL
QIB7322 I2C SCL line GPIO number.
Definition qib7322.h:187
QIB7322_RECV_HEADERS_ALIGN
#define QIB7322_RECV_HEADERS_ALIGN
RX header alignment.
Definition qib7322.h:300
QIB7322_SENDBUFAVAIL_ALIGN
#define QIB7322_SENDBUFAVAIL_ALIGN
DMA alignment for send buffer availability.
Definition qib7322.h:97
QIB7322_GPIO_SDA
#define QIB7322_GPIO_SDA
QIB7322 I2C SDA line GPIO number.
Definition qib7322.h:190
QIB7322_EAGER_ARRAY_SIZE_10CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER
Definition qib7322.h:265
QIB7322_MAX_PORTS
#define QIB7322_MAX_PORTS
QIB7322 maximum number of ports.
Definition qib7322.h:169
QIB7322_SMALL_SEND_BUF_USED
#define QIB7322_SMALL_SEND_BUF_USED
Number of small send buffers used.
Definition qib7322.h:246
QIB7322_AHB_LOC_ADDRESS
#define QIB7322_AHB_LOC_ADDRESS(_location)
QIB7322 AHB locations.
Definition qib7322.h:340
QIB7322_LINK_STATE_ACT_DEFER
@ QIB7322_LINK_STATE_ACT_DEFER
Definition qib7322.h:363
QIB7322_LINK_STATE_DOWN
@ QIB7322_LINK_STATE_DOWN
Definition qib7322.h:359
QIB7322_LINK_STATE_INIT
@ QIB7322_LINK_STATE_INIT
Definition qib7322.h:360
QIB7322_LINK_STATE_ACTIVE
@ QIB7322_LINK_STATE_ACTIVE
Definition qib7322.h:362
QIB7322_LINK_STATE_ARM
@ QIB7322_LINK_STATE_ARM
Definition qib7322.h:361
QIB7322_PORT_BASE
#define QIB7322_PORT_BASE
QIB7322 base port number.
Definition qib7322.h:166
QIB7322_EAGER_BUFFER_ALIGN
#define QIB7322_EAGER_BUFFER_ALIGN
Eager buffer required alignment.
Definition qib7322.h:270
QIB7322_EAGER_ARRAY_SIZE_18CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER
Definition qib7322.h:267
QIB7322_RECV_HEADER_COUNT
#define QIB7322_RECV_HEADER_COUNT
Number of RX headers per context.
Definition qib7322.h:287
QIB7322_EEPROM_SERIAL_SIZE
#define QIB7322_EEPROM_SERIAL_SIZE
Board serial number size within EEPROM.
Definition qib7322.h:202
QIB7322_EEPROM_SERIAL_OFFSET
#define QIB7322_EEPROM_SERIAL_OFFSET
Board serial number offset within EEPROM.
Definition qib7322.h:199
QIB7322_RECV_HEADER_SIZE
#define QIB7322_RECV_HEADER_SIZE
Maximum size of each RX header.
Definition qib7322.h:293
QIB7322_BOARD_QMH7342
@ QIB7322_BOARD_QMH7342
Definition qib7322.h:182
QIB7322_VL15_PORT0_SEND_BUF_SIZE
#define QIB7322_VL15_PORT0_SEND_BUF_SIZE
QIB7322 VL15 port 0 send buffer size.
Definition qib7322.h:229
QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL
ContextCfg values for different numbers of contexts.
Definition qib7322.h:262
QIB7322_EAGER_BUFFER_NONE
@ QIB7322_EAGER_BUFFER_NONE
Definition qib7322.h:274
QIB7322_EAGER_BUFFER_16K
@ QIB7322_EAGER_BUFFER_16K
Definition qib7322.h:278
QIB7322_EAGER_BUFFER_8K
@ QIB7322_EAGER_BUFFER_8K
Definition qib7322.h:277
QIB7322_EAGER_BUFFER_32K
@ QIB7322_EAGER_BUFFER_32K
Definition qib7322.h:279
QIB7322_EAGER_BUFFER_2K
@ QIB7322_EAGER_BUFFER_2K
Definition qib7322.h:275
QIB7322_EAGER_BUFFER_64K
@ QIB7322_EAGER_BUFFER_64K
Definition qib7322.h:280
QIB7322_EAGER_BUFFER_4K
@ QIB7322_EAGER_BUFFER_4K
Definition qib7322.h:276
QIB7322_EAGER_ARRAY_SIZE_6CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER
Definition qib7322.h:263
QIB7322_NUM_CONTEXTS
#define QIB7322_NUM_CONTEXTS
Number of contexts (including kernel context)
Definition qib7322.h:252
QIB7322_MAX_CREDITS_VL15
#define QIB7322_MAX_CREDITS_VL15
Number of credits to advertise for VL15.
Definition qib7322.h:320
QIB7322_MAX_CREDITS_VL0
#define QIB7322_MAX_CREDITS_VL0
Number of credits to advertise for VL0.
Definition qib7322.h:326
QIB7322_AHB_LOCATION
#define QIB7322_AHB_LOCATION(_port, _channel, _register)
Definition qib7322.h:352
QIB7322_AHB_LOC_TARGET
#define QIB7322_AHB_LOC_TARGET(_location)
Definition qib7322.h:341
QIB7322_EEPROM_GUID_OFFSET
#define QIB7322_EEPROM_GUID_OFFSET
GUID offset within EEPROM.
Definition qib7322.h:193
QIB7322_CONTEXTCFG_18CTX
@ QIB7322_CONTEXTCFG_18CTX
Definition qib7322.h:258
QIB7322_CONTEXTCFG_10CTX
@ QIB7322_CONTEXTCFG_10CTX
Definition qib7322.h:257
QIB7322_CONTEXTCFG_6CTX
@ QIB7322_CONTEXTCFG_6CTX
Definition qib7322.h:256
QIB7322_MAX_WIDTH
#define QIB7322_MAX_WIDTH
QIB7322 maximum width.
Definition qib7322.h:172
QIB7322_VL15_PORT0_SEND_BUF_START
#define QIB7322_VL15_PORT0_SEND_BUF_START
QIB7322 VL15 port 0 send buffer starting index.
Definition qib7322.h:223
QIB7322_RECV_PAYLOAD_SIZE
#define QIB7322_RECV_PAYLOAD_SIZE
RX payload size.
Definition qib7322.h:306
QIB7322_VL15_PORT1_SEND_BUF_START
#define QIB7322_VL15_PORT1_SEND_BUF_START
QIB7322 VL15 port 0 send buffer starting index.
Definition qib7322.h:232
QIB_7322_SendCtrl_0_offset
#define QIB_7322_SendCtrl_0_offset
Definition qib_7322_regs.h:2898
QIB_7322_RcvCtrl_0_offset
#define QIB_7322_RcvCtrl_0_offset
Definition qib_7322_regs.h:2712
QIB_7322_SendCtrl_offset
#define QIB_7322_SendCtrl_offset
Definition qib_7322_regs.h:725
QIB_7322_Control_offset
#define QIB_7322_Control_offset
Definition qib_7322_regs.h:54
QIB_7322_RxCreditVL0_1_offset
#define QIB_7322_RxCreditVL0_1_offset
Definition qib_7322_regs.h:4366
QIB_7322_IBCCtrlB_1_offset
#define QIB_7322_IBCCtrlB_1_offset
Definition qib_7322_regs.h:4498
QIB_7322_RcvEgrBase_offset
#define QIB_7322_RcvEgrBase_offset
Definition qib_7322_regs.h:683
QIB_7322_IBPCSConfig_1_offset
#define QIB_7322_IBPCSConfig_1_offset
Definition qib_7322_regs.h:4595
QIB_7322_RcvQPMapTableB_0_offset
#define QIB_7322_RcvQPMapTableB_0_offset
Definition qib_7322_regs.h:2754
QIB_7322_IBCStatusA_0_offset
#define QIB_7322_IBCStatusA_0_offset
Definition qib_7322_regs.h:3098
QIB_7322_IBCCtrlA_0_offset
#define QIB_7322_IBCCtrlA_0_offset
Definition qib_7322_regs.h:3146
QIB_7322_RcvCtrl_offset
#define QIB_7322_RcvCtrl_offset
Definition qib_7322_regs.h:651
QIB_7322_RcvQPMulticastContext_0_offset
#define QIB_7322_RcvQPMulticastContext_0_offset
Definition qib_7322_regs.h:2848
QIB_7322_ErrStatus_0_offset
#define QIB_7322_ErrStatus_0_offset
Definition qib_7322_regs.h:2584
QIB_7322_SendBufBase_offset
#define QIB_7322_SendBufBase_offset
Definition qib_7322_regs.h:745
QIB_7322_RcvHdrCnt_offset
#define QIB_7322_RcvHdrCnt_offset
Definition qib_7322_regs.h:671
QIB_7322_GPIOOut_offset
#define QIB_7322_GPIOOut_offset
Definition qib_7322_regs.h:639
QIB_7322_RcvHdrHead0_offset
#define QIB_7322_RcvHdrHead0_offset
Definition qib_7322_regs.h:6581
QIB_7322_RcvQPMapTableB_1_offset
#define QIB_7322_RcvQPMapTableB_1_offset
Definition qib_7322_regs.h:4087
QIB_7322_RcvQPMapTableA_1_offset
#define QIB_7322_RcvQPMapTableA_1_offset
Definition qib_7322_regs.h:4072
QIB_7322_RcvBTHQP_0_offset
#define QIB_7322_RcvBTHQP_0_offset
Definition qib_7322_regs.h:2729
QIB_7322_RcvBTHQP_1_offset
#define QIB_7322_RcvBTHQP_1_offset
Definition qib_7322_regs.h:4062
QIB_7322_EXTCtrl_offset
#define QIB_7322_EXTCtrl_offset
Definition qib_7322_regs.h:613
QIB_7322_ErrClear_0_offset
#define QIB_7322_ErrClear_0_offset
Definition qib_7322_regs.h:2637
QIB_7322_EXTStatus_offset
#define QIB_7322_EXTStatus_offset
Definition qib_7322_regs.h:600
QIB_7322_ahb_transaction_reg_offset
#define QIB_7322_ahb_transaction_reg_offset
Definition qib_7322_regs.h:949
QIB_7322_IBCCtrlB_0_offset
#define QIB_7322_IBCCtrlB_0_offset
Definition qib_7322_regs.h:3168
QIB_7322_SendCtrl_1_offset
#define QIB_7322_SendCtrl_1_offset
Definition qib_7322_regs.h:4231
QIB_7322_RcvQPMulticastContext_1_offset
#define QIB_7322_RcvQPMulticastContext_1_offset
Definition qib_7322_regs.h:4181
QIB_7322_SendBufAvailAddr_offset
#define QIB_7322_SendBufAvailAddr_offset
Definition qib_7322_regs.h:781
QIB_7322_Revision_offset
#define QIB_7322_Revision_offset
Definition qib_7322_regs.h:38
QIB_7322_RcvQPMapTableA_0_offset
#define QIB_7322_RcvQPMapTableA_0_offset
Definition qib_7322_regs.h:2739
QIB_7322_RcvHdrTailAddr0_offset
#define QIB_7322_RcvHdrTailAddr0_offset
Definition qib_7322_regs.h:828
QIB_7322_RcvEgrIndexHead0_offset
#define QIB_7322_RcvEgrIndexHead0_offset
Definition qib_7322_regs.h:6595
QIB_7322_active_feature_mask_offset
#define QIB_7322_active_feature_mask_offset
Definition qib_7322_regs.h:710
QIB_7322_RcvHdrEntSize_offset
#define QIB_7322_RcvHdrEntSize_offset
Definition qib_7322_regs.h:674
QIB_7322_IBPCSConfig_0_offset
#define QIB_7322_IBPCSConfig_0_offset
Definition qib_7322_regs.h:3265
QIB_7322_RxCreditVL0_0_offset
#define QIB_7322_RxCreditVL0_0_offset
Definition qib_7322_regs.h:3033
QIB_7322_RcvCtrl_1_offset
#define QIB_7322_RcvCtrl_1_offset
Definition qib_7322_regs.h:4045
QIB_7322_ahb_access_ctrl_offset
#define QIB_7322_ahb_access_ctrl_offset
Definition qib_7322_regs.h:938
QIB_7322_RcvHdrAddr0_offset
#define QIB_7322_RcvHdrAddr0_offset
Definition qib_7322_regs.h:817
QIB_7322_IBCCtrlA_1_offset
#define QIB_7322_IBCCtrlA_1_offset
Definition qib_7322_regs.h:4476
free
static void(* free)(struct refcnt *refcnt))
Definition refcnt.h:55
dword
unsigned long int dword
Definition smc9000.h:40
container_of
#define container_of(ptr, type, field)
Get containing structure.
Definition stddef.h:36
strerror
char * strerror(int errno)
Retrieve string representation of error number.
Definition strerror.c:79
QIB_7322_Control
Definition qib_7322_regs.h:65
QIB_7322_EXTCtrl
Definition qib_7322_regs.h:623
QIB_7322_EXTStatus
Definition qib_7322_regs.h:608
QIB_7322_ErrStatus_0
Definition qib_7322_regs.h:2632
QIB_7322_GPIO
Definition qib7322.h:45
QIB_7322_IBCCtrlA_0
Definition qib_7322_regs.h:3163
QIB_7322_IBCCtrlB_0
Definition qib_7322_regs.h:3191
QIB_7322_IBCStatusA_0
Definition qib_7322_regs.h:3124
QIB_7322_IBPCSConfig_0
Definition qib_7322_regs.h:3274
QIB_7322_RcvBTHQP_0
Definition qib_7322_regs.h:2734
QIB_7322_RcvCtrl_0
Definition qib_7322_regs.h:2724
QIB_7322_RcvCtrl_P
Definition qib7322.h:109
QIB_7322_RcvCtrl
Definition qib_7322_regs.h:663
QIB_7322_RcvEgr
Definition qib7322.h:119
QIB_7322_RcvHdrAddr0
Definition qib_7322_regs.h:823
QIB_7322_RcvHdrFlags
Definition qib7322.h:145
QIB_7322_RcvHdrHead0
Definition qib_7322_regs.h:6587
QIB_7322_RcvHdrTailAddr0
Definition qib_7322_regs.h:834
QIB_7322_RcvQPMapTableA_0
Definition qib_7322_regs.h:2749
QIB_7322_RcvQPMapTableA_1
Definition qib_7322_regs.h:4082
QIB_7322_RcvQPMapTableB_0
Definition qib_7322_regs.h:2764
QIB_7322_RcvQPMapTableB_1
Definition qib_7322_regs.h:4097
QIB_7322_RcvQPMulticastContext_0
Definition qib_7322_regs.h:2853
QIB_7322_RcvQPMulticastContext_1
Definition qib_7322_regs.h:4186
QIB_7322_Revision
Definition qib_7322_regs.h:49
QIB_7322_RxCreditVL0_0
Definition qib_7322_regs.h:3040
QIB_7322_SendBufAvailAddr
Definition qib_7322_regs.h:787
QIB_7322_SendBufAvail
Definition qib7322.h:92
QIB_7322_SendBufBase
Definition qib_7322_regs.h:752
QIB_7322_SendCtrl_0
Definition qib_7322_regs.h:2916
QIB_7322_SendCtrl
Definition qib_7322_regs.h:740
QIB_7322_SendPbc
Definition qib7322.h:83
QIB_7322_ahb_access_ctrl
Definition qib_7322_regs.h:944
QIB_7322_ahb_transaction_reg
Definition qib_7322_regs.h:959
QIB_7322_feature_mask
Definition qib7322.h:63
QIB_7322_scalar
Definition qib7322.h:53
bit_basher_operations
Bit-bashing operations.
Definition bitbash.h:16
bit_basher
A bit-bashing interface.
Definition bitbash.h:56
i2c_bit_basher
A bit-bashing I2C interface.
Definition i2c.h:91
i2c_bit_basher::i2c
struct i2c_interface i2c
I2C interface.
Definition i2c.h:93
i2c_bit_basher::basher
struct bit_basher basher
Bit-bashing interface.
Definition i2c.h:95
i2c_device
An I2C device.
Definition i2c.h:20
i2c_interface
An I2C interface.
Definition i2c.h:57
i2c_interface::read
int(* read)(struct i2c_interface *i2c, struct i2c_device *i2cdev, unsigned int offset, uint8_t *data, unsigned int len)
Read data from I2C device.
Definition i2c.h:68
ib_address_vector
An Infiniband Address Vector.
Definition infiniband.h:73
ib_completion_queue
An Infiniband Completion Queue.
Definition infiniband.h:225
ib_completion_queue::cqn
unsigned long cqn
Completion queue number.
Definition infiniband.h:231
ib_completion_queue::work_queues
struct list_head work_queues
List of work queues completing to this queue.
Definition infiniband.h:243
ib_device_operations
Infiniband device operations.
Definition infiniband.h:255
ib_device
An Infiniband device.
Definition infiniband.h:399
ib_device::link_width_enabled
uint8_t link_width_enabled
Link width enabled.
Definition infiniband.h:430
ib_device::link_speed_active
uint8_t link_speed_active
Link speed active.
Definition infiniband.h:438
ib_device::ports
unsigned int ports
Total ports on device.
Definition infiniband.h:421
ib_device::link_speed_supported
uint8_t link_speed_supported
Link speed supported.
Definition infiniband.h:434
ib_device::op
struct ib_device_operations * op
Infiniband operations.
Definition infiniband.h:417
ib_device::node_guid
union ib_guid node_guid
Node GUID.
Definition infiniband.h:440
ib_device::dev
struct device * dev
Underlying device.
Definition infiniband.h:411
ib_device::link_width_active
uint8_t link_width_active
Link width active.
Definition infiniband.h:432
ib_device::link_speed_enabled
uint8_t link_speed_enabled
Link speed enabled.
Definition infiniband.h:436
ib_device::link_width_supported
uint8_t link_width_supported
Link width supported.
Definition infiniband.h:428
ib_device::port_state
uint8_t port_state
Port state.
Definition infiniband.h:426
ib_device::gid
union ib_gid gid
Port GID (comprising GID prefix and port GUID)
Definition infiniband.h:442
ib_device::port
unsigned int port
Port number.
Definition infiniband.h:419
ib_port_info
A Port Information attribute.
Definition ib_mad.h:105
ib_queue_pair
An Infiniband Queue Pair.
Definition infiniband.h:158
ib_queue_pair::recv
struct ib_work_queue recv
Receive queue.
Definition infiniband.h:181
ib_queue_pair::qpn
unsigned long qpn
Queue pair number.
Definition infiniband.h:166
ib_work_queue
An Infiniband Work Queue.
Definition infiniband.h:101
ib_work_queue::fill
unsigned int fill
Number of occupied work queue entries.
Definition infiniband.h:115
ib_work_queue::iobufs
struct io_buffer ** iobufs
I/O buffers assigned to work queue.
Definition infiniband.h:125
ib_work_queue::cq
struct ib_completion_queue * cq
Associated completion queue.
Definition infiniband.h:107
ib_work_queue::list
struct list_head list
List of work queues on this completion queue.
Definition infiniband.h:109
ib_work_queue::qp
struct ib_queue_pair * qp
Containing queue pair.
Definition infiniband.h:103
ib_work_queue::is_send
int is_send
"Is a send queue" flag
Definition infiniband.h:105
ib_work_queue::num_wqes
unsigned int num_wqes
Number of work queue entries.
Definition infiniband.h:113
io_buffer
A persistent I/O buffer.
Definition iobuf.h:38
io_buffer::data
void * data
Start of data.
Definition iobuf.h:53
pci_config_backup
A PCI configuration space backup.
Definition pcibackup.h:22
pci_device_id
A PCI device ID list entry.
Definition pci.h:175
pci_device
A PCI device.
Definition pci.h:211
pci_device::membase
unsigned long membase
Memory base.
Definition pci.h:220
pci_device::dev
struct device dev
Generic device.
Definition pci.h:213
pci_driver
A PCI driver.
Definition pci.h:252
pci_driver::probe
int(* probe)(struct pci_device *pci)
Probe device.
Definition pci.h:265
qib7322_recv_work_queue
A QIB7322 receive work queue.
Definition qib7322.c:83
qib7322_recv_work_queue::eager_array
unsigned long eager_array
Offset within register space of the eager array.
Definition qib7322.c:91
qib7322_recv_work_queue::header_prod
struct QIB_7322_scalar header_prod
Receive header producer offset (written by hardware)
Definition qib7322.c:87
qib7322_recv_work_queue::header_cons
unsigned int header_cons
Receive header consumer offset.
Definition qib7322.c:89
qib7322_recv_work_queue::eager_prod
unsigned int eager_prod
Eager array producer index.
Definition qib7322.c:95
qib7322_recv_work_queue::eager_entries
unsigned int eager_entries
Number of entries in eager array.
Definition qib7322.c:93
qib7322_recv_work_queue::eager_cons
unsigned int eager_cons
Eager array consumer index.
Definition qib7322.c:97
qib7322_recv_work_queue::header
void * header
Receive header ring.
Definition qib7322.c:85
qib7322_send_buffers
A QIB7322 send buffer set.
Definition qib7322.c:50
qib7322_send_buffers::avail
uint16_t avail[0]
Send buffer availability.
Definition qib7322.c:67
qib7322_send_buffers::prod
unsigned int prod
Send buffer availability producer counter.
Definition qib7322.c:63
qib7322_send_buffers::size
unsigned int size
Send buffer size.
Definition qib7322.c:54
qib7322_send_buffers::count
unsigned int count
Number of send buffers.
Definition qib7322.c:61
qib7322_send_buffers::base
unsigned long base
Offset within register space of the first send buffer.
Definition qib7322.c:52
qib7322_send_buffers::start
unsigned int start
Index of first send buffer.
Definition qib7322.c:56
qib7322_send_buffers::cons
unsigned int cons
Send buffer availability consumer counter.
Definition qib7322.c:65
qib7322_send_work_queue
A QIB7322 send work queue.
Definition qib7322.c:71
qib7322_send_work_queue::used
uint16_t * used
Send buffer usage.
Definition qib7322.c:75
qib7322_send_work_queue::cons
unsigned int cons
Consumer index.
Definition qib7322.c:79
qib7322_send_work_queue::send_bufs
struct qib7322_send_buffers * send_bufs
Send buffer set.
Definition qib7322.c:73
qib7322_send_work_queue::prod
unsigned int prod
Producer index.
Definition qib7322.c:77
qib7322
A QIB7322 HCA.
Definition qib7322.c:101
qib7322::i2c
struct i2c_bit_basher i2c
I2C bit-bashing interface.
Definition qib7322.c:122
qib7322::sendbufavail
struct QIB_7322_SendBufAvail * sendbufavail
Send buffer availability (reported by hardware)
Definition qib7322.c:113
qib7322::send_bufs_vl15_port0
struct qib7322_send_buffers * send_bufs_vl15_port0
VL15 port 0 send buffers.
Definition qib7322.c:117
qib7322::guid
union ib_guid guid
Base GUID.
Definition qib7322.c:127
qib7322::eeprom
struct i2c_device eeprom
I2C serial EEPROM.
Definition qib7322.c:124
qib7322::recv_wq
struct qib7322_recv_work_queue recv_wq[QIB7322_NUM_CONTEXTS]
Receive work queues.
Definition qib7322.c:110
qib7322::send_bufs_vl15_port1
struct qib7322_send_buffers * send_bufs_vl15_port1
VL15 port 1 send buffers.
Definition qib7322.c:119
qib7322::regs
void * regs
Registers.
Definition qib7322.c:103
qib7322::ibdev
struct ib_device * ibdev[QIB7322_MAX_PORTS]
Infiniband devices.
Definition qib7322.c:129
qib7322::send_bufs_small
struct qib7322_send_buffers * send_bufs_small
Small send buffers.
Definition qib7322.c:115
qib7322::used_ctx
uint8_t used_ctx[QIB7322_NUM_CONTEXTS]
In-use contexts.
Definition qib7322.c:106
qib7322::send_wq
struct qib7322_send_work_queue send_wq[QIB7322_NUM_CONTEXTS]
Send work queues.
Definition qib7322.c:108
mdelay
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition timer.c:79
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition timer.c:61
ib_gid
An Infiniband Global Identifier.
Definition ib_packet.h:34
ib_gid::s
struct ib_gid::@251011351113275240012301235177256303262052134237 s
ib_gid::guid
union ib_guid guid
Definition ib_packet.h:41
ib_guid
An Infiniband Globally Unique Identifier.
Definition ib_packet.h:19
ib_guid::bytes
uint8_t bytes[8]
Definition ib_packet.h:20
ib_mad
A management datagram.
Definition ib_mad.h:611
writel
#define writel
Definition w89c840.c:160
remove
static struct xen_remove_from_physmap * remove
Definition xenmem.h:40
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