iPXE
qib7322.c
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1 /*
2  * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  *
19  * You can also choose to distribute this program under the terms of
20  * the Unmodified Binary Distribution Licence (as given in the file
21  * COPYING.UBDL), provided that you have satisfied its requirements.
22  */
23 
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
25 
26 #include <stdint.h>
27 #include <stdlib.h>
28 #include <errno.h>
29 #include <unistd.h>
30 #include <assert.h>
31 #include <ipxe/io.h>
32 #include <ipxe/pci.h>
33 #include <ipxe/infiniband.h>
34 #include <ipxe/i2c.h>
35 #include <ipxe/bitbash.h>
36 #include <ipxe/malloc.h>
37 #include <ipxe/iobuf.h>
38 #include <ipxe/pcibackup.h>
39 #include "qib7322.h"
40 
41 /**
42  * @file
43  *
44  * QLogic QIB7322 Infiniband HCA
45  *
46  */
47 
48 /** A QIB7322 send buffer set */
49 struct qib7322_send_buffers {
50  /** Offset within register space of the first send buffer */
51  unsigned long base;
52  /** Send buffer size */
53  unsigned int size;
54  /** Index of first send buffer */
55  unsigned int start;
56  /** Number of send buffers
57  *
58  * Must be a power of two.
59  */
60  unsigned int count;
61  /** Send buffer availability producer counter */
62  unsigned int prod;
63  /** Send buffer availability consumer counter */
64  unsigned int cons;
65  /** Send buffer availability */
66  uint16_t avail[0];
67 };
68 
69 /** A QIB7322 send work queue */
70 struct qib7322_send_work_queue {
71  /** Send buffer set */
72  struct qib7322_send_buffers *send_bufs;
73  /** Send buffer usage */
74  uint16_t *used;
75  /** Producer index */
76  unsigned int prod;
77  /** Consumer index */
78  unsigned int cons;
79 };
80 
81 /** A QIB7322 receive work queue */
82 struct qib7322_recv_work_queue {
83  /** Receive header ring */
84  void *header;
85  /** Receive header producer offset (written by hardware) */
86  struct QIB_7322_scalar header_prod;
87  /** Receive header consumer offset */
88  unsigned int header_cons;
89  /** Offset within register space of the eager array */
90  unsigned long eager_array;
91  /** Number of entries in eager array */
92  unsigned int eager_entries;
93  /** Eager array producer index */
94  unsigned int eager_prod;
95  /** Eager array consumer index */
96  unsigned int eager_cons;
97 };
98 
99 /** A QIB7322 HCA */
100 struct qib7322 {
101  /** Registers */
102  void *regs;
103 
104  /** In-use contexts */
105  uint8_t used_ctx[QIB7322_NUM_CONTEXTS];
106  /** Send work queues */
107  struct qib7322_send_work_queue send_wq[QIB7322_NUM_CONTEXTS];
108  /** Receive work queues */
109  struct qib7322_recv_work_queue recv_wq[QIB7322_NUM_CONTEXTS];
110 
111  /** Send buffer availability (reported by hardware) */
112  struct QIB_7322_SendBufAvail *sendbufavail;
113  /** Small send buffers */
114  struct qib7322_send_buffers *send_bufs_small;
115  /** VL15 port 0 send buffers */
116  struct qib7322_send_buffers *send_bufs_vl15_port0;
117  /** VL15 port 1 send buffers */
118  struct qib7322_send_buffers *send_bufs_vl15_port1;
119 
120  /** I2C bit-bashing interface */
121  struct i2c_bit_basher i2c;
122  /** I2C serial EEPROM */
123  struct i2c_device eeprom;
124 
125  /** Base GUID */
126  union ib_guid guid;
127  /** Infiniband devices */
128  struct ib_device *ibdev[QIB7322_MAX_PORTS];
129 };
130 
131 /***************************************************************************
132  *
133  * QIB7322 register access
134  *
135  ***************************************************************************
136  *
137  * This card requires atomic 64-bit accesses. Strange things happen
138  * if you try to use 32-bit accesses; sometimes they work, sometimes
139  * they don't, sometimes you get random data.
140  */
141 
142 /**
143  * Read QIB7322 qword register
144  *
145  * @v qib7322 QIB7322 device
146  * @v qword Register buffer to read into
147  * @v offset Register offset
148  */
149 static void qib7322_readq ( struct qib7322 *qib7322, uint64_t *qword,
150  unsigned long offset ) {
151  *qword = readq ( qib7322->regs + offset );
152 }
153 #define qib7322_readq( _qib7322, _ptr, _offset ) \
154  qib7322_readq ( (_qib7322), (_ptr)->u.qwords, (_offset) )
155 #define qib7322_readq_array8b( _qib7322, _ptr, _offset, _idx ) \
156  qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
157 #define qib7322_readq_array64k( _qib7322, _ptr, _offset, _idx ) \
158  qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ) )
159 #define qib7322_readq_port( _qib7322, _ptr, _offset, _port ) \
160  qib7322_readq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ) )
161 
162 /**
163  * Write QIB7322 qword register
164  *
165  * @v qib7322 QIB7322 device
166  * @v qword Register buffer to write
167  * @v offset Register offset
168  */
169 static void qib7322_writeq ( struct qib7322 *qib7322, const uint64_t *qword,
170  unsigned long offset ) {
171  writeq ( *qword, ( qib7322->regs + offset ) );
172 }
173 #define qib7322_writeq( _qib7322, _ptr, _offset ) \
174  qib7322_writeq ( (_qib7322), (_ptr)->u.qwords, (_offset) )
175 #define qib7322_writeq_array8b( _qib7322, _ptr, _offset, _idx ) \
176  qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 8 ) ) )
177 #define qib7322_writeq_array64k( _qib7322, _ptr, _offset, _idx ) \
178  qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_idx) * 65536 ) ))
179 #define qib7322_writeq_port( _qib7322, _ptr, _offset, _port ) \
180  qib7322_writeq ( (_qib7322), (_ptr), ( (_offset) + ( (_port) * 4096 ) ))
181 
182 /**
183  * Write QIB7322 dword register
184  *
185  * @v qib7322 QIB7322 device
186  * @v dword Value to write
187  * @v offset Register offset
188  */
189 static void qib7322_writel ( struct qib7322 *qib7322, uint32_t dword,
190  unsigned long offset ) {
191  writel ( dword, ( qib7322->regs + offset ) );
192 }
193 
194 /***************************************************************************
195  *
196  * Link state management
197  *
198  ***************************************************************************
199  */
200 
201 /**
202  * Textual representation of link state
203  *
204  * @v link_state Link state
205  * @ret link_text Link state text
206  */
207 static const char * qib7322_link_state_text ( unsigned int link_state ) {
208  switch ( link_state ) {
209  case QIB7322_LINK_STATE_DOWN: return "DOWN";
210  case QIB7322_LINK_STATE_INIT: return "INIT";
211  case QIB7322_LINK_STATE_ARM: return "ARM";
212  case QIB7322_LINK_STATE_ACTIVE: return "ACTIVE";
213  case QIB7322_LINK_STATE_ACT_DEFER: return "ACT_DEFER";
214  default: return "UNKNOWN";
215  }
216 }
217 
218 /**
219  * Handle link state change
220  *
221  * @v qib7322 QIB7322 device
222  */
223 static void qib7322_link_state_changed ( struct ib_device *ibdev ) {
224  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
225  struct QIB_7322_IBCStatusA_0 ibcstatusa;
226  struct QIB_7322_EXTCtrl extctrl;
227  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
228  unsigned int link_training_state;
229  unsigned int link_state;
230  unsigned int link_width;
231  unsigned int link_speed;
232  unsigned int link_speed_qdr;
233  unsigned int green;
234  unsigned int yellow;
235 
236  /* Read link state */
237  qib7322_readq_port ( qib7322, &ibcstatusa,
238  QIB_7322_IBCStatusA_0_offset, port );
239  link_training_state = BIT_GET ( &ibcstatusa, LinkTrainingState );
240  link_state = BIT_GET ( &ibcstatusa, LinkState );
241  link_width = BIT_GET ( &ibcstatusa, LinkWidthActive );
242  link_speed = BIT_GET ( &ibcstatusa, LinkSpeedActive );
243  link_speed_qdr = BIT_GET ( &ibcstatusa, LinkSpeedQDR );
244  DBGC ( qib7322, "QIB7322 %p port %d training state %#x link state %s "
245  "(%s %s)\n", qib7322, port, link_training_state,
246  qib7322_link_state_text ( link_state ),
247  ( link_speed_qdr ? "QDR" : ( link_speed ? "DDR" : "SDR" ) ),
248  ( link_width ? "x4" : "x1" ) );
249 
250  /* Set LEDs according to link state */
251  qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
252  green = ( ( link_state >= QIB7322_LINK_STATE_INIT ) ? 1 : 0 );
253  yellow = ( ( link_state >= QIB7322_LINK_STATE_ACTIVE ) ? 1 : 0 );
254  if ( port == 0 ) {
255  BIT_SET ( &extctrl, LEDPort0GreenOn, green );
256  BIT_SET ( &extctrl, LEDPort0YellowOn, yellow );
257  } else {
258  BIT_SET ( &extctrl, LEDPort1GreenOn, green );
259  BIT_SET ( &extctrl, LEDPort1YellowOn, yellow );
260  }
261  qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
262 
263  /* Notify Infiniband core of link state change */
264  ibdev->port_state = ( link_state + 1 );
265  ibdev->link_width_active =
266  ( link_width ? IB_LINK_WIDTH_4X : IB_LINK_WIDTH_1X );
267  ibdev->link_speed_active =
268  ( link_speed ? IB_LINK_SPEED_DDR : IB_LINK_SPEED_SDR );
269  ib_link_state_changed ( ibdev );
270 }
271 
272 /**
273  * Wait for link state change to take effect
274  *
275  * @v ibdev Infiniband device
276  * @v new_link_state Expected link state
277  * @ret rc Return status code
278  */
279 static int qib7322_link_state_check ( struct ib_device *ibdev,
280  unsigned int new_link_state ) {
281  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
282  struct QIB_7322_IBCStatusA_0 ibcstatusa;
283  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
284  unsigned int link_state;
285  unsigned int i;
286 
287  for ( i = 0 ; i < QIB7322_LINK_STATE_MAX_WAIT_US ; i++ ) {
288  qib7322_readq_port ( qib7322, &ibcstatusa,
289  QIB_7322_IBCStatusA_0_offset, port );
290  link_state = BIT_GET ( &ibcstatusa, LinkState );
291  if ( link_state == new_link_state )
292  return 0;
293  udelay ( 1 );
294  }
295 
296  DBGC ( qib7322, "QIB7322 %p port %d timed out waiting for link state "
297  "%s\n", qib7322, port, qib7322_link_state_text ( link_state ) );
298  return -ETIMEDOUT;
299 }
300 
301 /**
302  * Set port information
303  *
304  * @v ibdev Infiniband device
305  * @v mad Set port information MAD
306  */
307 static int qib7322_set_port_info ( struct ib_device *ibdev,
308  union ib_mad *mad ) {
309  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
310  struct ib_port_info *port_info = &mad->smp.smp_data.port_info;
311  struct QIB_7322_IBCCtrlA_0 ibcctrla;
312  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
313  unsigned int port_state;
314  unsigned int link_state;
315 
316  /* Set new link state */
317  port_state = ( port_info->link_speed_supported__port_state & 0xf );
318  if ( port_state ) {
319  link_state = ( port_state - 1 );
320  DBGC ( qib7322, "QIB7322 %p set link state to %s (%x)\n",
321  qib7322, qib7322_link_state_text ( link_state ),
322  link_state );
323  qib7322_readq_port ( qib7322, &ibcctrla,
324  QIB_7322_IBCCtrlA_0_offset, port );
325  BIT_SET ( &ibcctrla, LinkCmd, link_state );
326  qib7322_writeq_port ( qib7322, &ibcctrla,
327  QIB_7322_IBCCtrlA_0_offset, port );
328 
329  /* Wait for link state change to take effect. Ignore
330  * errors; the current link state will be returned via
331  * the GetResponse MAD.
332  */
333  qib7322_link_state_check ( ibdev, link_state );
334  }
335 
336  /* Detect and report link state change */
337  qib7322_link_state_changed ( ibdev );
338 
339  return 0;
340 }
341 
342 /**
343  * Set partition key table
344  *
345  * @v ibdev Infiniband device
346  * @v mad Set partition key table MAD
347  */
348 static int qib7322_set_pkey_table ( struct ib_device *ibdev __unused,
349  union ib_mad *mad __unused ) {
350  /* Nothing to do */
351  return 0;
352 }
353 
354 /***************************************************************************
355  *
356  * Context allocation
357  *
358  ***************************************************************************
359  */
360 
361 /**
362  * Allocate a context and set queue pair number
363  *
364  * @v ibdev Infiniband device
365  * @v qp Queue pair
366  * @ret rc Return status code
367  */
368 static int qib7322_alloc_ctx ( struct ib_device *ibdev,
369  struct ib_queue_pair *qp ) {
370  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
371  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
372  unsigned int ctx;
373 
374  for ( ctx = port ; ctx < QIB7322_NUM_CONTEXTS ; ctx += 2 ) {
375 
376  if ( ! qib7322->used_ctx[ctx] ) {
377  qib7322->used_ctx[ctx] = 1;
378  qp->qpn = ( ctx & ~0x01 );
379  DBGC2 ( qib7322, "QIB7322 %p port %d QPN %ld is CTX "
380  "%d\n", qib7322, port, qp->qpn, ctx );
381  return 0;
382  }
383  }
384 
385  DBGC ( qib7322, "QIB7322 %p port %d out of available contexts\n",
386  qib7322, port );
387  return -ENOENT;
388 }
389 
390 /**
391  * Get queue pair context number
392  *
393  * @v ibdev Infiniband device
394  * @v qp Queue pair
395  * @ret ctx Context index
396  */
397 static unsigned int qib7322_ctx ( struct ib_device *ibdev,
398  struct ib_queue_pair *qp ) {
399  return ( qp->qpn + ( ibdev->port - QIB7322_PORT_BASE ) );
400 }
401 
402 /**
403  * Free a context
404  *
405  * @v qib7322 QIB7322 device
406  * @v ctx Context index
407  */
408 static void qib7322_free_ctx ( struct ib_device *ibdev,
409  struct ib_queue_pair *qp ) {
410  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
411  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
412  unsigned int ctx = qib7322_ctx ( ibdev, qp );
413 
414  qib7322->used_ctx[ctx] = 0;
415  DBGC2 ( qib7322, "QIB7322 %p port %d CTX %d freed\n",
416  qib7322, port, ctx );
417 }
418 
419 /***************************************************************************
420  *
421  * Send datapath
422  *
423  ***************************************************************************
424  */
425 
426 /** Send buffer toggle bit
427  *
428  * We encode send buffers as 15 bits of send buffer index plus a
429  * single bit which should match the "check" bit in the SendBufAvail
430  * array.
431  */
432 #define QIB7322_SEND_BUF_TOGGLE 0x8000
433 
434 /**
435  * Create send buffer set
436  *
437  * @v qib7322 QIB7322 device
438  * @v base Send buffer base offset
439  * @v size Send buffer size
440  * @v start Index of first send buffer
441  * @v count Number of send buffers
442  * @ret send_bufs Send buffer set
443  */
444 static struct qib7322_send_buffers *
445 qib7322_create_send_bufs ( struct qib7322 *qib7322, unsigned long base,
446  unsigned int size, unsigned int start,
447  unsigned int count ) {
448  struct qib7322_send_buffers *send_bufs;
449  unsigned int i;
450 
451  /* Allocate send buffer set */
452  send_bufs = zalloc ( sizeof ( *send_bufs ) +
453  ( count * sizeof ( send_bufs->avail[0] ) ) );
454  if ( ! send_bufs )
455  return NULL;
456 
457  /* Populate send buffer set */
458  send_bufs->base = base;
459  send_bufs->size = size;
460  send_bufs->start = start;
461  send_bufs->count = count;
462  for ( i = 0 ; i < count ; i++ )
463  send_bufs->avail[i] = ( start + i );
464 
465  DBGC2 ( qib7322, "QIB7322 %p send buffer set %p [%d,%d] at %lx\n",
466  qib7322, send_bufs, start, ( start + count - 1 ),
467  send_bufs->base );
468 
469  return send_bufs;
470 }
471 
472 /**
473  * Destroy send buffer set
474  *
475  * @v qib7322 QIB7322 device
476  * @v send_bufs Send buffer set
477  */
478 static void
479 qib7322_destroy_send_bufs ( struct qib7322 *qib7322 __unused,
480  struct qib7322_send_buffers *send_bufs ) {
481  free ( send_bufs );
482 }
483 
484 /**
485  * Allocate a send buffer
486  *
487  * @v qib7322 QIB7322 device
488  * @v send_bufs Send buffer set
489  * @ret send_buf Send buffer, or negative error
490  */
491 static int qib7322_alloc_send_buf ( struct qib7322 *qib7322,
492  struct qib7322_send_buffers *send_bufs ) {
493  unsigned int used;
494  unsigned int mask;
495  unsigned int send_buf;
496 
497  used = ( send_bufs->cons - send_bufs->prod );
498  if ( used >= send_bufs->count ) {
499  DBGC ( qib7322, "QIB7322 %p send buffer set %p out of "
500  "buffers\n", qib7322, send_bufs );
501  return -ENOBUFS;
502  }
503 
504  mask = ( send_bufs->count - 1 );
505  send_buf = send_bufs->avail[ send_bufs->cons++ & mask ];
506  send_buf ^= QIB7322_SEND_BUF_TOGGLE;
507  return send_buf;
508 }
509 
510 /**
511  * Free a send buffer
512  *
513  * @v qib7322 QIB7322 device
514  * @v send_bufs Send buffer set
515  * @v send_buf Send buffer
516  */
517 static void qib7322_free_send_buf ( struct qib7322 *qib7322 __unused,
518  struct qib7322_send_buffers *send_bufs,
519  unsigned int send_buf ) {
520  unsigned int mask;
521 
522  mask = ( send_bufs->count - 1 );
523  send_bufs->avail[ send_bufs->prod++ & mask ] = send_buf;
524 }
525 
526 /**
527  * Check to see if send buffer is in use
528  *
529  * @v qib7322 QIB7322 device
530  * @v send_buf Send buffer
531  * @ret in_use Send buffer is in use
532  */
533 static int qib7322_send_buf_in_use ( struct qib7322 *qib7322,
534  unsigned int send_buf ) {
535  unsigned int send_idx;
536  unsigned int send_check;
537  unsigned int inusecheck;
538  unsigned int inuse;
539  unsigned int check;
540 
541  send_idx = ( send_buf & ~QIB7322_SEND_BUF_TOGGLE );
542  send_check = ( !! ( send_buf & QIB7322_SEND_BUF_TOGGLE ) );
543  inusecheck = BIT_GET ( qib7322->sendbufavail, InUseCheck[send_idx] );
544  inuse = ( !! ( inusecheck & 0x02 ) );
545  check = ( !! ( inusecheck & 0x01 ) );
546  return ( inuse || ( check != send_check ) );
547 }
548 
549 /**
550  * Calculate starting offset for send buffer
551  *
552  * @v qib7322 QIB7322 device
553  * @v send_buf Send buffer
554  * @ret offset Starting offset
555  */
556 static unsigned long
557 qib7322_send_buffer_offset ( struct qib7322 *qib7322 __unused,
558  struct qib7322_send_buffers *send_bufs,
559  unsigned int send_buf ) {
560  unsigned int index;
561 
562  index = ( ( send_buf & ~QIB7322_SEND_BUF_TOGGLE ) - send_bufs->start );
563  return ( send_bufs->base + ( index * send_bufs->size ) );
564 }
565 
566 /**
567  * Create send work queue
568  *
569  * @v ibdev Infiniband device
570  * @v qp Queue pair
571  */
572 static int qib7322_create_send_wq ( struct ib_device *ibdev,
573  struct ib_queue_pair *qp ) {
574  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
575  struct ib_work_queue *wq = &qp->send;
576  struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
577  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
578 
579  /* Select send buffer set */
580  if ( qp->type == IB_QPT_SMI ) {
581  if ( port == 0 ) {
582  qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port0;
583  } else {
584  qib7322_wq->send_bufs = qib7322->send_bufs_vl15_port1;
585  }
586  } else {
587  qib7322_wq->send_bufs = qib7322->send_bufs_small;
588  }
589 
590  /* Allocate space for send buffer usage list */
591  qib7322_wq->used = zalloc ( qp->send.num_wqes *
592  sizeof ( qib7322_wq->used[0] ) );
593  if ( ! qib7322_wq->used )
594  return -ENOMEM;
595 
596  /* Reset work queue */
597  qib7322_wq->prod = 0;
598  qib7322_wq->cons = 0;
599 
600  return 0;
601 }
602 
603 /**
604  * Destroy send work queue
605  *
606  * @v ibdev Infiniband device
607  * @v qp Queue pair
608  */
609 static void qib7322_destroy_send_wq ( struct ib_device *ibdev __unused,
610  struct ib_queue_pair *qp ) {
611  struct ib_work_queue *wq = &qp->send;
612  struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
613 
614  free ( qib7322_wq->used );
615 }
616 
617 /**
618  * Initialise send datapath
619  *
620  * @v qib7322 QIB7322 device
621  * @ret rc Return status code
622  */
623 static int qib7322_init_send ( struct qib7322 *qib7322 ) {
624  struct QIB_7322_SendBufBase sendbufbase;
625  struct QIB_7322_SendBufAvailAddr sendbufavailaddr;
626  struct QIB_7322_SendCtrl sendctrl;
627  struct QIB_7322_SendCtrl_0 sendctrlp;
628  unsigned long baseaddr_smallpio;
629  unsigned long baseaddr_largepio;
630  unsigned long baseaddr_vl15_port0;
631  unsigned long baseaddr_vl15_port1;
632  int rc;
633 
634  /* Create send buffer sets */
635  qib7322_readq ( qib7322, &sendbufbase, QIB_7322_SendBufBase_offset );
636  baseaddr_smallpio = BIT_GET ( &sendbufbase, BaseAddr_SmallPIO );
637  baseaddr_largepio = BIT_GET ( &sendbufbase, BaseAddr_LargePIO );
638  baseaddr_vl15_port0 = ( baseaddr_largepio +
639  ( QIB7322_LARGE_SEND_BUF_SIZE *
640  QIB7322_LARGE_SEND_BUF_COUNT ) );
641  baseaddr_vl15_port1 = ( baseaddr_vl15_port0 +
642  QIB7322_VL15_PORT0_SEND_BUF_SIZE );
643  qib7322->send_bufs_small =
644  qib7322_create_send_bufs ( qib7322, baseaddr_smallpio,
645  QIB7322_SMALL_SEND_BUF_SIZE,
646  QIB7322_SMALL_SEND_BUF_START,
647  QIB7322_SMALL_SEND_BUF_USED );
648  if ( ! qib7322->send_bufs_small ) {
649  rc = -ENOMEM;
650  goto err_create_send_bufs_small;
651  }
652  qib7322->send_bufs_vl15_port0 =
653  qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port0,
654  QIB7322_VL15_PORT0_SEND_BUF_SIZE,
655  QIB7322_VL15_PORT0_SEND_BUF_START,
656  QIB7322_VL15_PORT0_SEND_BUF_COUNT );
657  if ( ! qib7322->send_bufs_vl15_port0 ) {
658  rc = -ENOMEM;
659  goto err_create_send_bufs_vl15_port0;
660  }
661  qib7322->send_bufs_vl15_port1 =
662  qib7322_create_send_bufs ( qib7322, baseaddr_vl15_port1,
663  QIB7322_VL15_PORT1_SEND_BUF_SIZE,
664  QIB7322_VL15_PORT1_SEND_BUF_START,
665  QIB7322_VL15_PORT1_SEND_BUF_COUNT );
666  if ( ! qib7322->send_bufs_vl15_port1 ) {
667  rc = -ENOMEM;
668  goto err_create_send_bufs_vl15_port1;
669  }
670 
671  /* Allocate space for the SendBufAvail array */
672  qib7322->sendbufavail = malloc_phys ( sizeof ( *qib7322->sendbufavail ),
673  QIB7322_SENDBUFAVAIL_ALIGN );
674  if ( ! qib7322->sendbufavail ) {
675  rc = -ENOMEM;
676  goto err_alloc_sendbufavail;
677  }
678  memset ( qib7322->sendbufavail, 0, sizeof ( *qib7322->sendbufavail ) );
679 
680  /* Program SendBufAvailAddr into the hardware */
681  memset ( &sendbufavailaddr, 0, sizeof ( sendbufavailaddr ) );
682  BIT_FILL_1 ( &sendbufavailaddr, SendBufAvailAddr,
683  ( virt_to_bus ( qib7322->sendbufavail ) >> 6 ) );
684  qib7322_writeq ( qib7322, &sendbufavailaddr,
685  QIB_7322_SendBufAvailAddr_offset );
686 
687  /* Enable sending */
688  memset ( &sendctrlp, 0, sizeof ( sendctrlp ) );
689  BIT_FILL_1 ( &sendctrlp, SendEnable, 1 );
690  qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_0_offset );
691  qib7322_writeq ( qib7322, &sendctrlp, QIB_7322_SendCtrl_1_offset );
692 
693  /* Enable DMA of SendBufAvail */
694  memset ( &sendctrl, 0, sizeof ( sendctrl ) );
695  BIT_FILL_1 ( &sendctrl, SendBufAvailUpd, 1 );
696  qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
697 
698  return 0;
699 
700  free_phys ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
701  err_alloc_sendbufavail:
702  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
703  err_create_send_bufs_vl15_port1:
704  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
705  err_create_send_bufs_vl15_port0:
706  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
707  err_create_send_bufs_small:
708  return rc;
709 }
710 
711 /**
712  * Shut down send datapath
713  *
714  * @v qib7322 QIB7322 device
715  */
716 static void qib7322_fini_send ( struct qib7322 *qib7322 ) {
717  struct QIB_7322_SendCtrl sendctrl;
718 
719  /* Disable sending and DMA of SendBufAvail */
720  memset ( &sendctrl, 0, sizeof ( sendctrl ) );
721  qib7322_writeq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
722  mb();
723 
724  /* Ensure hardware has seen this disable */
725  qib7322_readq ( qib7322, &sendctrl, QIB_7322_SendCtrl_offset );
726 
727  free_phys ( qib7322->sendbufavail, sizeof ( *qib7322->sendbufavail ) );
728  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port1 );
729  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_vl15_port0 );
730  qib7322_destroy_send_bufs ( qib7322, qib7322->send_bufs_small );
731 }
732 
733 /***************************************************************************
734  *
735  * Receive datapath
736  *
737  ***************************************************************************
738  */
739 
740 /**
741  * Create receive work queue
742  *
743  * @v ibdev Infiniband device
744  * @v qp Queue pair
745  * @ret rc Return status code
746  */
747 static int qib7322_create_recv_wq ( struct ib_device *ibdev,
748  struct ib_queue_pair *qp ) {
749  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
750  struct ib_work_queue *wq = &qp->recv;
751  struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
752  struct QIB_7322_RcvHdrAddr0 rcvhdraddr;
753  struct QIB_7322_RcvHdrTailAddr0 rcvhdrtailaddr;
754  struct QIB_7322_RcvHdrHead0 rcvhdrhead;
755  struct QIB_7322_scalar rcvegrindexhead;
756  struct QIB_7322_RcvCtrl rcvctrl;
757  struct QIB_7322_RcvCtrl_P rcvctrlp;
758  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
759  unsigned int ctx = qib7322_ctx ( ibdev, qp );
760  int rc;
761 
762  /* Reset context information */
763  memset ( &qib7322_wq->header_prod, 0,
764  sizeof ( qib7322_wq->header_prod ) );
765  qib7322_wq->header_cons = 0;
766  qib7322_wq->eager_prod = 0;
767  qib7322_wq->eager_cons = 0;
768 
769  /* Allocate receive header buffer */
770  qib7322_wq->header = malloc_phys ( QIB7322_RECV_HEADERS_SIZE,
771  QIB7322_RECV_HEADERS_ALIGN );
772  if ( ! qib7322_wq->header ) {
773  rc = -ENOMEM;
774  goto err_alloc_header;
775  }
776 
777  /* Enable context in hardware */
778  memset ( &rcvhdraddr, 0, sizeof ( rcvhdraddr ) );
779  BIT_FILL_1 ( &rcvhdraddr, RcvHdrAddr,
780  ( virt_to_bus ( qib7322_wq->header ) >> 2 ) );
781  qib7322_writeq_array8b ( qib7322, &rcvhdraddr,
782  QIB_7322_RcvHdrAddr0_offset, ctx );
783  memset ( &rcvhdrtailaddr, 0, sizeof ( rcvhdrtailaddr ) );
784  BIT_FILL_1 ( &rcvhdrtailaddr, RcvHdrTailAddr,
785  ( virt_to_bus ( &qib7322_wq->header_prod ) >> 2 ) );
786  qib7322_writeq_array8b ( qib7322, &rcvhdrtailaddr,
787  QIB_7322_RcvHdrTailAddr0_offset, ctx );
788  memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
789  BIT_FILL_1 ( &rcvhdrhead, counter, 1 );
790  qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
791  QIB_7322_RcvHdrHead0_offset, ctx );
792  memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
793  BIT_FILL_1 ( &rcvegrindexhead, Value, 1 );
794  qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
795  QIB_7322_RcvEgrIndexHead0_offset, ctx );
796  qib7322_readq_port ( qib7322, &rcvctrlp,
797  QIB_7322_RcvCtrl_0_offset, port );
798  BIT_SET ( &rcvctrlp, ContextEnable[ctx], 1 );
799  qib7322_writeq_port ( qib7322, &rcvctrlp,
800  QIB_7322_RcvCtrl_0_offset, port );
801  qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
802  BIT_SET ( &rcvctrl, IntrAvail[ctx], 1 );
803  qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
804 
805  DBGC ( qib7322, "QIB7322 %p port %d QPN %ld CTX %d hdrs [%lx,%lx) prod "
806  "%lx\n", qib7322, port, qp->qpn, ctx,
807  virt_to_bus ( qib7322_wq->header ),
808  ( virt_to_bus ( qib7322_wq->header )
809  + QIB7322_RECV_HEADERS_SIZE ),
810  virt_to_bus ( &qib7322_wq->header_prod ) );
811  return 0;
812 
813  free_phys ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
814  err_alloc_header:
815  return rc;
816 }
817 
818 /**
819  * Destroy receive work queue
820  *
821  * @v ibdev Infiniband device
822  * @v qp Queue pair
823  */
824 static void qib7322_destroy_recv_wq ( struct ib_device *ibdev,
825  struct ib_queue_pair *qp ) {
826  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
827  struct ib_work_queue *wq = &qp->recv;
828  struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
829  struct QIB_7322_RcvCtrl rcvctrl;
830  struct QIB_7322_RcvCtrl_P rcvctrlp;
831  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
832  unsigned int ctx = qib7322_ctx ( ibdev, qp );
833 
834  /* Disable context in hardware */
835  qib7322_readq_port ( qib7322, &rcvctrlp,
836  QIB_7322_RcvCtrl_0_offset, port );
837  BIT_SET ( &rcvctrlp, ContextEnable[ctx], 0 );
838  qib7322_writeq_port ( qib7322, &rcvctrlp,
839  QIB_7322_RcvCtrl_0_offset, port );
840  qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
841  BIT_SET ( &rcvctrl, IntrAvail[ctx], 0 );
842  qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
843 
844  /* Make sure the hardware has seen that the context is disabled */
845  qib7322_readq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
846  mb();
847 
848  /* Free headers ring */
849  free_phys ( qib7322_wq->header, QIB7322_RECV_HEADERS_SIZE );
850 }
851 
852 /**
853  * Initialise receive datapath
854  *
855  * @v qib7322 QIB7322 device
856  * @ret rc Return status code
857  */
858 static int qib7322_init_recv ( struct qib7322 *qib7322 ) {
859  struct QIB_7322_RcvCtrl rcvctrl;
860  struct QIB_7322_RcvCtrl_0 rcvctrlp;
861  struct QIB_7322_RcvQPMapTableA_0 rcvqpmaptablea0;
862  struct QIB_7322_RcvQPMapTableB_0 rcvqpmaptableb0;
863  struct QIB_7322_RcvQPMapTableA_1 rcvqpmaptablea1;
864  struct QIB_7322_RcvQPMapTableB_1 rcvqpmaptableb1;
865  struct QIB_7322_RcvQPMulticastContext_0 rcvqpmcastctx0;
866  struct QIB_7322_RcvQPMulticastContext_1 rcvqpmcastctx1;
867  struct QIB_7322_scalar rcvegrbase;
868  struct QIB_7322_scalar rcvhdrentsize;
869  struct QIB_7322_scalar rcvhdrcnt;
870  struct QIB_7322_RcvBTHQP_0 rcvbthqp;
871  struct QIB_7322_RxCreditVL0_0 rxcreditvl;
872  unsigned int contextcfg;
873  unsigned long egrbase;
874  unsigned int eager_array_size_kernel;
875  unsigned int eager_array_size_user;
876  unsigned int ctx;
877 
878  /* Select configuration based on number of contexts */
879  switch ( QIB7322_NUM_CONTEXTS ) {
880  case 6:
881  contextcfg = QIB7322_CONTEXTCFG_6CTX;
882  eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL;
883  eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_6CTX_USER;
884  break;
885  case 10:
886  contextcfg = QIB7322_CONTEXTCFG_10CTX;
887  eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL;
888  eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_10CTX_USER;
889  break;
890  case 18:
891  contextcfg = QIB7322_CONTEXTCFG_18CTX;
892  eager_array_size_kernel = QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL;
893  eager_array_size_user = QIB7322_EAGER_ARRAY_SIZE_18CTX_USER;
894  break;
895  default:
896  build_assert ( 0 );
897  return -EINVAL;
898  }
899 
900  /* Configure number of contexts */
901  memset ( &rcvctrl, 0, sizeof ( rcvctrl ) );
902  BIT_FILL_2 ( &rcvctrl,
903  TailUpd, 1,
904  ContextCfg, contextcfg );
905  qib7322_writeq ( qib7322, &rcvctrl, QIB_7322_RcvCtrl_offset );
906 
907  /* Map QPNs to contexts */
908  memset ( &rcvctrlp, 0, sizeof ( rcvctrlp ) );
909  BIT_FILL_3 ( &rcvctrlp,
910  RcvIBPortEnable, 1,
911  RcvQPMapEnable, 1,
912  RcvPartitionKeyDisable, 1 );
913  qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_0_offset );
914  qib7322_writeq ( qib7322, &rcvctrlp, QIB_7322_RcvCtrl_1_offset );
915  memset ( &rcvqpmaptablea0, 0, sizeof ( rcvqpmaptablea0 ) );
916  BIT_FILL_6 ( &rcvqpmaptablea0,
917  RcvQPMapContext0, 0,
918  RcvQPMapContext1, 2,
919  RcvQPMapContext2, 4,
920  RcvQPMapContext3, 6,
921  RcvQPMapContext4, 8,
922  RcvQPMapContext5, 10 );
923  qib7322_writeq ( qib7322, &rcvqpmaptablea0,
924  QIB_7322_RcvQPMapTableA_0_offset );
925  memset ( &rcvqpmaptableb0, 0, sizeof ( rcvqpmaptableb0 ) );
926  BIT_FILL_3 ( &rcvqpmaptableb0,
927  RcvQPMapContext6, 12,
928  RcvQPMapContext7, 14,
929  RcvQPMapContext8, 16 );
930  qib7322_writeq ( qib7322, &rcvqpmaptableb0,
931  QIB_7322_RcvQPMapTableB_0_offset );
932  memset ( &rcvqpmaptablea1, 0, sizeof ( rcvqpmaptablea1 ) );
933  BIT_FILL_6 ( &rcvqpmaptablea1,
934  RcvQPMapContext0, 1,
935  RcvQPMapContext1, 3,
936  RcvQPMapContext2, 5,
937  RcvQPMapContext3, 7,
938  RcvQPMapContext4, 9,
939  RcvQPMapContext5, 11 );
940  qib7322_writeq ( qib7322, &rcvqpmaptablea1,
941  QIB_7322_RcvQPMapTableA_1_offset );
942  memset ( &rcvqpmaptableb1, 0, sizeof ( rcvqpmaptableb1 ) );
943  BIT_FILL_3 ( &rcvqpmaptableb1,
944  RcvQPMapContext6, 13,
945  RcvQPMapContext7, 15,
946  RcvQPMapContext8, 17 );
947  qib7322_writeq ( qib7322, &rcvqpmaptableb1,
948  QIB_7322_RcvQPMapTableB_1_offset );
949 
950  /* Map multicast QPNs to contexts */
951  memset ( &rcvqpmcastctx0, 0, sizeof ( rcvqpmcastctx0 ) );
952  BIT_FILL_1 ( &rcvqpmcastctx0, RcvQpMcContext, 0 );
953  qib7322_writeq ( qib7322, &rcvqpmcastctx0,
954  QIB_7322_RcvQPMulticastContext_0_offset );
955  memset ( &rcvqpmcastctx1, 0, sizeof ( rcvqpmcastctx1 ) );
956  BIT_FILL_1 ( &rcvqpmcastctx1, RcvQpMcContext, 1 );
957  qib7322_writeq ( qib7322, &rcvqpmcastctx1,
958  QIB_7322_RcvQPMulticastContext_1_offset );
959 
960  /* Configure receive header buffer sizes */
961  memset ( &rcvhdrcnt, 0, sizeof ( rcvhdrcnt ) );
962  BIT_FILL_1 ( &rcvhdrcnt, Value, QIB7322_RECV_HEADER_COUNT );
963  qib7322_writeq ( qib7322, &rcvhdrcnt, QIB_7322_RcvHdrCnt_offset );
964  memset ( &rcvhdrentsize, 0, sizeof ( rcvhdrentsize ) );
965  BIT_FILL_1 ( &rcvhdrentsize, Value, ( QIB7322_RECV_HEADER_SIZE >> 2 ) );
966  qib7322_writeq ( qib7322, &rcvhdrentsize,
967  QIB_7322_RcvHdrEntSize_offset );
968 
969  /* Calculate eager array start addresses for each context */
970  qib7322_readq ( qib7322, &rcvegrbase, QIB_7322_RcvEgrBase_offset );
971  egrbase = BIT_GET ( &rcvegrbase, Value );
972  for ( ctx = 0 ; ctx < QIB7322_MAX_PORTS ; ctx++ ) {
973  qib7322->recv_wq[ctx].eager_array = egrbase;
974  qib7322->recv_wq[ctx].eager_entries = eager_array_size_kernel;
975  egrbase += ( eager_array_size_kernel *
976  sizeof ( struct QIB_7322_RcvEgr ) );
977  }
978  for ( ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
979  qib7322->recv_wq[ctx].eager_array = egrbase;
980  qib7322->recv_wq[ctx].eager_entries = eager_array_size_user;
981  egrbase += ( eager_array_size_user *
982  sizeof ( struct QIB_7322_RcvEgr ) );
983  }
984  for ( ctx = 0 ; ctx < QIB7322_NUM_CONTEXTS ; ctx++ ) {
985  DBGC ( qib7322, "QIB7322 %p CTX %d eager array at %lx (%d "
986  "entries)\n", qib7322, ctx,
987  qib7322->recv_wq[ctx].eager_array,
988  qib7322->recv_wq[ctx].eager_entries );
989  }
990 
991  /* Set the BTH QP for Infinipath packets to an unused value */
992  memset ( &rcvbthqp, 0, sizeof ( rcvbthqp ) );
993  BIT_FILL_1 ( &rcvbthqp, RcvBTHQP, QIB7322_QP_IDETH );
994  qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_0_offset );
995  qib7322_writeq ( qib7322, &rcvbthqp, QIB_7322_RcvBTHQP_1_offset );
996 
997  /* Assign initial credits */
998  memset ( &rxcreditvl, 0, sizeof ( rxcreditvl ) );
999  BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL0 );
1000  qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1001  QIB_7322_RxCreditVL0_0_offset, 0 );
1002  qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1003  QIB_7322_RxCreditVL0_1_offset, 0 );
1004  BIT_FILL_1 ( &rxcreditvl, RxMaxCreditVL, QIB7322_MAX_CREDITS_VL15 );
1005  qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1006  QIB_7322_RxCreditVL0_0_offset, 15 );
1007  qib7322_writeq_array8b ( qib7322, &rxcreditvl,
1008  QIB_7322_RxCreditVL0_1_offset, 15 );
1009 
1010  return 0;
1011 }
1012 
1013 /**
1014  * Shut down receive datapath
1015  *
1016  * @v qib7322 QIB7322 device
1017  */
1018 static void qib7322_fini_recv ( struct qib7322 *qib7322 __unused ) {
1019  /* Nothing to do; all contexts were already disabled when the
1020  * queue pairs were destroyed
1021  */
1022 }
1023 
1024 /***************************************************************************
1025  *
1026  * Completion queue operations
1027  *
1028  ***************************************************************************
1029  */
1030 
1031 /**
1032  * Create completion queue
1033  *
1034  * @v ibdev Infiniband device
1035  * @v cq Completion queue
1036  * @ret rc Return status code
1037  */
1038 static int qib7322_create_cq ( struct ib_device *ibdev,
1039  struct ib_completion_queue *cq ) {
1040  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1041  static int cqn;
1042 
1043  /* The hardware has no concept of completion queues. We
1044  * simply use the association between CQs and WQs (already
1045  * handled by the IB core) to decide which WQs to poll.
1046  *
1047  * We do set a CQN, just to avoid confusing debug messages
1048  * from the IB core.
1049  */
1050  cq->cqn = ++cqn;
1051  DBGC ( qib7322, "QIB7322 %p CQN %ld created\n", qib7322, cq->cqn );
1052 
1053  return 0;
1054 }
1055 
1056 /**
1057  * Destroy completion queue
1058  *
1059  * @v ibdev Infiniband device
1060  * @v cq Completion queue
1061  */
1062 static void qib7322_destroy_cq ( struct ib_device *ibdev,
1063  struct ib_completion_queue *cq ) {
1064  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1065 
1066  /* Nothing to do */
1067  DBGC ( qib7322, "QIB7322 %p CQN %ld destroyed\n", qib7322, cq->cqn );
1068 }
1069 
1070 /***************************************************************************
1071  *
1072  * Queue pair operations
1073  *
1074  ***************************************************************************
1075  */
1076 
1077 /**
1078  * Create queue pair
1079  *
1080  * @v ibdev Infiniband device
1081  * @v qp Queue pair
1082  * @ret rc Return status code
1083  */
1084 static int qib7322_create_qp ( struct ib_device *ibdev,
1085  struct ib_queue_pair *qp ) {
1086  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1087  unsigned int ctx;
1088  int rc;
1089 
1090  /* Allocate a context and QPN */
1091  if ( ( rc = qib7322_alloc_ctx ( ibdev, qp ) ) != 0 )
1092  goto err_alloc_ctx;
1093  ctx = qib7322_ctx ( ibdev, qp );
1094 
1095  /* Set work-queue private data pointers */
1096  ib_wq_set_drvdata ( &qp->send, &qib7322->send_wq[ctx] );
1097  ib_wq_set_drvdata ( &qp->recv, &qib7322->recv_wq[ctx] );
1098 
1099  /* Create receive work queue */
1100  if ( ( rc = qib7322_create_recv_wq ( ibdev, qp ) ) != 0 )
1101  goto err_create_recv_wq;
1102 
1103  /* Create send work queue */
1104  if ( ( rc = qib7322_create_send_wq ( ibdev, qp ) ) != 0 )
1105  goto err_create_send_wq;
1106 
1107  return 0;
1108 
1109  qib7322_destroy_send_wq ( ibdev, qp );
1110  err_create_send_wq:
1111  qib7322_destroy_recv_wq ( ibdev, qp );
1112  err_create_recv_wq:
1113  qib7322_free_ctx ( ibdev, qp );
1114  err_alloc_ctx:
1115  return rc;
1116 }
1117 
1118 /**
1119  * Modify queue pair
1120  *
1121  * @v ibdev Infiniband device
1122  * @v qp Queue pair
1123  * @ret rc Return status code
1124  */
1125 static int qib7322_modify_qp ( struct ib_device *ibdev,
1126  struct ib_queue_pair *qp ) {
1127  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1128 
1129  /* Nothing to do; the hardware doesn't have a notion of queue
1130  * keys
1131  */
1132  DBGC2 ( qib7322, "QIB7322 %p QPN %ld modified\n", qib7322, qp->qpn );
1133  return 0;
1134 }
1135 
1136 /**
1137  * Destroy queue pair
1138  *
1139  * @v ibdev Infiniband device
1140  * @v qp Queue pair
1141  */
1142 static void qib7322_destroy_qp ( struct ib_device *ibdev,
1143  struct ib_queue_pair *qp ) {
1144 
1145  qib7322_destroy_send_wq ( ibdev, qp );
1146  qib7322_destroy_recv_wq ( ibdev, qp );
1147  qib7322_free_ctx ( ibdev, qp );
1148 }
1149 
1150 /***************************************************************************
1151  *
1152  * Work request operations
1153  *
1154  ***************************************************************************
1155  */
1156 
1157 /**
1158  * Post send work queue entry
1159  *
1160  * @v ibdev Infiniband device
1161  * @v qp Queue pair
1162  * @v dest Destination address vector
1163  * @v iobuf I/O buffer
1164  * @ret rc Return status code
1165  */
1166 static int qib7322_post_send ( struct ib_device *ibdev,
1167  struct ib_queue_pair *qp,
1168  struct ib_address_vector *dest,
1169  struct io_buffer *iobuf ) {
1170  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1171  struct ib_work_queue *wq = &qp->send;
1172  struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1173  struct QIB_7322_SendPbc sendpbc;
1174  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1175  uint8_t header_buf[IB_MAX_HEADER_SIZE];
1176  struct io_buffer headers;
1177  int send_buf;
1178  unsigned long start_offset;
1179  unsigned long offset;
1180  size_t len;
1181  ssize_t frag_len;
1182  uint32_t *data;
1183 
1184  /* Allocate send buffer and calculate offset */
1185  send_buf = qib7322_alloc_send_buf ( qib7322, qib7322_wq->send_bufs );
1186  if ( send_buf < 0 )
1187  return send_buf;
1188  start_offset = offset =
1189  qib7322_send_buffer_offset ( qib7322, qib7322_wq->send_bufs,
1190  send_buf );
1191 
1192  /* Store I/O buffer and send buffer index */
1193  assert ( wq->iobufs[qib7322_wq->prod] == NULL );
1194  wq->iobufs[qib7322_wq->prod] = iobuf;
1195  qib7322_wq->used[qib7322_wq->prod] = send_buf;
1196 
1197  /* Construct headers */
1198  iob_populate ( &headers, header_buf, 0, sizeof ( header_buf ) );
1199  iob_reserve ( &headers, sizeof ( header_buf ) );
1200  ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), dest );
1201 
1202  /* Calculate packet length */
1203  len = ( ( sizeof ( sendpbc ) + iob_len ( &headers ) +
1204  iob_len ( iobuf ) + 3 ) & ~3 );
1205 
1206  /* Construct send per-buffer control word */
1207  memset ( &sendpbc, 0, sizeof ( sendpbc ) );
1208  BIT_FILL_3 ( &sendpbc,
1209  LengthP1_toibc, ( ( len >> 2 ) - 1 ),
1210  Port, port,
1211  VL15, ( ( qp->type == IB_QPT_SMI ) ? 1 : 0 ) );
1212 
1213  /* Write SendPbc */
1214  DBG_DISABLE ( DBGLVL_IO );
1215  qib7322_writeq ( qib7322, &sendpbc, offset );
1216  offset += sizeof ( sendpbc );
1217 
1218  /* Write headers */
1219  for ( data = headers.data, frag_len = iob_len ( &headers ) ;
1220  frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1221  qib7322_writel ( qib7322, *data, offset );
1222  }
1223 
1224  /* Write data */
1225  for ( data = iobuf->data, frag_len = iob_len ( iobuf ) ;
1226  frag_len > 0 ; data++, offset += 4, frag_len -= 4 ) {
1227  qib7322_writel ( qib7322, *data, offset );
1228  }
1229  DBG_ENABLE ( DBGLVL_IO );
1230 
1231  assert ( ( start_offset + len ) == offset );
1232  DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) posted [%lx,%lx)\n",
1233  qib7322, qp->qpn, send_buf, qib7322_wq->prod,
1234  start_offset, offset );
1235 
1236  /* Increment producer counter */
1237  qib7322_wq->prod = ( ( qib7322_wq->prod + 1 ) & ( wq->num_wqes - 1 ) );
1238 
1239  return 0;
1240 }
1241 
1242 /**
1243  * Complete send work queue entry
1244  *
1245  * @v ibdev Infiniband device
1246  * @v qp Queue pair
1247  * @v wqe_idx Work queue entry index
1248  */
1249 static void qib7322_complete_send ( struct ib_device *ibdev,
1250  struct ib_queue_pair *qp,
1251  unsigned int wqe_idx ) {
1252  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1253  struct ib_work_queue *wq = &qp->send;
1254  struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1255  struct io_buffer *iobuf;
1256  unsigned int send_buf;
1257 
1258  /* Parse completion */
1259  send_buf = qib7322_wq->used[wqe_idx];
1260  DBGC2 ( qib7322, "QIB7322 %p QPN %ld TX %04x(%04x) complete\n",
1261  qib7322, qp->qpn, send_buf, wqe_idx );
1262 
1263  /* Complete work queue entry */
1264  iobuf = wq->iobufs[wqe_idx];
1265  assert ( iobuf != NULL );
1266  ib_complete_send ( ibdev, qp, iobuf, 0 );
1267  wq->iobufs[wqe_idx] = NULL;
1268 
1269  /* Free send buffer */
1270  qib7322_free_send_buf ( qib7322, qib7322_wq->send_bufs, send_buf );
1271 }
1272 
1273 /**
1274  * Poll send work queue
1275  *
1276  * @v ibdev Infiniband device
1277  * @v qp Queue pair
1278  */
1279 static void qib7322_poll_send_wq ( struct ib_device *ibdev,
1280  struct ib_queue_pair *qp ) {
1281  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1282  struct ib_work_queue *wq = &qp->send;
1283  struct qib7322_send_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1284  unsigned int send_buf;
1285 
1286  /* Look for completions */
1287  while ( wq->fill ) {
1288 
1289  /* Check to see if send buffer has completed */
1290  send_buf = qib7322_wq->used[qib7322_wq->cons];
1291  if ( qib7322_send_buf_in_use ( qib7322, send_buf ) )
1292  break;
1293 
1294  /* Complete this buffer */
1295  qib7322_complete_send ( ibdev, qp, qib7322_wq->cons );
1296 
1297  /* Increment consumer counter */
1298  qib7322_wq->cons = ( ( qib7322_wq->cons + 1 ) &
1299  ( wq->num_wqes - 1 ) );
1300  }
1301 }
1302 
1303 /**
1304  * Post receive work queue entry
1305  *
1306  * @v ibdev Infiniband device
1307  * @v qp Queue pair
1308  * @v iobuf I/O buffer
1309  * @ret rc Return status code
1310  */
1311 static int qib7322_post_recv ( struct ib_device *ibdev,
1312  struct ib_queue_pair *qp,
1313  struct io_buffer *iobuf ) {
1314  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1315  struct ib_work_queue *wq = &qp->recv;
1316  struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1317  struct QIB_7322_RcvEgr rcvegr;
1318  struct QIB_7322_scalar rcvegrindexhead;
1319  unsigned int ctx = qib7322_ctx ( ibdev, qp );
1320  physaddr_t addr;
1321  size_t len;
1322  unsigned int wqe_idx;
1323  unsigned int bufsize;
1324 
1325  /* Sanity checks */
1326  addr = virt_to_bus ( iobuf->data );
1327  len = iob_tailroom ( iobuf );
1328  if ( addr & ( QIB7322_EAGER_BUFFER_ALIGN - 1 ) ) {
1329  DBGC ( qib7322, "QIB7322 %p QPN %ld misaligned RX buffer "
1330  "(%08lx)\n", qib7322, qp->qpn, addr );
1331  return -EINVAL;
1332  }
1333  if ( len != QIB7322_RECV_PAYLOAD_SIZE ) {
1334  DBGC ( qib7322, "QIB7322 %p QPN %ld wrong RX buffer size "
1335  "(%zd)\n", qib7322, qp->qpn, len );
1336  return -EINVAL;
1337  }
1338 
1339  /* Calculate eager producer index and WQE index */
1340  wqe_idx = ( qib7322_wq->eager_prod & ( wq->num_wqes - 1 ) );
1341  assert ( wq->iobufs[wqe_idx] == NULL );
1342 
1343  /* Store I/O buffer */
1344  wq->iobufs[wqe_idx] = iobuf;
1345 
1346  /* Calculate buffer size */
1347  switch ( QIB7322_RECV_PAYLOAD_SIZE ) {
1348  case 2048: bufsize = QIB7322_EAGER_BUFFER_2K; break;
1349  case 4096: bufsize = QIB7322_EAGER_BUFFER_4K; break;
1350  case 8192: bufsize = QIB7322_EAGER_BUFFER_8K; break;
1351  case 16384: bufsize = QIB7322_EAGER_BUFFER_16K; break;
1352  case 32768: bufsize = QIB7322_EAGER_BUFFER_32K; break;
1353  case 65536: bufsize = QIB7322_EAGER_BUFFER_64K; break;
1354  default: build_assert ( 0 );
1355  bufsize = QIB7322_EAGER_BUFFER_NONE;
1356  }
1357 
1358  /* Post eager buffer */
1359  memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1360  BIT_FILL_2 ( &rcvegr,
1361  Addr, ( addr >> 11 ),
1362  BufSize, bufsize );
1363  qib7322_writeq_array8b ( qib7322, &rcvegr, qib7322_wq->eager_array,
1364  qib7322_wq->eager_prod );
1365  DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x(%04x) posted "
1366  "[%lx,%lx)\n", qib7322, qp->qpn, qib7322_wq->eager_prod,
1367  wqe_idx, addr, ( addr + len ) );
1368 
1369  /* Increment producer index */
1370  qib7322_wq->eager_prod = ( ( qib7322_wq->eager_prod + 1 ) &
1371  ( qib7322_wq->eager_entries - 1 ) );
1372 
1373  /* Update head index */
1374  memset ( &rcvegrindexhead, 0, sizeof ( rcvegrindexhead ) );
1375  BIT_FILL_1 ( &rcvegrindexhead,
1376  Value, ( ( qib7322_wq->eager_prod + 1 ) &
1377  ( qib7322_wq->eager_entries - 1 ) ) );
1378  qib7322_writeq_array64k ( qib7322, &rcvegrindexhead,
1379  QIB_7322_RcvEgrIndexHead0_offset, ctx );
1380 
1381  return 0;
1382 }
1383 
1384 /**
1385  * Complete receive work queue entry
1386  *
1387  * @v ibdev Infiniband device
1388  * @v qp Queue pair
1389  * @v header_offs Header offset
1390  */
1391 static void qib7322_complete_recv ( struct ib_device *ibdev,
1392  struct ib_queue_pair *qp,
1393  unsigned int header_offs ) {
1394  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1395  struct ib_work_queue *wq = &qp->recv;
1396  struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1397  struct QIB_7322_RcvHdrFlags *rcvhdrflags;
1398  struct QIB_7322_RcvEgr rcvegr;
1399  struct io_buffer headers;
1400  struct io_buffer *iobuf;
1401  struct ib_queue_pair *intended_qp;
1402  struct ib_address_vector dest;
1403  struct ib_address_vector source;
1404  unsigned int rcvtype;
1405  unsigned int pktlen;
1406  unsigned int egrindex;
1407  unsigned int useegrbfr;
1408  unsigned int iberr, mkerr, tiderr, khdrerr, mtuerr;
1409  unsigned int lenerr, parityerr, vcrcerr, icrcerr;
1410  unsigned int err;
1411  unsigned int hdrqoffset;
1412  unsigned int header_len;
1413  unsigned int padded_payload_len;
1414  unsigned int wqe_idx;
1415  size_t payload_len;
1416  int qp0;
1417  int rc;
1418 
1419  /* RcvHdrFlags are at the end of the header entry */
1420  rcvhdrflags = ( qib7322_wq->header + header_offs +
1421  QIB7322_RECV_HEADER_SIZE - sizeof ( *rcvhdrflags ) );
1422  rcvtype = BIT_GET ( rcvhdrflags, RcvType );
1423  pktlen = ( BIT_GET ( rcvhdrflags, PktLen ) << 2 );
1424  egrindex = BIT_GET ( rcvhdrflags, EgrIndex );
1425  useegrbfr = BIT_GET ( rcvhdrflags, UseEgrBfr );
1426  hdrqoffset = ( BIT_GET ( rcvhdrflags, HdrqOffset ) << 2 );
1427  iberr = BIT_GET ( rcvhdrflags, IBErr );
1428  mkerr = BIT_GET ( rcvhdrflags, MKErr );
1429  tiderr = BIT_GET ( rcvhdrflags, TIDErr );
1430  khdrerr = BIT_GET ( rcvhdrflags, KHdrErr );
1431  mtuerr = BIT_GET ( rcvhdrflags, MTUErr );
1432  lenerr = BIT_GET ( rcvhdrflags, LenErr );
1433  parityerr = BIT_GET ( rcvhdrflags, ParityErr );
1434  vcrcerr = BIT_GET ( rcvhdrflags, VCRCErr );
1435  icrcerr = BIT_GET ( rcvhdrflags, ICRCErr );
1436  header_len = ( QIB7322_RECV_HEADER_SIZE - hdrqoffset -
1437  sizeof ( *rcvhdrflags ) );
1438  padded_payload_len = ( pktlen - header_len - 4 /* ICRC */ );
1439  err = ( iberr | mkerr | tiderr | khdrerr | mtuerr |
1440  lenerr | parityerr | vcrcerr | icrcerr );
1441  /* IB header is placed immediately before RcvHdrFlags */
1442  iob_populate ( &headers, ( ( ( void * ) rcvhdrflags ) - header_len ),
1443  header_len, header_len );
1444 
1445  /* Dump diagnostic information */
1446  DBGC2 ( qib7322, "QIB7322 %p QPN %ld RX egr %04x%s hdr %d type %d len "
1447  "%d(%d+%d+4)%s%s%s%s%s%s%s%s%s%s%s\n", qib7322, qp->qpn,
1448  egrindex, ( useegrbfr ? "" : "(unused)" ),
1449  ( header_offs / QIB7322_RECV_HEADER_SIZE ),
1450  rcvtype, pktlen, header_len, padded_payload_len,
1451  ( err ? " [Err" : "" ), ( iberr ? " IB" : "" ),
1452  ( mkerr ? " MK" : "" ), ( tiderr ? " TID" : "" ),
1453  ( khdrerr ? " KHdr" : "" ), ( mtuerr ? " MTU" : "" ),
1454  ( lenerr ? " Len" : "" ), ( parityerr ? " Parity" : ""),
1455  ( vcrcerr ? " VCRC" : "" ), ( icrcerr ? " ICRC" : "" ),
1456  ( err ? "]" : "" ) );
1457  DBGCP_HDA ( qib7322, hdrqoffset, headers.data,
1458  ( header_len + sizeof ( *rcvhdrflags ) ) );
1459 
1460  /* Parse header to generate address vector */
1461  qp0 = ( qp->qpn == 0 );
1462  intended_qp = NULL;
1463  if ( ( rc = ib_pull ( ibdev, &headers, ( qp0 ? &intended_qp : NULL ),
1464  &payload_len, &dest, &source ) ) != 0 ) {
1465  DBGC ( qib7322, "QIB7322 %p could not parse headers: %s\n",
1466  qib7322, strerror ( rc ) );
1467  err = 1;
1468  }
1469  if ( ! intended_qp )
1470  intended_qp = qp;
1471 
1472  /* Complete this buffer and any skipped buffers. Note that
1473  * when the hardware runs out of buffers, it will repeatedly
1474  * report the same buffer (the tail) as a TID error, and that
1475  * it also has a habit of sometimes skipping over several
1476  * buffers at once.
1477  */
1478  while ( 1 ) {
1479 
1480  /* If we have caught up to the producer counter, stop.
1481  * This will happen when the hardware first runs out
1482  * of buffers and starts reporting TID errors against
1483  * the eager buffer it wants to use next.
1484  */
1485  if ( qib7322_wq->eager_cons == qib7322_wq->eager_prod )
1486  break;
1487 
1488  /* If we have caught up to where we should be after
1489  * completing this egrindex, stop. We phrase the test
1490  * this way to avoid completing the entire ring when
1491  * we receive the same egrindex twice in a row.
1492  */
1493  if ( ( qib7322_wq->eager_cons ==
1494  ( ( egrindex + 1 ) & ( qib7322_wq->eager_entries - 1 ))))
1495  break;
1496 
1497  /* Identify work queue entry and corresponding I/O
1498  * buffer.
1499  */
1500  wqe_idx = ( qib7322_wq->eager_cons & ( wq->num_wqes - 1 ) );
1501  iobuf = wq->iobufs[wqe_idx];
1502  assert ( iobuf != NULL );
1503  wq->iobufs[wqe_idx] = NULL;
1504 
1505  /* Complete the eager buffer */
1506  if ( qib7322_wq->eager_cons == egrindex ) {
1507  /* Completing the eager buffer described in
1508  * this header entry.
1509  */
1510  if ( payload_len <= iob_tailroom ( iobuf ) ) {
1511  iob_put ( iobuf, payload_len );
1512  rc = ( err ?
1513  -EIO : ( useegrbfr ? 0 : -ECANCELED ) );
1514  } else {
1515  DBGC ( qib7322, "QIB7322 %p bad payload len "
1516  "%zd\n", qib7322, payload_len );
1517  rc = -EPROTO;
1518  }
1519  /* Redirect to target QP if necessary */
1520  if ( qp != intended_qp ) {
1521  DBGC2 ( qib7322, "QIB7322 %p redirecting QPN "
1522  "%ld => %ld\n",
1523  qib7322, qp->qpn, intended_qp->qpn );
1524  /* Compensate for incorrect fill levels */
1525  qp->recv.fill--;
1526  intended_qp->recv.fill++;
1527  }
1528  ib_complete_recv ( ibdev, intended_qp, &dest, &source,
1529  iobuf, rc );
1530  } else {
1531  /* Completing on a skipped-over eager buffer */
1532  ib_complete_recv ( ibdev, qp, &dest, &source, iobuf,
1533  -ECANCELED );
1534  }
1535 
1536  /* Clear eager buffer */
1537  memset ( &rcvegr, 0, sizeof ( rcvegr ) );
1538  qib7322_writeq_array8b ( qib7322, &rcvegr,
1539  qib7322_wq->eager_array,
1540  qib7322_wq->eager_cons );
1541 
1542  /* Increment consumer index */
1543  qib7322_wq->eager_cons = ( ( qib7322_wq->eager_cons + 1 ) &
1544  ( qib7322_wq->eager_entries - 1 ) );
1545  }
1546 }
1547 
1548 /**
1549  * Poll receive work queue
1550  *
1551  * @v ibdev Infiniband device
1552  * @v qp Queue pair
1553  */
1554 static void qib7322_poll_recv_wq ( struct ib_device *ibdev,
1555  struct ib_queue_pair *qp ) {
1556  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1557  struct ib_work_queue *wq = &qp->recv;
1558  struct qib7322_recv_work_queue *qib7322_wq = ib_wq_get_drvdata ( wq );
1559  struct QIB_7322_RcvHdrHead0 rcvhdrhead;
1560  unsigned int ctx = qib7322_ctx ( ibdev, qp );
1561  unsigned int header_prod;
1562 
1563  /* Check for received packets */
1564  header_prod = ( BIT_GET ( &qib7322_wq->header_prod, Value ) << 2 );
1565  if ( header_prod == qib7322_wq->header_cons )
1566  return;
1567 
1568  /* Process all received packets */
1569  while ( qib7322_wq->header_cons != header_prod ) {
1570 
1571  /* Complete the receive */
1572  qib7322_complete_recv ( ibdev, qp, qib7322_wq->header_cons );
1573 
1574  /* Increment the consumer offset */
1575  qib7322_wq->header_cons += QIB7322_RECV_HEADER_SIZE;
1576  qib7322_wq->header_cons %= QIB7322_RECV_HEADERS_SIZE;
1577 
1578  /* QIB7322 has only one send buffer per port for VL15,
1579  * which almost always leads to send buffer exhaustion
1580  * and dropped MADs. Mitigate this by refusing to
1581  * process more than one VL15 MAD per poll, which will
1582  * enforce interleaved TX/RX polls.
1583  */
1584  if ( qp->type == IB_QPT_SMI )
1585  break;
1586  }
1587 
1588  /* Update consumer offset */
1589  memset ( &rcvhdrhead, 0, sizeof ( rcvhdrhead ) );
1590  BIT_FILL_2 ( &rcvhdrhead,
1591  RcvHeadPointer, ( qib7322_wq->header_cons >> 2 ),
1592  counter, 1 );
1593  qib7322_writeq_array64k ( qib7322, &rcvhdrhead,
1594  QIB_7322_RcvHdrHead0_offset, ctx );
1595 }
1596 
1597 /**
1598  * Poll completion queue
1599  *
1600  * @v ibdev Infiniband device
1601  * @v cq Completion queue
1602  */
1603 static void qib7322_poll_cq ( struct ib_device *ibdev,
1604  struct ib_completion_queue *cq ) {
1605  struct ib_work_queue *wq;
1606 
1607  /* Poll associated send and receive queues */
1608  list_for_each_entry ( wq, &cq->work_queues, list ) {
1609  if ( wq->is_send ) {
1610  qib7322_poll_send_wq ( ibdev, wq->qp );
1611  } else {
1612  qib7322_poll_recv_wq ( ibdev, wq->qp );
1613  }
1614  }
1615 }
1616 
1617 /***************************************************************************
1618  *
1619  * Event queues
1620  *
1621  ***************************************************************************
1622  */
1623 
1624 /**
1625  * Poll event queue
1626  *
1627  * @v ibdev Infiniband device
1628  */
1629 static void qib7322_poll_eq ( struct ib_device *ibdev ) {
1630  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1631  struct QIB_7322_ErrStatus_0 errstatus;
1632  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1633 
1634  /* Check for and clear status bits */
1635  DBG_DISABLE ( DBGLVL_IO );
1636  qib7322_readq_port ( qib7322, &errstatus,
1637  QIB_7322_ErrStatus_0_offset, port );
1638  if ( errstatus.u.qwords[0] ) {
1639  DBGC ( qib7322, "QIB7322 %p port %d status %08x%08x\n", qib7322,
1640  port, errstatus.u.dwords[1], errstatus.u.dwords[0] );
1641  qib7322_writeq_port ( qib7322, &errstatus,
1642  QIB_7322_ErrClear_0_offset, port );
1643  }
1644  DBG_ENABLE ( DBGLVL_IO );
1645 
1646  /* Check for link status changes */
1647  if ( BIT_GET ( &errstatus, IBStatusChanged ) )
1648  qib7322_link_state_changed ( ibdev );
1649 }
1650 
1651 /***************************************************************************
1652  *
1653  * Infiniband link-layer operations
1654  *
1655  ***************************************************************************
1656  */
1657 
1658 /**
1659  * Determine supported link speeds
1660  *
1661  * @v qib7322 QIB7322 device
1662  * @ret supported Supported link speeds
1663  */
1664 static unsigned int qib7322_link_speed_supported ( struct qib7322 *qib7322,
1665  unsigned int port ) {
1666  struct QIB_7322_feature_mask features;
1667  struct QIB_7322_Revision revision;
1668  unsigned int supported;
1669  unsigned int boardid;
1670 
1671  /* Read the active feature mask */
1672  qib7322_readq ( qib7322, &features,
1673  QIB_7322_active_feature_mask_offset );
1674  switch ( port ) {
1675  case 0 :
1676  supported = BIT_GET ( &features, Port0_Link_Speed_Supported );
1677  break;
1678  case 1 :
1679  supported = BIT_GET ( &features, Port1_Link_Speed_Supported );
1680  break;
1681  default:
1682  DBGC ( qib7322, "QIB7322 %p port %d is invalid\n",
1683  qib7322, port );
1684  supported = 0;
1685  break;
1686  }
1687 
1688  /* Apply hacks for specific board IDs */
1689  qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
1690  boardid = BIT_GET ( &revision, BoardID );
1691  switch ( boardid ) {
1692  case QIB7322_BOARD_QMH7342 :
1693  DBGC2 ( qib7322, "QIB7322 %p is a QMH7342; forcing QDR-only\n",
1694  qib7322 );
1695  supported = IB_LINK_SPEED_QDR;
1696  break;
1697  default:
1698  /* Do nothing */
1699  break;
1700  }
1701 
1702  DBGC2 ( qib7322, "QIB7322 %p port %d %s%s%s%s\n", qib7322, port,
1703  ( supported ? "supports" : "disabled" ),
1704  ( ( supported & IB_LINK_SPEED_SDR ) ? " SDR" : "" ),
1705  ( ( supported & IB_LINK_SPEED_DDR ) ? " DDR" : "" ),
1706  ( ( supported & IB_LINK_SPEED_QDR ) ? " QDR" : "" ) );
1707  return supported;
1708 }
1709 
1710 /**
1711  * Initialise Infiniband link
1712  *
1713  * @v ibdev Infiniband device
1714  * @ret rc Return status code
1715  */
1716 static int qib7322_open ( struct ib_device *ibdev ) {
1717  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1718  struct QIB_7322_IBCCtrlA_0 ibcctrla;
1719  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1720 
1721  /* Enable link */
1722  qib7322_readq_port ( qib7322, &ibcctrla,
1723  QIB_7322_IBCCtrlA_0_offset, port );
1724  BIT_SET ( &ibcctrla, IBLinkEn, 1 );
1725  qib7322_writeq_port ( qib7322, &ibcctrla,
1726  QIB_7322_IBCCtrlA_0_offset, port );
1727 
1728  return 0;
1729 }
1730 
1731 /**
1732  * Close Infiniband link
1733  *
1734  * @v ibdev Infiniband device
1735  */
1736 static void qib7322_close ( struct ib_device *ibdev ) {
1737  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1738  struct QIB_7322_IBCCtrlA_0 ibcctrla;
1739  unsigned int port = ( ibdev->port - QIB7322_PORT_BASE );
1740 
1741  /* Disable link */
1742  qib7322_readq_port ( qib7322, &ibcctrla,
1743  QIB_7322_IBCCtrlA_0_offset, port );
1744  BIT_SET ( &ibcctrla, IBLinkEn, 0 );
1745  qib7322_writeq_port ( qib7322, &ibcctrla,
1746  QIB_7322_IBCCtrlA_0_offset, port );
1747 }
1748 
1749 /***************************************************************************
1750  *
1751  * Multicast group operations
1752  *
1753  ***************************************************************************
1754  */
1755 
1756 /**
1757  * Attach to multicast group
1758  *
1759  * @v ibdev Infiniband device
1760  * @v qp Queue pair
1761  * @v gid Multicast GID
1762  * @ret rc Return status code
1763  */
1764 static int qib7322_mcast_attach ( struct ib_device *ibdev,
1765  struct ib_queue_pair *qp,
1766  union ib_gid *gid ) {
1767  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1768 
1769  ( void ) qib7322;
1770  ( void ) qp;
1771  ( void ) gid;
1772  return 0;
1773 }
1774 
1775 /**
1776  * Detach from multicast group
1777  *
1778  * @v ibdev Infiniband device
1779  * @v qp Queue pair
1780  * @v gid Multicast GID
1781  */
1782 static void qib7322_mcast_detach ( struct ib_device *ibdev,
1783  struct ib_queue_pair *qp,
1784  union ib_gid *gid ) {
1785  struct qib7322 *qib7322 = ib_get_drvdata ( ibdev );
1786 
1787  ( void ) qib7322;
1788  ( void ) qp;
1789  ( void ) gid;
1790  }
1791 
1792 /** QIB7322 Infiniband operations */
1793 static struct ib_device_operations qib7322_ib_operations = {
1794  .create_cq = qib7322_create_cq,
1795  .destroy_cq = qib7322_destroy_cq,
1796  .create_qp = qib7322_create_qp,
1797  .modify_qp = qib7322_modify_qp,
1798  .destroy_qp = qib7322_destroy_qp,
1799  .post_send = qib7322_post_send,
1800  .post_recv = qib7322_post_recv,
1801  .poll_cq = qib7322_poll_cq,
1802  .poll_eq = qib7322_poll_eq,
1803  .open = qib7322_open,
1804  .close = qib7322_close,
1805  .mcast_attach = qib7322_mcast_attach,
1806  .mcast_detach = qib7322_mcast_detach,
1807  .set_port_info = qib7322_set_port_info,
1808  .set_pkey_table = qib7322_set_pkey_table,
1809 };
1810 
1811 /***************************************************************************
1812  *
1813  * I2C bus operations
1814  *
1815  ***************************************************************************
1816  */
1817 
1818 /** QIB7322 I2C bit to GPIO mappings */
1819 static unsigned int qib7322_i2c_bits[] = {
1820  [I2C_BIT_SCL] = ( 1 << QIB7322_GPIO_SCL ),
1821  [I2C_BIT_SDA] = ( 1 << QIB7322_GPIO_SDA ),
1822 };
1823 
1824 /**
1825  * Read QIB7322 I2C line status
1826  *
1827  * @v basher Bit-bashing interface
1828  * @v bit_id Bit number
1829  * @ret zero Input is a logic 0
1830  * @ret non-zero Input is a logic 1
1831  */
1832 static int qib7322_i2c_read_bit ( struct bit_basher *basher,
1833  unsigned int bit_id ) {
1834  struct qib7322 *qib7322 =
1835  container_of ( basher, struct qib7322, i2c.basher );
1836  struct QIB_7322_EXTStatus extstatus;
1837  unsigned int status;
1838 
1839  DBG_DISABLE ( DBGLVL_IO );
1840 
1841  qib7322_readq ( qib7322, &extstatus, QIB_7322_EXTStatus_offset );
1842  status = ( BIT_GET ( &extstatus, GPIOIn ) & qib7322_i2c_bits[bit_id] );
1843 
1844  DBG_ENABLE ( DBGLVL_IO );
1845 
1846  return status;
1847 }
1848 
1849 /**
1850  * Write QIB7322 I2C line status
1851  *
1852  * @v basher Bit-bashing interface
1853  * @v bit_id Bit number
1854  * @v data Value to write
1855  */
1856 static void qib7322_i2c_write_bit ( struct bit_basher *basher,
1857  unsigned int bit_id, unsigned long data ) {
1858  struct qib7322 *qib7322 =
1859  container_of ( basher, struct qib7322, i2c.basher );
1860  struct QIB_7322_EXTCtrl extctrl;
1861  struct QIB_7322_GPIO gpioout;
1862  unsigned int bit = qib7322_i2c_bits[bit_id];
1863  unsigned int outputs = 0;
1864  unsigned int output_enables = 0;
1865 
1866  DBG_DISABLE ( DBGLVL_IO );
1867 
1868  /* Read current GPIO mask and outputs */
1869  qib7322_readq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1870  qib7322_readq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1871 
1872  /* Update outputs and output enables. I2C lines are tied
1873  * high, so we always set the output to 0 and use the output
1874  * enable to control the line.
1875  */
1876  output_enables = BIT_GET ( &extctrl, GPIOOe );
1877  output_enables = ( ( output_enables & ~bit ) | ( ~data & bit ) );
1878  outputs = BIT_GET ( &gpioout, GPIO );
1879  outputs = ( outputs & ~bit );
1880  BIT_SET ( &extctrl, GPIOOe, output_enables );
1881  BIT_SET ( &gpioout, GPIO, outputs );
1882 
1883  /* Write the output enable first; that way we avoid logic
1884  * hazards.
1885  */
1886  qib7322_writeq ( qib7322, &extctrl, QIB_7322_EXTCtrl_offset );
1887  qib7322_writeq ( qib7322, &gpioout, QIB_7322_GPIOOut_offset );
1888  mb();
1889 
1890  DBG_ENABLE ( DBGLVL_IO );
1891 }
1892 
1893 /** QIB7322 I2C bit-bashing interface operations */
1894 static struct bit_basher_operations qib7322_i2c_basher_ops = {
1895  .read = qib7322_i2c_read_bit,
1896  .write = qib7322_i2c_write_bit,
1897 };
1898 
1899 /**
1900  * Initialise QIB7322 I2C subsystem
1901  *
1902  * @v qib7322 QIB7322 device
1903  * @ret rc Return status code
1904  */
1905 static int qib7322_init_i2c ( struct qib7322 *qib7322 ) {
1906  static int try_eeprom_address[] = { 0x51, 0x50 };
1907  unsigned int i;
1908  int rc;
1909 
1910  /* Initialise bus */
1911  if ( ( rc = init_i2c_bit_basher ( &qib7322->i2c,
1912  &qib7322_i2c_basher_ops ) ) != 0 ) {
1913  DBGC ( qib7322, "QIB7322 %p could not initialise I2C bus: %s\n",
1914  qib7322, strerror ( rc ) );
1915  return rc;
1916  }
1917 
1918  /* Probe for devices */
1919  for ( i = 0 ; i < ( sizeof ( try_eeprom_address ) /
1920  sizeof ( try_eeprom_address[0] ) ) ; i++ ) {
1921  init_i2c_eeprom ( &qib7322->eeprom, try_eeprom_address[i] );
1922  if ( ( rc = i2c_check_presence ( &qib7322->i2c.i2c,
1923  &qib7322->eeprom ) ) == 0 ) {
1924  DBGC2 ( qib7322, "QIB7322 %p found EEPROM at %02x\n",
1925  qib7322, try_eeprom_address[i] );
1926  return 0;
1927  }
1928  }
1929 
1930  DBGC ( qib7322, "QIB7322 %p could not find EEPROM\n", qib7322 );
1931  return -ENODEV;
1932 }
1933 
1934 /**
1935  * Read EEPROM parameters
1936  *
1937  * @v qib7322 QIB7322 device
1938  * @ret rc Return status code
1939  */
1940 static int qib7322_read_eeprom ( struct qib7322 *qib7322 ) {
1941  struct i2c_interface *i2c = &qib7322->i2c.i2c;
1942  union ib_guid *guid = &qib7322->guid;
1943  int rc;
1944 
1945  /* Read GUID */
1946  if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1947  QIB7322_EEPROM_GUID_OFFSET, guid->bytes,
1948  sizeof ( *guid ) ) ) != 0 ) {
1949  DBGC ( qib7322, "QIB7322 %p could not read GUID: %s\n",
1950  qib7322, strerror ( rc ) );
1951  return rc;
1952  }
1953  DBGC2 ( qib7322, "QIB7322 %p has GUID " IB_GUID_FMT "\n",
1954  qib7322, IB_GUID_ARGS ( guid ) );
1955 
1956  /* Read serial number (debug only) */
1957  if ( DBG_LOG ) {
1958  uint8_t serial[QIB7322_EEPROM_SERIAL_SIZE + 1];
1959 
1960  serial[ sizeof ( serial ) - 1 ] = '\0';
1961  if ( ( rc = i2c->read ( i2c, &qib7322->eeprom,
1962  QIB7322_EEPROM_SERIAL_OFFSET, serial,
1963  ( sizeof ( serial ) - 1 ) ) ) != 0 ) {
1964  DBGC ( qib7322, "QIB7322 %p could not read serial: "
1965  "%s\n", qib7322, strerror ( rc ) );
1966  return rc;
1967  }
1968  DBGC2 ( qib7322, "QIB7322 %p has serial number \"%s\"\n",
1969  qib7322, serial );
1970  }
1971 
1972  return 0;
1973 }
1974 
1975 /***************************************************************************
1976  *
1977  * Advanced High-performance Bus (AHB) access
1978  *
1979  ***************************************************************************
1980  */
1981 
1982 /**
1983  * Wait for AHB transaction to complete
1984  *
1985  * @v qib7322 QIB7322 device
1986  * @ret rc Return status code
1987  */
1988 static int qib7322_ahb_wait ( struct qib7322 *qib7322 ) {
1989  struct QIB_7322_ahb_transaction_reg transaction;
1990  unsigned int i;
1991 
1992  /* Wait for Ready bit to be asserted */
1993  for ( i = 0 ; i < QIB7322_AHB_MAX_WAIT_US ; i++ ) {
1994  qib7322_readq ( qib7322, &transaction,
1995  QIB_7322_ahb_transaction_reg_offset );
1996  if ( BIT_GET ( &transaction, ahb_rdy ) )
1997  return 0;
1998  udelay ( 1 );
1999  }
2000 
2001  DBGC ( qib7322, "QIB7322 %p timed out waiting for AHB transaction\n",
2002  qib7322 );
2003  return -ETIMEDOUT;
2004 }
2005 
2006 /**
2007  * Request ownership of the AHB
2008  *
2009  * @v qib7322 QIB7322 device
2010  * @v location AHB location
2011  * @ret rc Return status code
2012  */
2013 static int qib7322_ahb_request ( struct qib7322 *qib7322,
2014  unsigned int location ) {
2015  struct QIB_7322_ahb_access_ctrl access;
2016  int rc;
2017 
2018  /* Request ownership */
2019  memset ( &access, 0, sizeof ( access ) );
2020  BIT_FILL_2 ( &access,
2021  sw_ahb_sel, 1,
2022  sw_sel_ahb_trgt, QIB7322_AHB_LOC_TARGET ( location ) );
2023  qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2024 
2025  /* Wait for ownership to be granted */
2026  if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 ) {
2027  DBGC ( qib7322, "QIB7322 %p could not obtain AHB ownership: "
2028  "%s\n", qib7322, strerror ( rc ) );
2029  return rc;
2030  }
2031 
2032  return 0;
2033 }
2034 
2035 /**
2036  * Release ownership of the AHB
2037  *
2038  * @v qib7322 QIB7322 device
2039  */
2040 static void qib7322_ahb_release ( struct qib7322 *qib7322 ) {
2041  struct QIB_7322_ahb_access_ctrl access;
2042 
2043  memset ( &access, 0, sizeof ( access ) );
2044  qib7322_writeq ( qib7322, &access, QIB_7322_ahb_access_ctrl_offset );
2045 }
2046 
2047 /**
2048  * Read data via AHB
2049  *
2050  * @v qib7322 QIB7322 device
2051  * @v location AHB location
2052  * @v data Data to read
2053  * @ret rc Return status code
2054  *
2055  * You must have already acquired ownership of the AHB.
2056  */
2057 static int qib7322_ahb_read ( struct qib7322 *qib7322, unsigned int location,
2058  uint32_t *data ) {
2059  struct QIB_7322_ahb_transaction_reg xact;
2060  int rc;
2061 
2062  /* Avoid returning uninitialised data on error */
2063  *data = 0;
2064 
2065  /* Initiate transaction */
2066  memset ( &xact, 0, sizeof ( xact ) );
2067  BIT_FILL_2 ( &xact,
2068  ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2069  write_not_read, 0 );
2070  qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2071 
2072  /* Wait for transaction to complete */
2073  if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2074  return rc;
2075 
2076  /* Read transaction data */
2077  qib7322_readq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2078  *data = BIT_GET ( &xact, ahb_data );
2079  return 0;
2080 }
2081 
2082 /**
2083  * Write data via AHB
2084  *
2085  * @v qib7322 QIB7322 device
2086  * @v location AHB location
2087  * @v data Data to write
2088  * @ret rc Return status code
2089  *
2090  * You must have already acquired ownership of the AHB.
2091  */
2092 static int qib7322_ahb_write ( struct qib7322 *qib7322, unsigned int location,
2093  uint32_t data ) {
2094  struct QIB_7322_ahb_transaction_reg xact;
2095  int rc;
2096 
2097  /* Initiate transaction */
2098  memset ( &xact, 0, sizeof ( xact ) );
2099  BIT_FILL_3 ( &xact,
2100  ahb_address, QIB7322_AHB_LOC_ADDRESS ( location ),
2101  write_not_read, 1,
2102  ahb_data, data );
2103  qib7322_writeq ( qib7322, &xact, QIB_7322_ahb_transaction_reg_offset );
2104 
2105  /* Wait for transaction to complete */
2106  if ( ( rc = qib7322_ahb_wait ( qib7322 ) ) != 0 )
2107  return rc;
2108 
2109  return 0;
2110 }
2111 
2112 /**
2113  * Read/modify/write AHB register
2114  *
2115  * @v qib7322 QIB7322 device
2116  * @v location AHB location
2117  * @v value Value to set
2118  * @v mask Mask to apply to old value
2119  * @ret rc Return status code
2120  */
2121 static int qib7322_ahb_mod_reg ( struct qib7322 *qib7322, unsigned int location,
2122  uint32_t value, uint32_t mask ) {
2123  uint32_t old_value;
2124  uint32_t new_value;
2125  int rc;
2126 
2127  DBG_DISABLE ( DBGLVL_IO );
2128 
2129  /* Sanity check */
2130  assert ( ( value & mask ) == value );
2131 
2132  /* Acquire bus ownership */
2133  if ( ( rc = qib7322_ahb_request ( qib7322, location ) ) != 0 )
2134  goto out;
2135 
2136  /* Read existing value */
2137  if ( ( rc = qib7322_ahb_read ( qib7322, location, &old_value ) ) != 0 )
2138  goto out_release;
2139 
2140  /* Update value */
2141  new_value = ( ( old_value & ~mask ) | value );
2142  DBGCP ( qib7322, "QIB7322 %p AHB %x %#08x => %#08x\n",
2143  qib7322, location, old_value, new_value );
2144  if ( ( rc = qib7322_ahb_write ( qib7322, location, new_value ) ) != 0 )
2145  goto out_release;
2146 
2147  out_release:
2148  /* Release bus */
2149  qib7322_ahb_release ( qib7322 );
2150  out:
2151  DBG_ENABLE ( DBGLVL_IO );
2152  return rc;
2153 }
2154 
2155 /**
2156  * Read/modify/write AHB register across all ports and channels
2157  *
2158  * @v qib7322 QIB7322 device
2159  * @v reg AHB register
2160  * @v value Value to set
2161  * @v mask Mask to apply to old value
2162  * @ret rc Return status code
2163  */
2164 static int qib7322_ahb_mod_reg_all ( struct qib7322 *qib7322, unsigned int reg,
2165  uint32_t value, uint32_t mask ) {
2166  unsigned int port;
2167  unsigned int channel;
2168  unsigned int location;
2169  int rc;
2170 
2171  for ( port = 0 ; port < QIB7322_MAX_PORTS ; port++ ) {
2172  for ( channel = 0 ; channel < QIB7322_MAX_WIDTH ; channel++ ) {
2173  location = QIB7322_AHB_LOCATION ( port, channel, reg );
2174  if ( ( rc = qib7322_ahb_mod_reg ( qib7322, location,
2175  value, mask ) ) != 0 )
2176  return rc;
2177  }
2178  }
2179  return 0;
2180 }
2181 
2182 /***************************************************************************
2183  *
2184  * Infiniband SerDes initialisation
2185  *
2186  ***************************************************************************
2187  */
2188 
2189 /**
2190  * Initialise the IB SerDes
2191  *
2192  * @v qib7322 QIB7322 device
2193  * @ret rc Return status code
2194  */
2195 static int qib7322_init_ib_serdes ( struct qib7322 *qib7322 ) {
2196  struct QIB_7322_IBCCtrlA_0 ibcctrla;
2197  struct QIB_7322_IBCCtrlB_0 ibcctrlb;
2198  struct QIB_7322_IBPCSConfig_0 ibpcsconfig;
2199 
2200  /* Configure sensible defaults for IBC */
2201  memset ( &ibcctrla, 0, sizeof ( ibcctrla ) );
2202  BIT_FILL_5 ( &ibcctrla, /* Tuning values taken from Linux driver */
2203  FlowCtrlPeriod, 0x03,
2204  FlowCtrlWaterMark, 0x05,
2205  MaxPktLen, ( ( QIB7322_RECV_HEADER_SIZE +
2206  QIB7322_RECV_PAYLOAD_SIZE +
2207  4 /* ICRC */ ) >> 2 ),
2208  PhyerrThreshold, 0xf,
2209  OverrunThreshold, 0xf );
2210  qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_0_offset );
2211  qib7322_writeq ( qib7322, &ibcctrla, QIB_7322_IBCCtrlA_1_offset );
2212 
2213  /* Force SDR only to avoid needing all the DDR tuning,
2214  * Mellanox compatibility hacks etc. SDR is plenty for
2215  * boot-time operation.
2216  */
2217  qib7322_readq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2218  BIT_SET ( &ibcctrlb, IB_ENHANCED_MODE, 0 );
2219  BIT_SET ( &ibcctrlb, SD_SPEED_SDR, 1 );
2220  BIT_SET ( &ibcctrlb, SD_SPEED_DDR, 0 );
2221  BIT_SET ( &ibcctrlb, SD_SPEED_QDR, 0 );
2222  BIT_SET ( &ibcctrlb, IB_NUM_CHANNELS, 1 ); /* 4X only */
2223  BIT_SET ( &ibcctrlb, IB_LANE_REV_SUPPORTED, 0 );
2224  BIT_SET ( &ibcctrlb, HRTBT_ENB, 0 );
2225  BIT_SET ( &ibcctrlb, HRTBT_AUTO, 0 );
2226  qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_0_offset );
2227  qib7322_writeq ( qib7322, &ibcctrlb, QIB_7322_IBCCtrlB_1_offset );
2228 
2229  /* Tune SerDes */
2230  qib7322_ahb_mod_reg_all ( qib7322, 2, 0, 0x00000e00UL );
2231 
2232  /* Bring XGXS out of reset */
2233  memset ( &ibpcsconfig, 0, sizeof ( ibpcsconfig ) );
2234  qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_0_offset );
2235  qib7322_writeq ( qib7322, &ibpcsconfig, QIB_7322_IBPCSConfig_1_offset );
2236 
2237  return 0;
2238 }
2239 
2240 /***************************************************************************
2241  *
2242  * PCI layer interface
2243  *
2244  ***************************************************************************
2245  */
2246 
2247 /**
2248  * Reset QIB7322
2249  *
2250  * @v qib7322 QIB7322 device
2251  * @v pci PCI device
2252  * @ret rc Return status code
2253  */
2254 static void qib7322_reset ( struct qib7322 *qib7322, struct pci_device *pci ) {
2255  struct QIB_7322_Control control;
2256  struct pci_config_backup backup;
2257 
2258  /* Back up PCI configuration space */
2259  pci_backup ( pci, &backup, PCI_CONFIG_BACKUP_ALL, NULL );
2260 
2261  /* Assert reset */
2262  memset ( &control, 0, sizeof ( control ) );
2263  BIT_FILL_1 ( &control, SyncReset, 1 );
2264  qib7322_writeq ( qib7322, &control, QIB_7322_Control_offset );
2265 
2266  /* Wait for reset to complete */
2267  mdelay ( 1000 );
2268 
2269  /* Restore PCI configuration space */
2270  pci_restore ( pci, &backup, PCI_CONFIG_BACKUP_ALL, NULL );
2271 }
2272 
2273 /**
2274  * Probe PCI device
2275  *
2276  * @v pci PCI device
2277  * @v id PCI ID
2278  * @ret rc Return status code
2279  */
2280 static int qib7322_probe ( struct pci_device *pci ) {
2281  struct qib7322 *qib7322;
2282  struct QIB_7322_Revision revision;
2283  struct ib_device *ibdev;
2284  unsigned int link_speed_supported;
2285  int i;
2286  int rc;
2287 
2288  /* Allocate QIB7322 device */
2289  qib7322 = zalloc ( sizeof ( *qib7322 ) );
2290  if ( ! qib7322 ) {
2291  rc = -ENOMEM;
2292  goto err_alloc_qib7322;
2293  }
2294  pci_set_drvdata ( pci, qib7322 );
2295 
2296  /* Fix up PCI device */
2297  adjust_pci_device ( pci );
2298 
2299  /* Map PCI BARs */
2300  qib7322->regs = pci_ioremap ( pci, pci->membase, QIB7322_BAR0_SIZE );
2301  DBGC2 ( qib7322, "QIB7322 %p has BAR at %08lx\n",
2302  qib7322, pci->membase );
2303 
2304  /* Reset device */
2305  qib7322_reset ( qib7322, pci );
2306 
2307  /* Print some general data */
2308  qib7322_readq ( qib7322, &revision, QIB_7322_Revision_offset );
2309  DBGC2 ( qib7322, "QIB7322 %p board %02lx v%ld.%ld.%ld.%ld\n", qib7322,
2310  BIT_GET ( &revision, BoardID ),
2311  BIT_GET ( &revision, R_SW ),
2312  BIT_GET ( &revision, R_Arch ),
2313  BIT_GET ( &revision, R_ChipRevMajor ),
2314  BIT_GET ( &revision, R_ChipRevMinor ) );
2315 
2316  /* Initialise I2C subsystem */
2317  if ( ( rc = qib7322_init_i2c ( qib7322 ) ) != 0 )
2318  goto err_init_i2c;
2319 
2320  /* Read EEPROM parameters */
2321  if ( ( rc = qib7322_read_eeprom ( qib7322 ) ) != 0 )
2322  goto err_read_eeprom;
2323 
2324  /* Initialise send datapath */
2325  if ( ( rc = qib7322_init_send ( qib7322 ) ) != 0 )
2326  goto err_init_send;
2327 
2328  /* Initialise receive datapath */
2329  if ( ( rc = qib7322_init_recv ( qib7322 ) ) != 0 )
2330  goto err_init_recv;
2331 
2332  /* Initialise the IB SerDes */
2333  if ( ( rc = qib7322_init_ib_serdes ( qib7322 ) ) != 0 )
2334  goto err_init_ib_serdes;
2335 
2336  /* Allocate Infiniband devices */
2337  for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2338  link_speed_supported =
2339  qib7322_link_speed_supported ( qib7322, i );
2340  if ( ! link_speed_supported )
2341  continue;
2342  ibdev = alloc_ibdev ( 0 );
2343  if ( ! ibdev ) {
2344  rc = -ENOMEM;
2345  goto err_alloc_ibdev;
2346  }
2347  qib7322->ibdev[i] = ibdev;
2348  ibdev->dev = &pci->dev;
2349  ibdev->op = &qib7322_ib_operations;
2350  ibdev->port = ( QIB7322_PORT_BASE + i );
2351  ibdev->ports = QIB7322_MAX_PORTS;
2352  ibdev->link_width_enabled = ibdev->link_width_supported =
2353  IB_LINK_WIDTH_4X; /* 1x does not work */
2354  ibdev->link_speed_enabled = ibdev->link_speed_supported =
2355  IB_LINK_SPEED_SDR; /* to avoid need for link tuning */
2356  memcpy ( &ibdev->node_guid, &qib7322->guid,
2357  sizeof ( ibdev->node_guid ) );
2358  memcpy ( &ibdev->gid.s.guid, &qib7322->guid,
2359  sizeof ( ibdev->gid.s.guid ) );
2360  assert ( ( ibdev->gid.s.guid.bytes[7] & i ) == 0 );
2361  ibdev->gid.s.guid.bytes[7] |= i;
2362  ib_set_drvdata ( ibdev, qib7322 );
2363  }
2364 
2365  /* Register Infiniband devices */
2366  for ( i = 0 ; i < QIB7322_MAX_PORTS ; i++ ) {
2367  if ( ! qib7322->ibdev[i] )
2368  continue;
2369  if ( ( rc = register_ibdev ( qib7322->ibdev[i] ) ) != 0 ) {
2370  DBGC ( qib7322, "QIB7322 %p port %d could not register "
2371  "IB device: %s\n", qib7322, i, strerror ( rc ) );
2372  goto err_register_ibdev;
2373  }
2374  }
2375 
2376  return 0;
2377 
2378  i = QIB7322_MAX_PORTS;
2379  err_register_ibdev:
2380  for ( i-- ; i >= 0 ; i-- ) {
2381  if ( qib7322->ibdev[i] )
2382  unregister_ibdev ( qib7322->ibdev[i] );
2383  }
2384  i = QIB7322_MAX_PORTS;
2385  err_alloc_ibdev:
2386  for ( i-- ; i >= 0 ; i-- )
2387  ibdev_put ( qib7322->ibdev[i] );
2388  err_init_ib_serdes:
2389  qib7322_fini_send ( qib7322 );
2390  err_init_send:
2391  qib7322_fini_recv ( qib7322 );
2392  err_init_recv:
2393  err_read_eeprom:
2394  err_init_i2c:
2395  iounmap ( qib7322->regs );
2396  free ( qib7322 );
2397  err_alloc_qib7322:
2398  return rc;
2399 }
2400 
2401 /**
2402  * Remove PCI device
2403  *
2404  * @v pci PCI device
2405  */
2406 static void qib7322_remove ( struct pci_device *pci ) {
2407  struct qib7322 *qib7322 = pci_get_drvdata ( pci );
2408  int i;
2409 
2410  for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- ) {
2411  if ( qib7322->ibdev[i] )
2412  unregister_ibdev ( qib7322->ibdev[i] );
2413  }
2414  for ( i = ( QIB7322_MAX_PORTS - 1 ) ; i >= 0 ; i-- )
2415  ibdev_put ( qib7322->ibdev[i] );
2416  qib7322_fini_send ( qib7322 );
2417  qib7322_fini_recv ( qib7322 );
2418  iounmap ( qib7322->regs );
2419  free ( qib7322 );
2420 }
2421 
2422 static struct pci_device_id qib7322_nics[] = {
2423  PCI_ROM ( 0x1077, 0x7322, "iba7322", "IBA7322 QDR InfiniBand HCA", 0 ),
2424 };
2425 
2426 struct pci_driver qib7322_driver __pci_driver = {
2427  .ids = qib7322_nics,
2428  .id_count = ( sizeof ( qib7322_nics ) / sizeof ( qib7322_nics[0] ) ),
2429  .probe = qib7322_probe,
2430  .remove = qib7322_remove,
2431 };
unregister_ibdev
void unregister_ibdev(struct ib_device *ibdev)
Unregister Infiniband device.
Definition: infiniband.c:985
qib7322_ahb_mod_reg_all
static int qib7322_ahb_mod_reg_all(struct qib7322 *qib7322, unsigned int reg, uint32_t value, uint32_t mask)
Read/modify/write AHB register across all ports and channels.
Definition: qib7322.c:2164
QIB_7322_ahb_access_ctrl_offset
#define QIB_7322_ahb_access_ctrl_offset
Definition: qib_7322_regs.h:938
qib7322_complete_recv
static void qib7322_complete_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, unsigned int header_offs)
Complete receive work queue entry.
Definition: qib7322.c:1391
qib7322_i2c_read_bit
static int qib7322_i2c_read_bit(struct bit_basher *basher, unsigned int bit_id)
Read QIB7322 I2C line status.
Definition: qib7322.c:1832
base
uint32_t base
Base.
Definition: librm.h:252
EINVAL
#define EINVAL
Invalid argument.
Definition: errno.h:428
ib_set_drvdata
static __always_inline void ib_set_drvdata(struct ib_device *ibdev, void *priv)
Set Infiniband device driver-private data.
Definition: infiniband.h:697
pci_device::membase
unsigned long membase
Memory base.
Definition: pci.h:215
io.h
iPXE I/O API
rc
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
QIB_7322_RcvHdrAddr0
Definition: qib_7322_regs.h:823
QIB_7322_RcvCtrl_0
Definition: qib_7322_regs.h:2724
infiniband.h
Infiniband protocol.
pci_restore
void pci_restore(struct pci_device *pci, struct pci_config_backup *backup, unsigned int limit, const uint8_t *exclude)
Restore PCI configuration space.
Definition: pcibackup.c:87
uint16_t
unsigned short uint16_t
Definition: stdint.h:11
QIB7322_MAX_CREDITS_VL0
#define QIB7322_MAX_CREDITS_VL0
Number of credits to advertise for VL0.
Definition: qib7322.h:326
QIB_7322_RcvCtrl_1_offset
#define QIB_7322_RcvCtrl_1_offset
Definition: qib_7322_regs.h:4045
BIT_FILL_5
#define BIT_FILL_5(_ptr, _field1,...)
Definition: pseudobit.h:205
qib7322_send_buffers::start
unsigned int start
Index of first send buffer.
Definition: qib7322.c:55
iob_put
#define iob_put(iobuf, len)
Definition: iobuf.h:120
BIT_FILL_6
#define BIT_FILL_6(_ptr, _field1,...)
Definition: pseudobit.h:210
QIB_7322_RcvCtrl_offset
#define QIB_7322_RcvCtrl_offset
Definition: qib_7322_regs.h:651
QIB7322_EAGER_BUFFER_ALIGN
#define QIB7322_EAGER_BUFFER_ALIGN
Eager buffer required alignment.
Definition: qib7322.h:270
qib7322_recv_work_queue::header
void * header
Receive header ring.
Definition: qib7322.c:84
QIB7322_RECV_HEADERS_ALIGN
#define QIB7322_RECV_HEADERS_ALIGN
RX header alignment.
Definition: qib7322.h:300
qib7322_alloc_send_buf
static int qib7322_alloc_send_buf(struct qib7322 *qib7322, struct qib7322_send_buffers *send_bufs)
Allocate a send buffer.
Definition: qib7322.c:491
pci_driver
A PCI driver.
Definition: pci.h:247
DBGLVL_IO
#define DBGLVL_IO
Definition: compiler.h:322
QIB7322_SMALL_SEND_BUF_USED
#define QIB7322_SMALL_SEND_BUF_USED
Number of small send buffers used.
Definition: qib7322.h:246
ib_gid::guid
union ib_guid guid
Definition: ib_packet.h:40
ib_device::gid
union ib_gid gid
Port GID (comprising GID prefix and port GUID)
Definition: infiniband.h:441
reg
static unsigned int unsigned int reg
Definition: myson.h:162
ib_device_operations
Infiniband device operations.
Definition: infiniband.h:254
IB_LINK_SPEED_QDR
#define IB_LINK_SPEED_QDR
Definition: ib_mad.h:146
qib7322_ahb_mod_reg
static int qib7322_ahb_mod_reg(struct qib7322 *qib7322, unsigned int location, uint32_t value, uint32_t mask)
Read/modify/write AHB register.
Definition: qib7322.c:2121
qib7322_destroy_send_bufs
static void qib7322_destroy_send_bufs(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs)
Destroy send buffer set.
Definition: qib7322.c:479
QIB_7322_RcvQPMapTableB_1_offset
#define QIB_7322_RcvQPMapTableB_1_offset
Definition: qib_7322_regs.h:4087
qib7322_send_work_queue::used
uint16_t * used
Send buffer usage.
Definition: qib7322.c:74
QIB_7322_RxCreditVL0_0
Definition: qib_7322_regs.h:3040
QIB_7322_ErrClear_0_offset
#define QIB_7322_ErrClear_0_offset
Definition: qib_7322_regs.h:2637
qib7322_destroy_cq
static void qib7322_destroy_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Destroy completion queue.
Definition: qib7322.c:1062
qib7322_ib_operations
static struct ib_device_operations qib7322_ib_operations
QIB7322 Infiniband operations.
Definition: qib7322.c:1793
qib7322_poll_send_wq
static void qib7322_poll_send_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Poll send work queue.
Definition: qib7322.c:1279
errno.h
Error codes.
qib7322::used_ctx
uint8_t used_ctx[QIB7322_NUM_CONTEXTS]
In-use contexts.
Definition: qib7322.c:105
qib7322_writeq_port
#define qib7322_writeq_port(_qib7322, _ptr, _offset, _port)
Definition: qib7322.c:179
bit_basher_operations
Bit-bashing operations.
Definition: bitbash.h:15
QIB_7322_RcvCtrl_P
Definition: qib7322.h:109
QIB_7322_RcvCtrl
Definition: qib_7322_regs.h:663
readq
uint64_t readq(volatile uint64_t *io_addr)
Read 64-bit qword from memory-mapped device.
qib7322_send_work_queue
A QIB7322 send work queue.
Definition: qib7322.c:70
QIB7322_VL15_PORT1_SEND_BUF_COUNT
#define QIB7322_VL15_PORT1_SEND_BUF_COUNT
QIB7322 VL15 port 0 send buffer count.
Definition: qib7322.h:235
QIB_7322_SendBufBase_offset
#define QIB_7322_SendBufBase_offset
Definition: qib_7322_regs.h:745
qib7322_recv_work_queue::eager_cons
unsigned int eager_cons
Eager array consumer index.
Definition: qib7322.c:96
iobuf.h
I/O buffers.
qib7322_writeq_array8b
#define qib7322_writeq_array8b(_qib7322, _ptr, _offset, _idx)
Definition: qib7322.c:175
i2c_check_presence
static int i2c_check_presence(struct i2c_interface *i2c, struct i2c_device *i2cdev)
Check presence of I2C device.
Definition: i2c.h:135
DBG_ENABLE
#define DBG_ENABLE(level)
Definition: compiler.h:313
pci_driver::ids
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:249
QIB7322_AHB_MAX_WAIT_US
#define QIB7322_AHB_MAX_WAIT_US
Maximum time for wait for AHB, in us.
Definition: qib7322.h:337
qib7322_create_send_wq
static int qib7322_create_send_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create send work queue.
Definition: qib7322.c:572
QIB_7322_RcvHdrFlags
Definition: qib7322.h:145
size
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
qib7322_readq
#define qib7322_readq(_qib7322, _ptr, _offset)
Definition: qib7322.c:153
qib7322_send_work_queue::send_bufs
struct qib7322_send_buffers * send_bufs
Send buffer set.
Definition: qib7322.c:72
__pci_driver
struct pci_driver qib7322_driver __pci_driver
Definition: qib7322.c:2426
ib_pull
int ib_pull(struct ib_device *ibdev, struct io_buffer *iobuf, struct ib_queue_pair **qp, size_t *payload_len, struct ib_address_vector *dest, struct ib_address_vector *source)
Remove IB headers.
Definition: ib_packet.c:133
QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL
ContextCfg values for different numbers of contexts.
Definition: qib7322.h:262
QIB_7322_SendPbc
Definition: qib7322.h:83
DBGC
#define DBGC(...)
Definition: compiler.h:505
QIB7322_EEPROM_GUID_OFFSET
#define QIB7322_EEPROM_GUID_OFFSET
GUID offset within EEPROM.
Definition: qib7322.h:193
IB_GUID_ARGS
#define IB_GUID_ARGS(guid)
Infiniband Globally Unique Identifier debug message arguments.
Definition: ib_packet.h:29
qib7322_destroy_send_wq
static void qib7322_destroy_send_wq(struct ib_device *ibdev __unused, struct ib_queue_pair *qp)
Destroy send work queue.
Definition: qib7322.c:609
ib_mad_smp::smp_data
union ib_smp_data smp_data
Definition: ib_mad.h:590
qib7322_send_buf_in_use
static int qib7322_send_buf_in_use(struct qib7322 *qib7322, unsigned int send_buf)
Check to see if send buffer is in use.
Definition: qib7322.c:533
IB_LINK_SPEED_SDR
#define IB_LINK_SPEED_SDR
Definition: ib_mad.h:144
QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL
Definition: qib7322.h:264
index
long index
Definition: bigint.h:62
ENOENT
#define ENOENT
No such file or directory.
Definition: errno.h:514
ib_device::dev
struct device * dev
Underlying device.
Definition: infiniband.h:410
QIB_7322_GPIOOut_offset
#define QIB_7322_GPIOOut_offset
Definition: qib_7322_regs.h:639
QIB_7322_RcvBTHQP_0_offset
#define QIB_7322_RcvBTHQP_0_offset
Definition: qib_7322_regs.h:2729
uint64_t
unsigned long long uint64_t
Definition: stdint.h:13
QIB_7322_RcvHdrHead0_offset
#define QIB_7322_RcvHdrHead0_offset
Definition: qib_7322_regs.h:6581
DBG_DISABLE
#define DBG_DISABLE(level)
Definition: compiler.h:312
malloc_phys
static void *__malloc malloc_phys(size_t size, size_t phys_align)
Allocate memory with specified physical alignment.
Definition: malloc.h:61
BIT_SET
#define BIT_SET(_ptr, _field, _value)
Definition: pseudobit.h:238
i2c_bit_basher
A bit-bashing I2C interface.
Definition: i2c.h:91
qib7322_ahb_write
static int qib7322_ahb_write(struct qib7322 *qib7322, unsigned int location, uint32_t data)
Write data via AHB.
Definition: qib7322.c:2092
QIB_7322_RcvHdrCnt_offset
#define QIB_7322_RcvHdrCnt_offset
Definition: qib_7322_regs.h:671
qib7322_writeq_array64k
#define qib7322_writeq_array64k(_qib7322, _ptr, _offset, _idx)
Definition: qib7322.c:177
QIB_7322_SendBufAvailAddr_offset
#define QIB_7322_SendBufAvailAddr_offset
Definition: qib_7322_regs.h:781
qib7322_ahb_read
static int qib7322_ahb_read(struct qib7322 *qib7322, unsigned int location, uint32_t *data)
Read data via AHB.
Definition: qib7322.c:2057
bit
static unsigned int unsigned int bit
Definition: bigint.h:391
QIB_7322_RxCreditVL0_1_offset
#define QIB_7322_RxCreditVL0_1_offset
Definition: qib_7322_regs.h:4366
qib7322_mcast_attach
static int qib7322_mcast_attach(struct ib_device *ibdev, struct ib_queue_pair *qp, union ib_gid *gid)
Attach to multicast group.
Definition: qib7322.c:1764
i2c_interface
An I2C interface.
Definition: i2c.h:57
ib_link_state_changed
void ib_link_state_changed(struct ib_device *ibdev)
Notify of Infiniband link state change.
Definition: infiniband.c:637
QIB7322_GPIO_SDA
#define QIB7322_GPIO_SDA
QIB7322 I2C SDA line GPIO number.
Definition: qib7322.h:190
QIB_7322_RcvQPMapTableB_0
Definition: qib_7322_regs.h:2764
ctx
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
ib_queue_pair::recv
struct ib_work_queue recv
Receive queue.
Definition: infiniband.h:180
QIB_7322_SendCtrl_1_offset
#define QIB_7322_SendCtrl_1_offset
Definition: qib_7322_regs.h:4231
iob_populate
static void iob_populate(struct io_buffer *iobuf, void *data, size_t len, size_t max_len)
Create a temporary I/O buffer.
Definition: iobuf.h:190
qib7322_send_buffers::size
unsigned int size
Send buffer size.
Definition: qib7322.c:53
qib7322_i2c_basher_ops
static struct bit_basher_operations qib7322_i2c_basher_ops
QIB7322 I2C bit-bashing interface operations.
Definition: qib7322.c:1894
qib7322_i2c_bits
static unsigned int qib7322_i2c_bits[]
QIB7322 I2C bit to GPIO mappings.
Definition: qib7322.c:1819
PCI_CONFIG_BACKUP_ALL
#define PCI_CONFIG_BACKUP_ALL
Limit of PCI configuration space.
Definition: pcibackup.h:15
ib_device::link_speed_enabled
uint8_t link_speed_enabled
Link speed enabled.
Definition: infiniband.h:435
QIB_7322_ErrStatus_0
Definition: qib_7322_regs.h:2632
qib7322::ibdev
struct ib_device * ibdev[QIB7322_MAX_PORTS]
Infiniband devices.
Definition: qib7322.c:128
qib7322::eeprom
struct i2c_device eeprom
I2C serial EEPROM.
Definition: qib7322.c:123
qib7322_close
static void qib7322_close(struct ib_device *ibdev)
Close Infiniband link.
Definition: qib7322.c:1736
qib7322_recv_work_queue::eager_entries
unsigned int eager_entries
Number of entries in eager array.
Definition: qib7322.c:92
adjust_pci_device
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:154
QIB7322_EEPROM_SERIAL_OFFSET
#define QIB7322_EEPROM_SERIAL_OFFSET
Board serial number offset within EEPROM.
Definition: qib7322.h:199
qib7322_init_ib_serdes
static int qib7322_init_ib_serdes(struct qib7322 *qib7322)
Initialise the IB SerDes.
Definition: qib7322.c:2195
out
__be32 out[4]
Definition: CIB_PRM.h:36
ib_gid
An Infiniband Global Identifier.
Definition: ib_packet.h:33
qib7322_free_ctx
static void qib7322_free_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Free a context.
Definition: qib7322.c:408
QIB7322_VL15_PORT0_SEND_BUF_START
#define QIB7322_VL15_PORT0_SEND_BUF_START
QIB7322 VL15 port 0 send buffer starting index.
Definition: qib7322.h:223
QIB_7322_IBCCtrlA_0_offset
#define QIB_7322_IBCCtrlA_0_offset
Definition: qib_7322_regs.h:3146
pci_device::dev
struct device dev
Generic device.
Definition: pci.h:208
QIB_7322_IBPCSConfig_0_offset
#define QIB_7322_IBPCSConfig_0_offset
Definition: qib_7322_regs.h:3265
QIB7322_NUM_CONTEXTS
#define QIB7322_NUM_CONTEXTS
Number of contexts (including kernel context)
Definition: qib7322.h:252
qib7322_recv_work_queue::eager_prod
unsigned int eager_prod
Eager array producer index.
Definition: qib7322.c:94
ib_device::link_width_enabled
uint8_t link_width_enabled
Link width enabled.
Definition: infiniband.h:429
QIB7322_VL15_PORT1_SEND_BUF_START
#define QIB7322_VL15_PORT1_SEND_BUF_START
QIB7322 VL15 port 0 send buffer starting index.
Definition: qib7322.h:232
port_info
struct ib_port_info port_info
Definition: ib_mad.h:14
QIB7322_SMALL_SEND_BUF_START
#define QIB7322_SMALL_SEND_BUF_START
QIB7322 small send buffer starting index.
Definition: qib7322.h:208
ib_device::link_width_supported
uint8_t link_width_supported
Link width supported.
Definition: infiniband.h:427
qib7322_send_buffers::prod
unsigned int prod
Send buffer availability producer counter.
Definition: qib7322.c:62
ECANCELED
#define ECANCELED
Operation canceled.
Definition: errno.h:343
qib7322_post_recv
static int qib7322_post_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, struct io_buffer *iobuf)
Post receive work queue entry.
Definition: qib7322.c:1311
qib7322_i2c_write_bit
static void qib7322_i2c_write_bit(struct bit_basher *basher, unsigned int bit_id, unsigned long data)
Write QIB7322 I2C line status.
Definition: qib7322.c:1856
ib_smp_data::port_info
struct ib_port_info port_info
Definition: ib_mad.h:184
QIB7322_VL15_PORT0_SEND_BUF_SIZE
#define QIB7322_VL15_PORT0_SEND_BUF_SIZE
QIB7322 VL15 port 0 send buffer size.
Definition: qib7322.h:229
malloc.h
Dynamic memory allocation.
QIB7322_SENDBUFAVAIL_ALIGN
#define QIB7322_SENDBUFAVAIL_ALIGN
DMA alignment for send buffer availability.
Definition: qib7322.h:97
QIB_7322_RcvCtrl_0_offset
#define QIB_7322_RcvCtrl_0_offset
Definition: qib_7322_regs.h:2712
eeprom
eeprom
Definition: 3c90x.h:232
QIB_7322_Revision_offset
#define QIB_7322_Revision_offset
Definition: qib_7322_regs.h:38
qib7322_send_buffers::base
unsigned long base
Offset within register space of the first send buffer.
Definition: qib7322.c:51
qib7322_send_buffers
A QIB7322 send buffer set.
Definition: qib7322.c:49
QIB_7322_RcvQPMapTableA_0
Definition: qib_7322_regs.h:2749
start
uint32_t start
Starting offset.
Definition: netvsc.h:12
QIB7322_VL15_PORT1_SEND_BUF_SIZE
#define QIB7322_VL15_PORT1_SEND_BUF_SIZE
QIB7322 VL15 port 0 send buffer size.
Definition: qib7322.h:238
ib_device
An Infiniband device.
Definition: infiniband.h:398
IB_LINK_WIDTH_4X
#define IB_LINK_WIDTH_4X
Definition: ib_mad.h:140
ib_work_queue::cq
struct ib_completion_queue * cq
Associated completion queue.
Definition: infiniband.h:106
QIB_7322_RcvQPMulticastContext_1
Definition: qib_7322_regs.h:4186
qib7322_send_work_queue::prod
unsigned int prod
Producer index.
Definition: qib7322.c:76
DBGCP_HDA
#define DBGCP_HDA(...)
Definition: compiler.h:540
qib7322_send_buffers::count
unsigned int count
Number of send buffers.
Definition: qib7322.c:60
QIB7322_LARGE_SEND_BUF_SIZE
#define QIB7322_LARGE_SEND_BUF_SIZE
QIB7322 large send buffer size.
Definition: qib7322.h:214
pci_set_drvdata
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:359
init_i2c_eeprom
static __always_inline void init_i2c_eeprom(struct i2c_device *i2cdev, unsigned int dev_addr)
Initialise generic I2C EEPROM device.
Definition: i2c.h:149
ENOMEM
#define ENOMEM
Not enough space.
Definition: errno.h:534
qib7322_mcast_detach
static void qib7322_mcast_detach(struct ib_device *ibdev, struct ib_queue_pair *qp, union ib_gid *gid)
Detach from multicast group.
Definition: qib7322.c:1782
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
QIB_7322_RxCreditVL0_0_offset
#define QIB_7322_RxCreditVL0_0_offset
Definition: qib_7322_regs.h:3033
QIB_7322_IBCStatusA_0
Definition: qib_7322_regs.h:3124
qib7322_init_send
static int qib7322_init_send(struct qib7322 *qib7322)
Initialise send datapath.
Definition: qib7322.c:623
QIB_7322_RcvEgr
Definition: qib7322.h:119
QIB7322_EAGER_ARRAY_SIZE_18CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER
Definition: qib7322.h:267
IB_GUID_FMT
#define IB_GUID_FMT
Infiniband Globally Unique Identifier debug message format.
Definition: ib_packet.h:26
port
u8 port
Port number.
Definition: CIB_PRM.h:31
ib_get_drvdata
static __always_inline void * ib_get_drvdata(struct ib_device *ibdev)
Get Infiniband device driver-private data.
Definition: infiniband.h:708
QIB7322_AHB_LOC_TARGET
#define QIB7322_AHB_LOC_TARGET(_location)
Definition: qib7322.h:341
virt_to_bus
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
qib7322::i2c
struct i2c_bit_basher i2c
I2C bit-bashing interface.
Definition: qib7322.c:121
QIB7322_SEND_BUF_TOGGLE
#define QIB7322_SEND_BUF_TOGGLE
Send buffer toggle bit.
Definition: qib7322.c:432
qib7322::recv_wq
struct qib7322_recv_work_queue recv_wq[QIB7322_NUM_CONTEXTS]
Receive work queues.
Definition: qib7322.c:109
qib7322_create_recv_wq
static int qib7322_create_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create receive work queue.
Definition: qib7322.c:747
assert.h
Assertions.
qib7322_destroy_qp
static void qib7322_destroy_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Destroy queue pair.
Definition: qib7322.c:1142
QIB_7322_Control_offset
#define QIB_7322_Control_offset
Definition: qib_7322_regs.h:54
assert
assert((readw(&hdr->flags) &(GTF_reading|GTF_writing))==0)
qib7322_ahb_release
static void qib7322_ahb_release(struct qib7322 *qib7322)
Release ownership of the AHB.
Definition: qib7322.c:2040
QIB_7322_IBPCSConfig_0
Definition: qib_7322_regs.h:3274
container_of
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
ib_device::op
struct ib_device_operations * op
Infiniband operations.
Definition: infiniband.h:416
qib7322_reset
static void qib7322_reset(struct qib7322 *qib7322, struct pci_device *pci)
Reset QIB7322.
Definition: qib7322.c:2254
ib_work_queue
An Infiniband Work Queue.
Definition: infiniband.h:100
i2c_bit_basher::i2c
struct i2c_interface i2c
I2C interface.
Definition: i2c.h:93
list_for_each_entry
#define list_for_each_entry(pos, head, member)
Iterate over entries in a list.
Definition: list.h:431
qib7322_post_send
static int qib7322_post_send(struct ib_device *ibdev, struct ib_queue_pair *qp, struct ib_address_vector *dest, struct io_buffer *iobuf)
Post send work queue entry.
Definition: qib7322.c:1166
value
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
__unused
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
qib7322_fini_recv
static void qib7322_fini_recv(struct qib7322 *qib7322 __unused)
Shut down receive datapath.
Definition: qib7322.c:1018
ib_port_info::link_speed_supported__port_state
uint8_t link_speed_supported__port_state
Definition: ib_mad.h:116
qib7322_complete_send
static void qib7322_complete_send(struct ib_device *ibdev, struct ib_queue_pair *qp, unsigned int wqe_idx)
Complete send work queue entry.
Definition: qib7322.c:1249
ib_complete_send
void ib_complete_send(struct ib_device *ibdev, struct ib_queue_pair *qp, struct io_buffer *iobuf, int rc)
Complete send work queue entry.
Definition: infiniband.c:515
writel
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
QIB_7322_SendBufAvailAddr
Definition: qib_7322_regs.h:787
QIB_7322_IBCCtrlA_0
Definition: qib_7322_regs.h:3163
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
build_assert
#define build_assert(condition)
Assert a condition at build time (after dead code elimination)
Definition: assert.h:76
bitbash.h
Bit-bashing interfaces.
qib7322_init_i2c
static int qib7322_init_i2c(struct qib7322 *qib7322)
Initialise QIB7322 I2C subsystem.
Definition: qib7322.c:1905
QIB_7322_SendBufAvail
Definition: qib7322.h:92
QIB_7322_RcvEgrIndexHead0_offset
#define QIB_7322_RcvEgrIndexHead0_offset
Definition: qib_7322_regs.h:6595
ib_queue_pair::qpn
unsigned long qpn
Queue pair number.
Definition: infiniband.h:165
qib7322_open
static int qib7322_open(struct ib_device *ibdev)
Initialise Infiniband link.
Definition: qib7322.c:1716
BIT_GET
#define BIT_GET(_ptr, _field)
Extract value of named field (for fields up to the size of a long)
Definition: pseudobit.h:235
count
uint16_t count
Number of entries.
Definition: ena.h:22
QIB_7322_RcvQPMapTableB_1
Definition: qib_7322_regs.h:4097
qib7322_set_pkey_table
static int qib7322_set_pkey_table(struct ib_device *ibdev __unused, union ib_mad *mad __unused)
Set partition key table.
Definition: qib7322.c:348
channel
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
qib7322_poll_eq
static void qib7322_poll_eq(struct ib_device *ibdev)
Poll event queue.
Definition: qib7322.c:1629
qib7322_init_recv
static int qib7322_init_recv(struct qib7322 *qib7322)
Initialise receive datapath.
Definition: qib7322.c:858
ib_work_queue::num_wqes
unsigned int num_wqes
Number of work queue entries.
Definition: infiniband.h:112
QIB7322_EAGER_ARRAY_SIZE_10CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER
Definition: qib7322.h:265
QIB_7322_RcvBTHQP_1_offset
#define QIB_7322_RcvBTHQP_1_offset
Definition: qib_7322_regs.h:4062
EPROTO
#define EPROTO
Protocol error.
Definition: errno.h:624
ib_completion_queue::work_queues
struct list_head work_queues
List of work queues completing to this queue.
Definition: infiniband.h:242
QIB7322_AHB_LOCATION
#define QIB7322_AHB_LOCATION(_port, _channel, _register)
Definition: qib7322.h:352
QIB7322_GPIO_SCL
#define QIB7322_GPIO_SCL
QIB7322 I2C SCL line GPIO number.
Definition: qib7322.h:187
BIT_FILL_3
#define BIT_FILL_3(_ptr, _field1,...)
Definition: pseudobit.h:195
qib7322_destroy_recv_wq
static void qib7322_destroy_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Destroy receive work queue.
Definition: qib7322.c:824
revision
uint32_t revision
Entry point revision.
Definition: ib_mad.h:20
QIB_7322_ahb_transaction_reg
Definition: qib_7322_regs.h:959
i2c_bit_basher::basher
struct bit_basher basher
Bit-bashing interface.
Definition: i2c.h:95
QIB_7322_Revision
Definition: qib_7322_regs.h:49
qib7322_writeq
#define qib7322_writeq(_qib7322, _ptr, _offset)
Definition: qib7322.c:173
bit_basher_operations::read
int(* read)(struct bit_basher *basher, unsigned int bit_id)
Read input bit.
Definition: bitbash.h:51
QIB_7322_IBCCtrlB_0
Definition: qib_7322_regs.h:3191
QIB7322_BAR0_SIZE
#define QIB7322_BAR0_SIZE
QIB7322 memory BAR size.
Definition: qib7322.h:163
bit_basher
A bit-bashing interface.
Definition: bitbash.h:55
ib_device::port
unsigned int port
Port number.
Definition: infiniband.h:418
ibdev_put
static __always_inline void ibdev_put(struct ib_device *ibdev)
Drop reference to Infiniband device.
Definition: infiniband.h:598
I2C_BIT_SDA
Serial data.
Definition: i2c.h:116
strerror
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
free
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
ib_mad::smp
struct ib_mad_smp smp
Definition: ib_mad.h:612
qib7322_link_speed_supported
static unsigned int qib7322_link_speed_supported(struct qib7322 *qib7322, unsigned int port)
Determine supported link speeds.
Definition: qib7322.c:1664
QIB_7322_IBCCtrlA_1_offset
#define QIB_7322_IBCCtrlA_1_offset
Definition: qib_7322_regs.h:4476
QIB_7322_RcvQPMapTableA_1
Definition: qib_7322_regs.h:4082
zalloc
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:640
pci.h
PCI bus.
pci_device
A PCI device.
Definition: pci.h:206
features
uint32_t features
Supported features.
Definition: ena.h:16
iob_len
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:155
ib_wq_get_drvdata
static __always_inline void * ib_wq_get_drvdata(struct ib_work_queue *wq)
Get Infiniband work queue driver-private data.
Definition: infiniband.h:620
alloc_ibdev
struct ib_device * alloc_ibdev(size_t priv_size)
Allocate Infiniband device.
Definition: infiniband.c:917
QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL
#define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL
Definition: qib7322.h:266
qib7322::sendbufavail
struct QIB_7322_SendBufAvail * sendbufavail
Send buffer availability (reported by hardware)
Definition: qib7322.c:112
pci_config_backup
A PCI configuration space backup.
Definition: pcibackup.h:21
ib_guid
An Infiniband Globally Unique Identifier.
Definition: ib_packet.h:18
QIB7322_PORT_BASE
#define QIB7322_PORT_BASE
QIB7322 base port number.
Definition: qib7322.h:166
control
uint32_t control
Control.
Definition: myson.h:14
QIB7322_LARGE_SEND_BUF_COUNT
#define QIB7322_LARGE_SEND_BUF_COUNT
QIB7322 large send buffer count.
Definition: qib7322.h:220
QIB7322_RECV_HEADERS_SIZE
#define QIB7322_RECV_HEADERS_SIZE
Total size of an RX header ring.
Definition: qib7322.h:296
serial
uint64_t serial
Serial number.
Definition: edd.h:30
port_state
u8 port_state
Definition: CIB_PRM.h:38
QIB_7322_EXTCtrl
Definition: qib_7322_regs.h:623
iob_tailroom
static size_t iob_tailroom(struct io_buffer *iobuf)
Calculate available space at end of an I/O buffer.
Definition: iobuf.h:175
QIB_7322_SendCtrl
Definition: qib_7322_regs.h:740
ib_device::node_guid
union ib_guid node_guid
Node GUID.
Definition: infiniband.h:439
ENODEV
#define ENODEV
No such device.
Definition: errno.h:509
ib_work_queue::fill
unsigned int fill
Number of occupied work queue entries.
Definition: infiniband.h:114
ib_completion_queue
An Infiniband Completion Queue.
Definition: infiniband.h:224
qib7322_poll_recv_wq
static void qib7322_poll_recv_wq(struct ib_device *ibdev, struct ib_queue_pair *qp)
Poll receive work queue.
Definition: qib7322.c:1554
qib7322_readq_port
#define qib7322_readq_port(_qib7322, _ptr, _offset, _port)
Definition: qib7322.c:159
uint8_t
unsigned char uint8_t
Definition: stdint.h:10
qib7322.h
QLogic QIB7322 Infiniband HCA.
I2C_BIT_SCL
Serial clock.
Definition: i2c.h:114
QIB_7322_RcvHdrHead0
Definition: qib_7322_regs.h:6587
qib7322_free_send_buf
static void qib7322_free_send_buf(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs, unsigned int send_buf)
Free a send buffer.
Definition: qib7322.c:517
QIB7322_RECV_HEADER_SIZE
#define QIB7322_RECV_HEADER_SIZE
Maximum size of each RX header.
Definition: qib7322.h:293
ib_device::link_width_active
uint8_t link_width_active
Link width active.
Definition: infiniband.h:431
QIB7322_MAX_PORTS
#define QIB7322_MAX_PORTS
QIB7322 maximum number of ports.
Definition: qib7322.h:169
qib7322_send_buffers::cons
unsigned int cons
Send buffer availability consumer counter.
Definition: qib7322.c:64
QIB_7322_RcvEgrBase_offset
#define QIB_7322_RcvEgrBase_offset
Definition: qib_7322_regs.h:683
register_ibdev
int register_ibdev(struct ib_device *ibdev)
Register Infiniband device.
Definition: infiniband.c:944
QIB_7322_IBCCtrlB_0_offset
#define QIB_7322_IBCCtrlB_0_offset
Definition: qib_7322_regs.h:3168
QIB_7322_EXTStatus
Definition: qib_7322_regs.h:608
pci_device_id
A PCI device ID list entry.
Definition: pci.h:170
ib_work_queue::qp
struct ib_queue_pair * qp
Containing queue pair.
Definition: infiniband.h:102
headers
uint8_t headers[IB_MAX_HEADER_SIZE]
Definition: arbel.h:14
QIB_7322_EXTCtrl_offset
#define QIB_7322_EXTCtrl_offset
Definition: qib_7322_regs.h:613
i2c_interface::read
int(* read)(struct i2c_interface *i2c, struct i2c_device *i2cdev, unsigned int offset, uint8_t *data, unsigned int len)
Read data from I2C device.
Definition: i2c.h:68
ib_device::ports
unsigned int ports
Total ports on device.
Definition: infiniband.h:420
uint32_t
unsigned int uint32_t
Definition: stdint.h:12
qib7322_fini_send
static void qib7322_fini_send(struct qib7322 *qib7322)
Shut down send datapath.
Definition: qib7322.c:716
QIB_7322_ahb_transaction_reg_offset
#define QIB_7322_ahb_transaction_reg_offset
Definition: qib_7322_regs.h:949
qib7322_ahb_request
static int qib7322_ahb_request(struct qib7322 *qib7322, unsigned int location)
Request ownership of the AHB.
Definition: qib7322.c:2013
qib7322_ctx
static unsigned int qib7322_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Get queue pair context number.
Definition: qib7322.c:397
QIB_7322_RcvHdrAddr0_offset
#define QIB_7322_RcvHdrAddr0_offset
Definition: qib_7322_regs.h:817
remove
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
qib7322_send_buffers::avail
uint16_t avail[0]
Send buffer availability.
Definition: qib7322.c:66
QIB_7322_SendCtrl_offset
#define QIB_7322_SendCtrl_offset
Definition: qib_7322_regs.h:725
qib7322
A QIB7322 HCA.
Definition: qib7322.c:100
status
uint8_t status
Status.
Definition: ena.h:16
guid
uint64_t guid
GUID.
Definition: edd.h:30
QIB_7322_RcvQPMapTableA_0_offset
#define QIB_7322_RcvQPMapTableA_0_offset
Definition: qib_7322_regs.h:2739
ib_work_queue::list
struct list_head list
List of work queues on this completion queue.
Definition: infiniband.h:108
ib_queue_pair
An Infiniband Queue Pair.
Definition: infiniband.h:157
qib7322_set_port_info
static int qib7322_set_port_info(struct ib_device *ibdev, union ib_mad *mad)
Set port information.
Definition: qib7322.c:307
qib7322_ahb_wait
static int qib7322_ahb_wait(struct qib7322 *qib7322)
Wait for AHB transaction to complete.
Definition: qib7322.c:1988
qib7322_recv_work_queue::header_prod
struct QIB_7322_scalar header_prod
Receive header producer offset (written by hardware)
Definition: qib7322.c:86
ib_gid::s
struct ib_gid::@613 s
QIB7322_AHB_LOC_ADDRESS
#define QIB7322_AHB_LOC_ADDRESS(_location)
QIB7322 AHB locations.
Definition: qib7322.h:340
physaddr_t
unsigned long physaddr_t
Definition: stdint.h:20
qib7322_link_state_check
static int qib7322_link_state_check(struct ib_device *ibdev, unsigned int new_link_state)
Wait for link state change to take effect.
Definition: qib7322.c:279
xact
uint32_t xact
Requester transaction ID.
Definition: eth_slow.h:18
QIB_7322_RcvQPMulticastContext_0
Definition: qib_7322_regs.h:2853
pci_get_drvdata
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:369
qp
struct arbelprm_qp_db_record qp
Definition: arbel.h:13
IB_LINK_WIDTH_1X
#define IB_LINK_WIDTH_1X
Definition: ib_mad.h:139
BIT_FILL_2
#define BIT_FILL_2(_ptr, _field1,...)
Definition: pseudobit.h:190
mdelay
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
iob_reserve
#define iob_reserve(iobuf, len)
Definition: iobuf.h:67
QIB7322_QP_IDETH
#define QIB7322_QP_IDETH
QPN used for Infinipath Packets.
Definition: qib7322.h:334
QIB_7322_RcvQPMapTableA_1_offset
#define QIB_7322_RcvQPMapTableA_1_offset
Definition: qib_7322_regs.h:4072
qib7322_poll_cq
static void qib7322_poll_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Poll completion queue.
Definition: qib7322.c:1603
qib7322::send_bufs_vl15_port0
struct qib7322_send_buffers * send_bufs_vl15_port0
VL15 port 0 send buffers.
Definition: qib7322.c:116
ENOBUFS
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
DBGC2
#define DBGC2(...)
Definition: compiler.h:522
pci_backup
void pci_backup(struct pci_device *pci, struct pci_config_backup *backup, unsigned int limit, const uint8_t *exclude)
Back up PCI configuration space.
Definition: pcibackup.c:67
QIB7322_EEPROM_SERIAL_SIZE
#define QIB7322_EEPROM_SERIAL_SIZE
Board serial number size within EEPROM.
Definition: qib7322.h:202
pci_driver::probe
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:260
QIB7322_RECV_HEADER_COUNT
#define QIB7322_RECV_HEADER_COUNT
Number of RX headers per context.
Definition: qib7322.h:287
QIB_7322_ErrStatus_0_offset
#define QIB_7322_ErrStatus_0_offset
Definition: qib_7322_regs.h:2584
ib_device::link_speed_active
uint8_t link_speed_active
Link speed active.
Definition: infiniband.h:437
qib7322::send_bufs_small
struct qib7322_send_buffers * send_bufs_small
Small send buffers.
Definition: qib7322.c:114
QIB7322_VL15_PORT0_SEND_BUF_COUNT
#define QIB7322_VL15_PORT0_SEND_BUF_COUNT
QIB7322 VL15 port 0 send buffer count.
Definition: qib7322.h:226
qib7322_link_state_text
static const char * qib7322_link_state_text(unsigned int link_state)
Textual representation of link state.
Definition: qib7322.c:207
QIB_7322_IBCStatusA_0_offset
#define QIB_7322_IBCStatusA_0_offset
Definition: qib_7322_regs.h:3098
IB_LINK_SPEED_DDR
#define IB_LINK_SPEED_DDR
Definition: ib_mad.h:145
qib7322::guid
union ib_guid guid
Base GUID.
Definition: qib7322.c:126
QIB_7322_SendCtrl_0
Definition: qib_7322_regs.h:2916
qib7322::send_bufs_vl15_port1
struct qib7322_send_buffers * send_bufs_vl15_port1
VL15 port 1 send buffers.
Definition: qib7322.c:118
BIT_FILL_1
#define BIT_FILL_1(_ptr, _field1,...)
Definition: pseudobit.h:185
io_buffer::data
void * data
Start of data.
Definition: iobuf.h:48
addr
u32 addr
Definition: sky2.h:8
qib7322_recv_work_queue::header_cons
unsigned int header_cons
Receive header consumer offset.
Definition: qib7322.c:88
EIO
#define EIO
Input/output error.
Definition: errno.h:433
QIB_7322_RcvHdrTailAddr0_offset
#define QIB_7322_RcvHdrTailAddr0_offset
Definition: qib_7322_regs.h:828
qib7322_create_send_bufs
static struct qib7322_send_buffers * qib7322_create_send_bufs(struct qib7322 *qib7322, unsigned long base, unsigned int size, unsigned int start, unsigned int count)
Create send buffer set.
Definition: qib7322.c:445
QIB_7322_IBCCtrlB_1_offset
#define QIB_7322_IBCCtrlB_1_offset
Definition: qib_7322_regs.h:4498
qib7322_writel
static void qib7322_writel(struct qib7322 *qib7322, uint32_t dword, unsigned long offset)
Write QIB7322 dword register.
Definition: qib7322.c:189
QIB_7322_EXTStatus_offset
#define QIB_7322_EXTStatus_offset
Definition: qib_7322_regs.h:600
QIB_7322_active_feature_mask_offset
#define QIB_7322_active_feature_mask_offset
Definition: qib_7322_regs.h:710
qib7322_create_qp
static int qib7322_create_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Create queue pair.
Definition: qib7322.c:1084
ib_device::port_state
uint8_t port_state
Port state.
Definition: infiniband.h:425
ib_completion_queue::cqn
unsigned long cqn
Completion queue number.
Definition: infiniband.h:230
dest
if(len >=6 *4) __asm__ __volatile__("movsl" if(len >=5 *4) __asm__ __volatile__("movsl" if(len >=4 *4) __asm__ __volatile__("movsl" if(len >=3 *4) __asm__ __volatile__("movsl" if(len >=2 *4) __asm__ __volatile__("movsl" if(len >=1 *4) __asm__ __volatile__("movsl" if((len % 4) >=2) __asm__ __volatile__("movsw" if((len % 2) >=1) __asm__ __volatile__("movsb" return dest
Definition: string.h:150
QIB_7322_RcvBTHQP_0
Definition: qib_7322_regs.h:2734
iounmap
void iounmap(volatile const void *io_addr)
Unmap I/O address.
data
uint8_t data[48]
Additional event data.
Definition: ena.h:22
QIB7322_MAX_WIDTH
#define QIB7322_MAX_WIDTH
QIB7322 maximum width.
Definition: qib7322.h:172
qib7322::send_wq
struct qib7322_send_work_queue send_wq[QIB7322_NUM_CONTEXTS]
Send work queues.
Definition: qib7322.c:107
qib7322_send_work_queue::cons
unsigned int cons
Consumer index.
Definition: qib7322.c:78
ib_mad
A management datagram.
Definition: ib_mad.h:610
DBGCP
#define DBGCP(...)
Definition: compiler.h:539
QIB_7322_feature_mask
Definition: qib7322.h:63
ib_guid::bytes
uint8_t bytes[8]
Definition: ib_packet.h:19
ib_device::link_speed_supported
uint8_t link_speed_supported
Link speed supported.
Definition: infiniband.h:433
ib_complete_recv
void ib_complete_recv(struct ib_device *ibdev, struct ib_queue_pair *qp, struct ib_address_vector *dest, struct ib_address_vector *source, struct io_buffer *iobuf, int rc)
Complete receive work queue entry.
Definition: infiniband.c:536
qib7322_read_eeprom
static int qib7322_read_eeprom(struct qib7322 *qib7322)
Read EEPROM parameters.
Definition: qib7322.c:1940
qib7322_nics
static struct pci_device_id qib7322_nics[]
Definition: qib7322.c:2422
qib7322_modify_qp
static int qib7322_modify_qp(struct ib_device *ibdev, struct ib_queue_pair *qp)
Modify queue pair.
Definition: qib7322.c:1125
free_phys
static void free_phys(void *ptr, size_t size)
Free memory allocated with malloc_phys()
Definition: malloc.h:76
ib_address_vector
An Infiniband Address Vector.
Definition: infiniband.h:72
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
QIB_7322_scalar
Definition: qib7322.h:53
mb
void mb(void)
Memory barrier.
QIB7322_EAGER_ARRAY_SIZE_6CTX_USER
#define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER
Definition: qib7322.h:263
qib7322_recv_work_queue
A QIB7322 receive work queue.
Definition: qib7322.c:82
ssize_t
signed long ssize_t
Definition: stdint.h:7
QIB_7322_SendBufBase
Definition: qib_7322_regs.h:752
qib7322_probe
static int qib7322_probe(struct pci_device *pci)
Probe PCI device.
Definition: qib7322.c:2280
qib7322_create_cq
static int qib7322_create_cq(struct ib_device *ibdev, struct ib_completion_queue *cq)
Create completion queue.
Definition: qib7322.c:1038
qib7322::regs
void * regs
Registers.
Definition: qib7322.c:102
qib7322_link_state_changed
static void qib7322_link_state_changed(struct ib_device *ibdev)
Handle link state change.
Definition: qib7322.c:223
supported
uint32_t supported
Bitmask of supported AENQ groups (device -> host)
Definition: ena.h:12
QIB7322_SMALL_SEND_BUF_SIZE
#define QIB7322_SMALL_SEND_BUF_SIZE
QIB7322 small send buffer size.
Definition: qib7322.h:205
cqn
__be32 cqn
Definition: CIB_PRM.h:29
pci_ioremap
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
bufsize
uint8_t bufsize
Size of the packet, in bytes.
Definition: int13.h:12
ib_work_queue::is_send
int is_send
"Is a send queue" flag
Definition: infiniband.h:104
gid
u8 gid[16]
Definition: CIB_PRM.h:31
QIB_7322_RcvHdrEntSize_offset
#define QIB_7322_RcvHdrEntSize_offset
Definition: qib_7322_regs.h:674
init_i2c_bit_basher
int init_i2c_bit_basher(struct i2c_bit_basher *i2cbit, struct bit_basher_operations *bash_op)
Initialise I2C bit-bashing interface.
Definition: i2c_bit.c:387
DBG_LOG
#define DBG_LOG
Definition: compiler.h:317
qib7322_remove
static void qib7322_remove(struct pci_device *pci)
Remove PCI device.
Definition: qib7322.c:2406
qib7322_alloc_ctx
static int qib7322_alloc_ctx(struct ib_device *ibdev, struct ib_queue_pair *qp)
Allocate a context and set queue pair number.
Definition: qib7322.c:368
qib7322_recv_work_queue::eager_array
unsigned long eager_array
Offset within register space of the eager array.
Definition: qib7322.c:90
QIB_7322_RcvQPMulticastContext_0_offset
#define QIB_7322_RcvQPMulticastContext_0_offset
Definition: qib_7322_regs.h:2848
len
uint32_t len
Length.
Definition: ena.h:14
QIB_7322_RcvQPMulticastContext_1_offset
#define QIB_7322_RcvQPMulticastContext_1_offset
Definition: qib_7322_regs.h:4181
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
QIB_7322_GPIO
Definition: qib7322.h:45
QIB_7322_ahb_access_ctrl
Definition: qib_7322_regs.h:944
ETIMEDOUT
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
ib_push
int ib_push(struct ib_device *ibdev, struct io_buffer *iobuf, struct ib_queue_pair *qp, size_t payload_len, const struct ib_address_vector *dest)
Add IB headers.
Definition: ib_packet.c:52
PCI_ROM
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:303
QIB_7322_Control
Definition: qib_7322_regs.h:65
ib_port_info
A Port Information attribute.
Definition: ib_mad.h:104
ib_wq_set_drvdata
static __always_inline void ib_wq_set_drvdata(struct ib_work_queue *wq, void *priv)
Set Infiniband work queue driver-private data.
Definition: infiniband.h:609
writeq
void writeq(uint64_t data, volatile uint64_t *io_addr)
Write 64-bit qword to memory-mapped device.
dword
unsigned long int dword
Definition: smc9000.h:40
QIB_7322_RcvQPMapTableB_0_offset
#define QIB_7322_RcvQPMapTableB_0_offset
Definition: qib_7322_regs.h:2754
IB_MAX_HEADER_SIZE
#define IB_MAX_HEADER_SIZE
Maximum size required for IB headers.
Definition: ib_packet.h:156
i2c_device
An I2C device.
Definition: i2c.h:20
QIB_7322_RcvHdrTailAddr0
Definition: qib_7322_regs.h:834
mad
union ib_mad mad
Definition: arbel.h:12
ib_device_operations::create_cq
int(* create_cq)(struct ib_device *ibdev, struct ib_completion_queue *cq)
Create completion queue.
Definition: infiniband.h:261
QIB_7322_SendCtrl_0_offset
#define QIB_7322_SendCtrl_0_offset
Definition: qib_7322_regs.h:2898
QIB_7322_IBPCSConfig_1_offset
#define QIB_7322_IBPCSConfig_1_offset
Definition: qib_7322_regs.h:4595
QIB7322_MAX_CREDITS_VL15
#define QIB7322_MAX_CREDITS_VL15
Number of credits to advertise for VL15.
Definition: qib7322.h:320
QIB7322_RECV_PAYLOAD_SIZE
#define QIB7322_RECV_PAYLOAD_SIZE
RX payload size.
Definition: qib7322.h:306
QIB7322_LINK_STATE_MAX_WAIT_US
#define QIB7322_LINK_STATE_MAX_WAIT_US
Maximum time to wait for link state changes, in us.
Definition: qib7322.h:367
FILE_LICENCE
FILE_LICENCE(GPL2_OR_LATER_OR_UBDL)
qib7322_send_buffer_offset
static unsigned long qib7322_send_buffer_offset(struct qib7322 *qib7322 __unused, struct qib7322_send_buffers *send_bufs, unsigned int send_buf)
Calculate starting offset for send buffer.
Definition: qib7322.c:557
memset
void * memset(void *dest, int character, size_t len) __nonnull
io_buffer
A persistent I/O buffer.
Definition: iobuf.h:33
pcibackup.h
PCI configuration space backup and restoration.
i2c.h
I2C interface.
ib_work_queue::iobufs
struct io_buffer ** iobufs
I/O buffers assigned to work queue.
Definition: infiniband.h:124
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