iPXE
Macros | Functions
ath9k_ar9002_mac.c File Reference
#include <ipxe/io.h>
#include "hw.h"

Go to the source code of this file.

Macros

#define AR_BufLen   0x00000fff
 

Functions

static void ar9002_hw_rx_enable (struct ath_hw *ah)
 
static void ar9002_hw_set_desc_link (void *ds, u32 ds_link)
 
static void ar9002_hw_get_desc_link (void *ds, u32 **ds_link)
 
static int ar9002_hw_get_isr (struct ath_hw *ah, enum ath9k_int *masked)
 
static void ar9002_hw_fill_txdesc (struct ath_hw *ah __unused, void *ds, u32 seglen, int is_firstseg, int is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu __unused)
 
static int ar9002_hw_proc_txdesc (struct ath_hw *ah, void *ds, struct ath_tx_status *ts)
 
static void ar9002_hw_set11n_txdesc (struct ath_hw *ah, void *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
 
static void ar9002_hw_set_clrdmask (struct ath_hw *ah __unused, void *ds, int val)
 
static void ar9002_hw_set11n_ratescenario (struct ath_hw *ah __unused, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration __unused, struct ath9k_11n_rate_series series[], u32 nseries __unused, u32 flags)
 
static void ar9002_hw_set11n_aggr_first (struct ath_hw *ah __unused, void *ds, u32 aggrLen)
 
static void ar9002_hw_set11n_aggr_middle (struct ath_hw *ah __unused, void *ds, u32 numDelims)
 
static void ar9002_hw_set11n_aggr_last (struct ath_hw *ah __unused, void *ds)
 
static void ar9002_hw_clr11n_aggr (struct ath_hw *ah __unused, void *ds)
 
void ath9k_hw_setuprxdesc (struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags)
 
void ar9002_hw_attach_mac_ops (struct ath_hw *ah)
 

Macro Definition Documentation

◆ AR_BufLen

#define AR_BufLen   0x00000fff

Definition at line 24 of file ath9k_ar9002_mac.c.

Function Documentation

◆ ar9002_hw_rx_enable()

static void ar9002_hw_rx_enable ( struct ath_hw ah)
static

Definition at line 26 of file ath9k_ar9002_mac.c.

27 {
29 }
#define AR_CR_RXE
Definition: reg.h:25
#define AR_CR
Definition: reg.h:24
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85

References ah, AR_CR, AR_CR_RXE, and REG_WRITE.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set_desc_link()

static void ar9002_hw_set_desc_link ( void *  ds,
u32  ds_link 
)
static

Definition at line 31 of file ath9k_ar9002_mac.c.

32 {
33  ((struct ath_desc*) ds)->ds_link = ds_link;
34 }
Definition: mac.h:240
u32 ds_link
Definition: desc.h:129
uint32_t ds
Definition: librm.h:254

References ds, and ds_link.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_get_desc_link()

static void ar9002_hw_get_desc_link ( void *  ds,
u32 **  ds_link 
)
static

Definition at line 36 of file ath9k_ar9002_mac.c.

37 {
38  *ds_link = &((struct ath_desc *)ds)->ds_link;
39 }
Definition: mac.h:240
u32 ds_link
Definition: desc.h:129
uint32_t ds
Definition: librm.h:254

References ds, and ds_link.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_get_isr()

static int ar9002_hw_get_isr ( struct ath_hw ah,
enum ath9k_int masked 
)
static

Definition at line 41 of file ath9k_ar9002_mac.c.

42 {
43  u32 isr = 0;
44  u32 mask2 = 0;
45  struct ath9k_hw_capabilities *pCap = &ah->caps;
46  u32 sync_cause = 0;
47  int fatal_int = 0;
48 
49  if (!AR_SREV_9100(ah) && (ah->ah_ier & AR_IER_ENABLE)) {
52  == AR_RTC_STATUS_ON) {
53  isr = REG_READ(ah, AR_ISR);
54  }
55  }
56 
57  sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
59 
60  *masked = 0;
61 
62  if (!isr && !sync_cause)
63  return 0;
64  } else {
65  *masked = 0;
66  isr = REG_READ(ah, AR_ISR);
67  }
68 
69  if (isr) {
70  if (isr & AR_ISR_BCNMISC) {
71  u32 isr2;
72  isr2 = REG_READ(ah, AR_ISR_S2);
73  if (isr2 & AR_ISR_S2_TIM)
74  mask2 |= ATH9K_INT_TIM;
75  if (isr2 & AR_ISR_S2_DTIM)
76  mask2 |= ATH9K_INT_DTIM;
77  if (isr2 & AR_ISR_S2_DTIMSYNC)
78  mask2 |= ATH9K_INT_DTIMSYNC;
79  if (isr2 & (AR_ISR_S2_CABEND))
80  mask2 |= ATH9K_INT_CABEND;
81  if (isr2 & AR_ISR_S2_GTT)
82  mask2 |= ATH9K_INT_GTT;
83  if (isr2 & AR_ISR_S2_CST)
84  mask2 |= ATH9K_INT_CST;
85  if (isr2 & AR_ISR_S2_TSFOOR)
86  mask2 |= ATH9K_INT_TSFOOR;
87  }
88 
90  if (isr == 0xffffffff) {
91  *masked = 0;
92  return 0;
93  }
94 
95  *masked = isr & ATH9K_INT_COMMON;
96 
99  *masked |= ATH9K_INT_RX;
100 
101  if (isr &
103  AR_ISR_TXEOL)) {
104  u32 s0_s, s1_s;
105 
106  *masked |= ATH9K_INT_TX;
107 
108  s0_s = REG_READ(ah, AR_ISR_S0_S);
109  ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
110  ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
111 
112  s1_s = REG_READ(ah, AR_ISR_S1_S);
113  ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
114  ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
115  }
116 
117  if (isr & AR_ISR_RXORN) {
118  DBG("ath9k: "
119  "receive FIFO overrun interrupt\n");
120  }
121 
122  *masked |= mask2;
123  }
124 
125  if (AR_SREV_9100(ah))
126  return 1;
127 
128  if (isr & AR_ISR_GENTMR) {
129  u32 s5_s;
130 
131  s5_s = REG_READ(ah, AR_ISR_S5_S);
132  ah->intr_gen_timer_trigger =
134 
135  ah->intr_gen_timer_thresh =
137 
138  if (ah->intr_gen_timer_trigger)
139  *masked |= ATH9K_INT_GENTIMER;
140 
141  if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
142  !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
143  *masked |= ATH9K_INT_TIM_TIMER;
144  }
145 
146  if (sync_cause) {
147  fatal_int =
148  (sync_cause &
150  ? 1 : 0;
151 
152  if (fatal_int) {
153  if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
154  DBG("ath9k: "
155  "received PCI FATAL interrupt\n");
156  }
157  if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
158  DBG("ath9k: "
159  "received PCI PERR interrupt\n");
160  }
161  *masked |= ATH9K_INT_FATAL;
162  }
163  if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
164  DBG("ath9k: "
165  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
167  REG_WRITE(ah, AR_RC, 0);
168  *masked |= ATH9K_INT_FATAL;
169  }
170  if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
171  DBG("ath9k: "
172  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
173  }
174 
175  REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
177  }
178 
179  return 1;
180 }
#define AR_ISR_RAC
Definition: reg.h:333
#define AR_RTC_STATUS_ON
Definition: reg.h:1208
#define AR_INTR_SYNC_CAUSE_CLR
Definition: reg.h:923
#define AR_RTC_STATUS
Definition: reg.h:1199
#define AR_INTR_ASYNC_CAUSE
Definition: reg.h:975
#define AR_ISR_S2_DTIM
Definition: reg.h:229
#define AR_ISR_S5_TIM_TIMER
Definition: reg.h:244
#define AR_ISR_S1_S
Definition: reg.h:340
#define AR_ISR_S2_CST
Definition: reg.h:222
#define MS(_v, _f)
Definition: hw.h:102
#define AR_ISR_S5_GENTIMER_THRESH
Definition: reg.h:251
#define AR_ISR_TXEOL
Definition: reg.h:184
#define AR_SREV_9100(ah)
Definition: reg.h:810
#define AR_ISR_S2_GTT
Definition: reg.h:223
#define AR_ISR_S2_TSFOOR
Definition: reg.h:230
#define AR_RTC_STATUS_M
Definition: reg.h:1202
#define AR_IER_ENABLE
Definition: reg.h:55
#define AR_RC_HOSTIF
Definition: reg.h:696
#define AR_ISR_S1_QCU_TXERR
Definition: reg.h:341
#define AR_ISR_S0_QCU_TXOK
Definition: reg.h:335
#define AR_ISR_RXORN
Definition: reg.h:179
#define AR_ISR_S5_S
Definition: reg.h:349
#define AR_ISR_S5_GENTIMER_TRIG
Definition: reg.h:249
#define AR_ISR_TXDESC
Definition: reg.h:181
#define AR_ISR_S0_QCU_TXDESC
Definition: reg.h:337
#define AR_ISR_S0_S
Definition: reg.h:334
#define AR_ISR_RXOK
Definition: reg.h:172
Definition: sis900.h:26
#define AR_ISR_TXOK
Definition: reg.h:180
#define AR_INTR_SYNC_CAUSE
Definition: reg.h:922
#define AR_ISR_S2
Definition: reg.h:219
#define AR_ISR_S2_CABEND
Definition: reg.h:225
#define AR_ISR_S2_DTIMSYNC
Definition: reg.h:226
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define AR_ISR_TXERR
Definition: reg.h:182
#define AR_ISR_S1_QCU_TXEOL
Definition: reg.h:343
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_INTR_MAC_IRQ
Definition: reg.h:915
#define AR_ISR_RXMINTR
Definition: reg.h:203
#define AR_ISR_BCNMISC
Definition: reg.h:195
#define AR_ISR_GENTMR
Definition: reg.h:200
#define AR_ISR
Definition: reg.h:171
uint8_t ah
Definition: registers.h:85
#define AR_ISR_RXINTM
Definition: reg.h:205
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define AR_ISR_RXERR
Definition: reg.h:176
#define AR_RC
Definition: reg.h:693
uint32_t u32
Definition: stdint.h:23
#define AR_ISR_S2_TIM
Definition: reg.h:224

References ah, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_CAUSE_CLR, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_HOST1_FATAL, AR_INTR_SYNC_HOST1_PERR, AR_INTR_SYNC_LOCAL_TIMEOUT, AR_INTR_SYNC_RADM_CPL_TIMEOUT, AR_ISR, AR_ISR_BCNMISC, AR_ISR_GENTMR, AR_ISR_RAC, AR_ISR_RXERR, AR_ISR_RXINTM, AR_ISR_RXMINTR, AR_ISR_RXOK, AR_ISR_RXORN, AR_ISR_S0_QCU_TXDESC, AR_ISR_S0_QCU_TXOK, AR_ISR_S0_S, AR_ISR_S1_QCU_TXEOL, AR_ISR_S1_QCU_TXERR, AR_ISR_S1_S, AR_ISR_S2, AR_ISR_S2_CABEND, AR_ISR_S2_CST, AR_ISR_S2_DTIM, AR_ISR_S2_DTIMSYNC, AR_ISR_S2_GTT, AR_ISR_S2_TIM, AR_ISR_S2_TSFOOR, AR_ISR_S5_GENTIMER_THRESH, AR_ISR_S5_GENTIMER_TRIG, AR_ISR_S5_S, AR_ISR_S5_TIM_TIMER, AR_ISR_TXDESC, AR_ISR_TXEOL, AR_ISR_TXERR, AR_ISR_TXOK, AR_RC, AR_RC_HOSTIF, AR_RTC_STATUS, AR_RTC_STATUS_M, AR_RTC_STATUS_ON, AR_SREV_9100, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_INT_CABEND, ATH9K_INT_COMMON, ATH9K_INT_CST, ATH9K_INT_DTIM, ATH9K_INT_DTIMSYNC, ATH9K_INT_FATAL, ATH9K_INT_GENTIMER, ATH9K_INT_GTT, ATH9K_INT_RX, ATH9K_INT_TIM, ATH9K_INT_TIM_TIMER, ATH9K_INT_TSFOOR, ATH9K_INT_TX, DBG, ath9k_hw_capabilities::hw_caps, isr, MS, REG_READ, and REG_WRITE.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_fill_txdesc()

static void ar9002_hw_fill_txdesc ( struct ath_hw *ah  __unused,
void *  ds,
u32  seglen,
int  is_firstseg,
int  is_lastseg,
const void *  ds0,
u32  buf_addr,
unsigned int qcu  __unused 
)
static

Definition at line 182 of file ath9k_ar9002_mac.c.

186 {
187  struct ar5416_desc *ads = AR5416DESC(ds);
188 
189  ads->ds_data = buf_addr;
190 
191  if (is_firstseg) {
192  ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
193  } else if (is_lastseg) {
194  ads->ds_ctl0 = 0;
195  ads->ds_ctl1 = seglen;
196  ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
197  ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
198  } else {
199  ads->ds_ctl0 = 0;
200  ads->ds_ctl1 = seglen | AR_TxMore;
201  ads->ds_ctl2 = 0;
202  ads->ds_ctl3 = 0;
203  }
204  ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
205  ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
206  ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
207  ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
208  ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
209 }
u32 ds_ctl0
Definition: mac.h:279
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
uint32_t ds
Definition: librm.h:254
#define AR5416DESC_CONST(_ds)
Definition: mac.h:319
#define AR_TxMore
Definition: mac.h:366
u32 ds_data
Definition: mac.h:278

References AR5416DESC, AR5416DESC_CONST, AR_TxMore, ds, ar5416_desc::ds_ctl0, ar5416_desc::ds_ctl1, and ar5416_desc::ds_data.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_proc_txdesc()

static int ar9002_hw_proc_txdesc ( struct ath_hw ah,
void *  ds,
struct ath_tx_status ts 
)
static

Definition at line 211 of file ath9k_ar9002_mac.c.

213 {
214  struct ar5416_desc *ads = AR5416DESC(ds);
215  u32 status;
216 
217  status = *(volatile typeof(ads->ds_txstatus9) *)&(ads->ds_txstatus9);
218  if ((status & AR_TxDone) == 0)
219  return -EINPROGRESS;
220 
221  ts->ts_tstamp = ads->AR_SendTimestamp;
222  ts->ts_status = 0;
223  ts->ts_flags = 0;
224 
225  if (status & AR_TxOpExceeded)
227  ts->tid = MS(status, AR_TxTid);
229  ts->ts_seqnum = MS(status, AR_SeqNum);
230 
231  status = *(volatile typeof(ads->ds_txstatus0) *)&(ads->ds_txstatus0);
235  if (status & AR_TxBaStatus) {
236  ts->ts_flags |= ATH9K_TX_BA;
237  ts->ba_low = ads->AR_BaBitmapLow;
238  ts->ba_high = ads->AR_BaBitmapHigh;
239  }
240 
241  status = *(volatile typeof(ads->ds_txstatus1) *)&(ads->ds_txstatus1);
242  if (status & AR_FrmXmitOK)
243  ts->ts_status |= ATH9K_TX_ACKED;
244  else {
247  if (status & AR_Filtered)
249  if (status & AR_FIFOUnderrun) {
252  }
253  }
256  if (status & AR_DescCfgErr)
258  if (status & AR_TxDataUnderrun) {
261  }
262  if (status & AR_TxDelimUnderrun) {
265  }
269 
270  status = *(volatile typeof(ads->ds_txstatus5) *)&(ads->ds_txstatus5);
275 
276  ts->evm0 = ads->AR_TxEVM0;
277  ts->evm1 = ads->AR_TxEVM1;
278  ts->evm2 = ads->AR_TxEVM2;
279 
280  return 0;
281 }
#define ATH9K_TX_DATA_UNDERRUN
Definition: mac.h:96
u8 ts_flags
Definition: mac.h:119
u8 ts_longretry
Definition: mac.h:117
int8_t ts_rssi_ext1
Definition: mac.h:124
#define ATH9K_TXERR_FILT
Definition: mac.h:84
#define AR_TxRSSIAnt10
Definition: mac.h:482
#define AR_VirtRetryCnt
Definition: mac.h:470
u32 evm0
Definition: mac.h:131
int8_t ts_rssi_ctl1
Definition: mac.h:121
#define AR_TxRSSIAnt12
Definition: mac.h:486
int8_t ts_rssi
Definition: mac.h:115
#define MS(_v, _f)
Definition: hw.h:102
u8 ts_status
Definition: mac.h:113
#define AR_TxRSSIAnt01
Definition: mac.h:449
u16 ts_seqnum
Definition: mac.h:112
#define AR_TxDone
Definition: mac.h:498
u8 ts_rateindex
Definition: mac.h:114
uint8_t status
Status.
Definition: ena.h:16
u8 tid
Definition: mac.h:128
#define ATH9K_TX_BA
Definition: mac.h:93
#define AR_TxOpExceeded
Definition: mac.h:502
#define AR_TxDelimUnderrun
Definition: mac.h:472
#define AR_TxTid
Definition: mac.h:491
#define AR_TxRSSICombined
Definition: mac.h:488
#define AR5416DESC(_ds)
Definition: mac.h:318
int8_t ts_rssi_ext0
Definition: mac.h:123
int8_t ts_rssi_ctl0
Definition: mac.h:120
u32 ba_high
Definition: mac.h:130
#define ATH9K_TX_DESC_CFG_ERR
Definition: mac.h:95
#define EINPROGRESS
Operation in progress.
Definition: errno.h:418
#define ATH9K_TX_ACKED
Definition: mac.h:88
u8 ts_shortretry
Definition: mac.h:116
u32 evm2
Definition: mac.h:133
#define AR_TxRSSIAnt02
Definition: mac.h:451
#define AR_SeqNum
Definition: mac.h:499
u32 ts_tstamp
Definition: mac.h:111
#define AR_FinalTxIdx
Definition: mac.h:504
int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
Definition: ath9k_mac.c:101
#define AR_RTSFailCnt
Definition: mac.h:466
#define AR_Filtered
Definition: mac.h:465
uint32_t ds
Definition: librm.h:254
#define ATH9K_TXERR_FIFO
Definition: mac.h:85
#define AR_TxRSSIAnt00
Definition: mac.h:447
int8_t ts_rssi_ext2
Definition: mac.h:125
#define AR_ExcessiveRetries
Definition: mac.h:463
u32 evm1
Definition: mac.h:132
#define AR_TxDataUnderrun
Definition: mac.h:473
#define ATH9K_TX_DELIM_UNDERRUN
Definition: mac.h:97
#define ATH9K_TXERR_XTXOP
Definition: mac.h:86
#define ATH9K_TXERR_TIMER_EXPIRED
Definition: mac.h:87
#define AR_TxRSSIAnt11
Definition: mac.h:484
#define AR_TxTimerExpired
Definition: mac.h:475
#define AR_FrmXmitOK
Definition: mac.h:462
uint8_t ah
Definition: registers.h:85
#define AR_DescCfgErr
Definition: mac.h:474
#define AR_DataFailCnt
Definition: mac.h:468
int8_t ts_rssi_ctl2
Definition: mac.h:122
#define AR_TxBaStatus
Definition: mac.h:454
#define ATH9K_TXERR_XRETRY
Definition: mac.h:83
u32 ba_low
Definition: mac.h:129
u8 ts_virtcol
Definition: mac.h:118
uint32_t u32
Definition: stdint.h:23
#define AR_FIFOUnderrun
Definition: mac.h:464

References ah, AR5416DESC, AR_DataFailCnt, AR_DescCfgErr, AR_ExcessiveRetries, AR_FIFOUnderrun, AR_Filtered, AR_FinalTxIdx, AR_FrmXmitOK, AR_RTSFailCnt, AR_SeqNum, AR_TxBaStatus, AR_TxDataUnderrun, AR_TxDelimUnderrun, AR_TxDone, AR_TxOpExceeded, AR_TxRSSIAnt00, AR_TxRSSIAnt01, AR_TxRSSIAnt02, AR_TxRSSIAnt10, AR_TxRSSIAnt11, AR_TxRSSIAnt12, AR_TxRSSICombined, AR_TxTid, AR_TxTimerExpired, AR_VirtRetryCnt, ath9k_hw_updatetxtriglevel(), ATH9K_TX_ACKED, ATH9K_TX_BA, ATH9K_TX_DATA_UNDERRUN, ATH9K_TX_DELIM_UNDERRUN, ATH9K_TX_DESC_CFG_ERR, ATH9K_TXERR_FIFO, ATH9K_TXERR_FILT, ATH9K_TXERR_TIMER_EXPIRED, ATH9K_TXERR_XRETRY, ATH9K_TXERR_XTXOP, ath_tx_status::ba_high, ath_tx_status::ba_low, ds, EINPROGRESS, ath_tx_status::evm0, ath_tx_status::evm1, ath_tx_status::evm2, MS, status, ath_tx_status::tid, ath_tx_status::ts_flags, ath_tx_status::ts_longretry, ath_tx_status::ts_rateindex, ath_tx_status::ts_rssi, ath_tx_status::ts_rssi_ctl0, ath_tx_status::ts_rssi_ctl1, ath_tx_status::ts_rssi_ctl2, ath_tx_status::ts_rssi_ext0, ath_tx_status::ts_rssi_ext1, ath_tx_status::ts_rssi_ext2, ath_tx_status::ts_seqnum, ath_tx_status::ts_shortretry, ath_tx_status::ts_status, ath_tx_status::ts_tstamp, and ath_tx_status::ts_virtcol.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set11n_txdesc()

static void ar9002_hw_set11n_txdesc ( struct ath_hw ah,
void *  ds,
u32  pktLen,
enum ath9k_pkt_type  type,
u32  txPower,
u32  keyIx,
enum ath9k_key_type  keyType,
u32  flags 
)
static

Definition at line 283 of file ath9k_ar9002_mac.c.

287 {
288  struct ar5416_desc *ads = AR5416DESC(ds);
289 
290  if (txPower > 63)
291  txPower = 63;
292 
293  ads->ds_ctl0 = (pktLen & AR_FrameLen)
295  | SM(txPower, AR_XmitPower)
296  | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
298  | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
299 
300  ads->ds_ctl1 =
301  (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
302  | SM(type, AR_FrameType)
303  | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
306 
307  ads->ds_ctl6 = SM(keyType, AR_EncrType);
308 
309  if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
310  ads->ds_ctl8 = 0;
311  ads->ds_ctl9 = 0;
312  ads->ds_ctl10 = 0;
313  ads->ds_ctl11 = 0;
314  }
315 }
#define ATH9K_TXDESC_NOACK
Definition: mac.h:249
u32 ds_ctl0
Definition: mac.h:279
#define ATH9K_TXDESC_EXT_ONLY
Definition: mac.h:267
#define ATH9K_TXDESC_VEOL
Definition: mac.h:266
uint8_t type
Type.
Definition: ena.h:16
#define AR_TxIntrReq
Definition: mac.h:362
#define ATH9K_TXDESC_EXT_AND_CTL
Definition: mac.h:268
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define AR_ExtAndCtl
Definition: mac.h:375
#define ATH9K_TXDESC_INTREQ
Definition: mac.h:265
#define AR_EncrType
Definition: mac.h:419
#define AR_FrameType
Definition: mac.h:369
#define AR_DestIdxValid
Definition: mac.h:363
#define AR_NoAck
Definition: mac.h:371
#define SM(_v, _f)
Definition: hw.h:101
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
#define AR_FrameLen
Definition: mac.h:353
#define AR_VirtMoreFrag
Definition: mac.h:354
uint32_t ds
Definition: librm.h:254
#define AR_DestIdx
Definition: mac.h:367
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define ATH9K_TXDESC_VMF
Definition: mac.h:269
#define AR_ExtOnly
Definition: mac.h:374
uint8_t ah
Definition: registers.h:85
#define AR_XmitPower
Definition: mac.h:356
#define AR_VEOL
Definition: mac.h:359
#define ATH9K_TXKEYIX_INVALID
Definition: mac.h:204
uint8_t flags
Flags.
Definition: ena.h:18

References ah, AR5416DESC, AR_DestIdx, AR_DestIdxValid, AR_EncrType, AR_ExtAndCtl, AR_ExtOnly, AR_FrameLen, AR_FrameType, AR_NoAck, AR_SREV_9271, AR_SREV_9285, AR_TxIntrReq, AR_VEOL, AR_VirtMoreFrag, AR_XmitPower, ATH9K_TXDESC_EXT_AND_CTL, ATH9K_TXDESC_EXT_ONLY, ATH9K_TXDESC_INTREQ, ATH9K_TXDESC_NOACK, ATH9K_TXDESC_VEOL, ATH9K_TXDESC_VMF, ATH9K_TXKEYIX_INVALID, ds, ar5416_desc::ds_ctl0, ar5416_desc::ds_ctl1, flags, SM, and type.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set_clrdmask()

static void ar9002_hw_set_clrdmask ( struct ath_hw *ah  __unused,
void *  ds,
int  val 
)
static

Definition at line 317 of file ath9k_ar9002_mac.c.

318 {
319  struct ar5416_desc *ads = AR5416DESC(ds);
320 
321  if (val)
322  ads->ds_ctl0 |= AR_ClrDestMask;
323  else
324  ads->ds_ctl0 &= ~AR_ClrDestMask;
325 }
u32 ds_ctl0
Definition: mac.h:279
#define AR_ClrDestMask
Definition: mac.h:360
#define AR5416DESC(_ds)
Definition: mac.h:318
uint32_t ds
Definition: librm.h:254
void __asmcall int val
Definition: setjmp.h:28

References AR5416DESC, AR_ClrDestMask, ds, ar5416_desc::ds_ctl0, and val.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set11n_ratescenario()

static void ar9002_hw_set11n_ratescenario ( struct ath_hw *ah  __unused,
void *  ds,
void *  lastds,
u32  durUpdateEn,
u32  rtsctsRate,
u32 rtsctsDuration  __unused,
struct ath9k_11n_rate_series  series[],
u32 nseries  __unused,
u32  flags 
)
static

Definition at line 327 of file ath9k_ar9002_mac.c.

333 {
334  struct ar5416_desc *ads = AR5416DESC(ds);
335  struct ar5416_desc *last_ads = AR5416DESC(lastds);
336  u32 ds_ctl0;
337 
339  ds_ctl0 = ads->ds_ctl0;
340 
341  if (flags & ATH9K_TXDESC_RTSENA) {
342  ds_ctl0 &= ~AR_CTSEnable;
344  } else {
345  ds_ctl0 &= ~AR_RTSEnable;
347  }
348 
349  ads->ds_ctl0 = ds_ctl0;
350  } else {
351  ads->ds_ctl0 =
352  (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
353  }
354 
355  ads->ds_ctl2 = set11nTries(series, 0)
356  | set11nTries(series, 1)
357  | set11nTries(series, 2)
358  | set11nTries(series, 3)
359  | (durUpdateEn ? AR_DurUpdateEna : 0)
360  | SM(0, AR_BurstDur);
361 
362  ads->ds_ctl3 = set11nRate(series, 0)
363  | set11nRate(series, 1)
364  | set11nRate(series, 2)
365  | set11nRate(series, 3);
366 
367  ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
368  | set11nPktDurRTSCTS(series, 1);
369 
370  ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
371  | set11nPktDurRTSCTS(series, 3);
372 
373  ads->ds_ctl7 = set11nRateFlags(series, 0)
374  | set11nRateFlags(series, 1)
375  | set11nRateFlags(series, 2)
376  | set11nRateFlags(series, 3)
377  | SM(rtsctsRate, AR_RTSCTSRate);
378  last_ads->ds_ctl2 = ads->ds_ctl2;
379  last_ads->ds_ctl3 = ads->ds_ctl3;
380 }
u32 ds_ctl0
Definition: mac.h:279
#define ATH9K_TXDESC_CTSENA
Definition: mac.h:251
#define AR_RTSCTSRate
Definition: mac.h:440
#define AR_RTSEnable
Definition: mac.h:358
#define AR_DurUpdateEna
Definition: mac.h:381
#define set11nTries(_series, _index)
Definition: mac.h:31
#define set11nRate(_series, _index)
Definition: mac.h:34
#define set11nRateFlags(_series, _index)
Definition: mac.h:42
#define set11nPktDurRTSCTS(_series, _index)
Definition: mac.h:37
#define SM(_v, _f)
Definition: hw.h:101
#define AR_BurstDur
Definition: mac.h:379
#define AR5416DESC(_ds)
Definition: mac.h:318
#define ATH9K_TXDESC_RTSENA
Definition: mac.h:250
uint32_t ds
Definition: librm.h:254
uint32_t u32
Definition: stdint.h:23
#define AR_CTSEnable
Definition: mac.h:364
uint8_t flags
Flags.
Definition: ena.h:18

References AR5416DESC, AR_BurstDur, AR_CTSEnable, AR_DurUpdateEna, AR_RTSCTSRate, AR_RTSEnable, ATH9K_TXDESC_CTSENA, ATH9K_TXDESC_RTSENA, ds, ar5416_desc::ds_ctl0, flags, set11nPktDurRTSCTS, set11nRate, set11nRateFlags, set11nTries, and SM.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set11n_aggr_first()

static void ar9002_hw_set11n_aggr_first ( struct ath_hw *ah  __unused,
void *  ds,
u32  aggrLen 
)
static

Definition at line 382 of file ath9k_ar9002_mac.c.

384 {
385  struct ar5416_desc *ads = AR5416DESC(ds);
386 
387  ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
388  ads->ds_ctl6 &= ~AR_AggrLen;
389  ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
390 }
#define AR_IsAggr
Definition: mac.h:377
#define AR_MoreAggr
Definition: mac.h:376
#define SM(_v, _f)
Definition: hw.h:101
#define AR5416DESC(_ds)
Definition: mac.h:318
#define AR_AggrLen
Definition: mac.h:414
u32 ds_ctl1
Definition: mac.h:280
uint32_t ds
Definition: librm.h:254

References AR5416DESC, AR_AggrLen, AR_IsAggr, AR_MoreAggr, ds, ar5416_desc::ds_ctl1, and SM.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set11n_aggr_middle()

static void ar9002_hw_set11n_aggr_middle ( struct ath_hw *ah  __unused,
void *  ds,
u32  numDelims 
)
static

Definition at line 392 of file ath9k_ar9002_mac.c.

394 {
395  struct ar5416_desc *ads = AR5416DESC(ds);
396  unsigned int ctl6;
397 
398  ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
399 
400  ctl6 = ads->ds_ctl6;
401  ctl6 &= ~AR_PadDelim;
402  ctl6 |= SM(numDelims, AR_PadDelim);
403  ads->ds_ctl6 = ctl6;
404 }
#define AR_IsAggr
Definition: mac.h:377
#define AR_PadDelim
Definition: mac.h:417
#define AR_MoreAggr
Definition: mac.h:376
#define SM(_v, _f)
Definition: hw.h:101
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
u32 ctl6
Definition: mac.h:287
uint32_t ds
Definition: librm.h:254

References AR5416DESC, AR_IsAggr, AR_MoreAggr, AR_PadDelim, ar5416_desc::ctl6, ds, ar5416_desc::ds_ctl1, and SM.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_set11n_aggr_last()

static void ar9002_hw_set11n_aggr_last ( struct ath_hw *ah  __unused,
void *  ds 
)
static

Definition at line 406 of file ath9k_ar9002_mac.c.

407 {
408  struct ar5416_desc *ads = AR5416DESC(ds);
409 
410  ads->ds_ctl1 |= AR_IsAggr;
411  ads->ds_ctl1 &= ~AR_MoreAggr;
412  ads->ds_ctl6 &= ~AR_PadDelim;
413 }
#define AR_IsAggr
Definition: mac.h:377
#define AR_PadDelim
Definition: mac.h:417
#define AR_MoreAggr
Definition: mac.h:376
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
uint32_t ds
Definition: librm.h:254

References AR5416DESC, AR_IsAggr, AR_MoreAggr, AR_PadDelim, ds, and ar5416_desc::ds_ctl1.

Referenced by ar9002_hw_attach_mac_ops().

◆ ar9002_hw_clr11n_aggr()

static void ar9002_hw_clr11n_aggr ( struct ath_hw *ah  __unused,
void *  ds 
)
static

Definition at line 415 of file ath9k_ar9002_mac.c.

416 {
417  struct ar5416_desc *ads = AR5416DESC(ds);
418 
419  ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
420 }
#define AR_IsAggr
Definition: mac.h:377
#define AR_MoreAggr
Definition: mac.h:376
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
uint32_t ds
Definition: librm.h:254

References AR5416DESC, AR_IsAggr, AR_MoreAggr, ds, and ar5416_desc::ds_ctl1.

Referenced by ar9002_hw_attach_mac_ops().

◆ ath9k_hw_setuprxdesc()

void ath9k_hw_setuprxdesc ( struct ath_hw ah,
struct ath_desc ds,
u32  size,
u32  flags 
)

Definition at line 422 of file ath9k_ar9002_mac.c.

424 {
425  struct ar5416_desc *ads = AR5416DESC(ds);
426  struct ath9k_hw_capabilities *pCap = &ah->caps;
427 
428  ads->ds_ctl1 = size & AR_BufLen;
430  ads->ds_ctl1 |= AR_RxIntrReq;
431 
432  ads->ds_rxstatus8 &= ~AR_RxDone;
433  if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
434  memset(&(ads->u), 0, sizeof(ads->u));
435 }
#define AR_RxDone
Definition: mac.h:555
#define AR5416DESC(_ds)
Definition: mac.h:318
u32 ds_ctl1
Definition: mac.h:280
uint32_t ds
Definition: librm.h:254
#define ATH9K_RXDESC_INTREQ
Definition: mac.h:274
#define AR_RxIntrReq
Definition: mac.h:513
#define AR_BufLen
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
uint8_t ah
Definition: registers.h:85
union ar5416_desc::@32 u
void * memset(void *dest, int character, size_t len) __nonnull
uint8_t flags
Flags.
Definition: ena.h:18

References ah, AR5416DESC, AR_BufLen, AR_RxDone, AR_RxIntrReq, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_RXDESC_INTREQ, ds, ar5416_desc::ds_ctl1, flags, ath9k_hw_capabilities::hw_caps, memset(), size, and ar5416_desc::u.

Referenced by ath_rx_buf_link().

◆ ar9002_hw_attach_mac_ops()

void ar9002_hw_attach_mac_ops ( struct ath_hw ah)

Definition at line 437 of file ath9k_ar9002_mac.c.

438 {
439  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
440 
444  ops->get_isr = ar9002_hw_get_isr;
454 }
static void ar9002_hw_clr11n_aggr(struct ath_hw *ah __unused, void *ds)
static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah __unused, void *ds, u32 numDelims)
static void ar9002_hw_rx_enable(struct ath_hw *ah)
void(* rx_enable)(struct ath_hw *ah)
Definition: hw.h:607
static void ar9002_hw_fill_txdesc(struct ath_hw *ah __unused, void *ds, u32 seglen, int is_firstseg, int is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu __unused)
void(* clr11n_aggr)(struct ath_hw *ah, void *ds)
Definition: hw.h:637
static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah __unused, void *ds)
void(* set11n_aggr_last)(struct ath_hw *ah, void *ds)
Definition: hw.h:636
static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah __unused, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration __unused, struct ath9k_11n_rate_series series[], u32 nseries __unused, u32 flags)
int(* get_isr)(struct ath_hw *ah, enum ath9k_int *masked)
Definition: hw.h:614
static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
static int ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
void(* set11n_ratescenario)(struct ath_hw *ah, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, struct ath9k_11n_rate_series series[], u32 nseries, u32 flags)
Definition: hw.h:626
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
void(* set11n_txdesc)(struct ath_hw *ah, void *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
Definition: hw.h:621
static void ar9002_hw_set_clrdmask(struct ath_hw *ah __unused, void *ds, int val)
static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_status *ts)
void(* set_clrdmask)(struct ath_hw *ah, void *ds, int val)
Definition: hw.h:638
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
int(* proc_txdesc)(struct ath_hw *ah, void *ds, struct ath_tx_status *ts)
Definition: hw.h:619
static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah __unused, void *ds, u32 aggrLen)
void(* set11n_aggr_middle)(struct ath_hw *ah, void *ds, u32 numDelims)
Definition: hw.h:634
void(* set11n_aggr_first)(struct ath_hw *ah, void *ds, u32 aggrLen)
Definition: hw.h:632
uint8_t ah
Definition: registers.h:85
static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
void(* fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, int is_firstseg, int is_is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu)
Definition: hw.h:615
void(* get_desc_link)(void *ds, u32 **link)
Definition: hw.h:609
void(* set_desc_link)(void *ds, u32 link)
Definition: hw.h:608

References ah, ar9002_hw_clr11n_aggr(), ar9002_hw_fill_txdesc(), ar9002_hw_get_desc_link(), ar9002_hw_get_isr(), ar9002_hw_proc_txdesc(), ar9002_hw_rx_enable(), ar9002_hw_set11n_aggr_first(), ar9002_hw_set11n_aggr_last(), ar9002_hw_set11n_aggr_middle(), ar9002_hw_set11n_ratescenario(), ar9002_hw_set11n_txdesc(), ar9002_hw_set_clrdmask(), ar9002_hw_set_desc_link(), ath9k_hw_ops(), ath_hw_ops::clr11n_aggr, ath_hw_ops::fill_txdesc, ath_hw_ops::get_desc_link, ath_hw_ops::get_isr, ath_hw_ops::proc_txdesc, ath_hw_ops::rx_enable, ath_hw_ops::set11n_aggr_first, ath_hw_ops::set11n_aggr_last, ath_hw_ops::set11n_aggr_middle, ath_hw_ops::set11n_ratescenario, ath_hw_ops::set11n_txdesc, ath_hw_ops::set_clrdmask, and ath_hw_ops::set_desc_link.

Referenced by ar9002_hw_attach_ops().