ath9k_ar9002_mac.c File Reference

#include <ipxe/io.h>
#include "hw.h"

Go to the source code of this file.

Macros
#define	AR_BufLen   0x00000fff

Functions
	FILE_SECBOOT (FORBIDDEN)
static void	ar9002_hw_rx_enable (struct ath_hw *ah)
static void	ar9002_hw_set_desc_link (void *ds, u32 ds_link)
static void	ar9002_hw_get_desc_link (void *ds, u32 **ds_link)
static int	ar9002_hw_get_isr (struct ath_hw *ah, enum ath9k_int *masked)
static void	ar9002_hw_fill_txdesc (struct ath_hw *ah __unused, void *ds, u32 seglen, int is_firstseg, int is_lastseg, const void *ds0, u32 buf_addr, unsigned int qcu __unused)
static int	ar9002_hw_proc_txdesc (struct ath_hw *ah, void *ds, struct ath_tx_status *ts)
static void	ar9002_hw_set11n_txdesc (struct ath_hw *ah, void *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags)
static void	ar9002_hw_set_clrdmask (struct ath_hw *ah __unused, void *ds, int val)
static void	ar9002_hw_set11n_ratescenario (struct ath_hw *ah __unused, void *ds, void *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration __unused, struct ath9k_11n_rate_series series[], u32 nseries __unused, u32 flags)
static void	ar9002_hw_set11n_aggr_first (struct ath_hw *ah __unused, void *ds, u32 aggrLen)
static void	ar9002_hw_set11n_aggr_middle (struct ath_hw *ah __unused, void *ds, u32 numDelims)
static void	ar9002_hw_set11n_aggr_last (struct ath_hw *ah __unused, void *ds)
static void	ar9002_hw_clr11n_aggr (struct ath_hw *ah __unused, void *ds)
void	ath9k_hw_setuprxdesc (struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags)
void	ar9002_hw_attach_mac_ops (struct ath_hw *ah)

Macro Definition Documentation

AR_BufLen

#define AR_BufLen   0x00000fff

Definition at line 26 of file ath9k_ar9002_mac.c.

Function Documentation

FILE_SECBOOT()

FILE_SECBOOT

(

FORBIDDEN

)

ar9002_hw_rx_enable()

void ar9002_hw_rx_enable ( struct ath_hw * ah )

static

Definition at line 28 of file ath9k_ar9002_mac.c.

{
        REG_WRITE(ah, AR_CR, AR_CR_RXE);
}

References ah, AR_CR, AR_CR_RXE, and REG_WRITE.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set_desc_link()

void ar9002_hw_set_desc_link ( void * ds, u32 ds_link )

static

Definition at line 33 of file ath9k_ar9002_mac.c.

{
        ((struct ath_desc*) ds)->ds_link = ds_link;
}

References ds, ds_link, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_get_desc_link()

void ar9002_hw_get_desc_link ( void * ds, u32 ** ds_link )

static

Definition at line 38 of file ath9k_ar9002_mac.c.

{
        *ds_link = &((struct ath_desc *)ds)->ds_link;
}

References ds, ds_link, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_get_isr()

int ar9002_hw_get_isr ( struct ath_hw * ah, enum ath9k_int * masked )

static

Definition at line 43 of file ath9k_ar9002_mac.c.

{
        u32 isr = 0;
        u32 mask2 = 0;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        u32 sync_cause = 0;
        int fatal_int = 0;
 
        if (!AR_SREV_9100(ah) && (ah->ah_ier & AR_IER_ENABLE)) {
                if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
                        if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
                            == AR_RTC_STATUS_ON) {
                                isr = REG_READ(ah, AR_ISR);
                        }
                }
 
                sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
                        AR_INTR_SYNC_DEFAULT;
 
                *masked = 0;
 
                if (!isr && !sync_cause)
                        return 0;
        } else {
                *masked = 0;
                isr = REG_READ(ah, AR_ISR);
        }
 
        if (isr) {
                if (isr & AR_ISR_BCNMISC) {
                        u32 isr2;
                        isr2 = REG_READ(ah, AR_ISR_S2);
                        if (isr2 & AR_ISR_S2_TIM)
                                mask2 |= ATH9K_INT_TIM;
                        if (isr2 & AR_ISR_S2_DTIM)
                                mask2 |= ATH9K_INT_DTIM;
                        if (isr2 & AR_ISR_S2_DTIMSYNC)
                                mask2 |= ATH9K_INT_DTIMSYNC;
                        if (isr2 & (AR_ISR_S2_CABEND))
                                mask2 |= ATH9K_INT_CABEND;
                        if (isr2 & AR_ISR_S2_GTT)
                                mask2 |= ATH9K_INT_GTT;
                        if (isr2 & AR_ISR_S2_CST)
                                mask2 |= ATH9K_INT_CST;
                        if (isr2 & AR_ISR_S2_TSFOOR)
                                mask2 |= ATH9K_INT_TSFOOR;
                }
 
                isr = REG_READ(ah, AR_ISR_RAC);
                if (isr == 0xffffffff) {
                        *masked = 0;
                        return 0;
                }
 
                *masked = isr & ATH9K_INT_COMMON;
 
                if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
                           AR_ISR_RXOK | AR_ISR_RXERR))
                        *masked |= ATH9K_INT_RX;
 
                if (isr &
                    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
                     AR_ISR_TXEOL)) {
                        u32 s0_s, s1_s;
 
                        *masked |= ATH9K_INT_TX;
 
                        s0_s = REG_READ(ah, AR_ISR_S0_S);
                        ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
                        ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
 
                        s1_s = REG_READ(ah, AR_ISR_S1_S);
                        ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
                        ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
                }
 
                if (isr & AR_ISR_RXORN) {
                        DBG("ath9k: "
                                "receive FIFO overrun interrupt\n");
                }
 
                *masked |= mask2;
        }
 
        if (AR_SREV_9100(ah))
                return 1;
 
        if (isr & AR_ISR_GENTMR) {
                u32 s5_s;
 
                s5_s = REG_READ(ah, AR_ISR_S5_S);
                ah->intr_gen_timer_trigger =
                                MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
 
                ah->intr_gen_timer_thresh =
                        MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
 
                if (ah->intr_gen_timer_trigger)
                        *masked |= ATH9K_INT_GENTIMER;
 
                if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
                    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                        *masked |= ATH9K_INT_TIM_TIMER;
        }
 
        if (sync_cause) {
                fatal_int =
                        (sync_cause &
                         (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
                        ? 1 : 0;
 
                if (fatal_int) {
                        if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
                                DBG("ath9k: "
                                        "received PCI FATAL interrupt\n");
                        }
                        if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
                                DBG("ath9k: "
                                        "received PCI PERR interrupt\n");
                        }
                        *masked |= ATH9K_INT_FATAL;
                }
                if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
                        DBG("ath9k: "
                                "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
                        REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                        REG_WRITE(ah, AR_RC, 0);
                        *masked |= ATH9K_INT_FATAL;
                }
                if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
                        DBG("ath9k: "
                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
                }
 
                REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
                (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
        }
 
        return 1;
}

References ah, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_CAUSE_CLR, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_HOST1_FATAL, AR_INTR_SYNC_HOST1_PERR, AR_INTR_SYNC_LOCAL_TIMEOUT, AR_INTR_SYNC_RADM_CPL_TIMEOUT, AR_ISR, AR_ISR_BCNMISC, AR_ISR_GENTMR, AR_ISR_RAC, AR_ISR_RXERR, AR_ISR_RXINTM, AR_ISR_RXMINTR, AR_ISR_RXOK, AR_ISR_RXORN, AR_ISR_S0_QCU_TXDESC, AR_ISR_S0_QCU_TXOK, AR_ISR_S0_S, AR_ISR_S1_QCU_TXEOL, AR_ISR_S1_QCU_TXERR, AR_ISR_S1_S, AR_ISR_S2, AR_ISR_S2_CABEND, AR_ISR_S2_CST, AR_ISR_S2_DTIM, AR_ISR_S2_DTIMSYNC, AR_ISR_S2_GTT, AR_ISR_S2_TIM, AR_ISR_S2_TSFOOR, AR_ISR_S5_GENTIMER_THRESH, AR_ISR_S5_GENTIMER_TRIG, AR_ISR_S5_S, AR_ISR_S5_TIM_TIMER, AR_ISR_TXDESC, AR_ISR_TXEOL, AR_ISR_TXERR, AR_ISR_TXOK, AR_RC, AR_RC_HOSTIF, AR_RTC_STATUS, AR_RTC_STATUS_M, AR_RTC_STATUS_ON, AR_SREV_9100, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_INT_CABEND, ATH9K_INT_COMMON, ATH9K_INT_CST, ATH9K_INT_DTIM, ATH9K_INT_DTIMSYNC, ATH9K_INT_FATAL, ATH9K_INT_GENTIMER, ATH9K_INT_GTT, ATH9K_INT_RX, ATH9K_INT_TIM, ATH9K_INT_TIM_TIMER, ATH9K_INT_TSFOOR, ATH9K_INT_TX, DBG, ath9k_hw_capabilities::hw_caps, isr, MS, REG_READ, REG_WRITE, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_fill_txdesc()

void ar9002_hw_fill_txdesc ( struct ath_hw *ah __unused, void * ds, u32 seglen, int is_firstseg, int is_lastseg, const void * ds0, u32 buf_addr, unsigned int qcu __unused )

static

Definition at line 184 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        ads->ds_data = buf_addr;
 
        if (is_firstseg) {
                ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
        } else if (is_lastseg) {
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = seglen;
                ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
                ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
        } else {
                ads->ds_ctl0 = 0;
                ads->ds_ctl1 = seglen | AR_TxMore;
                ads->ds_ctl2 = 0;
                ads->ds_ctl3 = 0;
        }
        ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
        ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
        ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
        ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
        ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
}

References __unused, ah, AR5416DESC, AR5416DESC_CONST, AR_TxMore, ds, ar5416_desc::ds_ctl0, ar5416_desc::ds_ctl1, ar5416_desc::ds_data, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_proc_txdesc()

int ar9002_hw_proc_txdesc ( struct ath_hw * ah, void * ds, struct ath_tx_status * ts )

static

Definition at line 213 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
        u32 status;
 
        status = *(volatile typeof(ads->ds_txstatus9) *)&(ads->ds_txstatus9);
        if ((status & AR_TxDone) == 0)
                return -EINPROGRESS;
 
        ts->ts_tstamp = ads->AR_SendTimestamp;
        ts->ts_status = 0;
        ts->ts_flags = 0;
 
        if (status & AR_TxOpExceeded)
                ts->ts_status |= ATH9K_TXERR_XTXOP;
        ts->tid = MS(status, AR_TxTid);
        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
        ts->ts_seqnum = MS(status, AR_SeqNum);
 
        status = *(volatile typeof(ads->ds_txstatus0) *)&(ads->ds_txstatus0);
        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
        if (status & AR_TxBaStatus) {
                ts->ts_flags |= ATH9K_TX_BA;
                ts->ba_low = ads->AR_BaBitmapLow;
                ts->ba_high = ads->AR_BaBitmapHigh;
        }
 
        status = *(volatile typeof(ads->ds_txstatus1) *)&(ads->ds_txstatus1);
        if (status & AR_FrmXmitOK)
                ts->ts_status |= ATH9K_TX_ACKED;
        else {
                if (status & AR_ExcessiveRetries)
                        ts->ts_status |= ATH9K_TXERR_XRETRY;
                if (status & AR_Filtered)
                        ts->ts_status |= ATH9K_TXERR_FILT;
                if (status & AR_FIFOUnderrun) {
                        ts->ts_status |= ATH9K_TXERR_FIFO;
                        ath9k_hw_updatetxtriglevel(ah, 1);
                }
        }
        if (status & AR_TxTimerExpired)
                ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
        if (status & AR_DescCfgErr)
                ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
        if (status & AR_TxDataUnderrun) {
                ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                ath9k_hw_updatetxtriglevel(ah, 1);
        }
        if (status & AR_TxDelimUnderrun) {
                ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                ath9k_hw_updatetxtriglevel(ah, 1);
        }
        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
        ts->ts_longretry = MS(status, AR_DataFailCnt);
        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
        status = *(volatile typeof(ads->ds_txstatus5) *)&(ads->ds_txstatus5);
        ts->ts_rssi = MS(status, AR_TxRSSICombined);
        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
        ts->evm0 = ads->AR_TxEVM0;
        ts->evm1 = ads->AR_TxEVM1;
        ts->evm2 = ads->AR_TxEVM2;
 
        return 0;
}

References ah, AR5416DESC, AR_DataFailCnt, AR_DescCfgErr, AR_ExcessiveRetries, AR_FIFOUnderrun, AR_Filtered, AR_FinalTxIdx, AR_FrmXmitOK, AR_RTSFailCnt, AR_SeqNum, AR_TxBaStatus, AR_TxDataUnderrun, AR_TxDelimUnderrun, AR_TxDone, AR_TxOpExceeded, AR_TxRSSIAnt00, AR_TxRSSIAnt01, AR_TxRSSIAnt02, AR_TxRSSIAnt10, AR_TxRSSIAnt11, AR_TxRSSIAnt12, AR_TxRSSICombined, AR_TxTid, AR_TxTimerExpired, AR_VirtRetryCnt, ath9k_hw_updatetxtriglevel(), ATH9K_TX_ACKED, ATH9K_TX_BA, ATH9K_TX_DATA_UNDERRUN, ATH9K_TX_DELIM_UNDERRUN, ATH9K_TX_DESC_CFG_ERR, ATH9K_TXERR_FIFO, ATH9K_TXERR_FILT, ATH9K_TXERR_TIMER_EXPIRED, ATH9K_TXERR_XRETRY, ATH9K_TXERR_XTXOP, ath_tx_status::ba_high, ath_tx_status::ba_low, ds, EINPROGRESS, ath_tx_status::evm0, ath_tx_status::evm1, ath_tx_status::evm2, MS, status, ath_tx_status::tid, ath_tx_status::ts_flags, ath_tx_status::ts_longretry, ath_tx_status::ts_rateindex, ath_tx_status::ts_rssi, ath_tx_status::ts_rssi_ctl0, ath_tx_status::ts_rssi_ctl1, ath_tx_status::ts_rssi_ctl2, ath_tx_status::ts_rssi_ext0, ath_tx_status::ts_rssi_ext1, ath_tx_status::ts_rssi_ext2, ath_tx_status::ts_seqnum, ath_tx_status::ts_shortretry, ath_tx_status::ts_status, ath_tx_status::ts_tstamp, ath_tx_status::ts_virtcol, typeof(), and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set11n_txdesc()

void ar9002_hw_set11n_txdesc ( struct ath_hw * ah, void * ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags )

static

Definition at line 285 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        if (txPower > 63)
                txPower = 63;
 
        ads->ds_ctl0 = (pktLen & AR_FrameLen)
                | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
                | SM(txPower, AR_XmitPower)
                | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
                | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
                | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
 
        ads->ds_ctl1 =
                (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
                | SM(type, AR_FrameType)
                | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
                | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
                | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
 
        ads->ds_ctl6 = SM(keyType, AR_EncrType);
 
        if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
                ads->ds_ctl8 = 0;
                ads->ds_ctl9 = 0;
                ads->ds_ctl10 = 0;
                ads->ds_ctl11 = 0;
        }
}

References ah, AR5416DESC, AR_DestIdx, AR_DestIdxValid, AR_EncrType, AR_ExtAndCtl, AR_ExtOnly, AR_FrameLen, AR_FrameType, AR_NoAck, AR_SREV_9271, AR_SREV_9285, AR_TxIntrReq, AR_VEOL, AR_VirtMoreFrag, AR_XmitPower, ATH9K_TXDESC_EXT_AND_CTL, ATH9K_TXDESC_EXT_ONLY, ATH9K_TXDESC_INTREQ, ATH9K_TXDESC_NOACK, ATH9K_TXDESC_VEOL, ATH9K_TXDESC_VMF, ATH9K_TXKEYIX_INVALID, ds, ar5416_desc::ds_ctl0, ar5416_desc::ds_ctl1, flags, SM, type, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set_clrdmask()

void ar9002_hw_set_clrdmask ( struct ath_hw *ah __unused, void * ds, int val )

static

Definition at line 319 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        if (val)
                ads->ds_ctl0 |= AR_ClrDestMask;
        else
                ads->ds_ctl0 &= ~AR_ClrDestMask;
}

References __unused, ah, AR5416DESC, AR_ClrDestMask, ds, ar5416_desc::ds_ctl0, and val.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set11n_ratescenario()

void ar9002_hw_set11n_ratescenario ( struct ath_hw *ah __unused, void * ds, void * lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration __unused, struct ath9k_11n_rate_series series[], u32 nseries __unused, u32 flags )

static

Definition at line 329 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
        struct ar5416_desc *last_ads = AR5416DESC(lastds);
        u32 ds_ctl0;
 
        if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
                ds_ctl0 = ads->ds_ctl0;
 
                if (flags & ATH9K_TXDESC_RTSENA) {
                        ds_ctl0 &= ~AR_CTSEnable;
                        ds_ctl0 |= AR_RTSEnable;
                } else {
                        ds_ctl0 &= ~AR_RTSEnable;
                        ds_ctl0 |= AR_CTSEnable;
                }
 
                ads->ds_ctl0 = ds_ctl0;
        } else {
                ads->ds_ctl0 =
                        (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
        }
 
        ads->ds_ctl2 = set11nTries(series, 0)
                | set11nTries(series, 1)
                | set11nTries(series, 2)
                | set11nTries(series, 3)
                | (durUpdateEn ? AR_DurUpdateEna : 0)
                | SM(0, AR_BurstDur);
 
        ads->ds_ctl3 = set11nRate(series, 0)
                | set11nRate(series, 1)
                | set11nRate(series, 2)
                | set11nRate(series, 3);
 
        ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
                | set11nPktDurRTSCTS(series, 1);
 
        ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
                | set11nPktDurRTSCTS(series, 3);
 
        ads->ds_ctl7 = set11nRateFlags(series, 0)
                | set11nRateFlags(series, 1)
                | set11nRateFlags(series, 2)
                | set11nRateFlags(series, 3)
                | SM(rtsctsRate, AR_RTSCTSRate);
        last_ads->ds_ctl2 = ads->ds_ctl2;
        last_ads->ds_ctl3 = ads->ds_ctl3;
}

References __unused, ah, AR5416DESC, AR_BurstDur, AR_CTSEnable, AR_DurUpdateEna, AR_RTSCTSRate, AR_RTSEnable, ATH9K_TXDESC_CTSENA, ATH9K_TXDESC_RTSENA, ds, ar5416_desc::ds_ctl0, flags, set11nPktDurRTSCTS, set11nRate, set11nRateFlags, set11nTries, SM, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set11n_aggr_first()

void ar9002_hw_set11n_aggr_first ( struct ath_hw *ah __unused, void * ds, u32 aggrLen )

static

Definition at line 384 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
        ads->ds_ctl6 &= ~AR_AggrLen;
        ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
}

References __unused, ah, AR5416DESC, AR_AggrLen, AR_IsAggr, AR_MoreAggr, ds, ar5416_desc::ds_ctl1, SM, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set11n_aggr_middle()

void ar9002_hw_set11n_aggr_middle ( struct ath_hw *ah __unused, void * ds, u32 numDelims )

static

Definition at line 394 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
        unsigned int ctl6;
 
        ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
 
        ctl6 = ads->ds_ctl6;
        ctl6 &= ~AR_PadDelim;
        ctl6 |= SM(numDelims, AR_PadDelim);
        ads->ds_ctl6 = ctl6;
}

References __unused, ah, AR5416DESC, AR_IsAggr, AR_MoreAggr, AR_PadDelim, ar5416_desc::ctl6, ds, ar5416_desc::ds_ctl1, SM, and u32.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_set11n_aggr_last()

void ar9002_hw_set11n_aggr_last ( struct ath_hw *ah __unused, void * ds )

static

Definition at line 408 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        ads->ds_ctl1 |= AR_IsAggr;
        ads->ds_ctl1 &= ~AR_MoreAggr;
        ads->ds_ctl6 &= ~AR_PadDelim;
}

References __unused, ah, AR5416DESC, AR_IsAggr, AR_MoreAggr, AR_PadDelim, ds, and ar5416_desc::ds_ctl1.

Referenced by ar9002_hw_attach_mac_ops().

ar9002_hw_clr11n_aggr()

void ar9002_hw_clr11n_aggr ( struct ath_hw *ah __unused, void * ds )

static

Definition at line 417 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
 
        ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
}

References __unused, ah, AR5416DESC, AR_IsAggr, AR_MoreAggr, ds, and ar5416_desc::ds_ctl1.

Referenced by ar9002_hw_attach_mac_ops().

ath9k_hw_setuprxdesc()

void ath9k_hw_setuprxdesc	(	struct ath_hw *	ah,
		struct ath_desc *	ds,
		u32	size,
		u32	flags )

Definition at line 424 of file ath9k_ar9002_mac.c.

{
        struct ar5416_desc *ads = AR5416DESC(ds);
        struct ath9k_hw_capabilities *pCap = &ah->caps;
 
        ads->ds_ctl1 = size & AR_BufLen;
        if (flags & ATH9K_RXDESC_INTREQ)
                ads->ds_ctl1 |= AR_RxIntrReq;
 
        ads->ds_rxstatus8 &= ~AR_RxDone;
        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                memset(&(ads->u), 0, sizeof(ads->u));
}

References ah, AR5416DESC, AR_BufLen, AR_RxDone, AR_RxIntrReq, ATH9K_HW_CAP_AUTOSLEEP, ATH9K_RXDESC_INTREQ, ds, ar5416_desc::ds_ctl1, flags, ath9k_hw_capabilities::hw_caps, memset(), size, ar5416_desc::u, and u32.

Referenced by ath_rx_buf_link().

ar9002_hw_attach_mac_ops()

void ar9002_hw_attach_mac_ops

(

struct ath_hw *

ah

)

Definition at line 439 of file ath9k_ar9002_mac.c.

{
        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 
        ops->rx_enable = ar9002_hw_rx_enable;
        ops->set_desc_link = ar9002_hw_set_desc_link;
        ops->get_desc_link = ar9002_hw_get_desc_link;
        ops->get_isr = ar9002_hw_get_isr;
        ops->fill_txdesc = ar9002_hw_fill_txdesc;
        ops->proc_txdesc = ar9002_hw_proc_txdesc;
        ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
        ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
        ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
        ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
        ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
        ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
        ops->set_clrdmask = ar9002_hw_set_clrdmask;
}

References ah, ar9002_hw_clr11n_aggr(), ar9002_hw_fill_txdesc(), ar9002_hw_get_desc_link(), ar9002_hw_get_isr(), ar9002_hw_proc_txdesc(), ar9002_hw_rx_enable(), ar9002_hw_set11n_aggr_first(), ar9002_hw_set11n_aggr_last(), ar9002_hw_set11n_aggr_middle(), ar9002_hw_set11n_ratescenario(), ar9002_hw_set11n_txdesc(), ar9002_hw_set_clrdmask(), ar9002_hw_set_desc_link(), ath9k_hw_ops(), ath_hw_ops::clr11n_aggr, ath_hw_ops::fill_txdesc, ath_hw_ops::get_desc_link, ath_hw_ops::get_isr, ath_hw_ops::proc_txdesc, ath_hw_ops::rx_enable, ath_hw_ops::set11n_aggr_first, ath_hw_ops::set11n_aggr_last, ath_hw_ops::set11n_aggr_middle, ath_hw_ops::set11n_ratescenario, ath_hw_ops::set11n_txdesc, ath_hw_ops::set_clrdmask, and ath_hw_ops::set_desc_link.

Referenced by ar9002_hw_attach_ops().