ath9k_mac.c File Reference

#include <ipxe/io.h>
#include "hw.h"
#include "hw-ops.h"

Go to the source code of this file.

Macros
#define	AH_RX_STOP_DMA_TIMEOUT   10000 /* usec */

Functions
	FILE_SECBOOT (FORBIDDEN)
static void	ath9k_hw_set_txq_interrupts (struct ath_hw *ah, struct ath9k_tx_queue_info *qi __unused)
void	ath9k_hw_puttxbuf (struct ath_hw *ah, u32 q, u32 txdp)
void	ath9k_hw_txstart (struct ath_hw *ah, u32 q)
u32	ath9k_hw_numtxpending (struct ath_hw *ah, u32 q)
int	ath9k_hw_updatetxtriglevel (struct ath_hw *ah, int bIncTrigLevel)
	ath9k_hw_updatetxtriglevel - adjusts the frame trigger level More...
void	ath9k_hw_abort_tx_dma (struct ath_hw *ah)
void	ath9k_hw_gettxintrtxqs (struct ath_hw *ah, u32 *txqs)
int	ath9k_hw_set_txq_props (struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo)
int	ath9k_hw_setuptxqueue (struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo)
int	ath9k_hw_releasetxqueue (struct ath_hw *ah, u32 q)
int	ath9k_hw_resettxqueue (struct ath_hw *ah, u32 q)
int	ath9k_hw_rxprocdesc (struct ath_hw *ah, struct ath_desc *ds, struct ath_rx_status *rs, u64 tsf __unused)
int	ath9k_hw_setrxabort (struct ath_hw *ah, int set)
void	ath9k_hw_putrxbuf (struct ath_hw *ah, u32 rxdp)
void	ath9k_hw_startpcureceive (struct ath_hw *ah, int is_scanning)
void	ath9k_hw_abortpcurecv (struct ath_hw *ah)
int	ath9k_hw_stopdmarecv (struct ath_hw *ah, int *reset)
int	ath9k_hw_intrpend (struct ath_hw *ah)
void	ath9k_hw_disable_interrupts (struct ath_hw *ah)
void	ath9k_hw_enable_interrupts (struct ath_hw *ah)
void	ath9k_hw_set_interrupts (struct ath_hw *ah, unsigned int ints)

Macro Definition Documentation

AH_RX_STOP_DMA_TIMEOUT

#define AH_RX_STOP_DMA_TIMEOUT   10000 /* usec */

Function Documentation

FILE_SECBOOT()

FILE_SECBOOT

(

FORBIDDEN

)

ath9k_hw_set_txq_interrupts()

static void ath9k_hw_set_txq_interrupts ( struct ath_hw *  ah, struct ath9k_tx_queue_info *qi  __unused  )

static

Definition at line 27 of file ath9k_mac.c.

{
        DBG2("ath9k: "
                "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
                ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
                ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
                ah->txurn_interrupt_mask);

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_IMR_S0,
                  SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
                  | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
        REG_WRITE(ah, AR_IMR_S1,
                  SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
                  | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));

        ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
        ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);

        REGWRITE_BUFFER_FLUSH(ah);
}

References ah, AR_IMR_S0, AR_IMR_S0_QCU_TXDESC, AR_IMR_S0_QCU_TXOK, AR_IMR_S1, AR_IMR_S1_QCU_TXEOL, AR_IMR_S1_QCU_TXERR, AR_IMR_S2, AR_IMR_S2_QCU_TXURN, DBG2, ENABLE_REGWRITE_BUFFER, REG_WRITE, REGWRITE_BUFFER_FLUSH, and SM.

Referenced by ath9k_hw_releasetxqueue(), and ath9k_hw_resettxqueue().

ath9k_hw_puttxbuf()

void ath9k_hw_puttxbuf	(	struct ath_hw *	ah,
		u32	q,
		u32	txdp
	)

Definition at line 52 of file ath9k_mac.c.

{
        REG_WRITE(ah, AR_QTXDP(q), txdp);
}

References ah, AR_QTXDP, REG_WRITE, and txdp.

Referenced by ath_tx_txqaddbuf().

ath9k_hw_txstart()

void ath9k_hw_txstart	(	struct ath_hw *	ah,
		u32	q
	)

Definition at line 57 of file ath9k_mac.c.

{
        DBG2("ath9k: "
                "Enable TXE on queue: %d\n", q);
        REG_WRITE(ah, AR_Q_TXE, 1 << q);
}

References ah, AR_Q_TXE, DBG2, and REG_WRITE.

Referenced by ath_tx_txqaddbuf().

ath9k_hw_numtxpending()

u32 ath9k_hw_numtxpending	(	struct ath_hw *	ah,
		u32	q
	)

Definition at line 64 of file ath9k_mac.c.

{
        u32 npend;

        npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
        if (npend == 0) {

                if (REG_READ(ah, AR_Q_TXE) & (1 << q))
                        npend = 1;
        }

        return npend;
}

References ah, AR_Q_STS_PEND_FR_CNT, AR_Q_TXE, AR_QSTS, and REG_READ.

Referenced by ath9k_hw_abort_tx_dma(), ath9k_hw_channel_change(), and ath_drain_all_txq().

ath9k_hw_updatetxtriglevel()

int ath9k_hw_updatetxtriglevel	(	struct ath_hw *	ah,
		int	bIncTrigLevel
	)

ath9k_hw_updatetxtriglevel - adjusts the frame trigger level

@ah: atheros hardware struct @bIncTrigLevel: whether or not the frame trigger level should be updated

The frame trigger level specifies the minimum number of bytes, in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO before the PCU will initiate sending the frame on the air. This can mean we initiate transmit before a full frame is on the PCU TX FIFO. Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs first)

Caution must be taken to ensure to set the frame trigger level based on the DMA request size. For example if the DMA request size is set to 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because there need to be enough space in the tx FIFO for the requested transfer size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set the threshold to a value beyond 6, then the transmit will hang.

Current dual stream devices have a PCU TX FIFO size of 8 KB. Current single stream devices have a PCU TX FIFO size of 4 KB, however, there is a hardware issue which forces us to use 2 KB instead so the frame trigger level must not exceed 2 KB for these chipsets.

Definition at line 103 of file ath9k_mac.c.

{
        u32 txcfg, curLevel, newLevel;

        if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                return 0;

        ath9k_hw_disable_interrupts(ah);

        txcfg = REG_READ(ah, AR_TXCFG);
        curLevel = MS(txcfg, AR_FTRIG);
        newLevel = curLevel;
        if (bIncTrigLevel) {
                if (curLevel < ah->config.max_txtrig_level)
                        newLevel++;
        } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
                newLevel--;
        if (newLevel != curLevel)
                REG_WRITE(ah, AR_TXCFG,
                          (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));

        ath9k_hw_enable_interrupts(ah);

        ah->tx_trig_level = newLevel;

        return newLevel != curLevel;
}

References ah, AR_FTRIG, AR_TXCFG, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), MIN_TX_FIFO_THRESHOLD, MS, REG_READ, REG_WRITE, SM, and txcfg.

Referenced by ar9002_hw_proc_txdesc(), ar9003_hw_proc_txdesc(), and ath_isr().

ath9k_hw_abort_tx_dma()

void ath9k_hw_abort_tx_dma

(

struct ath_hw *

ah

)

Definition at line 131 of file ath9k_mac.c.

{
        int i, q;

        REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);

        REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
        REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);

        for (q = 0; q < AR_NUM_QCU; q++) {
                for (i = 0; i < 1000; i++) {
                        if (i)
                                udelay(5);

                        if (!ath9k_hw_numtxpending(ah, q))
                                break;
                }
        }

        REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
        REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
        REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);

        REG_WRITE(ah, AR_Q_TXD, 0);
}

References ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF, AR_DIAG_FORCE_CH_IDLE_HIGH, AR_DIAG_SW, AR_NUM_QCU, AR_PCU_CLEAR_VMF, AR_PCU_FORCE_QUIET_COLL, AR_PCU_MISC, AR_Q_TXD, AR_Q_TXD_M, ath9k_hw_numtxpending(), REG_CLR_BIT, REG_SET_BIT, REG_WRITE, and udelay().

Referenced by ath_drain_all_txq().

ath9k_hw_gettxintrtxqs()

void ath9k_hw_gettxintrtxqs	(	struct ath_hw *	ah,
		u32 *	txqs
	)

Definition at line 158 of file ath9k_mac.c.

{
        *txqs &= ah->intr_txqs;
        ah->intr_txqs &= ~(*txqs);
}

References ah.

Referenced by ath_tx_tasklet().

ath9k_hw_set_txq_props()

int ath9k_hw_set_txq_props	(	struct ath_hw *	ah,
		int	q,
		const struct ath9k_tx_queue_info *	qinfo
	)

Definition at line 164 of file ath9k_mac.c.

{
        u32 cw;
        struct ath9k_tx_queue_info *qi;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Set TXQ properties, inactive queue: %d\n", q);
                return 0;
        }

        DBG2("ath9k: Set queue properties for: %d\n", q);

        qi->tqi_ver = qinfo->tqi_ver;
        qi->tqi_subtype = qinfo->tqi_subtype;
        qi->tqi_qflags = qinfo->tqi_qflags;
        qi->tqi_priority = qinfo->tqi_priority;
        if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
                qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
        else
                qi->tqi_aifs = INIT_AIFS;
        if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
                cw = min(qinfo->tqi_cwmin, 1024U);
                qi->tqi_cwmin = 1;
                while (qi->tqi_cwmin < cw)
                        qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
        } else
                qi->tqi_cwmin = qinfo->tqi_cwmin;
        if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
                cw = min(qinfo->tqi_cwmax, 1024U);
                qi->tqi_cwmax = 1;
                while (qi->tqi_cwmax < cw)
                        qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
        } else
                qi->tqi_cwmax = INIT_CWMAX;

        if (qinfo->tqi_shretry != 0)
                qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
        else
                qi->tqi_shretry = INIT_SH_RETRY;
        if (qinfo->tqi_lgretry != 0)
                qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
        else
                qi->tqi_lgretry = INIT_LG_RETRY;
        qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
        qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
        qi->tqi_burstTime = qinfo->tqi_burstTime;
        qi->tqi_readyTime = qinfo->tqi_readyTime;

        return 1;
}

References ah, ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, min, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_priority, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_subtype, ath9k_tx_queue_info::tqi_type, and ath9k_tx_queue_info::tqi_ver.

Referenced by ath9k_hw_setuptxqueue().

ath9k_hw_setuptxqueue()

int ath9k_hw_setuptxqueue	(	struct ath_hw *	ah,
		enum ath9k_tx_queue	type,
		const struct ath9k_tx_queue_info *	qinfo
	)

Definition at line 218 of file ath9k_mac.c.

{
        struct ath9k_tx_queue_info *qi;
        int q;

        for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
                if (ah->txq[q].tqi_type ==
                    ATH9K_TX_QUEUE_INACTIVE)
                        break;
        if (q == ATH9K_NUM_TX_QUEUES) {
                DBG("No available TX queue\n");
                return -1;
        }

        DBG2("ath9K: Setup TX queue: %d\n", q);

        qi = &ah->txq[q];
        if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: TX queue: %d already active\n", q);
                return -1;
        }
        memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
        qi->tqi_type = type;
        if (qinfo == NULL) {
                qi->tqi_qflags =
                        TXQ_FLAG_TXOKINT_ENABLE
                        | TXQ_FLAG_TXERRINT_ENABLE
                        | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
                qi->tqi_aifs = INIT_AIFS;
                qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
                qi->tqi_cwmax = INIT_CWMAX;
                qi->tqi_shretry = INIT_SH_RETRY;
                qi->tqi_lgretry = INIT_LG_RETRY;
                qi->tqi_physCompBuf = 0;
        } else {
                qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
                (void) ath9k_hw_set_txq_props(ah, q, qinfo);
        }

        return q;
}

References ah, ath9k_hw_set_txq_props(), ATH9K_NUM_TX_QUEUES, ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USEDEFAULT, DBG, DBG2, INIT_AIFS, INIT_CWMAX, INIT_LG_RETRY, INIT_SH_RETRY, memset(), NULL, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_lgretry, ath9k_tx_queue_info::tqi_physCompBuf, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, and type.

Referenced by ath_txq_setup().

ath9k_hw_releasetxqueue()

int ath9k_hw_releasetxqueue	(	struct ath_hw *	ah,
		u32	q
	)

Definition at line 261 of file ath9k_mac.c.

{
        struct ath9k_tx_queue_info *qi;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Release TXQ, inactive queue: %d\n", q);
                return 0;
        }

        DBG2("ath9k: Release TX queue: %d\n", q);

        qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
        ah->txok_interrupt_mask &= ~(1 << q);
        ah->txerr_interrupt_mask &= ~(1 << q);
        ah->txdesc_interrupt_mask &= ~(1 << q);
        ah->txeol_interrupt_mask &= ~(1 << q);
        ah->txurn_interrupt_mask &= ~(1 << q);
        ath9k_hw_set_txq_interrupts(ah, qi);

        return 1;
}

References ah, ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, DBG, DBG2, and ath9k_tx_queue_info::tqi_type.

Referenced by ath_tx_cleanupq(), and ath_txq_setup().

ath9k_hw_resettxqueue()

int ath9k_hw_resettxqueue	(	struct ath_hw *	ah,
		u32	q
	)

Definition at line 285 of file ath9k_mac.c.

{
        struct ath9k_channel *chan = ah->curchan;
        struct ath9k_tx_queue_info *qi;
        u32 cwMin, chanCwMin, value __unused;

        qi = &ah->txq[q];
        if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
                DBG("ath9k: "
                        "Reset TXQ, inactive queue: %d\n", q);
                return 1;
        }

        DBG2("ath9k: Reset TX queue: %d\n", q);

        if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                if (chan && IS_CHAN_B(chan))
                        chanCwMin = INIT_CWMIN_11B;
                else
                        chanCwMin = INIT_CWMIN;

                for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
        } else
                cwMin = qi->tqi_cwmin;

        ENABLE_REGWRITE_BUFFER(ah);

        REG_WRITE(ah, AR_DLCL_IFS(q),
                  SM(cwMin, AR_D_LCL_IFS_CWMIN) |
                  SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
                  SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));

        REG_WRITE(ah, AR_DRETRY_LIMIT(q),
                  SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
                  SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
                  SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));

        REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);

        if (AR_SREV_9340(ah))
                REG_WRITE(ah, AR_DMISC(q),
                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
        else
                REG_WRITE(ah, AR_DMISC(q),
                          AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);

        if (qi->tqi_cbrPeriod) {
                REG_WRITE(ah, AR_QCBRCFG(q),
                          SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
                          SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
                            (qi->tqi_cbrOverflowLimit ?
                             AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
        }
        if (qi->tqi_readyTime) {
                REG_WRITE(ah, AR_QRDYTIMECFG(q),
                          SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
                          AR_Q_RDYTIMECFG_EN);
        }

        REG_WRITE(ah, AR_DCHNTIME(q),
                  SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
                  (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));

        if (qi->tqi_burstTime
            && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
                REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);

        if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);

        REGWRITE_BUFFER_FLUSH(ah);

        if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
                REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);

        if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
                REG_SET_BIT(ah, AR_DMISC(q),
                            SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
                               AR_D_MISC_ARB_LOCKOUT_CNTRL) |
                            AR_D_MISC_POST_FR_BKOFF_DIS);
        }

        if (AR_SREV_9300_20_OR_LATER(ah))
                REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);

        if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
                ah->txok_interrupt_mask |= 1 << q;
        else
                ah->txok_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
                ah->txerr_interrupt_mask |= 1 << q;
        else
                ah->txerr_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
                ah->txdesc_interrupt_mask |= 1 << q;
        else
                ah->txdesc_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
                ah->txeol_interrupt_mask |= 1 << q;
        else
                ah->txeol_interrupt_mask &= ~(1 << q);
        if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
                ah->txurn_interrupt_mask |= 1 << q;
        else
                ah->txurn_interrupt_mask &= ~(1 << q);
        ath9k_hw_set_txq_interrupts(ah, qi);

        return 1;
}

References __unused, ah, AR_D_CHNTIME_DUR, AR_D_CHNTIME_EN, AR_D_LCL_IFS_AIFS, AR_D_LCL_IFS_CWMAX, AR_D_LCL_IFS_CWMIN, AR_D_MISC_ARB_LOCKOUT_CNTRL, AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, AR_D_MISC_CW_BKOFF_EN, AR_D_MISC_FRAG_BKOFF_EN, AR_D_MISC_FRAG_WAIT_EN, AR_D_MISC_POST_FR_BKOFF_DIS, AR_D_RETRY_LIMIT_FR_SH, AR_D_RETRY_LIMIT_STA_LG, AR_D_RETRY_LIMIT_STA_SH, AR_DCHNTIME, AR_DLCL_IFS, AR_DMISC, AR_DRETRY_LIMIT, AR_Q_CBRCFG_INTERVAL, AR_Q_CBRCFG_OVF_THRESH, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN, AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN, AR_Q_MISC_DCU_EARLY_TERM_REQ, AR_Q_MISC_FSP_CBR, AR_Q_MISC_RDYTIME_EXP_POLICY, AR_Q_RDYTIMECFG_DURATION, AR_Q_RDYTIMECFG_EN, AR_QCBRCFG, AR_QMISC, AR_QRDYTIMECFG, AR_SREV_9300_20_OR_LATER, AR_SREV_9340, ath9k_hw_set_txq_interrupts(), ATH9K_TX_QUEUE_INACTIVE, ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS, ATH9K_TXQ_USEDEFAULT, ath9k_channel::chan, DBG, DBG2, ENABLE_REGWRITE_BUFFER, INIT_CWMIN, INIT_CWMIN_11B, INIT_SLG_RETRY, INIT_SSH_RETRY, IS_CHAN_B, REG_SET_BIT, REG_WRITE, REGWRITE_BUFFER_FLUSH, SM, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_burstTime, ath9k_tx_queue_info::tqi_cbrOverflowLimit, ath9k_tx_queue_info::tqi_cbrPeriod, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_intFlags, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_readyTime, ath9k_tx_queue_info::tqi_shretry, ath9k_tx_queue_info::tqi_type, TXQ_FLAG_BACKOFF_DISABLE, TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXEOLINT_ENABLE, TXQ_FLAG_TXERRINT_ENABLE, TXQ_FLAG_TXOKINT_ENABLE, TXQ_FLAG_TXURNINT_ENABLE, and value.

Referenced by ath9k_hw_reset().

ath9k_hw_rxprocdesc()

int ath9k_hw_rxprocdesc	(	struct ath_hw *	ah,
		struct ath_desc *	ds,
		struct ath_rx_status *	rs,
		u64 tsf	__unused
	)

Definition at line 396 of file ath9k_mac.c.

{
        struct ar5416_desc ads;
        struct ar5416_desc *adsp = AR5416DESC(ds);
        u32 phyerr;

        if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
                return -EINPROGRESS;

        ads.u.rx = adsp->u.rx;

        rs->rs_status = 0;
        rs->rs_flags = 0;

        rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
        rs->rs_tstamp = ads.AR_RcvTimestamp;

        if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
                rs->rs_rssi = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
                rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
        } else {
                rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
                rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt00);
                rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt01);
                rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
                                                AR_RxRSSIAnt02);
                rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt10);
                rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt11);
                rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
                                                AR_RxRSSIAnt12);
        }
        if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
                rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
        else
                rs->rs_keyix = ATH9K_RXKEYIX_INVALID;

        rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
        rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;

        rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
        rs->rs_moreaggr =
                (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
        rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
        rs->rs_flags =
                (ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
        rs->rs_flags |=
                (ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;

        if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
                rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
        if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
                rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
        if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
                rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;

        if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
                /*
                 * Treat these errors as mutually exclusive to avoid spurious
                 * extra error reports from the hardware. If a CRC error is
                 * reported, then decryption and MIC errors are irrelevant,
                 * the frame is going to be dropped either way
                 */
                if (ads.ds_rxstatus8 & AR_CRCErr)
                        rs->rs_status |= ATH9K_RXERR_CRC;
                else if (ads.ds_rxstatus8 & AR_PHYErr) {
                        rs->rs_status |= ATH9K_RXERR_PHY;
                        phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
                        rs->rs_phyerr = phyerr;
                } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
                else if (ads.ds_rxstatus8 & AR_MichaelErr)
                        rs->rs_status |= ATH9K_RXERR_MIC;
                else if (ads.ds_rxstatus8 & AR_KeyMiss)
                        rs->rs_status |= ATH9K_RXERR_DECRYPT;
        }

        return 0;
}

References ah, AR5416DESC, AR_2040, AR_CRCErr, AR_DataLen, AR_DecryptBusyErr, AR_DecryptCRCErr, AR_GI, AR_KeyIdx, AR_KeyMiss, AR_MichaelErr, AR_PHYErr, AR_PHYErrCode, AR_PostDelimCRCErr, AR_PreDelimCRCErr, AR_RxAggr, AR_RxAntenna, AR_RxDone, AR_RxFrameOK, AR_RxKeyIdxValid, AR_RxMore, AR_RxMoreAggr, AR_RxRSSIAnt00, AR_RxRSSIAnt01, AR_RxRSSIAnt02, AR_RxRSSIAnt10, AR_RxRSSIAnt11, AR_RxRSSIAnt12, AR_RxRSSICombined, ATH9K_RSSI_BAD, ATH9K_RX_2040, ATH9K_RX_DECRYPT_BUSY, ATH9K_RX_DELIM_CRC_POST, ATH9K_RX_DELIM_CRC_PRE, ATH9K_RX_GI, ATH9K_RXERR_CRC, ATH9K_RXERR_DECRYPT, ATH9K_RXERR_MIC, ATH9K_RXERR_PHY, ATH9K_RXKEYIX_INVALID, ds, EINPROGRESS, MS, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_flags, ath_rx_status::rs_isaggr, ath_rx_status::rs_keyix, ath_rx_status::rs_more, ath_rx_status::rs_moreaggr, ath_rx_status::rs_phyerr, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_rx_status::rs_rssi_ctl0, ath_rx_status::rs_rssi_ctl1, ath_rx_status::rs_rssi_ctl2, ath_rx_status::rs_rssi_ext0, ath_rx_status::rs_rssi_ext1, ath_rx_status::rs_rssi_ext2, ath_rx_status::rs_status, ath_rx_status::rs_tstamp, ar5416_desc::rx, RXSTATUS_RATE, and ar5416_desc::u.

Referenced by ath_get_next_rx_buf().

ath9k_hw_setrxabort()

int ath9k_hw_setrxabort	(	struct ath_hw *	ah,
		int	set
	)

Definition at line 492 of file ath9k_mac.c.

{
        u32 reg;

        if (set) {
                REG_SET_BIT(ah, AR_DIAG_SW,
                            (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));

                if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
                                   0, AH_WAIT_TIMEOUT)) {
                        REG_CLR_BIT(ah, AR_DIAG_SW,
                                    (AR_DIAG_RX_DIS |
                                     AR_DIAG_RX_ABORT));

                        reg = REG_READ(ah, AR_OBS_BUS_1);
                        DBG("ath9k: "
                                "RX failed to go idle in 10 ms RXSM=0x%x\n",
                                reg);

                        return 0;
                }
        } else {
                REG_CLR_BIT(ah, AR_DIAG_SW,
                            (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
        }

        return 1;
}

References ah, AH_WAIT_TIMEOUT, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, ath9k_hw_wait(), DBG, reg, REG_CLR_BIT, REG_READ, REG_SET_BIT, and set.

Referenced by ath_isr().

ath9k_hw_putrxbuf()

void ath9k_hw_putrxbuf	(	struct ath_hw *	ah,
		u32	rxdp
	)

Definition at line 521 of file ath9k_mac.c.

{
        REG_WRITE(ah, AR_RXDP, rxdp);
}

References ah, AR_RXDP, REG_WRITE, and rxdp.

Referenced by ath_rx_buf_link(), and ath_startrecv().

ath9k_hw_startpcureceive()

void ath9k_hw_startpcureceive	(	struct ath_hw *	ah,
		int	is_scanning
	)

Definition at line 526 of file ath9k_mac.c.

{
        ath9k_ani_reset(ah, is_scanning);

        REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
}

References ah, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, ath9k_ani_reset(), and REG_CLR_BIT.

Referenced by ath_startrecv().

ath9k_hw_abortpcurecv()

void ath9k_hw_abortpcurecv

(

struct ath_hw *

ah

)

Definition at line 533 of file ath9k_mac.c.

{
        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
}

References ah, AR_DIAG_RX_ABORT, AR_DIAG_RX_DIS, AR_DIAG_SW, and REG_SET_BIT.

Referenced by ath_stoprecv().

ath9k_hw_stopdmarecv()

int ath9k_hw_stopdmarecv	(	struct ath_hw *	ah,
		int *	reset
	)

Definition at line 538 of file ath9k_mac.c.

{
#define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
        u32 mac_status, last_mac_status = 0;
        int i;

        /* Enable access to the DMA observation bus */
        REG_WRITE(ah, AR_MACMISC,
                  ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
                   (AR_MACMISC_MISC_OBS_BUS_1 <<
                    AR_MACMISC_MISC_OBS_BUS_MSB_S)));

        REG_WRITE(ah, AR_CR, AR_CR_RXD);

        /* Wait for rx enable bit to go low */
        for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
                if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
                        break;

                if (!AR_SREV_9300_20_OR_LATER(ah)) {
                        mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
                        if (mac_status == 0x1c0 && mac_status == last_mac_status) {
                                *reset = 1;
                                break;
                        }

                        last_mac_status = mac_status;
                }

                udelay(AH_TIME_QUANTUM);
        }

        if (i == 0) {
                DBG("ath9k: "
                        "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
                        AH_RX_STOP_DMA_TIMEOUT / 1000,
                        REG_READ(ah, AR_CR),
                        REG_READ(ah, AR_DIAG_SW),
                        REG_READ(ah, AR_DMADBG_7));
                return 0;
        } else {
                return 1;
        }

#undef AH_RX_STOP_DMA_TIMEOUT
}

References ah, AH_RX_STOP_DMA_TIMEOUT, AH_TIME_QUANTUM, AR_CR, AR_CR_RXD, AR_CR_RXE, AR_DIAG_SW, AR_DMADBG_7, AR_MACMISC, AR_MACMISC_DMA_OBS_LINE_8, AR_MACMISC_DMA_OBS_S, AR_MACMISC_MISC_OBS_BUS_1, AR_MACMISC_MISC_OBS_BUS_MSB_S, AR_SREV_9300_20_OR_LATER, DBG, REG_READ, REG_WRITE, and udelay().

Referenced by ath_stoprecv().

ath9k_hw_intrpend()

int ath9k_hw_intrpend

(

struct ath_hw *

ah

)

Definition at line 585 of file ath9k_mac.c.

{
        u32 host_isr;

        if (AR_SREV_9100(ah) || !(ah->ah_ier & AR_IER_ENABLE))
                return 1;

        host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
        if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
                return 1;

        host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
        if ((host_isr & AR_INTR_SYNC_DEFAULT)
            && (host_isr != AR_INTR_SPURIOUS))
                return 1;

        return 0;
}

References ah, AR_IER_ENABLE, AR_INTR_ASYNC_CAUSE, AR_INTR_MAC_IRQ, AR_INTR_SPURIOUS, AR_INTR_SYNC_CAUSE, AR_INTR_SYNC_DEFAULT, AR_SREV_9100, and REG_READ.

Referenced by ath_isr().

ath9k_hw_disable_interrupts()

void ath9k_hw_disable_interrupts

(

struct ath_hw *

ah

)

Definition at line 604 of file ath9k_mac.c.

{
        DBG2("ath9k: disable IER\n");
        REG_WRITE(ah, AR_IER, ah->ah_ier);
        (void) REG_READ(ah, AR_IER);
        if (!AR_SREV_9100(ah)) {
                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
                (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);

                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
                (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
        }
}

References ah, AR_IER, AR_INTR_ASYNC_ENABLE, AR_INTR_SYNC_ENABLE, AR_SREV_9100, DBG2, REG_READ, and REG_WRITE.

Referenced by ath9k_hw_set_interrupts(), ath9k_hw_updatetxtriglevel(), ath9k_stop(), ath_isr(), ath_radio_disable(), ath_reset(), and ath_set_channel().

ath9k_hw_enable_interrupts()

void ath9k_hw_enable_interrupts

(

struct ath_hw *

ah

)

Definition at line 618 of file ath9k_mac.c.

{
        u32 sync_default = AR_INTR_SYNC_DEFAULT;

        if (!(ah->imask & ATH9K_INT_GLOBAL))
                return;

        if (AR_SREV_9340(ah))
                sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;

        DBG2("ath9k: enable IER\n");
        REG_WRITE(ah, AR_IER, ah->ah_ier);
        if (!AR_SREV_9100(ah)) {
                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
                          AR_INTR_MAC_IRQ);
                REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);


                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
                REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
        }
        DBG2("ath9k: AR_IMR 0x%x IER 0x%x\n",
                REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
}

References ah, AR_IER, AR_IMR, AR_INTR_ASYNC_ENABLE, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ, AR_INTR_SYNC_DEFAULT, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_HOST1_FATAL, AR_INTR_SYNC_MASK, AR_SREV_9100, AR_SREV_9340, ATH9K_INT_GLOBAL, DBG2, REG_READ, and REG_WRITE.

Referenced by ath9k_hw_set_interrupts(), ath9k_hw_updatetxtriglevel(), and ath9k_tasklet().

ath9k_hw_set_interrupts()

void ath9k_hw_set_interrupts	(	struct ath_hw *	ah,
		unsigned int	ints
	)

Definition at line 643 of file ath9k_mac.c.

{
        enum ath9k_int omask = ah->imask;
        u32 mask, mask2;
        struct ath9k_hw_capabilities *pCap = &ah->caps;

        if (!(ints & ATH9K_INT_GLOBAL))
                ath9k_hw_disable_interrupts(ah);

        DBG2("ath9k: 0x%x => 0x%x\n", omask, ints);

        /* TODO: global int Ref count */
        mask = ints & ATH9K_INT_COMMON;
        mask2 = 0;

        if (ints & ATH9K_INT_TX) {
                if (ah->config.tx_intr_mitigation)
                        mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
                else {
                        if (ah->txok_interrupt_mask)
                                mask |= AR_IMR_TXOK;
                        if (ah->txdesc_interrupt_mask)
                                mask |= AR_IMR_TXDESC;
                }
                if (ah->txerr_interrupt_mask)
                        mask |= AR_IMR_TXERR;
                if (ah->txeol_interrupt_mask)
                        mask |= AR_IMR_TXEOL;
        }
        if (ints & ATH9K_INT_RX) {
                if (AR_SREV_9300_20_OR_LATER(ah)) {
                        mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
                        if (ah->config.rx_intr_mitigation) {
                                mask &= ~AR_IMR_RXOK_LP;
                                mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
                        } else {
                                mask |= AR_IMR_RXOK_LP;
                        }
                } else {
                        if (ah->config.rx_intr_mitigation)
                                mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
                        else
                                mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
                }
                if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                        mask |= AR_IMR_GENTMR;
        }

        if (ints & ATH9K_INT_GENTIMER)
                mask |= AR_IMR_GENTMR;

        if (ints & (ATH9K_INT_BMISC)) {
                mask |= AR_IMR_BCNMISC;
                if (ints & ATH9K_INT_TIM)
                        mask2 |= AR_IMR_S2_TIM;
                if (ints & ATH9K_INT_DTIM)
                        mask2 |= AR_IMR_S2_DTIM;
                if (ints & ATH9K_INT_DTIMSYNC)
                        mask2 |= AR_IMR_S2_DTIMSYNC;
                if (ints & ATH9K_INT_CABEND)
                        mask2 |= AR_IMR_S2_CABEND;
                if (ints & ATH9K_INT_TSFOOR)
                        mask2 |= AR_IMR_S2_TSFOOR;
        }

        if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
                mask |= AR_IMR_BCNMISC;
                if (ints & ATH9K_INT_GTT)
                        mask2 |= AR_IMR_S2_GTT;
                if (ints & ATH9K_INT_CST)
                        mask2 |= AR_IMR_S2_CST;
        }

        DBG2("ath9k: new IMR 0x%x\n", mask);
        REG_WRITE(ah, AR_IMR, mask);
        ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                           AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
                           AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
        ah->imrs2_reg |= mask2;
        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);

        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
                if (ints & ATH9K_INT_TIM_TIMER)
                        REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
                else
                        REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
        }

        if (ints & ATH9K_INT_GLOBAL)
                ath9k_hw_enable_interrupts(ah);

        return;
}

References ah, AR_IMR, AR_IMR_BCNMISC, AR_IMR_GENTMR, AR_IMR_RXDESC, AR_IMR_RXERR, AR_IMR_RXINTM, AR_IMR_RXMINTR, AR_IMR_RXOK, AR_IMR_RXOK_HP, AR_IMR_RXOK_LP, AR_IMR_S2, AR_IMR_S2_CABEND, AR_IMR_S2_CABTO, AR_IMR_S2_CST, AR_IMR_S2_DTIM, AR_IMR_S2_DTIMSYNC, AR_IMR_S2_GTT, AR_IMR_S2_TIM, AR_IMR_S2_TSFOOR, AR_IMR_S5, AR_IMR_S5_TIM_TIMER, AR_IMR_TXDESC, AR_IMR_TXEOL, AR_IMR_TXERR, AR_IMR_TXINTM, AR_IMR_TXMINTR, AR_IMR_TXOK, AR_SREV_9300_20_OR_LATER, ATH9K_HW_CAP_AUTOSLEEP, ath9k_hw_disable_interrupts(), ath9k_hw_enable_interrupts(), ATH9K_INT_BMISC, ATH9K_INT_CABEND, ATH9K_INT_COMMON, ATH9K_INT_CST, ATH9K_INT_DTIM, ATH9K_INT_DTIMSYNC, ATH9K_INT_GENTIMER, ATH9K_INT_GLOBAL, ATH9K_INT_GTT, ATH9K_INT_RX, ATH9K_INT_TIM, ATH9K_INT_TIM_TIMER, ATH9K_INT_TSFOOR, ATH9K_INT_TX, DBG2, ath9k_hw_capabilities::hw_caps, REG_CLR_BIT, REG_SET_BIT, and REG_WRITE.

Referenced by ath9k_irq(), ath9k_start(), ath_reset(), and ath_set_channel().