26#define AR_EEPROM_MODAL_SPURS 5
31#if __BYTE_ORDER == __BIG_ENDIAN
32#define AR5416_EEPROM_MAGIC 0x5aa5
34#define AR5416_EEPROM_MAGIC 0xa55a
37#define CTRY_DEBUG 0x1ff
40#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
41#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
42#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
43#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
44#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
45#define AR_EEPROM_EEPCAP_MAXQCU_S 4
46#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
47#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
48#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
50#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
51#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
52#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
53#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
54#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
55#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
57#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
58#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
60#define AR5416_EEPROM_MAGIC_OFFSET 0x0
61#define AR5416_EEPROM_S 2
62#define AR5416_EEPROM_OFFSET 0x2000
63#define AR5416_EEPROM_MAX 0xae0
65#define AR5416_EEPROM_START_ADDR \
66 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
79#define EXT_ADDITIVE (0x8000)
80#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
81#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
82#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
84#define SUB_NUM_CTL_MODES_AT_5G_40 2
85#define SUB_NUM_CTL_MODES_AT_2G_40 3
87#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
88#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
100#define AR9285_RDEXT_DEFAULT 0x1F
102#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
103#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
104#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
106#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
107#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
108 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
109#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
110 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
112#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
113#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
114#define AR_EEPROM_RFSILENT_POLARITY 0x0002
115#define AR_EEPROM_RFSILENT_POLARITY_S 1
117#define EEP_RFSILENT_ENABLED 0x0001
118#define EEP_RFSILENT_ENABLED_S 0
119#define EEP_RFSILENT_POLARITY 0x0002
120#define EEP_RFSILENT_POLARITY_S 1
121#define EEP_RFSILENT_GPIO_SEL 0x001c
122#define EEP_RFSILENT_GPIO_SEL_S 2
124#define AR5416_OPFLAGS_11A 0x01
125#define AR5416_OPFLAGS_11G 0x02
126#define AR5416_OPFLAGS_N_5G_HT40 0x04
127#define AR5416_OPFLAGS_N_2G_HT40 0x08
128#define AR5416_OPFLAGS_N_5G_HT20 0x10
129#define AR5416_OPFLAGS_N_2G_HT20 0x20
131#define AR5416_EEP_NO_BACK_VER 0x1
132#define AR5416_EEP_VER 0xE
133#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
134#define AR5416_EEP_MINOR_VER_2 0x2
135#define AR5416_EEP_MINOR_VER_3 0x3
136#define AR5416_EEP_MINOR_VER_7 0x7
137#define AR5416_EEP_MINOR_VER_9 0x9
138#define AR5416_EEP_MINOR_VER_16 0x10
139#define AR5416_EEP_MINOR_VER_17 0x11
140#define AR5416_EEP_MINOR_VER_19 0x13
141#define AR5416_EEP_MINOR_VER_20 0x14
142#define AR5416_EEP_MINOR_VER_21 0x15
143#define AR5416_EEP_MINOR_VER_22 0x16
145#define AR5416_NUM_5G_CAL_PIERS 8
146#define AR5416_NUM_2G_CAL_PIERS 4
147#define AR5416_NUM_5G_20_TARGET_POWERS 8
148#define AR5416_NUM_5G_40_TARGET_POWERS 8
149#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
150#define AR5416_NUM_2G_20_TARGET_POWERS 4
151#define AR5416_NUM_2G_40_TARGET_POWERS 4
152#define AR5416_NUM_CTLS 24
153#define AR5416_NUM_BAND_EDGES 8
154#define AR5416_NUM_PD_GAINS 4
155#define AR5416_PD_GAINS_IN_MASK 4
156#define AR5416_PD_GAIN_ICEPTS 5
157#define AR5416_NUM_PDADC_VALUES 128
158#define AR5416_BCHAN_UNUSED 0xFF
159#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
160#define AR5416_MAX_CHAINS 3
161#define AR9300_MAX_CHAINS 3
162#define AR5416_PWR_TABLE_OFFSET_DB -5
165#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
166#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
167#define AR5416_EEP_RXGAIN_ORIG 2
170#define AR5416_EEP_TXGAIN_ORIGINAL 0
171#define AR5416_EEP_TXGAIN_HIGH_POWER 1
173#define AR5416_EEP4K_START_LOC 64
174#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
175#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
176#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
177#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
178#define AR5416_EEP4K_NUM_CTLS 12
179#define AR5416_EEP4K_NUM_BAND_EDGES 4
180#define AR5416_EEP4K_NUM_PD_GAINS 2
181#define AR5416_EEP4K_MAX_CHAINS 1
183#define AR9280_TX_GAIN_TABLE_SIZE 22
185#define AR9287_EEP_VER 0xE
186#define AR9287_EEP_VER_MINOR_MASK 0xFFF
187#define AR9287_EEP_MINOR_VER_1 0x1
188#define AR9287_EEP_MINOR_VER_2 0x2
189#define AR9287_EEP_MINOR_VER_3 0x3
190#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
191#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
192#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
194#define AR9287_EEP_START_LOC 128
195#define AR9287_HTC_EEP_START_LOC 256
196#define AR9287_NUM_2G_CAL_PIERS 3
197#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
198#define AR9287_NUM_2G_20_TARGET_POWERS 3
199#define AR9287_NUM_2G_40_TARGET_POWERS 3
200#define AR9287_NUM_CTLS 12
201#define AR9287_NUM_BAND_EDGES 4
202#define AR9287_PD_GAIN_ICEPTS 1
203#define AR9287_EEPMISC_BIG_ENDIAN 0x01
204#define AR9287_EEPMISC_WOW 0x02
205#define AR9287_MAX_CHAINS 2
206#define AR9287_ANT_16S 32
208#define AR9287_DATA_SZ 32
210#define AR9287_PWR_TABLE_OFFSET_DB -5
212#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
214#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
215#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
217#define LNA_CTL_BUF_MODE BIT(0)
218#define LNA_CTL_ISEL_LO BIT(1)
219#define LNA_CTL_ISEL_HI BIT(2)
220#define LNA_CTL_BUF_IN BIT(3)
221#define LNA_CTL_FEM_BAND BIT(4)
222#define LNA_CTL_LOCAL_BIAS BIT(5)
223#define LNA_CTL_FORCE_XPA BIT(6)
224#define LNA_CTL_USE_ANT1 BIT(7)
407#ifdef __BIG_ENDIAN_BITFIELD
423#ifdef __BIG_ENDIAN_BITFIELD
429#ifdef __BIG_ENDIAN_BITFIELD
447#define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
662 u16 cfgCtl,
u8 twiceAntennaReduction,
663 u8 twiceMaxRegulatoryPower,
u8 powerLimit,
675 u16 *indexL,
u16 *indexR);
678 int eep_start_loc,
int size);
680 u8 *pVpdList,
u16 numIntercepts,
687 u16 numRates,
int isExtTarget);
693 u16 numRates,
int isHt40Target);
695 int is2GHz,
int num_band_edges);
702 u8 *bChans,
u16 availPiers,
704 u16 *pPdGainBoundaries,
u8 *pPDADCValues,
707#define ar5416_get_ntxchains(_txchainmask) \
708 (((_txchainmask >> 2) & 1) + \
709 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
#define AR5416_EEP4K_NUM_PD_GAINS
#define AR9287_NUM_2G_20_TARGET_POWERS
int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR)
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains)
#define AR5416_EEP4K_MAX_CHAINS
#define AR5416_PD_GAIN_ICEPTS
#define AR5416_NUM_5G_40_TARGET_POWERS
#define AR5416_NUM_2G_CAL_PIERS
#define AR9287_NUM_2G_CCK_TARGET_POWERS
#define AR5416_NUM_5G_CAL_PIERS
#define AR9287_NUM_BAND_EDGES
void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, int isHt40Target)
#define AR5416_NUM_2G_40_TARGET_POWERS
int ath9k_hw_eeprom_init(struct ath_hw *ah)
void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
#define AR9287_NUM_2G_40_TARGET_POWERS
#define AR_EEPROM_MODAL_SPURS
#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
#define AR9287_MAX_CHAINS
@ EEP_TEMPSENSE_SLOPE_PAL_ON
#define AR5416_EEP4K_NUM_CTLS
#define AR5416_NUM_BAND_EDGES
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t targetLeft, int16_t targetRight)
#define AR5416_NUM_5G_20_TARGET_POWERS
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, int isExtTarget)
#define AR9287_PD_GAIN_ICEPTS
#define AR5416_NUM_PD_GAINS
@ ATH9K_HAL_FREQ_BAND_2GHZ
@ ATH9K_HAL_FREQ_BAND_5GHZ
#define AR9287_NUM_2G_CAL_PIERS
#define AR5416_EEP4K_NUM_2G_CAL_PIERS
#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
#define AR5416_MAX_CHAINS
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
#define AR5416_NUM_2G_20_TARGET_POWERS
void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, u8 *pVpdList, u16 numIntercepts, u8 *pRetVpdList)
@ REG_EXT_JAPAN_NONDFS_HT40
#define AR5416_EEP4K_NUM_BAND_EDGES
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, int is2GHz, int num_band_edges)
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
#define AR5416_NUM_2G_CCK_TARGET_POWERS
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size)
#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
const struct eeprom_ops eep_ar9300_ops
const struct eeprom_ops eep_4k_ops
const struct eeprom_ops eep_ar9287_ops
const struct eeprom_ops eep_def_ops
uint8_t data[48]
Additional event data.
uint16_t size
Buffer size.
#define FILE_LICENCE(_licence)
Declare a particular licence as applying to a file.
#define FILE_SECBOOT(_status)
Declare a file's UEFI Secure Boot permission status.
struct ib_cm_common common
struct hv_monitor_parameter param[4][32]
Parameters.
static unsigned int unsigned int reg
struct base_eep_header_4k baseEepHeader
struct cal_data_per_freq_4k calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]
u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]
struct cal_target_power_leg calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]
struct modal_eep_4k_header modalHeader
struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]
struct cal_target_power_leg calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]
struct cal_target_power_ht calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]
u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]
struct cal_target_power_ht calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]
struct modal_eep_header modalHeader[2]
u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]
struct cal_target_power_leg calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]
struct cal_target_power_ht calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]
struct base_eep_header baseEepHeader
u8 ctlIndex[AR5416_NUM_CTLS]
struct cal_target_power_ht calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]
struct cal_target_power_ht calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]
struct cal_target_power_leg calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]
struct cal_ctl_data ctlData[AR5416_NUM_CTLS]
struct cal_data_per_freq calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]
struct cal_target_power_leg calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]
u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]
struct cal_target_power_ht calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]
struct cal_data_per_freq calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]
struct base_eep_ar9287_header baseEepHeader
struct cal_target_power_ht calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]
u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]
struct modal_eep_ar9287_header modalHeader
struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]
u8 ctlIndex[AR9287_NUM_CTLS]
union cal_data_per_freq_ar9287_u calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]
struct cal_target_power_leg calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]
struct cal_target_power_ht calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]
struct cal_target_power_leg calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]
u8 custData[AR9287_DATA_SZ]
struct cal_ctl_edges ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]
struct cal_ctl_edges ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]
struct cal_ctl_edges ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
void(* set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan)
u32(* get_eeprom)(struct ath_hw *hw, enum eeprom_param param)
int(* check_eeprom)(struct ath_hw *hw)
void(* set_addac)(struct ath_hw *hw, struct ath9k_channel *chan)
void(* set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
int(* fill_eeprom)(struct ath_hw *hw)
int(* get_eeprom_ver)(struct ath_hw *hw)
u16(* get_spur_channel)(struct ath_hw *ah, u16 i, int is2GHz)
int(* get_eeprom_rev)(struct ath_hw *hw)
struct cal_data_op_loop_ar9287 calDataOpen
struct cal_data_per_freq_ar9287 calDataClose