iPXE
eeprom.h
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef EEPROM_H
21 #define EEPROM_H
22 
23 FILE_LICENCE ( BSD2 );
24 
25 #define AR_EEPROM_MODAL_SPURS 5
26 
27 #include "../ath.h"
28 #include "ar9003_eeprom.h"
29 
30 #if __BYTE_ORDER == __BIG_ENDIAN
31 #define AR5416_EEPROM_MAGIC 0x5aa5
32 #else
33 #define AR5416_EEPROM_MAGIC 0xa55a
34 #endif
35 
36 #define CTRY_DEBUG 0x1ff
37 #define CTRY_DEFAULT 0
38 
39 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
40 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
41 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
42 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
43 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
44 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
45 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
46 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
47 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
48 
49 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
50 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
51 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
52 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
53 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
54 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
55 
56 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
57 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
58 
59 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
60 #define AR5416_EEPROM_S 2
61 #define AR5416_EEPROM_OFFSET 0x2000
62 #define AR5416_EEPROM_MAX 0xae0
63 
64 #define AR5416_EEPROM_START_ADDR \
65  (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
66 
67 #define SD_NO_CTL 0xE0
68 #define NO_CTL 0xff
69 #define CTL_MODE_M 0xf
70 #define CTL_11A 0
71 #define CTL_11B 1
72 #define CTL_11G 2
73 #define CTL_2GHT20 5
74 #define CTL_5GHT20 6
75 #define CTL_2GHT40 7
76 #define CTL_5GHT40 8
77 
78 #define EXT_ADDITIVE (0x8000)
79 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
80 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
81 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
82 
83 #define SUB_NUM_CTL_MODES_AT_5G_40 2
84 #define SUB_NUM_CTL_MODES_AT_2G_40 3
85 
86 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
87 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
88 
89 /*
90  * For AR9285 and later chipsets, the following bits are not being programmed
91  * in EEPROM and so need to be enabled always.
92  *
93  * Bit 0: en_fcc_mid
94  * Bit 1: en_jap_mid
95  * Bit 2: en_fcc_dfs_ht40
96  * Bit 3: en_jap_ht40
97  * Bit 4: en_jap_dfs_ht40
98  */
99 #define AR9285_RDEXT_DEFAULT 0x1F
100 
101 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
102 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
103 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
104 
105 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
106 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
107  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
108 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \
109  ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
110 
111 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
112 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
113 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
114 #define AR_EEPROM_RFSILENT_POLARITY_S 1
115 
116 #define EEP_RFSILENT_ENABLED 0x0001
117 #define EEP_RFSILENT_ENABLED_S 0
118 #define EEP_RFSILENT_POLARITY 0x0002
119 #define EEP_RFSILENT_POLARITY_S 1
120 #define EEP_RFSILENT_GPIO_SEL 0x001c
121 #define EEP_RFSILENT_GPIO_SEL_S 2
122 
123 #define AR5416_OPFLAGS_11A 0x01
124 #define AR5416_OPFLAGS_11G 0x02
125 #define AR5416_OPFLAGS_N_5G_HT40 0x04
126 #define AR5416_OPFLAGS_N_2G_HT40 0x08
127 #define AR5416_OPFLAGS_N_5G_HT20 0x10
128 #define AR5416_OPFLAGS_N_2G_HT20 0x20
129 
130 #define AR5416_EEP_NO_BACK_VER 0x1
131 #define AR5416_EEP_VER 0xE
132 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
133 #define AR5416_EEP_MINOR_VER_2 0x2
134 #define AR5416_EEP_MINOR_VER_3 0x3
135 #define AR5416_EEP_MINOR_VER_7 0x7
136 #define AR5416_EEP_MINOR_VER_9 0x9
137 #define AR5416_EEP_MINOR_VER_16 0x10
138 #define AR5416_EEP_MINOR_VER_17 0x11
139 #define AR5416_EEP_MINOR_VER_19 0x13
140 #define AR5416_EEP_MINOR_VER_20 0x14
141 #define AR5416_EEP_MINOR_VER_21 0x15
142 #define AR5416_EEP_MINOR_VER_22 0x16
143 
144 #define AR5416_NUM_5G_CAL_PIERS 8
145 #define AR5416_NUM_2G_CAL_PIERS 4
146 #define AR5416_NUM_5G_20_TARGET_POWERS 8
147 #define AR5416_NUM_5G_40_TARGET_POWERS 8
148 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
149 #define AR5416_NUM_2G_20_TARGET_POWERS 4
150 #define AR5416_NUM_2G_40_TARGET_POWERS 4
151 #define AR5416_NUM_CTLS 24
152 #define AR5416_NUM_BAND_EDGES 8
153 #define AR5416_NUM_PD_GAINS 4
154 #define AR5416_PD_GAINS_IN_MASK 4
155 #define AR5416_PD_GAIN_ICEPTS 5
156 #define AR5416_NUM_PDADC_VALUES 128
157 #define AR5416_BCHAN_UNUSED 0xFF
158 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
159 #define AR5416_MAX_CHAINS 3
160 #define AR9300_MAX_CHAINS 3
161 #define AR5416_PWR_TABLE_OFFSET_DB -5
162 
163 /* Rx gain type values */
164 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
165 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
166 #define AR5416_EEP_RXGAIN_ORIG 2
167 
168 /* Tx gain type values */
169 #define AR5416_EEP_TXGAIN_ORIGINAL 0
170 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
171 
172 #define AR5416_EEP4K_START_LOC 64
173 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
174 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
175 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
176 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
177 #define AR5416_EEP4K_NUM_CTLS 12
178 #define AR5416_EEP4K_NUM_BAND_EDGES 4
179 #define AR5416_EEP4K_NUM_PD_GAINS 2
180 #define AR5416_EEP4K_MAX_CHAINS 1
181 
182 #define AR9280_TX_GAIN_TABLE_SIZE 22
183 
184 #define AR9287_EEP_VER 0xE
185 #define AR9287_EEP_VER_MINOR_MASK 0xFFF
186 #define AR9287_EEP_MINOR_VER_1 0x1
187 #define AR9287_EEP_MINOR_VER_2 0x2
188 #define AR9287_EEP_MINOR_VER_3 0x3
189 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
190 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
191 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
192 
193 #define AR9287_EEP_START_LOC 128
194 #define AR9287_HTC_EEP_START_LOC 256
195 #define AR9287_NUM_2G_CAL_PIERS 3
196 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
197 #define AR9287_NUM_2G_20_TARGET_POWERS 3
198 #define AR9287_NUM_2G_40_TARGET_POWERS 3
199 #define AR9287_NUM_CTLS 12
200 #define AR9287_NUM_BAND_EDGES 4
201 #define AR9287_PD_GAIN_ICEPTS 1
202 #define AR9287_EEPMISC_BIG_ENDIAN 0x01
203 #define AR9287_EEPMISC_WOW 0x02
204 #define AR9287_MAX_CHAINS 2
205 #define AR9287_ANT_16S 32
206 
207 #define AR9287_DATA_SZ 32
208 
209 #define AR9287_PWR_TABLE_OFFSET_DB -5
210 
211 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
212 
213 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f)
214 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03)
215 
216 #define LNA_CTL_BUF_MODE BIT(0)
217 #define LNA_CTL_ISEL_LO BIT(1)
218 #define LNA_CTL_ISEL_HI BIT(2)
219 #define LNA_CTL_BUF_IN BIT(3)
220 #define LNA_CTL_FEM_BAND BIT(4)
221 #define LNA_CTL_LOCAL_BIAS BIT(5)
222 #define LNA_CTL_FORCE_XPA BIT(6)
223 #define LNA_CTL_USE_ANT1 BIT(7)
224 
261 };
262 
274 };
275 
279 };
280 
309 } __attribute__((packed));
310 
327 } __attribute__((packed));
328 
329 
330 struct spur_chan {
334 } __attribute__((packed));
335 
375 
377 } __attribute__((packed));
378 
380  u8 pwrPdg[2][5];
381  u8 vpdPdg[2][5];
382  u8 pcdac[2][5];
383  u8 empty[2][5];
384 } __attribute__((packed));
385 
406 #ifdef __BIG_ENDIAN_BITFIELD
407  u8 ob_1:4, ob_0:4;
408  u8 db1_1:4, db1_0:4;
409 #else
410  u8 ob_0:4, ob_1:4;
411  u8 db1_0:4, db1_1:4;
412 #endif
422 #ifdef __BIG_ENDIAN_BITFIELD
423  u8 db2_1:4, db2_0:4;
424 #else
425  u8 db2_0:4, db2_1:4;
426 #endif
428 #ifdef __BIG_ENDIAN_BITFIELD
429  u8 ob_3:4, ob_2:4;
430  u8 antdiv_ctl1:4, ob_4:4;
431  u8 db1_3:4, db1_2:4;
432  u8 antdiv_ctl2:4, db1_4:4;
433  u8 db2_2:4, db2_3:4;
434  u8 reserved:4, db2_4:4;
435 #else
436  u8 ob_2:4, ob_3:4;
438  u8 db1_2:4, db1_3:4;
440  u8 db2_2:4, db2_3:4;
442 #endif
446 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f
449 } __attribute__((packed));
450 
471 } __attribute__((packed));
472 
507 } __attribute__((packed));
508 
512 } __attribute__((packed));
513 
517 } __attribute__((packed));
518 
521  u8 tPow2x[4];
522 } __attribute__((packed));
523 
526  u8 tPow2x[8];
527 } __attribute__((packed));
528 
532 } __attribute__((packed));
533 
535  u8 pwrPdg[2][5];
536  u8 vpdPdg[2][5];
537  u8 pcdac[2][5];
538  u8 empty[2][5];
539 } __attribute__((packed));
540 
544 } __attribute__((packed));
545 
549 } __attribute__((packed));
550 
554 } __attribute__((packed));
555 
556 struct cal_ctl_data {
559 } __attribute__((packed));
560 
564 } __attribute__((packed));
565 
593 } __attribute__((packed));
594 
613 } __attribute__((packed));
614 
633 } __attribute__((packed));
634 
641 };
642 
649  u8 iso[3];
650 };
651 
652 struct eeprom_ops {
653  int (*check_eeprom)(struct ath_hw *hw);
655  int (*fill_eeprom)(struct ath_hw *hw);
656  int (*get_eeprom_ver)(struct ath_hw *hw);
657  int (*get_eeprom_rev)(struct ath_hw *hw);
658  void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
659  void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
660  void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
661  u16 cfgCtl, u8 twiceAntennaReduction,
662  u8 twiceMaxRegulatoryPower, u8 powerLimit,
663  int test);
664  u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, int is2GHz);
665 };
666 
668 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
669  u32 shift, u32 val);
670 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
671  int16_t targetLeft,
672  int16_t targetRight);
673 int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
674  u16 *indexL, u16 *indexR);
675 int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
676 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
677  int eep_start_loc, int size);
678 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
679  u8 *pVpdList, u16 numIntercepts,
680  u8 *pRetVpdList);
682  struct ath9k_channel *chan,
683  struct cal_target_power_leg *powInfo,
684  u16 numChannels,
685  struct cal_target_power_leg *pNewPower,
686  u16 numRates, int isExtTarget);
688  struct ath9k_channel *chan,
689  struct cal_target_power_ht *powInfo,
690  u16 numChannels,
691  struct cal_target_power_ht *pNewPower,
692  u16 numRates, int isHt40Target);
693 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
694  int is2GHz, int num_band_edges);
696 int ath9k_hw_eeprom_init(struct ath_hw *ah);
697 
699  struct ath9k_channel *chan,
700  void *pRawDataSet,
701  u8 *bChans, u16 availPiers,
702  u16 tPdGainOverlap,
703  u16 *pPdGainBoundaries, u8 *pPDADCValues,
704  u16 numXpdGains);
705 
706 #define ar5416_get_ntxchains(_txchainmask) \
707  (((_txchainmask >> 2) & 1) + \
708  ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
709 
710 extern const struct eeprom_ops eep_def_ops;
711 extern const struct eeprom_ops eep_4k_ops;
712 extern const struct eeprom_ops eep_ar9287_ops;
713 extern const struct eeprom_ops eep_ar9287_ops;
714 extern const struct eeprom_ops eep_ar9300_ops;
715 
716 #endif /* EEPROM_H */
struct cal_target_power_ht calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:626
#define AR5416_NUM_PD_GAINS
Definition: eeprom.h:153
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
u8 vpdPdg[2][5]
Definition: eeprom.h:381
#define __attribute__(x)
Definition: compiler.h:10
u32 antCtrlCommon
Definition: eeprom.h:338
u8 spurRangeHigh
Definition: eeprom.h:333
u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]
Definition: eeprom.h:619
#define AR9287_NUM_2G_CCK_TARGET_POWERS
Definition: eeprom.h:196
u8 bswMargin[AR9287_MAX_CHAINS]
Definition: eeprom.h:496
Definition: hw.h:656
const struct eeprom_ops eep_4k_ops
int8_t tempSensSlopePalOn
Definition: eeprom.h:469
u32 antCtrlChain[AR9287_MAX_CHAINS]
Definition: eeprom.h:474
u8 openLoopPwrCntl
Definition: eeprom.h:301
void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, int isHt40Target)
Definition: ath9k_eeprom.c:216
struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]
Definition: eeprom.h:376
#define AR5416_NUM_5G_CAL_PIERS
Definition: eeprom.h:144
const struct eeprom_ops eep_def_ops
u16 regDmn[2]
Definition: eeprom.h:287
#define AR9287_NUM_BAND_EDGES
Definition: eeprom.h:200
#define AR5416_EEP4K_NUM_PD_GAINS
Definition: eeprom.h:179
#define AR5416_EEP4K_MAX_CHAINS
Definition: eeprom.h:180
u8 custData[64]
Definition: eeprom.h:568
struct cal_ctl_edges ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]
Definition: eeprom.h:552
u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:418
u8 pwrDecreaseFor2Chain
Definition: eeprom.h:359
u32 binBuildNumber
Definition: eeprom.h:294
u8 antennaGainCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:339
u16 regDmn2G
Definition: eeprom.h:647
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:391
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
int8_t iqCalICh[AR9287_MAX_CHAINS]
Definition: eeprom.h:488
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, int is2GHz, int num_band_edges)
Definition: ath9k_eeprom.c:271
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:516
void(* set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
Definition: eeprom.h:660
struct cal_ctl_edges ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]
Definition: eeprom.h:557
int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR)
Definition: ath9k_eeprom.c:69
u8 iso[3]
Definition: eeprom.h:649
ar5416_rates
Definition: eeprom.h:263
u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]
Definition: eeprom.h:570
u16 blueToothOptions
Definition: eeprom.h:322
#define AR5416_EEP4K_NUM_CTLS
Definition: eeprom.h:177
#define AR9287_DATA_SZ
Definition: eeprom.h:207
void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, u8 *pVpdList, u16 numIntercepts, u8 *pRetVpdList)
Definition: ath9k_eeprom.c:134
#define AR5416_NUM_5G_20_TARGET_POWERS
Definition: eeprom.h:146
struct net80211_channel * chan
Definition: hw.h:347
int8_t antennaGainCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:476
struct cal_data_op_loop_ar9287 calDataOpen
Definition: eeprom.h:547
ath9k_hal_freq_band
Definition: eeprom.h:276
Definition: hw.c:16
u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:420
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
Definition: ath9k_eeprom.c:32
struct cal_target_power_leg calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:584
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:515
struct modal_eep_4k_header modalHeader
Definition: eeprom.h:598
u8 bb_scale_smrt_antenna
Definition: eeprom.h:445
u8 iqCalQCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:354
u8 pcdac[2][5]
Definition: eeprom.h:382
#define AR5416_NUM_5G_40_TARGET_POWERS
Definition: eeprom.h:147
const struct eeprom_ops eep_ar9287_ops
Definition: eeprom.h:713
u8 xatten2Db[AR5416_MAX_CHAINS]
Definition: eeprom.h:367
#define AR9287_NUM_2G_CAL_PIERS
Definition: eeprom.h:195
int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:485
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
Definition: eeprom.h:542
struct cal_target_power_leg calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:624
u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]
Definition: eeprom.h:599
int(* get_eeprom_ver)(struct ath_hw *hw)
Definition: eeprom.h:656
u8 bswAtten[AR5416_MAX_CHAINS]
Definition: eeprom.h:364
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t targetLeft, int16_t targetRight)
Definition: ath9k_eeprom.c:54
Definition: eeprom.h:643
u8 custData[20]
Definition: eeprom.h:597
u8 spurRangeLow
Definition: eeprom.h:332
#define u32
Definition: vga.h:21
u16 blueToothOptions
Definition: eeprom.h:292
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:510
u8 isMultidomain
Definition: eeprom.h:648
u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:392
Definition: eeprom.h:267
u32 antCtrlChain[AR5416_MAX_CHAINS]
Definition: eeprom.h:337
signed char int8_t
Definition: stdint.h:15
int ath9k_hw_eeprom_init(struct ath_hw *ah)
Definition: ath9k_eeprom.c:530
#define AR9287_NUM_2G_40_TARGET_POWERS
Definition: eeprom.h:198
struct cal_target_power_ht calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]
Definition: eeprom.h:578
Definition: eeprom.h:266
struct cal_target_power_leg calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]
Definition: eeprom.h:622
#define AR5416_PD_GAIN_ICEPTS
Definition: eeprom.h:155
void(* set_addac)(struct ath_hw *hw, struct ath9k_channel *chan)
Definition: eeprom.h:659
u16 spurChan
Definition: eeprom.h:331
#define AR5416_NUM_2G_CCK_TARGET_POWERS
Definition: eeprom.h:148
struct cal_target_power_leg calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:604
#define AR5416_NUM_BAND_EDGES
Definition: eeprom.h:152
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, int isExtTarget)
Definition: ath9k_eeprom.c:161
struct cal_ctl_data ctlData[AR5416_NUM_CTLS]
Definition: eeprom.h:591
#define AR5416_NUM_CTLS
Definition: eeprom.h:151
u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]
Definition: eeprom.h:610
#define AR9287_PD_GAIN_ICEPTS
Definition: eeprom.h:201
#define AR5416_EEP4K_NUM_BAND_EDGES
Definition: eeprom.h:178
static unsigned int unsigned int reg
Definition: intel.h:245
struct cal_target_power_leg calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]
Definition: eeprom.h:576
FILE_LICENCE(BSD2)
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]
Definition: eeprom.h:506
union cal_data_per_freq_ar9287_u calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]
Definition: eeprom.h:620
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:511
#define AR5416_NUM_2G_20_TARGET_POWERS
Definition: eeprom.h:149
struct cal_data_per_freq_ar9287 calDataClose
Definition: eeprom.h:548
u8 pwr_table_offset
Definition: eeprom.h:306
u16 regDmn5G
Definition: eeprom.h:646
#define AR9287_NUM_CTLS
Definition: eeprom.h:199
u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]
Definition: eeprom.h:571
u8 futureModal[6]
Definition: eeprom.h:374
#define AR9287_NUM_2G_20_TARGET_POWERS
Definition: eeprom.h:197
u8 xatten2Margin[AR5416_MAX_CHAINS]
Definition: eeprom.h:368
u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:404
u16 xpaBiasLvlFreq[3]
Definition: eeprom.h:373
struct modal_eep_header modalHeader[2]
Definition: eeprom.h:569
u32(* get_eeprom)(struct ath_hw *hw, enum eeprom_param param)
Definition: eeprom.h:654
u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:389
u8 pwrDecreaseFor3Chain
Definition: eeprom.h:360
#define AR5416_NUM_2G_40_TARGET_POWERS
Definition: eeprom.h:150
struct ib_cm_common common
Definition: ib_mad.h:11
u8 bswMargin[AR5416_MAX_CHAINS]
Definition: eeprom.h:365
u8 rxTxMarginCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:479
u8 futureBase_3[21]
Definition: eeprom.h:308
struct cal_target_power_ht calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]
Definition: eeprom.h:628
int(* check_eeprom)(struct ath_hw *hw)
Definition: eeprom.h:653
struct cal_target_power_ht calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:606
#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
Definition: eeprom.h:176
struct cal_target_power_leg calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]
Definition: eeprom.h:602
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
Definition: eeprom.h:543
u16 countryCode
Definition: eeprom.h:644
void __asmcall int val
Definition: setjmp.h:28
struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]
Definition: eeprom.h:448
#define AR5416_EEP4K_NUM_2G_CAL_PIERS
Definition: eeprom.h:173
#define AR5416_MAX_CHAINS
Definition: eeprom.h:159
struct cal_target_power_ht calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]
Definition: eeprom.h:580
struct cal_target_power_ht calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]
Definition: eeprom.h:586
struct cal_target_power_leg calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]
Definition: eeprom.h:582
u8 rxTxMarginCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:342
struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]
Definition: eeprom.h:631
u8 custData[AR9287_DATA_SZ]
Definition: eeprom.h:617
eeprom_param
Definition: eeprom.h:225
u8 desiredScaleCCK
Definition: eeprom.h:305
u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:395
u8 empty[2][5]
Definition: eeprom.h:383
u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:403
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains)
Definition: ath9k_eeprom.c:318
u8 ctlIndex[AR5416_NUM_CTLS]
Definition: eeprom.h:590
u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:387
#define AR5416_NUM_2G_CAL_PIERS
Definition: eeprom.h:145
void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
Definition: ath9k_eeprom.c:298
u8 dacHiPwrMode_5G
Definition: eeprom.h:300
struct cal_data_per_freq calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]
Definition: eeprom.h:572
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
u8 xlnaGainCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:345
u8 macAddr[6]
Definition: eeprom.h:288
void(* set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan)
Definition: eeprom.h:658
uint8_t ah
Definition: registers.h:85
const struct eeprom_ops eep_ar9300_ops
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size)
Definition: ath9k_eeprom.c:97
signed short int16_t
Definition: stdint.h:16
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
struct cal_target_power_ht calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]
Definition: eeprom.h:588
struct cal_data_per_freq_4k calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]
Definition: eeprom.h:600
u8 iqCalICh[AR5416_MAX_CHAINS]
Definition: eeprom.h:353
u8 pwrPdg[2][5]
Definition: eeprom.h:380
struct cal_target_power_ht calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]
Definition: eeprom.h:608
struct base_eep_header baseEepHeader
Definition: eeprom.h:567
struct base_eep_header_4k baseEepHeader
Definition: eeprom.h:596
struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]
Definition: eeprom.h:611
reg_ext_bitmap
Definition: eeprom.h:635
u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:421
struct cal_ctl_edges ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]
Definition: eeprom.h:562
#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
Definition: eeprom.h:175
struct modal_eep_ar9287_header modalHeader
Definition: eeprom.h:618
int(* fill_eeprom)(struct ath_hw *hw)
Definition: eeprom.h:655
u8 txRxAttenCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:478
Definition: eeprom.h:266
int(* get_eeprom_rev)(struct ath_hw *hw)
Definition: eeprom.h:657
u8 txRxAttenCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:341
u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:417
struct base_eep_ar9287_header baseEepHeader
Definition: eeprom.h:616
u8 ht40PowerIncForPdadc
Definition: eeprom.h:363
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
Definition: ath9k_eeprom.c:40
u8 bswAtten[AR9287_MAX_CHAINS]
Definition: eeprom.h:495
u8 ctlIndex[AR9287_NUM_CTLS]
Definition: eeprom.h:630
uint8_t u8
Definition: stdint.h:19
static int test
Definition: epic100.c:73
u16(* get_spur_channel)(struct ath_hw *ah, u16 i, int is2GHz)
Definition: eeprom.h:664
uint32_t u32
Definition: stdint.h:23
#define AR9287_MAX_CHAINS
Definition: eeprom.h:204
u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]
Definition: eeprom.h:400
Definition: eeprom.h:266
u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]
Definition: eeprom.h:350
struct cal_data_per_freq calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]
Definition: eeprom.h:574
u16 regDmnEnum
Definition: eeprom.h:645
#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
Definition: eeprom.h:174
u8 txFrameToDataStart
Definition: eeprom.h:361
int8_t iqCalQCh[AR9287_MAX_CHAINS]
Definition: eeprom.h:489