29 return (
u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
36 if (
ah->config.analog_shiftreg)
46 regVal |= (
val << shift) & mask;
50 if (
ah->config.analog_shiftreg)
59 if (srcRight == srcLeft) {
62 rv = (
int16_t) (((target - srcLeft) * targetRight +
63 (srcRight - target) * targetLeft) /
64 (srcRight - srcLeft));
74 if (target <= pList[0]) {
75 *indexL = *indexR = 0;
78 if (target >= pList[listSize - 1]) {
79 *indexL = *indexR = (
u16) (listSize - 1);
83 for (i = 0; i < listSize - 1; i++) {
84 if (pList[i] == target) {
85 *indexL = *indexR = i;
88 if (target < pList[i + 1]) {
90 *indexR = (
u16) (i + 1);
98 int eep_start_loc,
int size)
111 for (j = 0; j < i; j++) {
122 for (j = 0; j < i; j++) {
135 u8 *pVpdList,
u16 numIntercepts,
140 u16 idxL = 0, idxR = 0;
142 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
144 numIntercepts, &(idxL),
148 if (idxL == numIntercepts - 1)
149 idxL = (
u16) (numIntercepts - 2);
150 if (pPwrList[idxL] == pPwrList[idxR])
153 k = (
u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
154 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
155 (pPwrList[idxR] - pPwrList[idxL]));
156 pRetVpdList[i] = (
u8)
k;
166 u16 numRates,
int isExtTarget)
171 int matchIndex = -1, lowIndex = -1;
181 for (i = 0; (i < numChannels) &&
195 if ((matchIndex == -1) && (lowIndex == -1))
199 if (matchIndex != -1) {
200 *pNewPower = powInfo[matchIndex];
207 for (i = 0; i < numRates; i++) {
210 powInfo[lowIndex].
tPow2x[i],
211 powInfo[lowIndex + 1].
tPow2x[i]);
221 u16 numRates,
int isHt40Target)
226 int matchIndex = -1, lowIndex = -1;
235 for (i = 0; (i < numChannels) &&
250 if ((matchIndex == -1) && (lowIndex == -1))
254 if (matchIndex != -1) {
255 *pNewPower = powInfo[matchIndex];
262 for (i = 0; i < numRates; i++) {
265 powInfo[lowIndex].
tPow2x[i],
266 powInfo[lowIndex + 1].
tPow2x[i]);
272 int is2GHz,
int num_band_edges)
277 for (i = 0; (i < num_band_edges) &&
282 }
else if ((i > 0) &&
295 return twiceMaxEdgePower;
313 "Invalid chainmask configuration\n");
321 u8 *bChans,
u16 availPiers,
323 u16 *pPdGainBoundaries,
u8 *pPDADCValues,
328 u16 idxL = 0, idxR = 0, numPiers;
336 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
341 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
345 int pdgain_boundary_default;
360 for (numPiers = 0; numPiers < availPiers; numPiers++) {
367 bChans, numPiers, &idxL, &idxR);
371 for (i = 0; i < numXpdGains; i++) {
372 minPwrT4[i] = data_9287[idxL].
pwrPdg[i][0];
373 maxPwrT4[i] = data_9287[idxL].
pwrPdg[i][intercepts - 1];
375 data_9287[idxL].
pwrPdg[i],
376 data_9287[idxL].
vpdPdg[i],
380 }
else if (eeprom_4k) {
381 for (i = 0; i < numXpdGains; i++) {
382 minPwrT4[i] = data_4k[idxL].
pwrPdg[i][0];
383 maxPwrT4[i] = data_4k[idxL].
pwrPdg[i][intercepts - 1];
391 for (i = 0; i < numXpdGains; i++) {
392 minPwrT4[i] = data_def[idxL].
pwrPdg[i][0];
393 maxPwrT4[i] = data_def[idxL].
pwrPdg[i][intercepts - 1];
402 for (i = 0; i < numXpdGains; i++) {
404 pVpdL = data_9287[idxL].
vpdPdg[i];
405 pPwrL = data_9287[idxL].
pwrPdg[i];
406 pVpdR = data_9287[idxR].
vpdPdg[i];
407 pPwrR = data_9287[idxR].
pwrPdg[i];
408 }
else if (eeprom_4k) {
409 pVpdL = data_4k[idxL].
vpdPdg[i];
410 pPwrL = data_4k[idxL].
pwrPdg[i];
411 pVpdR = data_4k[idxR].
vpdPdg[i];
412 pPwrR = data_4k[idxR].
pwrPdg[i];
414 pVpdL = data_def[idxL].
vpdPdg[i];
415 pPwrL = data_def[idxL].
pwrPdg[i];
416 pVpdR = data_def[idxR].
vpdPdg[i];
417 pPwrR = data_def[idxR].
pwrPdg[i];
420 minPwrT4[i] =
max(pPwrL[0], pPwrR[0]);
423 min(pPwrL[intercepts - 1],
424 pPwrR[intercepts - 1]);
436 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
443 bChans[idxL], bChans[idxR],
444 vpdTableL[i][j], vpdTableR[i][j]));
451 for (i = 0; i < numXpdGains; i++) {
452 if (i == (numXpdGains - 1))
453 pPdGainBoundaries[i] =
454 (
u16)(maxPwrT4[i] / 2);
456 pPdGainBoundaries[i] =
457 (
u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
459 pPdGainBoundaries[i] =
463 minDelta = pPdGainBoundaries[0] - 23;
464 pPdGainBoundaries[0] = 23;
475 ss = (
int16_t)((pPdGainBoundaries[i - 1] -
477 tPdGainOverlap + 1 + minDelta);
479 vpdStep = (
int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
480 vpdStep = (
int16_t)((vpdStep < 1) ? 1 : vpdStep);
483 tmpVal = (
int16_t)(vpdTableI[i][0] +
ss * vpdStep);
484 pPDADCValues[
k++] = (
u8)((tmpVal < 0) ? 0 : tmpVal);
488 sizeCurrVpdTable = (
u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
489 tgtIndex = (
u8)(pPdGainBoundaries[i] + tPdGainOverlap -
491 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
492 tgtIndex : sizeCurrVpdTable;
495 pPDADCValues[
k++] = vpdTableI[i][
ss++];
498 vpdStep = (
int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
499 vpdTableI[i][sizeCurrVpdTable - 2]);
500 vpdStep = (
int16_t)((vpdStep < 1) ? 1 : vpdStep);
502 if (tgtIndex >= maxIndex) {
503 while ((
ss <= tgtIndex) &&
505 tmpVal = (
int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
506 (
ss - maxIndex + 1) * vpdStep));
507 pPDADCValues[
k++] = (
u8)((tmpVal > 255) ?
515 pdgain_boundary_default = 58;
517 pdgain_boundary_default = pPdGainBoundaries[i - 1];
520 pPdGainBoundaries[i] = pdgain_boundary_default;
525 pPDADCValues[
k] = pPDADCValues[
k - 1];
544 if (!
ah->eep_ops->fill_eeprom(
ah))
void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, int isHt40Target)
#define AR5416_NUM_PD_GAINS
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
#define AR_SREV_9280_20_OR_LATER(_ah)
static unsigned int unsigned int reg
#define ar5416_get_ntxchains(_txchainmask)
int ath9k_hw_eeprom_init(struct ath_hw *ah)
#define CTL_EDGE_FLAGS(_ctl)
uint8_t size
Entry size (in 32-bit words)
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
const struct eeprom_ops eep_4k_ops
#define AR_SREV_5416_20_OR_LATER(_ah)
#define AR_SREV_9285(_ah)
struct net80211_channel * chan
const struct eeprom_ops eep_def_ops
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t targetLeft, int16_t targetRight)
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
#define AR5416_PD_GAINS_IN_MASK
#define AR_SREV_9287(_ah)
void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, u8 *pVpdList, u16 numIntercepts, u8 *pRetVpdList)
#define AR_SREV_9300_20_OR_LATER(_ah)
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
#define REG_READ_MULTI(_ah, _addr, _val, _cnt)
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains)
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
const struct eeprom_ops eep_ar9300_ops
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
#define AR5416_PD_GAIN_ICEPTS
#define AR5416_NUM_PDADC_VALUES
const struct eeprom_ops eep_ar9287_ops
int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR)
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, int is2GHz, int num_band_edges)
#define AR5416_BCHAN_UNUSED
#define AR9287_PD_GAIN_ICEPTS
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
static const uint32_t k[64]
MD5 constants.
struct ib_cm_common common
#define REG_READ(_ah, _reg)
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, int isExtTarget)
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
#define INCREASE_MAXPOW_BY_TWO_CHAIN
#define INCREASE_MAXPOW_BY_THREE_CHAIN
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size)
#define REG_WRITE(_ah, _reg, _val)
#define EIO
Input/output error.
#define AR_SREV_9271(_ah)
uint8_t data[48]
Additional event data.
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB
void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
#define CTL_EDGE_TPOWER(_ctl)
#define AR5416_EEPROM_OFFSET
if(natsemi->flags &NATSEMI_64BIT) return 1
void * memset(void *dest, int character, size_t len) __nonnull