iPXE
ath9k_eeprom.c
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1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5  * Original from Linux kernel 3.0.1
6  *
7  * Permission to use, copy, modify, and/or distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <ipxe/io.h>
21 
22 #include "hw.h"
23 
24 static inline u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
25 {
26  if (fbin == AR5416_BCHAN_UNUSED)
27  return fbin;
28 
29  return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
30 }
31 
33 {
34  REG_WRITE(ah, reg, val);
35 
36  if (ah->config.analog_shiftreg)
37  udelay(100);
38 }
39 
41  u32 shift, u32 val)
42 {
43  u32 regVal;
44 
45  regVal = REG_READ(ah, reg) & ~mask;
46  regVal |= (val << shift) & mask;
47 
48  REG_WRITE(ah, reg, regVal);
49 
50  if (ah->config.analog_shiftreg)
51  udelay(100);
52 }
53 
54 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
55  int16_t targetLeft, int16_t targetRight)
56 {
57  int16_t rv;
58 
59  if (srcRight == srcLeft) {
60  rv = targetLeft;
61  } else {
62  rv = (int16_t) (((target - srcLeft) * targetRight +
63  (srcRight - target) * targetLeft) /
64  (srcRight - srcLeft));
65  }
66  return rv;
67 }
68 
69 int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
70  u16 *indexL, u16 *indexR)
71 {
72  u16 i;
73 
74  if (target <= pList[0]) {
75  *indexL = *indexR = 0;
76  return 1;
77  }
78  if (target >= pList[listSize - 1]) {
79  *indexL = *indexR = (u16) (listSize - 1);
80  return 1;
81  }
82 
83  for (i = 0; i < listSize - 1; i++) {
84  if (pList[i] == target) {
85  *indexL = *indexR = i;
86  return 1;
87  }
88  if (target < pList[i + 1]) {
89  *indexL = i;
90  *indexR = (u16) (i + 1);
91  return 0;
92  }
93  }
94  return 0;
95 }
96 
97 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
98  int eep_start_loc, int size)
99 {
100  int i = 0, j, addr;
101  u32 addrdata[8];
102  u32 data[8];
103 
104  for (addr = 0; addr < size; addr++) {
105  addrdata[i] = AR5416_EEPROM_OFFSET +
106  ((addr + eep_start_loc) << AR5416_EEPROM_S);
107  i++;
108  if (i == 8) {
109  REG_READ_MULTI(ah, addrdata, data, i);
110 
111  for (j = 0; j < i; j++) {
112  *eep_data = data[j];
113  eep_data++;
114  }
115  i = 0;
116  }
117  }
118 
119  if (i != 0) {
120  REG_READ_MULTI(ah, addrdata, data, i);
121 
122  for (j = 0; j < i; j++) {
123  *eep_data = data[j];
124  eep_data++;
125  }
126  }
127 }
128 
130 {
131  return common->bus_ops->eeprom_read(common, off, data);
132 }
133 
134 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
135  u8 *pVpdList, u16 numIntercepts,
136  u8 *pRetVpdList)
137 {
138  u16 i, k;
139  u8 currPwr = pwrMin;
140  u16 idxL = 0, idxR = 0;
141 
142  for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
143  ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
144  numIntercepts, &(idxL),
145  &(idxR));
146  if (idxR < 1)
147  idxR = 1;
148  if (idxL == numIntercepts - 1)
149  idxL = (u16) (numIntercepts - 2);
150  if (pPwrList[idxL] == pPwrList[idxR])
151  k = pVpdList[idxL];
152  else
153  k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
154  (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
155  (pPwrList[idxR] - pPwrList[idxL]));
156  pRetVpdList[i] = (u8) k;
157  currPwr += 2;
158  }
159 }
160 
162  struct ath9k_channel *chan,
163  struct cal_target_power_leg *powInfo,
164  u16 numChannels,
165  struct cal_target_power_leg *pNewPower,
166  u16 numRates, int isExtTarget)
167 {
168  struct chan_centers centers;
169  u16 clo, chi;
170  int i;
171  int matchIndex = -1, lowIndex = -1;
172  u16 freq;
173 
174  ath9k_hw_get_channel_centers(ah, chan, &centers);
175  freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
176 
177  if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
178  IS_CHAN_2GHZ(chan))) {
179  matchIndex = 0;
180  } else {
181  for (i = 0; (i < numChannels) &&
182  (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
183  if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
184  IS_CHAN_2GHZ(chan))) {
185  matchIndex = i;
186  break;
187  } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
188  IS_CHAN_2GHZ(chan)) && i > 0 &&
189  freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
190  IS_CHAN_2GHZ(chan))) {
191  lowIndex = i - 1;
192  break;
193  }
194  }
195  if ((matchIndex == -1) && (lowIndex == -1))
196  matchIndex = i - 1;
197  }
198 
199  if (matchIndex != -1) {
200  *pNewPower = powInfo[matchIndex];
201  } else {
202  clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
203  IS_CHAN_2GHZ(chan));
204  chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
205  IS_CHAN_2GHZ(chan));
206 
207  for (i = 0; i < numRates; i++) {
208  pNewPower->tPow2x[i] =
209  (u8)ath9k_hw_interpolate(freq, clo, chi,
210  powInfo[lowIndex].tPow2x[i],
211  powInfo[lowIndex + 1].tPow2x[i]);
212  }
213  }
214 }
215 
217  struct ath9k_channel *chan,
218  struct cal_target_power_ht *powInfo,
219  u16 numChannels,
220  struct cal_target_power_ht *pNewPower,
221  u16 numRates, int isHt40Target)
222 {
223  struct chan_centers centers;
224  u16 clo, chi;
225  int i;
226  int matchIndex = -1, lowIndex = -1;
227  u16 freq;
228 
229  ath9k_hw_get_channel_centers(ah, chan, &centers);
230  freq = isHt40Target ? centers.synth_center : centers.ctl_center;
231 
232  if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
233  matchIndex = 0;
234  } else {
235  for (i = 0; (i < numChannels) &&
236  (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
237  if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
238  IS_CHAN_2GHZ(chan))) {
239  matchIndex = i;
240  break;
241  } else
242  if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
243  IS_CHAN_2GHZ(chan)) && i > 0 &&
244  freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
245  IS_CHAN_2GHZ(chan))) {
246  lowIndex = i - 1;
247  break;
248  }
249  }
250  if ((matchIndex == -1) && (lowIndex == -1))
251  matchIndex = i - 1;
252  }
253 
254  if (matchIndex != -1) {
255  *pNewPower = powInfo[matchIndex];
256  } else {
257  clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
258  IS_CHAN_2GHZ(chan));
259  chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
260  IS_CHAN_2GHZ(chan));
261 
262  for (i = 0; i < numRates; i++) {
263  pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
264  clo, chi,
265  powInfo[lowIndex].tPow2x[i],
266  powInfo[lowIndex + 1].tPow2x[i]);
267  }
268  }
269 }
270 
271 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
272  int is2GHz, int num_band_edges)
273 {
274  u16 twiceMaxEdgePower = MAX_RATE_POWER;
275  int i;
276 
277  for (i = 0; (i < num_band_edges) &&
278  (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
279  if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
280  twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
281  break;
282  } else if ((i > 0) &&
283  (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
284  is2GHz))) {
285  if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
286  is2GHz) < freq &&
287  CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
288  twiceMaxEdgePower =
289  CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
290  }
291  break;
292  }
293  }
294 
295  return twiceMaxEdgePower;
296 }
297 
299 {
300  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
301 
302  switch (ar5416_get_ntxchains(ah->txchainmask)) {
303  case 1:
304  break;
305  case 2:
307  break;
308  case 3:
310  break;
311  default:
312  DBG2("ath9k: "
313  "Invalid chainmask configuration\n");
314  break;
315  }
316 }
317 
319  struct ath9k_channel *chan,
320  void *pRawDataSet,
321  u8 *bChans, u16 availPiers,
322  u16 tPdGainOverlap,
323  u16 *pPdGainBoundaries, u8 *pPDADCValues,
324  u16 numXpdGains)
325 {
326  int i, j, k;
327  int16_t ss;
328  u16 idxL = 0, idxR = 0, numPiers;
329  static u8 vpdTableL[AR5416_NUM_PD_GAINS]
331  static u8 vpdTableR[AR5416_NUM_PD_GAINS]
333  static u8 vpdTableI[AR5416_NUM_PD_GAINS]
335 
336  u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
337  u8 minPwrT4[AR5416_NUM_PD_GAINS];
338  u8 maxPwrT4[AR5416_NUM_PD_GAINS];
339  int16_t vpdStep;
340  int16_t tmpVal;
341  u16 sizeCurrVpdTable, maxIndex, tgtIndex;
342  int match;
343  int16_t minDelta = 0;
344  struct chan_centers centers;
345  int pdgain_boundary_default;
346  struct cal_data_per_freq *data_def = pRawDataSet;
347  struct cal_data_per_freq_4k *data_4k = pRawDataSet;
348  struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
349  int eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
350  int intercepts;
351 
352  if (AR_SREV_9287(ah))
353  intercepts = AR9287_PD_GAIN_ICEPTS;
354  else
355  intercepts = AR5416_PD_GAIN_ICEPTS;
356 
357  memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
358  ath9k_hw_get_channel_centers(ah, chan, &centers);
359 
360  for (numPiers = 0; numPiers < availPiers; numPiers++) {
361  if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
362  break;
363  }
364 
366  IS_CHAN_2GHZ(chan)),
367  bChans, numPiers, &idxL, &idxR);
368 
369  if (match) {
370  if (AR_SREV_9287(ah)) {
371  for (i = 0; i < numXpdGains; i++) {
372  minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
373  maxPwrT4[i] = data_9287[idxL].pwrPdg[i][intercepts - 1];
374  ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
375  data_9287[idxL].pwrPdg[i],
376  data_9287[idxL].vpdPdg[i],
377  intercepts,
378  vpdTableI[i]);
379  }
380  } else if (eeprom_4k) {
381  for (i = 0; i < numXpdGains; i++) {
382  minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
383  maxPwrT4[i] = data_4k[idxL].pwrPdg[i][intercepts - 1];
384  ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
385  data_4k[idxL].pwrPdg[i],
386  data_4k[idxL].vpdPdg[i],
387  intercepts,
388  vpdTableI[i]);
389  }
390  } else {
391  for (i = 0; i < numXpdGains; i++) {
392  minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
393  maxPwrT4[i] = data_def[idxL].pwrPdg[i][intercepts - 1];
394  ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
395  data_def[idxL].pwrPdg[i],
396  data_def[idxL].vpdPdg[i],
397  intercepts,
398  vpdTableI[i]);
399  }
400  }
401  } else {
402  for (i = 0; i < numXpdGains; i++) {
403  if (AR_SREV_9287(ah)) {
404  pVpdL = data_9287[idxL].vpdPdg[i];
405  pPwrL = data_9287[idxL].pwrPdg[i];
406  pVpdR = data_9287[idxR].vpdPdg[i];
407  pPwrR = data_9287[idxR].pwrPdg[i];
408  } else if (eeprom_4k) {
409  pVpdL = data_4k[idxL].vpdPdg[i];
410  pPwrL = data_4k[idxL].pwrPdg[i];
411  pVpdR = data_4k[idxR].vpdPdg[i];
412  pPwrR = data_4k[idxR].pwrPdg[i];
413  } else {
414  pVpdL = data_def[idxL].vpdPdg[i];
415  pPwrL = data_def[idxL].pwrPdg[i];
416  pVpdR = data_def[idxR].vpdPdg[i];
417  pPwrR = data_def[idxR].pwrPdg[i];
418  }
419 
420  minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
421 
422  maxPwrT4[i] =
423  min(pPwrL[intercepts - 1],
424  pPwrR[intercepts - 1]);
425 
426 
427  ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
428  pPwrL, pVpdL,
429  intercepts,
430  vpdTableL[i]);
431  ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
432  pPwrR, pVpdR,
433  intercepts,
434  vpdTableR[i]);
435 
436  for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
437  vpdTableI[i][j] =
439  FREQ2FBIN(centers.
440  synth_center,
442  (chan)),
443  bChans[idxL], bChans[idxR],
444  vpdTableL[i][j], vpdTableR[i][j]));
445  }
446  }
447  }
448 
449  k = 0;
450 
451  for (i = 0; i < numXpdGains; i++) {
452  if (i == (numXpdGains - 1))
453  pPdGainBoundaries[i] =
454  (u16)(maxPwrT4[i] / 2);
455  else
456  pPdGainBoundaries[i] =
457  (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
458 
459  pPdGainBoundaries[i] =
460  min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
461 
462  if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
463  minDelta = pPdGainBoundaries[0] - 23;
464  pPdGainBoundaries[0] = 23;
465  } else {
466  minDelta = 0;
467  }
468 
469  if (i == 0) {
471  ss = (int16_t)(0 - (minPwrT4[i] / 2));
472  else
473  ss = 0;
474  } else {
475  ss = (int16_t)((pPdGainBoundaries[i - 1] -
476  (minPwrT4[i] / 2)) -
477  tPdGainOverlap + 1 + minDelta);
478  }
479  vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
480  vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
481 
482  while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
483  tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
484  pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
485  ss++;
486  }
487 
488  sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
489  tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
490  (minPwrT4[i] / 2));
491  maxIndex = (tgtIndex < sizeCurrVpdTable) ?
492  tgtIndex : sizeCurrVpdTable;
493 
494  while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
495  pPDADCValues[k++] = vpdTableI[i][ss++];
496  }
497 
498  vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
499  vpdTableI[i][sizeCurrVpdTable - 2]);
500  vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
501 
502  if (tgtIndex >= maxIndex) {
503  while ((ss <= tgtIndex) &&
504  (k < (AR5416_NUM_PDADC_VALUES - 1))) {
505  tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
506  (ss - maxIndex + 1) * vpdStep));
507  pPDADCValues[k++] = (u8)((tmpVal > 255) ?
508  255 : tmpVal);
509  ss++;
510  }
511  }
512  }
513 
514  if (eeprom_4k)
515  pdgain_boundary_default = 58;
516  else
517  pdgain_boundary_default = pPdGainBoundaries[i - 1];
518 
519  while (i < AR5416_PD_GAINS_IN_MASK) {
520  pPdGainBoundaries[i] = pdgain_boundary_default;
521  i++;
522  }
523 
524  while (k < AR5416_NUM_PDADC_VALUES) {
525  pPDADCValues[k] = pPDADCValues[k - 1];
526  k++;
527  }
528 }
529 
531 {
532  int status;
533 
535  ah->eep_ops = &eep_ar9300_ops;
536  else if (AR_SREV_9287(ah)) {
537  ah->eep_ops = &eep_ar9287_ops;
538  } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
539  ah->eep_ops = &eep_4k_ops;
540  } else {
541  ah->eep_ops = &eep_def_ops;
542  }
543 
544  if (!ah->eep_ops->fill_eeprom(ah))
545  return -EIO;
546 
547  status = ah->eep_ops->check_eeprom(ah);
548 
549  return status;
550 }
void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, struct cal_target_power_ht *pNewPower, u16 numRates, int isHt40Target)
Definition: ath9k_eeprom.c:216
#define AR5416_NUM_PD_GAINS
Definition: eeprom.h:153
#define u16
Definition: vga.h:20
uint16_t u16
Definition: stdint.h:21
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
Definition: ath9k_eeprom.c:24
iPXE I/O API
Definition: hw.h:656
u16 synth_center
Definition: hw.h:422
#define max(x, y)
Definition: ath.h:39
#define AR_SREV_9280_20_OR_LATER(_ah)
Definition: reg.h:824
#define ar5416_get_ntxchains(_txchainmask)
Definition: eeprom.h:706
int ath9k_hw_eeprom_init(struct ath_hw *ah)
Definition: ath9k_eeprom.c:530
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define CTL_EDGE_FLAGS(_ctl)
Definition: eeprom.h:214
u16 ext_center
Definition: hw.h:424
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:516
#define min(x, y)
Definition: ath.h:34
const struct eeprom_ops eep_4k_ops
#define AR_SREV_5416_20_OR_LATER(_ah)
Definition: reg.h:801
#define AR_SREV_9285(_ah)
Definition: reg.h:829
struct net80211_channel * chan
Definition: hw.h:347
const struct eeprom_ops eep_def_ops
int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, int16_t targetLeft, int16_t targetRight)
Definition: ath9k_eeprom.c:54
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:515
#define FREQ2FBIN(x, y)
Definition: eeprom.h:102
#define AR5416_PD_GAINS_IN_MASK
Definition: eeprom.h:154
uint8_t status
Status.
Definition: ena.h:16
#define AR_SREV_9287(_ah)
Definition: reg.h:834
void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, u8 *pVpdList, u16 numIntercepts, u8 *pRetVpdList)
Definition: ath9k_eeprom.c:134
#define AR_SREV_9300_20_OR_LATER(_ah)
Definition: reg.h:864
void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
Definition: ath9k_eeprom.c:32
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
Definition: eeprom.h:542
#define REG_READ_MULTI(_ah, _addr, _val, _cnt)
Definition: hw.h:83
void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, void *pRawDataSet, u8 *bChans, u16 availPiers, u16 tPdGainOverlap, u16 *pPdGainBoundaries, u8 *pPDADCValues, u16 numXpdGains)
Definition: ath9k_eeprom.c:318
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
const struct eeprom_ops eep_ar9300_ops
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:510
#define u8
Definition: igbvf_osdep.h:38
#define AR5416_PD_GAIN_ICEPTS
Definition: eeprom.h:155
#define AR5416_NUM_PDADC_VALUES
Definition: eeprom.h:156
const struct eeprom_ops eep_ar9287_ops
int ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, u16 *indexL, u16 *indexR)
Definition: ath9k_eeprom.c:69
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, int is2GHz, int num_band_edges)
Definition: ath9k_eeprom.c:271
#define AR5416_BCHAN_UNUSED
Definition: eeprom.h:157
#define AR9287_PD_GAIN_ICEPTS
Definition: eeprom.h:201
static unsigned int unsigned int reg
Definition: intel.h:245
uint32_t ss
Definition: librm.h:250
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]
Definition: eeprom.h:511
u32 addr
Definition: sky2.h:8
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
Definition: ath9k_eeprom.c:40
static const uint32_t k[64]
MD5 constants.
Definition: md5.c:54
struct ib_cm_common common
Definition: ib_mad.h:11
#define REG_READ(_ah, _reg)
Definition: hw.h:80
void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, struct cal_target_power_leg *pNewPower, u16 numRates, int isExtTarget)
Definition: ath9k_eeprom.c:161
u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]
Definition: eeprom.h:543
#define INCREASE_MAXPOW_BY_TWO_CHAIN
Definition: eeprom.h:86
void __asmcall int val
Definition: setjmp.h:28
#define INCREASE_MAXPOW_BY_THREE_CHAIN
Definition: eeprom.h:87
void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, int eep_start_loc, int size)
Definition: ath9k_eeprom.c:97
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define EIO
Input/output error.
Definition: errno.h:433
#define AR_SREV_9271(_ah)
Definition: reg.h:853
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
uint8_t ah
Definition: registers.h:85
#define AR5416_MAX_PWR_RANGE_IN_HALF_DB
Definition: eeprom.h:158
#define AR5416_EEPROM_S
Definition: eeprom.h:60
void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
Definition: ath9k_eeprom.c:298
signed short int16_t
Definition: stdint.h:16
u8 tPow2x[4]
Definition: ar9003_eeprom.h:24
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
#define CTL_EDGE_TPOWER(_ctl)
Definition: eeprom.h:213
uint8_t u8
Definition: stdint.h:19
u16 max_power_level
Definition: ath.h:139
#define MAX_RATE_POWER
Definition: hw.h:144
uint32_t u32
Definition: stdint.h:23
#define AR5416_EEPROM_OFFSET
Definition: eeprom.h:61
#define DBG2(...)
Definition: compiler.h:515
if(natsemi->flags &NATSEMI_64BIT) return 1
void * memset(void *dest, int character, size_t len) __nonnull
u16 ctl_center
Definition: hw.h:423