iPXE
rhine.c
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1 /*
2  * Copyright (C) 2012 Adrian Jamroz <adrian.jamroz@gmail.com>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of the
7  * License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12  * General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17  * 02110-1301, USA.
18  */
19 
20 FILE_LICENCE ( GPL2_OR_LATER );
21 
22 #include <stdint.h>
23 #include <string.h>
24 #include <unistd.h>
25 #include <errno.h>
26 #include <byteswap.h>
27 #include <ipxe/netdevice.h>
28 #include <ipxe/ethernet.h>
29 #include <ipxe/if_ether.h>
30 #include <ipxe/iobuf.h>
31 #include <ipxe/malloc.h>
32 #include <ipxe/pci.h>
33 #include <ipxe/mii.h>
34 #include "rhine.h"
35 
36 /** @file
37  *
38  * VIA Rhine network driver
39  *
40  */
41 
42 /******************************************************************************
43  *
44  * MII interface
45  *
46  ******************************************************************************
47  */
48 
49 /**
50  * Read from MII register
51  *
52  * @v mdio MII interface
53  * @v phy PHY address
54  * @v reg Register address
55  * @ret value Data read, or negative error
56  */
57 static int rhine_mii_read ( struct mii_interface *mdio,
58  unsigned int phy __unused, unsigned int reg ) {
59  struct rhine_nic *rhn = container_of ( mdio, struct rhine_nic, mdio );
60  unsigned int timeout = RHINE_TIMEOUT_US;
61  uint8_t cr;
62 
63  DBGC2 ( rhn, "RHINE %p MII read reg %d\n", rhn, reg );
64 
65  /* Initiate read */
66  writeb ( reg, rhn->regs + RHINE_MII_ADDR );
67  cr = readb ( rhn->regs + RHINE_MII_CR );
68  writeb ( ( cr | RHINE_MII_CR_RDEN ), rhn->regs + RHINE_MII_CR );
69 
70  /* Wait for read to complete */
71  while ( timeout-- ) {
72  udelay ( 1 );
73  cr = readb ( rhn->regs + RHINE_MII_CR );
74  if ( ! ( cr & RHINE_MII_CR_RDEN ) )
75  return readw ( rhn->regs + RHINE_MII_RDWR );
76  }
77 
78  DBGC ( rhn, "RHINE %p MII read timeout\n", rhn );
79  return -ETIMEDOUT;
80 }
81 
82 /**
83  * Write to MII register
84  *
85  * @v mdio MII interface
86  * @v phy PHY address
87  * @v reg Register address
88  * @v data Data to write
89  * @ret rc Return status code
90  */
91 static int rhine_mii_write ( struct mii_interface *mdio,
92  unsigned int phy __unused, unsigned int reg,
93  unsigned int data ) {
94  struct rhine_nic *rhn = container_of ( mdio, struct rhine_nic, mdio );
95  unsigned int timeout = RHINE_TIMEOUT_US;
96  uint8_t cr;
97 
98  DBGC2 ( rhn, "RHINE %p MII write reg %d data 0x%04x\n",
99  rhn, reg, data );
100 
101  /* Initiate write */
102  writeb ( reg, rhn->regs + RHINE_MII_ADDR );
103  writew ( data, rhn->regs + RHINE_MII_RDWR );
104  cr = readb ( rhn->regs + RHINE_MII_CR );
105  writeb ( ( cr | RHINE_MII_CR_WREN ), rhn->regs + RHINE_MII_CR );
106 
107  /* Wait for write to complete */
108  while ( timeout-- ) {
109  udelay ( 1 );
110  cr = readb ( rhn->regs + RHINE_MII_CR );
111  if ( ! ( cr & RHINE_MII_CR_WREN ) )
112  return 0;
113  }
114 
115  DBGC ( rhn, "RHINE %p MII write timeout\n", rhn );
116  return -ETIMEDOUT;
117 }
118 
119 /** Rhine MII operations */
121  .read = rhine_mii_read,
122  .write = rhine_mii_write,
123 };
124 
125 /**
126  * Enable auto-polling
127  *
128  * @v rhn Rhine device
129  * @ret rc Return status code
130  *
131  * This is voodoo. There seems to be no documentation on exactly what
132  * we are waiting for, or why we have to do anything other than simply
133  * turn the feature on.
134  */
135 static int rhine_mii_autopoll ( struct rhine_nic *rhn ) {
136  unsigned int timeout = RHINE_TIMEOUT_US;
137  uint8_t addr;
138 
139  /* Initiate auto-polling */
140  writeb ( MII_BMSR, rhn->regs + RHINE_MII_ADDR );
142 
143  /* Wait for auto-polling to complete */
144  while ( timeout-- ) {
145  udelay ( 1 );
146  addr = readb ( rhn->regs + RHINE_MII_ADDR );
147  if ( ! ( addr & RHINE_MII_ADDR_MDONE ) ) {
149  rhn->regs + RHINE_MII_ADDR );
150  return 0;
151  }
152  }
153 
154  DBGC ( rhn, "RHINE %p MII auto-poll timeout\n", rhn );
155  return -ETIMEDOUT;
156 }
157 
158 /******************************************************************************
159  *
160  * Device reset
161  *
162  ******************************************************************************
163  */
164 
165 /**
166  * Reset hardware
167  *
168  * @v rhn Rhine device
169  * @ret rc Return status code
170  *
171  * We're using PIO because this might reset the MMIO enable bit.
172  */
173 static int rhine_reset ( struct rhine_nic *rhn ) {
174  unsigned int timeout = RHINE_TIMEOUT_US;
175  uint8_t cr1;
176 
177  DBGC ( rhn, "RHINE %p reset\n", rhn );
178 
179  /* Initiate reset */
180  outb ( RHINE_CR1_RESET, rhn->ioaddr + RHINE_CR1 );
181 
182  /* Wait for reset to complete */
183  while ( timeout-- ) {
184  udelay ( 1 );
185  cr1 = inb ( rhn->ioaddr + RHINE_CR1 );
186  if ( ! ( cr1 & RHINE_CR1_RESET ) )
187  return 0;
188  }
189 
190  DBGC ( rhn, "RHINE %p reset timeout\n", rhn );
191  return -ETIMEDOUT;
192 }
193 
194 /**
195  * Enable MMIO register access
196  *
197  * @v rhn Rhine device
198  * @v revision Card revision
199  */
200 static void rhine_enable_mmio ( struct rhine_nic *rhn, int revision ) {
201  uint8_t conf;
202 
203  if ( revision < RHINE_REVISION_OLD ) {
204  conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_A );
205  outb ( ( conf | RHINE_CHIPCFG_A_MMIO ),
206  rhn->ioaddr + RHINE_CHIPCFG_A );
207  } else {
208  conf = inb ( rhn->ioaddr + RHINE_CHIPCFG_D );
209  outb ( ( conf | RHINE_CHIPCFG_D_MMIO ),
210  rhn->ioaddr + RHINE_CHIPCFG_D );
211  }
212 }
213 
214 /**
215  * Reload EEPROM contents
216  *
217  * @v rhn Rhine device
218  * @ret rc Return status code
219  *
220  * We're using PIO because this might reset the MMIO enable bit.
221  */
222 static int rhine_reload_eeprom ( struct rhine_nic *rhn ) {
223  unsigned int timeout = RHINE_TIMEOUT_US;
224  uint8_t eeprom;
225 
226  /* Initiate reload */
227  eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
229  rhn->ioaddr + RHINE_EEPROM_CTRL );
230 
231  /* Wait for reload to complete */
232  while ( timeout-- ) {
233  udelay ( 1 );
234  eeprom = inb ( rhn->ioaddr + RHINE_EEPROM_CTRL );
235  if ( ! ( eeprom & RHINE_EEPROM_CTRL_RELOAD ) )
236  return 0;
237  }
238 
239  DBGC ( rhn, "RHINE %p EEPROM reload timeout\n", rhn );
240  return -ETIMEDOUT;
241 }
242 
243 /******************************************************************************
244  *
245  * Link state
246  *
247  ******************************************************************************
248  */
249 
250 /**
251  * Check link state
252  *
253  * @v netdev Network device
254  */
255 static void rhine_check_link ( struct net_device *netdev ) {
256  struct rhine_nic *rhn = netdev->priv;
257  uint8_t mii_sr;
258 
259  /* Read MII status register */
260  mii_sr = readb ( rhn->regs + RHINE_MII_SR );
261  DBGC ( rhn, "RHINE %p link status %02x\n", rhn, mii_sr );
262 
263  /* Report link state */
264  if ( ! ( mii_sr & RHINE_MII_SR_LINKPOLL ) ) {
266  } else if ( mii_sr & RHINE_MII_SR_PHYERR ) {
267  netdev_link_err ( netdev, -EIO );
268  } else {
270  }
271 }
272 
273 /******************************************************************************
274  *
275  * Network device interface
276  *
277  ******************************************************************************
278  */
279 
280 /**
281  * Create descriptor ring
282  *
283  * @v rhn Rhine device
284  * @v ring Descriptor ring
285  * @ret rc Return status code
286  */
287 static int rhine_create_ring ( struct rhine_nic *rhn,
288  struct rhine_ring *ring ) {
289  size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
290  struct rhine_descriptor *next;
292  unsigned int i;
293 
294  /* Allocate descriptors */
295  ring->desc = malloc_dma ( len, RHINE_RING_ALIGN );
296  if ( ! ring->desc )
297  return -ENOMEM;
298 
299  /* Initialise descriptor ring */
300  memset ( ring->desc, 0, len );
301  for ( i = 0 ; i < ring->count ; i++ ) {
302  next = &ring->desc[ ( i + 1 ) % ring->count ];
303  ring->desc[i].next = cpu_to_le32 ( virt_to_bus ( next ) );
304  }
305 
306  /* Program ring address */
307  address = virt_to_bus ( ring->desc );
308  writel ( address, rhn->regs + ring->reg );
309 
310  DBGC ( rhn, "RHINE %p ring %02x is at [%08llx,%08llx)\n",
311  rhn, ring->reg, ( ( unsigned long long ) address ),
312  ( ( unsigned long long ) address + len ) );
313 
314  return 0;
315 }
316 
317 /**
318  * Destroy descriptor ring
319  *
320  * @v rhn Rhine device
321  * @v ring Descriptor ring
322  */
323 static void rhine_destroy_ring ( struct rhine_nic *rhn,
324  struct rhine_ring *ring ) {
325  size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
326 
327  /* Clear ring address */
328  writel ( 0, rhn->regs + ring->reg );
329 
330  /* Free descriptor ring */
331  free_dma ( ring->desc, len );
332  ring->desc = NULL;
333  ring->prod = 0;
334  ring->cons = 0;
335 }
336 
337 /**
338  * Refill RX descriptor ring
339  *
340  * @v rhn Rhine device
341  */
342 static void rhine_refill_rx ( struct rhine_nic *rhn ) {
343  struct rhine_descriptor *desc;
344  struct io_buffer *iobuf;
345  unsigned int rx_idx;
347 
348  while ( ( rhn->rx.prod - rhn->rx.cons ) < RHINE_RXDESC_NUM ) {
349 
350  /* Allocate I/O buffer */
351  iobuf = alloc_iob ( RHINE_RX_MAX_LEN );
352  if ( ! iobuf ) {
353  /* Wait for next refill */
354  return;
355  }
356 
357  /* Populate next receive descriptor */
358  rx_idx = ( rhn->rx.prod++ % RHINE_RXDESC_NUM );
359  desc = &rhn->rx.desc[rx_idx];
360  address = virt_to_bus ( iobuf->data );
361  desc->buffer = cpu_to_le32 ( address );
362  desc->des1 =
365  wmb();
366  desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
367 
368  /* Record I/O buffer */
369  rhn->rx_iobuf[rx_idx] = iobuf;
370 
371  DBGC2 ( rhn, "RHINE %p RX %d is [%llx,%llx)\n", rhn, rx_idx,
372  ( ( unsigned long long ) address ),
373  ( ( unsigned long long ) address + RHINE_RX_MAX_LEN ) );
374  }
375 }
376 
377 /**
378  * Open network device
379  *
380  * @v netdev Network device
381  * @ret rc Return status code
382  */
383 static int rhine_open ( struct net_device *netdev ) {
384  struct rhine_nic *rhn = netdev->priv;
385  int rc;
386 
387  /* Create transmit ring */
388  if ( ( rc = rhine_create_ring ( rhn, &rhn->tx ) ) != 0 )
389  goto err_create_tx;
390 
391  /* Create receive ring */
392  if ( ( rc = rhine_create_ring ( rhn, &rhn->rx ) ) != 0 )
393  goto err_create_rx;
394 
395  /* Set receive configuration */
398 
399  /* Enable link status monitoring */
400  if ( ( rc = rhine_mii_autopoll ( rhn ) ) != 0 )
401  goto err_mii_autopoll;
402 
403  /* Some cards need an extra delay(observed with VT6102) */
404  mdelay ( 10 );
405 
406  /* Enable RX/TX of packets */
408  rhn->regs + RHINE_CR0 );
409 
410  /* Enable auto polling and full duplex operation */
411  rhn->cr1 = RHINE_CR1_FDX;
412  writeb ( rhn->cr1, rhn->regs + RHINE_CR1 );
413 
414  /* Refill RX ring */
415  rhine_refill_rx ( rhn );
416 
417  /* Update link state */
419 
420  return 0;
421 
422  err_mii_autopoll:
423  rhine_destroy_ring ( rhn, &rhn->rx );
424  err_create_rx:
425  rhine_destroy_ring ( rhn, &rhn->tx );
426  err_create_tx:
427  return rc;
428 }
429 
430 /**
431  * Close network device
432  *
433  * @v netdev Network device
434  */
435 static void rhine_close ( struct net_device *netdev ) {
436  struct rhine_nic *rhn = netdev->priv;
437  unsigned int i;
438 
439  /* Disable interrupts */
440  writeb ( 0, RHINE_IMR0 );
441  writeb ( 0, RHINE_IMR1 );
442 
443  /* Stop card, clear RXON and TXON bits */
445 
446  /* Destroy receive ring */
447  rhine_destroy_ring ( rhn, &rhn->rx );
448 
449  /* Discard any unused receive buffers */
450  for ( i = 0 ; i < RHINE_RXDESC_NUM ; i++ ) {
451  if ( rhn->rx_iobuf[i] )
452  free_iob ( rhn->rx_iobuf[i] );
453  rhn->rx_iobuf[i] = NULL;
454  }
455 
456  /* Destroy transmit ring */
457  rhine_destroy_ring ( rhn, &rhn->tx );
458 }
459 
460 /**
461  * Transmit packet
462  *
463  * @v netdev Network device
464  * @v iobuf I/O buffer
465  * @ret rc Return status code
466  */
467 static int rhine_transmit ( struct net_device *netdev,
468  struct io_buffer *iobuf ) {
469  struct rhine_nic *rhn = netdev->priv;
470  struct rhine_descriptor *desc;
472  unsigned int tx_idx;
473 
474  /* Get next transmit descriptor */
475  if ( ( rhn->tx.prod - rhn->tx.cons ) >= RHINE_TXDESC_NUM )
476  return -ENOBUFS;
477  tx_idx = ( rhn->tx.prod++ % RHINE_TXDESC_NUM );
478  desc = &rhn->tx.desc[tx_idx];
479 
480  /* Pad and align packet */
481  iob_pad ( iobuf, ETH_ZLEN );
482  address = virt_to_bus ( iobuf->data );
483 
484  /* Populate transmit descriptor */
485  desc->buffer = cpu_to_le32 ( address );
488  RHINE_DES1_SIZE ( iob_len ( iobuf ) ) );
489  wmb();
490  desc->des0 = cpu_to_le32 ( RHINE_DES0_OWN );
491  wmb();
492 
493  /* Notify card that there are packets ready to transmit */
494  writeb ( ( rhn->cr1 | RHINE_CR1_TXPOLL ), rhn->regs + RHINE_CR1 );
495 
496  DBGC2 ( rhn, "RHINE %p TX %d is [%llx,%llx)\n", rhn, tx_idx,
497  ( ( unsigned long long ) address ),
498  ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
499 
500  return 0;
501 }
502 
503 /**
504  * Poll for completed packets
505  *
506  * @v netdev Network device
507  */
508 static void rhine_poll_tx ( struct net_device *netdev ) {
509  struct rhine_nic *rhn = netdev->priv;
510  struct rhine_descriptor *desc;
511  unsigned int tx_idx;
512  uint32_t des0;
513 
514  /* Check for completed packets */
515  while ( rhn->tx.cons != rhn->tx.prod ) {
516 
517  /* Get next transmit descriptor */
518  tx_idx = ( rhn->tx.cons % RHINE_TXDESC_NUM );
519  desc = &rhn->tx.desc[tx_idx];
520 
521  /* Stop if descriptor is still in use */
522  if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
523  return;
524 
525  /* Complete TX descriptor */
526  des0 = le32_to_cpu ( desc->des0 );
527  if ( des0 & RHINE_TDES0_TERR ) {
528  DBGC ( rhn, "RHINE %p TX %d error (DES0 %08x)\n",
529  rhn, tx_idx, des0 );
531  } else {
532  DBGC2 ( rhn, "RHINE %p TX %d complete\n", rhn, tx_idx );
534  }
535  rhn->tx.cons++;
536  }
537 }
538 
539 /**
540  * Poll for received packets
541  *
542  * @v netdev Network device
543  */
544 static void rhine_poll_rx ( struct net_device *netdev ) {
545  struct rhine_nic *rhn = netdev->priv;
546  struct rhine_descriptor *desc;
547  struct io_buffer *iobuf;
548  unsigned int rx_idx;
549  uint32_t des0;
550  size_t len;
551 
552  /* Check for received packets */
553  while ( rhn->rx.cons != rhn->rx.prod ) {
554 
555  /* Get next receive descriptor */
556  rx_idx = ( rhn->rx.cons % RHINE_RXDESC_NUM );
557  desc = &rhn->rx.desc[rx_idx];
558 
559  /* Stop if descriptor is still in use */
560  if ( desc->des0 & cpu_to_le32 ( RHINE_DES0_OWN ) )
561  return;
562 
563  /* Populate I/O buffer */
564  iobuf = rhn->rx_iobuf[rx_idx];
565  rhn->rx_iobuf[rx_idx] = NULL;
566  des0 = le32_to_cpu ( desc->des0 );
567  len = ( RHINE_DES0_GETSIZE ( des0 ) - 4 /* strip CRC */ );
568  iob_put ( iobuf, len );
569 
570  /* Hand off to network stack */
571  if ( des0 & RHINE_RDES0_RXOK ) {
572  DBGC2 ( rhn, "RHINE %p RX %d complete (length %zd)\n",
573  rhn, rx_idx, len );
574  netdev_rx ( netdev, iobuf );
575  } else {
576  DBGC ( rhn, "RHINE %p RX %d error (length %zd, DES0 "
577  "%08x)\n", rhn, rx_idx, len, des0 );
578  netdev_rx_err ( netdev, iobuf, -EIO );
579  }
580  rhn->rx.cons++;
581  }
582 }
583 
584 /**
585  * Poll for completed and received packets
586  *
587  * @v netdev Network device
588  */
589 static void rhine_poll ( struct net_device *netdev ) {
590  struct rhine_nic *rhn = netdev->priv;
591  uint8_t isr0;
592  uint8_t isr1;
593 
594  /* Read and acknowledge interrupts */
595  isr0 = readb ( rhn->regs + RHINE_ISR0 );
596  isr1 = readb ( rhn->regs + RHINE_ISR1 );
597  if ( isr0 )
598  writeb ( isr0, rhn->regs + RHINE_ISR0 );
599  if ( isr1 )
600  writeb ( isr1, rhn->regs + RHINE_ISR1 );
601 
602  /* Report unexpected errors */
603  if ( ( isr0 & ( RHINE_ISR0_MIBOVFL | RHINE_ISR0_PCIERR |
605  ( isr1 & ( RHINE_ISR1_GPI | RHINE_ISR1_TXABORT |
607  RHINE_ISR1_TXFIFOUNFL ) ) ) {
608  DBGC ( rhn, "RHINE %p unexpected ISR0 %02x ISR1 %02x\n",
609  rhn, isr0, isr1 );
610  /* Report as a TX error */
611  netdev_tx_err ( netdev, NULL, -EIO );
612  }
613 
614  /* Poll for TX completions, if applicable */
615  if ( isr0 & ( RHINE_ISR0_TXDONE | RHINE_ISR0_TXERR ) )
616  rhine_poll_tx ( netdev );
617 
618  /* Poll for RX completions, if applicable */
619  if ( isr0 & ( RHINE_ISR0_RXDONE | RHINE_ISR0_RXERR ) )
620  rhine_poll_rx ( netdev );
621 
622  /* Handle RX buffer exhaustion */
623  if ( isr1 & RHINE_ISR1_RXNOBUF ) {
624  rhine_poll_rx ( netdev );
626  }
627 
628  /* Check link state, if applicable */
629  if ( isr1 & RHINE_ISR1_PORTSTATE )
631 
632  /* Refill RX ring */
633  rhine_refill_rx ( rhn );
634 }
635 
636 /**
637  * Enable or disable interrupts
638  *
639  * @v netdev Network device
640  * @v enable Interrupts should be enabled
641  */
642 static void rhine_irq ( struct net_device *netdev, int enable ) {
643  struct rhine_nic *nic = netdev->priv;
644 
645  if ( enable ) {
646  /* Enable interrupts */
647  writeb ( 0xff, nic->regs + RHINE_IMR0 );
648  writeb ( 0xff, nic->regs + RHINE_IMR1 );
649  } else {
650  /* Disable interrupts */
651  writeb ( 0, nic->regs + RHINE_IMR0 );
652  writeb ( 0, nic->regs + RHINE_IMR1 );
653  }
654 }
655 
656 /** Rhine network device operations */
658  .open = rhine_open,
659  .close = rhine_close,
660  .transmit = rhine_transmit,
661  .poll = rhine_poll,
662  .irq = rhine_irq,
663 };
664 
665 /******************************************************************************
666  *
667  * PCI interface
668  *
669  ******************************************************************************
670  */
671 
672 /**
673  * Probe PCI device
674  *
675  * @v pci PCI device
676  * @ret rc Return status code
677  */
678 static int rhine_probe ( struct pci_device *pci ) {
679  struct net_device *netdev;
680  struct rhine_nic *rhn;
682  unsigned int i;
683  int rc;
684 
685  /* Allocate and initialise net device */
686  netdev = alloc_etherdev ( sizeof ( *rhn ) );
687  if ( ! netdev ) {
688  rc = -ENOMEM;
689  goto err_alloc;
690  }
692  rhn = netdev->priv;
693  pci_set_drvdata ( pci, netdev );
694  netdev->dev = &pci->dev;
695  memset ( rhn, 0, sizeof ( *rhn ) );
696  rhine_init_ring ( &rhn->tx, RHINE_TXDESC_NUM, RHINE_TXQUEUE_BASE );
697  rhine_init_ring ( &rhn->rx, RHINE_RXDESC_NUM, RHINE_RXQUEUE_BASE );
698 
699  /* Fix up PCI device */
700  adjust_pci_device ( pci );
701 
702  /* Map registers */
703  rhn->regs = ioremap ( pci->membase, RHINE_BAR_SIZE );
704  rhn->ioaddr = pci->ioaddr;
705  DBGC ( rhn, "RHINE %p regs at %08lx, I/O at %04lx\n", rhn,
706  pci->membase, pci->ioaddr );
707 
708  /* Reset the NIC */
709  if ( ( rc = rhine_reset ( rhn ) ) != 0 )
710  goto err_reset;
711 
712  /* Reload EEPROM */
713  if ( ( rc = rhine_reload_eeprom ( rhn ) ) != 0 )
714  goto err_reload_eeprom;
715 
716  /* Read card revision and enable MMIO */
718  DBGC ( rhn, "RHINE %p revision %#02x detected\n", rhn, revision );
719  rhine_enable_mmio ( rhn, revision );
720 
721  /* Read MAC address */
722  for ( i = 0 ; i < ETH_ALEN ; i++ )
723  netdev->hw_addr[i] = readb ( rhn->regs + RHINE_MAC + i );
724 
725  /* Initialise and reset MII interface */
726  mdio_init ( &rhn->mdio, &rhine_mii_operations );
727  mii_init ( &rhn->mii, &rhn->mdio, 0 );
728  if ( ( rc = mii_reset ( &rhn->mii ) ) != 0 ) {
729  DBGC ( rhn, "RHINE %p could not reset MII: %s\n",
730  rhn, strerror ( rc ) );
731  goto err_mii_reset;
732  }
733  DBGC ( rhn, "RHINE PHY vendor %04x device %04x\n",
734  mii_read ( &rhn->mii, 0x02 ), mii_read ( &rhn->mii, 0x03 ) );
735 
736  /* Register network device */
737  if ( ( rc = register_netdev ( netdev ) ) != 0 )
738  goto err_register_netdev;
739 
740  /* Set initial link state */
742 
743  return 0;
744 
745  err_register_netdev:
746  err_mii_reset:
747  err_reload_eeprom:
748  rhine_reset ( rhn );
749  err_reset:
751  netdev_put ( netdev );
752  err_alloc:
753  return rc;
754 }
755 
756 /**
757  * Remove PCI device
758  *
759  * @v pci PCI device
760  */
761 static void rhine_remove ( struct pci_device *pci ) {
762  struct net_device *netdev = pci_get_drvdata ( pci );
763  struct rhine_nic *nic = netdev->priv;
764 
765  /* Unregister network device */
767 
768  /* Reset card */
769  rhine_reset ( nic );
770 
771  /* Free network device */
773  netdev_put ( netdev );
774 }
775 
776 /** Rhine PCI device IDs */
777 static struct pci_device_id rhine_nics[] = {
778  PCI_ROM ( 0x1106, 0x3065, "dlink-530tx", "VIA VT6102", 0 ),
779  PCI_ROM ( 0x1106, 0x3106, "vt6105", "VIA VT6105", 0 ),
780  PCI_ROM ( 0x1106, 0x3043, "dlink-530tx-old", "VIA VT3043", 0 ),
781  PCI_ROM ( 0x1106, 0x3053, "vt6105m", "VIA VT6105M", 0 ),
782  PCI_ROM ( 0x1106, 0x6100, "via-rhine-old", "VIA 86C100A", 0 )
783 };
784 
785 /** Rhine PCI driver */
786 struct pci_driver rhine_driver __pci_driver = {
787  .ids = rhine_nics,
788  .id_count = ( sizeof ( rhine_nics ) / sizeof ( rhine_nics[0] ) ),
789  .probe = rhine_probe,
790  .remove = rhine_remove,
791 };
#define RHINE_TDES1_EDP
Definition: rhine.h:28
static void rhine_poll_tx(struct net_device *netdev)
Poll for completed packets.
Definition: rhine.c:508
unsigned long membase
Memory base.
Definition: pci.h:194
#define RHINE_DES1_CHAIN
Definition: rhine.h:35
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
wmb()
#define RHINE_ISR1
Interrupt service 1.
Definition: rhine.h:122
uint8_t readb(volatile uint8_t *io_addr)
Read byte from memory-mapped device.
#define iob_put(iobuf, len)
Definition: iobuf.h:116
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition: netdevice.c:501
#define RHINE_ISR0_MIBOVFL
Definition: rhine.h:112
A PCI driver.
Definition: pci.h:224
static void rhine_destroy_ring(struct rhine_nic *rhn, struct rhine_ring *ring)
Destroy descriptor ring.
Definition: rhine.c:323
static void rhine_enable_mmio(struct rhine_nic *rhn, int revision)
Enable MMIO register access.
Definition: rhine.c:200
#define le32_to_cpu(value)
Definition: byteswap.h:113
int(* open)(struct net_device *netdev)
Open network device.
Definition: netdevice.h:222
unsigned long ioaddr
I/O address (some PIO access is always required)
Definition: rhine.h:233
uint32_t next
Next descriptor address.
Definition: myson.h:18
void netdev_tx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard transmitted packet.
Definition: netdevice.c:369
unsigned long ioaddr
I/O address.
Definition: pci.h:200
#define RHINE_CR1_RESET
Definition: rhine.h:100
Error codes.
unsigned int cons
Consumer index.
Definition: rhine.h:208
#define RHINE_ISR0_TXRINGERR
Definition: rhine.h:115
uint16_t readw(volatile uint16_t *io_addr)
Read 16-bit word from memory-mapped device.
static void netdev_tx_complete_next(struct net_device *netdev)
Complete network transmission.
Definition: netdevice.h:758
I/O buffers.
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
struct pci_device_id * ids
PCI ID table.
Definition: pci.h:226
uint64_t address
Base address.
Definition: ena.h:24
int(* read)(struct mii_interface *mdio, unsigned int phy, unsigned int reg)
Read from MII register.
Definition: mii.h:27
static int rhine_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: rhine.c:467
#define RHINE_CR0_STOPNIC
Definition: rhine.h:95
#define RHINE_ISR0_RXRINGERR
Definition: rhine.h:114
#define RHINE_CR0
Command 0 register.
Definition: rhine.h:90
#define DBGC(...)
Definition: compiler.h:505
#define RHINE_RING_ALIGN
Definition: rhine.h:65
#define RHINE_DES0_OWN
Definition: rhine.h:26
void netdev_tx_complete_next_err(struct net_device *netdev, int rc)
Complete network transmission.
Definition: netdevice.c:434
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:186
unsigned int reg
Register address.
Definition: rhine.h:213
FILE_LICENCE(GPL2_OR_LATER)
#define RHINE_CHIPCFG_D
Chip configuration D.
Definition: rhine.h:195
#define RHINE_MII_CR_AUTOPOLL
Definition: rhine.h:164
static struct pci_device_id rhine_nics[]
Rhine PCI device IDs.
Definition: rhine.c:777
#define RHINE_TDES1_STP
Definition: rhine.h:29
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
struct io_buffer * alloc_iob(size_t len)
Allocate I/O buffer.
Definition: iobuf.c:128
#define RHINE_ISR1_RXFIFOOVFL
Definition: rhine.h:127
struct device dev
Generic device.
Definition: pci.h:189
#define RHINE_TDES0_TERR
Definition: rhine.h:56
uint32_t des0
Definition: rhine.h:11
#define RHINE_RCR
Receive control register.
Definition: rhine.h:76
void writeb(uint8_t data, volatile uint8_t *io_addr)
Write byte to memory-mapped device.
static void mdio_init(struct mii_interface *mdio, struct mii_operations *op)
Initialise MII interface.
Definition: mii.h:63
Dynamic memory allocation.
A VIA Rhine descriptor ring.
Definition: rhine.h:202
eeprom
Definition: 3c90x.h:232
static void rhine_remove(struct pci_device *pci)
Remove PCI device.
Definition: rhine.c:761
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:498
static void rhine_check_link(struct net_device *netdev)
Check link state.
Definition: rhine.c:255
#define RHINE_CR0_TXEN
Definition: rhine.h:93
#define RHINE_ISR1_TXABORT
Definition: rhine.h:125
#define RHINE_TIMEOUT_US
Default timeout.
Definition: rhine.h:16
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:338
#define ENOMEM
Not enough space.
Definition: errno.h:534
#define RHINE_RXDESC_NUM
Rhine descriptor rings sizes.
Definition: rhine.h:68
#define RHINE_IMR1
Interrupt enable mask register 1.
Definition: rhine.h:136
#define RHINE_MII_SR_PHYERR
Definition: rhine.h:151
struct mii_interface mdio
MII interface.
Definition: rhine.h:240
#define RHINE_ISR1_PORTSTATE
Definition: rhine.h:124
#define RHINE_CR0_STARTNIC
Definition: rhine.h:96
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
static int rhine_create_ring(struct rhine_nic *rhn, struct rhine_ring *ring)
Create descriptor ring.
Definition: rhine.c:287
A VIA Rhine network card.
Definition: rhine.h:231
Rhine descriptor format.
Definition: rhine.h:19
#define RHINE_ISR1_RXNOBUF
Definition: rhine.h:126
#define RHINE_ISR0_RXDONE
Definition: rhine.h:119
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:555
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:35
Ethernet protocol.
struct mii_device mii
MII device.
Definition: rhine.h:242
#define RHINE_MII_ADDR_MSRCEN
Definition: rhine.h:172
void * priv
Driver private data.
Definition: netdevice.h:425
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:768
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
uint32_t des1
Definition: rhine.h:21
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
static struct net_device * netdev
Definition: gdbudp.c:52
uint32_t des0
Definition: rhine.h:20
struct pci_driver rhine_driver __pci_driver
Rhine PCI driver.
Definition: rhine.c:786
struct io_buffer * rx_iobuf[RHINE_RXDESC_NUM]
Receive I/O buffers.
Definition: rhine.h:249
#define RHINE_MII_ADDR_MDONE
Definition: rhine.h:173
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:844
#define RHINE_MII_CR
MII control register.
Definition: rhine.h:163
#define cpu_to_le32(value)
Definition: byteswap.h:107
#define RHINE_TXDESC_NUM
Definition: rhine.h:69
void * regs
Registers.
Definition: rhine.h:235
#define RHINE_MII_SR
MII status register.
Definition: rhine.h:148
uint32_t revision
Definition: ib_mad.h:20
char * strerror(int errno)
Retrieve string representation of error number.
Definition: strerror.c:78
#define RHINE_EEPROM_CTRL
EERPOM control/status register.
Definition: rhine.h:179
static int rhine_open(struct net_device *netdev)
Open network device.
Definition: rhine.c:383
#define RHINE_EEPROM_CTRL_RELOAD
Definition: rhine.h:181
#define RHINE_DES0_GETSIZE(_x)
Definition: rhine.h:37
static unsigned int unsigned int reg
Definition: intel.h:245
PCI bus.
#define RHINE_ISR0_RXERR
Definition: rhine.h:117
A PCI device.
Definition: pci.h:187
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:667
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition: iobuf.h:151
#define RHINE_CHIPCFG_D_MMIO
Definition: rhine.h:197
#define RHINE_RCR_BCAST_ACCEPT
Definition: rhine.h:79
A network device.
Definition: netdevice.h:348
#define RHINE_BAR_SIZE
Rhine BAR size.
Definition: rhine.h:13
#define RHINE_MII_RDWR
MII read/write data.
Definition: rhine.h:176
#define RHINE_CR1_TXPOLL
Definition: rhine.h:102
void netdev_link_err(struct net_device *netdev, int rc)
Mark network device as having a specific link state.
Definition: netdevice.c:163
Media Independent Interface.
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:511
u32 addr
Definition: sky2.h:8
unsigned char uint8_t
Definition: stdint.h:10
static void rhine_irq(struct net_device *netdev, int enable)
Enable or disable interrupts.
Definition: rhine.c:642
static int rhine_mii_write(struct mii_interface *mdio, unsigned int phy __unused, unsigned int reg, unsigned int data)
Write to MII register.
Definition: rhine.c:91
uint32_t buffer
Definition: rhine.h:22
int mii_reset(struct mii_device *mii)
Reset MII device.
Definition: mii.c:74
#define RHINE_MAC
Rhine MAC address registers.
Definition: rhine.h:73
uint8_t inb(volatile uint8_t *io_addr)
Read byte from I/O-mapped device.
#define ETH_ALEN
Definition: if_ether.h:8
static int rhine_probe(struct pci_device *pci)
Probe PCI device.
Definition: rhine.c:678
#define ETH_ZLEN
Definition: if_ether.h:10
A PCI device ID list entry.
Definition: pci.h:151
Definition: nic.h:49
unsigned int uint32_t
Definition: stdint.h:12
struct rhine_ring rx
Receive descriptor ring.
Definition: rhine.h:247
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
#define RHINE_MII_CR_RDEN
Definition: rhine.h:165
static int rhine_mii_read(struct mii_interface *mdio, unsigned int phy __unused, unsigned int reg)
Read from MII register.
Definition: rhine.c:57
Network device operations.
Definition: netdevice.h:213
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition: netdevice.c:470
struct device * dev
Underlying hardware device.
Definition: netdevice.h:360
static void mii_init(struct mii_device *mii, struct mii_interface *mdio, unsigned int address)
Initialise MII device.
Definition: mii.h:75
static void rhine_poll_rx(struct net_device *netdev)
Poll for received packets.
Definition: rhine.c:544
Network device management.
MII interface operations.
Definition: mii.h:18
unsigned long physaddr_t
Definition: stdint.h:20
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:348
static int rhine_reset(struct rhine_nic *rhn)
Reset hardware.
Definition: rhine.c:173
Definition: sis900.h:22
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
#define outb(data, io_addr)
Definition: io.h:309
static int rhine_reload_eeprom(struct rhine_nic *rhn)
Reload EEPROM contents.
Definition: rhine.c:222
#define RHINE_MII_SR_LINKPOLL
Definition: rhine.h:153
uint32_t len
Length.
Definition: ena.h:14
#define ENOBUFS
No buffer space available.
Definition: errno.h:498
#define DBGC2(...)
Definition: compiler.h:522
int(* probe)(struct pci_device *pci)
Probe device.
Definition: pci.h:237
#define RHINE_ISR0_TXERR
Definition: rhine.h:116
#define RHINE_ISR1_TXFIFOUNFL
Definition: rhine.h:129
#define RHINE_IMR0
Interrupt enable mask register 0.
Definition: rhine.h:133
unsigned int count
Number of descriptors.
Definition: rhine.h:211
#define RHINE_TXQUEUE_BASE
TX queue 0 descriptor base address.
Definition: rhine.h:142
#define writew
Definition: w89c840.c:159
#define RHINE_MII_ADDR
MII port address.
Definition: rhine.h:171
void * data
Start of data.
Definition: iobuf.h:44
#define EIO
Input/output error.
Definition: errno.h:433
#define RHINE_ISR1_RXFIFOUNFL
Definition: rhine.h:128
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:264
An MII interface.
Definition: mii.h:43
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
#define PCI_REVISION
PCI revision.
Definition: pci.h:43
#define RHINE_CHIPCFG_A_MMIO
Definition: rhine.h:186
uint32_t next
Definition: rhine.h:23
static int mii_read(int phy_id, int location)
Definition: epic100.c:499
void timeout(int)
#define RHINE_REVISION_OLD
Definition: rhine.h:199
#define RHINE_ISR0
Interrupt service 0.
Definition: rhine.h:111
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
static void rhine_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: rhine.c:589
#define RHINE_RX_MAX_LEN
Definition: rhine.h:70
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
uint8_t cr1
Cached value of CR1 (to avoid read-modify-write on fast path)
Definition: rhine.h:237
#define MII_BMSR
Definition: atl1e.h:872
#define RHINE_DES1_SIZE(_x)
Definition: rhine.h:36
#define RHINE_ISR0_TXDONE
Definition: rhine.h:118
static int rhine_mii_autopoll(struct rhine_nic *rhn)
Enable auto-polling.
Definition: rhine.c:135
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
struct rhine_descriptor * desc
Descriptors.
Definition: rhine.h:204
#define RHINE_RCR_PHYS_ACCEPT
Definition: rhine.h:78
static struct mii_operations rhine_mii_operations
Rhine MII operations.
Definition: rhine.c:120
static struct net_device_operations rhine_operations
Rhine network device operations.
Definition: rhine.c:657
unsigned int prod
Producer index.
Definition: rhine.h:206
static void rhine_refill_rx(struct rhine_nic *rhn)
Refill RX descriptor ring.
Definition: rhine.c:342
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:375
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define ETIMEDOUT
Connection timed out.
Definition: errno.h:669
String functions.
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define RHINE_ISR1_GPI
Definition: rhine.h:123
#define RHINE_CHIPCFG_A
Chip configuration A.
Definition: rhine.h:184
void iob_pad(struct io_buffer *iobuf, size_t min_len)
Pad I/O buffer.
Definition: iobpad.c:49
#define RHINE_CR1_FDX
Definition: rhine.h:104
VIA Rhine network driver.
struct rhine_ring tx
Transmit descriptor ring.
Definition: rhine.h:245
static void rhine_close(struct net_device *netdev)
Close network device.
Definition: rhine.c:435
#define RHINE_RXQUEUE_BASE
RX queue descriptor base address.
Definition: rhine.h:139
#define RHINE_MII_CR_WREN
Definition: rhine.h:166
#define RHINE_RDES0_RXOK
Definition: rhine.h:39
#define RHINE_DES1_IC
Definition: rhine.h:27
#define RHINE_CR0_RXEN
Definition: rhine.h:94
#define RHINE_ISR0_PCIERR
Definition: rhine.h:113
#define RHINE_CR1
Command 1 register.
Definition: rhine.h:99
void * memset(void *dest, int character, size_t len) __nonnull
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
A persistent I/O buffer.
Definition: iobuf.h:32
#define RHINE_RCR_RUNT_ACCEPT
Definition: rhine.h:81