iPXE
bnxt.c
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1
2FILE_LICENCE ( GPL2_ONLY );
3
4#include <mii.h>
5#include <stdio.h>
6#include <string.h>
7#include <errno.h>
8#include <unistd.h>
9#include <byteswap.h>
10#include <ipxe/pci.h>
11#include <ipxe/iobuf.h>
12#include <ipxe/dma.h>
13#include <ipxe/timer.h>
14#include <ipxe/malloc.h>
15#include <ipxe/if_ether.h>
16#include <ipxe/ethernet.h>
17#include <ipxe/netdevice.h>
18#include "bnxt.h"
19#include "bnxt_dbg.h"
20
21static void bnxt_service_cq ( struct net_device *dev );
22static void bnxt_tx_complete ( struct net_device *dev, u16 hw_idx );
23static void bnxt_adv_cq_index ( struct bnxt *bp, u16 cnt );
24static void bnxt_adv_nq_index ( struct bnxt *bp, u16 cnt );
25static int bnxt_rx_complete ( struct net_device *dev, struct rx_pkt_cmpl *rx );
26void bnxt_link_evt ( struct bnxt *bp, struct hwrm_async_event_cmpl *evt );
27
28static struct pci_device_id bnxt_nics[] = {
29 PCI_ROM( 0x14e4, 0x1604, "14e4-1604", "Broadcom BCM957454", 0 ),
30 PCI_ROM( 0x14e4, 0x1605, "14e4-1605", "Broadcom BCM957454 RDMA", 0 ),
31 PCI_ROM( 0x14e4, 0x1606, "14e4-1606", "Broadcom BCM957454 RDMA VF", BNXT_FLAG_PCI_VF ),
32 PCI_ROM( 0x14e4, 0x1607, "bcm957454-1607", "Broadcom BCM957454 HV VF", BNXT_FLAG_PCI_VF ),
33 PCI_ROM( 0x14e4, 0x1608, "bcm957454-1608", "Broadcom BCM957454 RDMA HV VF", BNXT_FLAG_PCI_VF ),
34 PCI_ROM( 0x14e4, 0x1609, "14e4-1609", "Broadcom BCM957454 VF", BNXT_FLAG_PCI_VF ),
35 PCI_ROM( 0x14e4, 0x1614, "14e4-1614", "Broadcom BCM957454", 0 ),
36 PCI_ROM( 0x14e4, 0x16bd, "bcm95741x-16bd", "Broadcom BCM95741x RDMA_HV_VF", BNXT_FLAG_PCI_VF ),
37 PCI_ROM( 0x14e4, 0x16c0, "14e4-16c0", "Broadcom BCM957417", 0 ),
38 PCI_ROM( 0x14e4, 0x16c1, "14e4-16c1", "Broadcom BCM95741x VF", BNXT_FLAG_PCI_VF ),
39 PCI_ROM( 0x14e4, 0x16c5, "bcm95741x-16c5", "Broadcom BCM95741x HV VF", BNXT_FLAG_PCI_VF ),
40 PCI_ROM( 0x14e4, 0x16c8, "14e4-16c8", "Broadcom BCM957301", 0 ),
41 PCI_ROM( 0x14e4, 0x16c9, "14e4-16c9", "Broadcom BCM957302", 0 ),
42 PCI_ROM( 0x14e4, 0x16ca, "14e4-16ca", "Broadcom BCM957304", 0 ),
43 PCI_ROM( 0x14e4, 0x16cc, "14e4-16cc", "Broadcom BCM957417 MF", 0 ),
44 PCI_ROM( 0x14e4, 0x16cd, "14e4-16cd", "Broadcom BCM958700", 0 ),
45 PCI_ROM( 0x14e4, 0x16ce, "14e4-16ce", "Broadcom BCM957311", 0 ),
46 PCI_ROM( 0x14e4, 0x16cf, "14e4-16cf", "Broadcom BCM957312", 0 ),
47 PCI_ROM( 0x14e4, 0x16d0, "14e4-16d0", "Broadcom BCM957402", 0 ),
48 PCI_ROM( 0x14e4, 0x16d1, "14e4-16d1", "Broadcom BCM957404", 0 ),
49 PCI_ROM( 0x14e4, 0x16d2, "14e4-16d2", "Broadcom BCM957406", 0 ),
50 PCI_ROM( 0x14e4, 0x16d4, "14e4-16d4", "Broadcom BCM957402 MF", 0 ),
51 PCI_ROM( 0x14e4, 0x16d5, "14e4-16d5", "Broadcom BCM957407", 0 ),
52 PCI_ROM( 0x14e4, 0x16d6, "14e4-16d6", "Broadcom BCM957412", 0 ),
53 PCI_ROM( 0x14e4, 0x16d7, "14e4-16d7", "Broadcom BCM957414", 0 ),
54 PCI_ROM( 0x14e4, 0x16d8, "14e4-16d8", "Broadcom BCM957416", 0 ),
55 PCI_ROM( 0x14e4, 0x16d9, "14e4-16d9", "Broadcom BCM957417", 0 ),
56 PCI_ROM( 0x14e4, 0x16da, "14e4-16da", "Broadcom BCM957402", 0 ),
57 PCI_ROM( 0x14e4, 0x16db, "14e4-16db", "Broadcom BCM957404", 0 ),
58 PCI_ROM( 0x14e4, 0x16dc, "14e4-16dc", "Broadcom BCM95741x VF", BNXT_FLAG_PCI_VF ),
59 PCI_ROM( 0x14e4, 0x16de, "14e4-16de", "Broadcom BCM957412 MF", 0 ),
60 PCI_ROM( 0x14e4, 0x16df, "14e4-16df", "Broadcom BCM957314", 0 ),
61 PCI_ROM( 0x14e4, 0x16e0, "14e4-16e0", "Broadcom BCM957317", 0 ),
62 PCI_ROM( 0x14e4, 0x16e2, "14e4-16e2", "Broadcom BCM957417", 0 ),
63 PCI_ROM( 0x14e4, 0x16e3, "14e4-16e3", "Broadcom BCM957416", 0 ),
64 PCI_ROM( 0x14e4, 0x16e4, "14e4-16e4", "Broadcom BCM957317", 0 ),
65 PCI_ROM( 0x14e4, 0x16e7, "14e4-16e7", "Broadcom BCM957404 MF", 0 ),
66 PCI_ROM( 0x14e4, 0x16e8, "14e4-16e8", "Broadcom BCM957406 MF", 0 ),
67 PCI_ROM( 0x14e4, 0x16e9, "14e4-16e9", "Broadcom BCM957407", 0 ),
68 PCI_ROM( 0x14e4, 0x16ea, "14e4-16ea", "Broadcom BCM957407 MF", 0 ),
69 PCI_ROM( 0x14e4, 0x16eb, "14e4-16eb", "Broadcom BCM957412 RDMA MF", 0 ),
70 PCI_ROM( 0x14e4, 0x16ec, "14e4-16ec", "Broadcom BCM957414 MF", 0 ),
71 PCI_ROM( 0x14e4, 0x16ed, "14e4-16ed", "Broadcom BCM957414 RDMA MF", 0 ),
72 PCI_ROM( 0x14e4, 0x16ee, "14e4-16ee", "Broadcom BCM957416 MF", 0 ),
73 PCI_ROM( 0x14e4, 0x16ef, "14e4-16ef", "Broadcom BCM957416 RDMA MF", 0 ),
74 PCI_ROM( 0x14e4, 0x16f0, "14e4-16f0", "Broadcom BCM957320", 0 ),
75 PCI_ROM( 0x14e4, 0x16f1, "14e4-16f1", "Broadcom BCM957320", 0 ),
76 PCI_ROM( 0x14e4, 0x1750, "14e4-1750", "Broadcom BCM957508", 0 ),
77 PCI_ROM( 0x14e4, 0x1751, "14e4-1751", "Broadcom BCM957504", 0 ),
78 PCI_ROM( 0x14e4, 0x1752, "14e4-1752", "Broadcom BCM957502", 0 ),
79 PCI_ROM( 0x14e4, 0x1760, "14e4-1760", "Broadcom BCM957608", 0 ),
80 PCI_ROM( 0x14e4, 0x1800, "14e4-1800", "Broadcom BCM957502 MF", 0 ),
81 PCI_ROM( 0x14e4, 0x1801, "14e4-1801", "Broadcom BCM957504 MF", 0 ),
82 PCI_ROM( 0x14e4, 0x1802, "14e4-1802", "Broadcom BCM957508 MF", 0 ),
83 PCI_ROM( 0x14e4, 0x1803, "14e4-1803", "Broadcom BCM957502 RDMA MF", 0 ),
84 PCI_ROM( 0x14e4, 0x1804, "14e4-1804", "Broadcom BCM957504 RDMA MF", 0 ),
85 PCI_ROM( 0x14e4, 0x1805, "14e4-1805", "Broadcom BCM957508 RDMA MF", 0 ),
86 PCI_ROM( 0x14e4, 0x1806, "14e4-1806", "Broadcom BCM9575xx VF", BNXT_FLAG_PCI_VF ),
87 PCI_ROM( 0x14e4, 0x1807, "14e4-1807", "Broadcom BCM9575xx RDMA VF", BNXT_FLAG_PCI_VF ),
88 PCI_ROM( 0x14e4, 0x1808, "14e4-1808", "Broadcom BCM9575xx HV VF", BNXT_FLAG_PCI_VF ),
89 PCI_ROM( 0x14e4, 0x1809, "14e4-1809", "Broadcom BCM9575xx RDMA HV VF", BNXT_FLAG_PCI_VF ),
90 PCI_ROM( 0x14e4, 0x1819, "bcm95760x-1819", "Broadcom BCM95760x VF", BNXT_FLAG_PCI_VF ),
91 PCI_ROM( 0x14e4, 0x181b, "bcm95760x-181b", "Broadcom BCM95760x HV VF", BNXT_FLAG_PCI_VF ),
92};
93
94/**
95 * Check if Virtual Function
96 */
97u8 bnxt_is_pci_vf ( struct pci_device *pdev )
98{
99 if ( FLAG_TEST ( pdev->id->driver_data, BNXT_FLAG_PCI_VF ) ) {
100 return 1;
101 }
102 return 0;
103}
104
105static void bnxt_down_pci ( struct bnxt *bp )
106{
107 DBGP ( "%s\n", __func__ );
108 if ( bp->bar2 ) {
109 iounmap ( bp->bar2 );
110 bp->bar2 = NULL;
111 }
112 if ( bp->bar1 ) {
113 iounmap ( bp->bar1 );
114 bp->bar1 = NULL;
115 }
116 if ( bp->bar0 ) {
117 iounmap ( bp->bar0 );
118 bp->bar0 = NULL;
119 }
120}
121
122static void *bnxt_pci_base ( struct pci_device *pdev, unsigned int reg )
123{
124 unsigned long reg_base, reg_size;
125
126 reg_base = pci_bar_start ( pdev, reg );
127 reg_size = pci_bar_size ( pdev, reg );
128 return pci_ioremap ( pdev, reg_base, reg_size );
129}
130
131static int bnxt_get_pci_info ( struct bnxt *bp )
132{
133 u16 cmd_reg = 0;
134
135 DBGP ( "%s\n", __func__ );
136 /* Disable Interrupt */
137 pci_read_config_word ( bp->pdev, PCI_COMMAND, &bp->cmd_reg );
138 cmd_reg = bp->cmd_reg | PCI_COMMAND_INTX_DISABLE;
139 pci_write_config_word ( bp->pdev, PCI_COMMAND, cmd_reg );
140 pci_read_config_word ( bp->pdev, PCI_COMMAND, &cmd_reg );
141
142 /* SSVID */
143 pci_read_config_word ( bp->pdev, PCI_SUBSYSTEM_VENDOR_ID,
144 &bp->subsystem_vendor );
145
146 /* SSDID */
147 pci_read_config_word ( bp->pdev, PCI_SUBSYSTEM_ID,
148 &bp->subsystem_device );
149
150 /* Function Number */
151 pci_read_config_byte ( bp->pdev, PCICFG_ME_REGISTER, &bp->pf_num);
152
153 /* Get Bar Address */
154 bp->bar0 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_0 );
155 bp->bar1 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_2 );
156 bp->bar2 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_4 );
157
158 /* Virtual function */
159 bp->vf = bnxt_is_pci_vf ( bp->pdev );
160
161 dbg_pci ( bp, __func__, cmd_reg );
162 return STATUS_SUCCESS;
163}
164
165static int bnxt_get_device_address ( struct bnxt *bp )
166{
167 struct net_device *dev = bp->dev;
168
169 DBGP ( "%s\n", __func__ );
170 memcpy ( &dev->hw_addr[0], ( char * ) &bp->mac_addr[0], ETH_ALEN );
171 if ( !is_valid_ether_addr ( &dev->hw_addr[0] ) ) {
172 DBGP ( "- %s ( ): Failed\n", __func__ );
173 return -EINVAL;
174 }
175
176 return STATUS_SUCCESS;
177}
178
179static void bnxt_set_link ( struct bnxt *bp )
180{
181 if ( bp->link_status == STATUS_LINK_ACTIVE )
182 netdev_link_up ( bp->dev );
183 else
184 netdev_link_down ( bp->dev );
185}
186
187static void dev_p5_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag )
188{
189 void *off;
190 u64 val;
191
192 if ( bp->vf )
193 off = ( void * ) ( bp->bar1 + DB_OFFSET_VF );
194 else
195 off = ( void * ) ( bp->bar1 + DB_OFFSET_PF );
196
197 val = ( ( u64 )DBC_MSG_XID ( xid, flag ) << 32 ) |
198 ( u64 )DBC_MSG_IDX ( idx );
199 writeq ( val, off );
200}
201
202static void dev_p7_db ( struct bnxt *bp, u32 idx, u32 xid, u32 flag, u32 epoch, u32 toggle )
203{
204 void *off;
205 u64 val;
206
207 off = ( void * ) ( bp->bar1 );
208
209 val = ( ( u64 ) DBC_MSG_XID ( xid, flag ) << 32 ) |
210 ( u64 ) DBC_MSG_IDX ( idx ) |
211 ( u64 ) DBC_MSG_EPCH ( epoch ) |
212 ( u64 ) DBC_MSG_TOGGLE ( toggle );
213 writeq ( val, off );
214}
215
216static void bnxt_db_nq ( struct bnxt *bp )
217{
218 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
219 dev_p7_db ( bp, ( u32 ) bp->nq.cons_id,
220 ( u32 ) bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM,
221 ( u32 ) bp->nq.epoch, 0 );
222 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
223 dev_p5_db ( bp, ( u32 ) bp->nq.cons_id,
224 ( u32 ) bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM );
225 else
226 writel ( CMPL_DOORBELL_KEY_CMPL, ( bp->bar1 + 0 ) );
227}
228
229static void bnxt_db_cq ( struct bnxt *bp )
230{
231 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
232 dev_p7_db ( bp, ( u32 ) bp->cq.cons_id,
233 ( u32 ) bp->cq_ring_id, DBC_DBC_TYPE_CQ,
234 ( u32 ) bp->cq.epoch, ( u32 )bp->nq.toggle );
235 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
236 dev_p5_db ( bp, ( u32 ) bp->cq.cons_id,
237 ( u32 ) bp->cq_ring_id, DBC_DBC_TYPE_CQ);
238 else
239 writel ( CQ_DOORBELL_KEY_IDX ( bp->cq.cons_id ),
240 ( bp->bar1 + 0 ) );
241}
242
243static void bnxt_db_rx ( struct bnxt *bp, u32 idx )
244{
245 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
246 dev_p7_db ( bp, idx, ( u32 ) bp->rx_ring_id, DBC_DBC_TYPE_SRQ,
247 ( u32 ) bp->rx.epoch, 0 );
248 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
249 dev_p5_db ( bp, idx, ( u32 ) bp->rx_ring_id, DBC_DBC_TYPE_SRQ );
250 else
251 writel ( RX_DOORBELL_KEY_RX | idx, ( bp->bar1 + 0 ) );
252}
253
254static void bnxt_db_tx ( struct bnxt *bp, u32 idx )
255{
256 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
257 dev_p7_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ,
258 ( u32 )bp->tx.epoch, 0 );
259 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
260 dev_p5_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ );
261 else
262 writel ( TX_DOORBELL_KEY_TX | idx, ( bp->bar1 + 0 ) );
263}
264
265void bnxt_add_vlan ( struct io_buffer *iob, u16 vlan )
266{
267 char *src = ( char * )iob->data;
268 u16 len = iob_len ( iob );
269
270 memmove ( ( char * ) &src[MAC_HDR_SIZE + VLAN_HDR_SIZE],
271 ( char * ) &src[MAC_HDR_SIZE],
272 ( len - MAC_HDR_SIZE ) );
273
274 * ( u16 * ) ( &src[MAC_HDR_SIZE] ) = BYTE_SWAP_S ( ETHERTYPE_VLAN );
275 * ( u16 * ) ( &src[MAC_HDR_SIZE + 2] ) = BYTE_SWAP_S ( vlan );
276 iob_put ( iob, VLAN_HDR_SIZE );
277}
278
279static u16 bnxt_get_pkt_vlan ( char *src )
280{
281 if ( * ( ( u16 * ) &src[MAC_HDR_SIZE] ) == BYTE_SWAP_S ( ETHERTYPE_VLAN ) )
282 return BYTE_SWAP_S ( * ( ( u16 * ) &src[MAC_HDR_SIZE + 2] ) );
283 return 0;
284}
285
286static inline u32 bnxt_tx_avail ( struct bnxt *bp )
287{
288 u32 avail;
289 u32 use;
290
291 barrier ( );
292 avail = TX_AVAIL ( bp->tx.ring_cnt );
293 use = TX_IN_USE ( bp->tx.prod_id, bp->tx.cons_id, bp->tx.ring_cnt );
294 dbg_tx_avail ( bp, avail, use );
295 return ( avail-use );
296}
297
298void bnxt_set_txq ( struct bnxt *bp, int entry, physaddr_t mapping, int len )
299{
300 struct tx_bd_short *prod_bd;
301
302 prod_bd = ( struct tx_bd_short * ) BD_NOW ( bp->tx.bd_virt,
303 entry, sizeof ( struct tx_bd_short ) );
304 if ( len < 512 )
305 prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT512;
306 else if ( len < 1024 )
307 prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT1K;
308 else if ( len < 2048 )
309 prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_LT2K;
310 else
311 prod_bd->flags_type = TX_BD_SHORT_FLAGS_LHINT_GTE2K;
312 prod_bd->flags_type |= TX_BD_FLAGS;
313 prod_bd->dma = mapping;
314 prod_bd->len = len;
315 prod_bd->opaque = ( u32 )entry;
316}
317
318static void bnxt_tx_complete ( struct net_device *dev, u16 hw_idx )
319{
320 struct bnxt *bp = dev->priv;
321 struct io_buffer *iob;
322
323 iob = bp->tx.iob[hw_idx];
324 dbg_tx_done ( iob->data, iob_len ( iob ), hw_idx );
325 netdev_tx_complete ( dev, iob );
326 bp->tx.cons_id = NEXT_IDX ( hw_idx, bp->tx.ring_cnt );
327 bp->tx.cnt++;
328 dump_tx_stat ( bp );
329}
330
331int bnxt_free_rx_iob ( struct bnxt *bp )
332{
333 unsigned int i;
334
335 DBGP ( "%s\n", __func__ );
336 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RX_IOB ) ) )
337 return STATUS_SUCCESS;
338
339 for ( i = 0; i < bp->rx.buf_cnt; i++ ) {
340 if ( bp->rx.iob[i] ) {
341 free_rx_iob ( bp->rx.iob[i] );
342 bp->rx.iob[i] = NULL;
343 }
344 }
345 bp->rx.iob_cnt = 0;
346
347 FLAG_RESET ( bp->flag_hwrm, VALID_RX_IOB );
348 return STATUS_SUCCESS;
349}
350
351static void bnxt_set_rx_desc ( u8 *buf, struct io_buffer *iob,
352 u16 cid, u32 idx )
353{
354 struct rx_prod_pkt_bd *desc;
355 u16 off = cid * sizeof ( struct rx_prod_pkt_bd );
356
357 desc = ( struct rx_prod_pkt_bd * ) &buf[off];
358 desc->flags_type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT;
359 desc->len = MAX_ETHERNET_PACKET_BUFFER_SIZE;
360 desc->opaque = idx;
361 desc->dma = iob_dma ( iob );
362}
363
364static int bnxt_alloc_rx_iob ( struct bnxt *bp, u16 cons_id, u16 iob_idx )
365{
366 struct io_buffer *iob;
367
368 iob = alloc_rx_iob ( BNXT_RX_STD_DMA_SZ, bp->dma );
369 if ( !iob ) {
370 DBGP ( "- %s ( ): alloc_iob Failed\n", __func__ );
371 return -ENOMEM;
372 }
373
374 dbg_alloc_rx_iob ( iob, iob_idx, cons_id );
375 bnxt_set_rx_desc ( ( u8 * )bp->rx.bd_virt, iob, cons_id,
376 ( u32 ) iob_idx );
377 bp->rx.iob[iob_idx] = iob;
378 return 0;
379}
380
381int bnxt_post_rx_buffers ( struct bnxt *bp )
382{
383 u16 cons_id = ( bp->rx.cons_id % bp->rx.ring_cnt );
384 u16 iob_idx;
385
386 while ( bp->rx.iob_cnt < bp->rx.buf_cnt ) {
387 iob_idx = ( cons_id % bp->rx.buf_cnt );
388 if ( !bp->rx.iob[iob_idx] ) {
389 if ( bnxt_alloc_rx_iob ( bp, cons_id, iob_idx ) < 0 ) {
390 dbg_alloc_rx_iob_fail ( iob_idx, cons_id );
391 break;
392 }
393 }
394 cons_id = NEXT_IDX ( cons_id, bp->rx.ring_cnt );
395 /* If the ring has wrapped, flip the epoch bit */
396 if ( iob_idx > cons_id )
397 bp->rx.epoch ^= 1;
398 bp->rx.iob_cnt++;
399 }
400
401 if ( cons_id != bp->rx.cons_id ) {
402 dbg_rx_cid ( bp->rx.cons_id, cons_id );
403 bp->rx.cons_id = cons_id;
404 bnxt_db_rx ( bp, ( u32 )cons_id );
405 }
406
407 FLAG_SET ( bp->flag_hwrm, VALID_RX_IOB );
408 return STATUS_SUCCESS;
409}
410
411u8 bnxt_rx_drop ( struct bnxt *bp, struct io_buffer *iob,
412 struct rx_pkt_cmpl *rx_cmp,
413 struct rx_pkt_cmpl_hi *rx_cmp_hi, u16 rx_len )
414{
415 struct rx_pkt_v3_cmpl *rx_cmp_v3 = ( struct rx_pkt_v3_cmpl * ) rx_cmp;
416 struct rx_pkt_v3_cmpl_hi *rx_cmp_hi_v3 = ( struct rx_pkt_v3_cmpl_hi * ) rx_cmp_hi;
417 u8 *rx_buf = ( u8 * ) iob->data;
418 u16 err_flags;
419 u8 ignore_chksum_err = 0;
420 int i;
421
422 if ( ( rx_cmp_v3->flags_type & RX_PKT_V3_CMPL_TYPE_MASK ) ==
423 RX_PKT_V3_CMPL_TYPE_RX_L2_V3 ) {
424 err_flags = rx_cmp_hi_v3->errors_v2 >> RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT;
425 } else
426 err_flags = rx_cmp_hi->errors_v2 >> RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT;
427 if ( rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21 )
428 ignore_chksum_err = 1;
429
430 if ( err_flags && !ignore_chksum_err ) {
431 bp->rx.drop_err++;
432 return 1;
433 }
434
435 for ( i = 0; i < 6; i++ ) {
436 if ( rx_buf[6 + i] != bp->mac_addr[i] )
437 break;
438 }
439
440 /* Drop the loopback packets */
441 if ( i == 6 ) {
442 bp->rx.drop_lb++;
443 return 2;
444 }
445
446 iob_put ( iob, rx_len );
447
448 bp->rx.good++;
449 return 0;
450}
451
452static void bnxt_adv_cq_index ( struct bnxt *bp, u16 cnt )
453{
454 u16 cons_id;
455
456 cons_id = bp->cq.cons_id + cnt;
457 if ( cons_id >= bp->cq.ring_cnt ) {
458 /* Toggle completion bit when the ring wraps. */
459 bp->cq.completion_bit ^= 1;
460 bp->cq.epoch ^= 1;
461 cons_id = cons_id - bp->cq.ring_cnt;
462 }
463 bp->cq.cons_id = cons_id;
464}
465
466void bnxt_rx_process ( struct net_device *dev, struct bnxt *bp,
467 struct rx_pkt_cmpl *rx_cmp,
468 struct rx_pkt_cmpl_hi *rx_cmp_hi )
469{
470 u32 desc_idx = rx_cmp->opaque;
471 struct io_buffer *iob = bp->rx.iob[desc_idx];
472 u8 drop;
473
474 dump_rx_bd ( rx_cmp, rx_cmp_hi, desc_idx );
475 assert ( iob );
476 drop = bnxt_rx_drop ( bp, iob, rx_cmp, rx_cmp_hi, rx_cmp->len );
477 dbg_rxp ( iob->data, rx_cmp->len, drop );
478 if ( drop )
479 netdev_rx_err ( dev, iob, -EINVAL );
480 else
481 netdev_rx ( dev, iob );
482
483 bp->rx.cnt++;
484 bp->rx.iob[desc_idx] = NULL;
485 bp->rx.iob_cnt--;
486 bnxt_post_rx_buffers ( bp );
487 bnxt_adv_cq_index ( bp, 2 ); /* Rx completion is 2 entries. */
488 dbg_rx_stat ( bp );
489}
490
491static int bnxt_rx_complete ( struct net_device *dev,
492 struct rx_pkt_cmpl *rx_cmp )
493{
494 struct bnxt *bp = dev->priv;
495 struct rx_pkt_cmpl_hi *rx_cmp_hi;
496 u8 cmpl_bit = bp->cq.completion_bit;
497
498 if ( bp->cq.cons_id == ( bp->cq.ring_cnt - 1 ) ) {
499 rx_cmp_hi = ( struct rx_pkt_cmpl_hi * ) CQ_DMA_ADDR ( bp );
500 cmpl_bit ^= 0x1; /* Ring has wrapped. */
501 } else
502 rx_cmp_hi = ( struct rx_pkt_cmpl_hi * ) ( rx_cmp + 1 );
503
504 if ( ! ( ( rx_cmp_hi->errors_v2 & RX_PKT_CMPL_V2 ) ^ cmpl_bit ) ) {
505 bnxt_rx_process ( dev, bp, rx_cmp, rx_cmp_hi );
506 return SERVICE_NEXT_CQ_BD;
507 } else
508 return NO_MORE_CQ_BD_TO_SERVICE;
509}
510
511void bnxt_mm_init_hwrm ( struct bnxt *bp, const char *func )
512{
513 DBGP ( "%s\n", __func__ );
514 memset ( bp->hwrm_addr_req, 0, REQ_BUFFER_SIZE );
515 memset ( bp->hwrm_addr_resp, 0, RESP_BUFFER_SIZE );
516 memset ( bp->hwrm_addr_dma, 0, DMA_BUFFER_SIZE );
517 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
518 bp->hwrm_cmd_timeout = HWRM_CMD_DEFAULT_TIMEOUT;
519 dbg_mem ( bp, func );
520}
521
522void bnxt_mm_init_rings ( struct bnxt *bp, const char *func )
523{
524 DBGP ( "%s\n", __func__ );
525 memset ( bp->tx.bd_virt, 0, TX_RING_BUFFER_SIZE );
526 memset ( bp->rx.bd_virt, 0, RX_RING_BUFFER_SIZE );
527 memset ( bp->cq.bd_virt, 0, CQ_RING_BUFFER_SIZE );
528 memset ( bp->nq.bd_virt, 0, NQ_RING_BUFFER_SIZE );
529
530 bp->link_status = STATUS_LINK_DOWN;
531 bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
532 bp->mtu = MAX_ETHERNET_PACKET_BUFFER_SIZE;
533 bp->nq.ring_cnt = MAX_NQ_DESC_CNT;
534 bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
535 bp->tx.ring_cnt = MAX_TX_DESC_CNT;
536 bp->rx.ring_cnt = MAX_RX_DESC_CNT;
537 bp->rx.buf_cnt = NUM_RX_BUFFERS;
538 dbg_mem ( bp, func );
539}
540
541void bnxt_mm_nic ( struct bnxt *bp )
542{
543 DBGP ( "%s\n", __func__ );
544 memset ( bp->cq.bd_virt, 0, CQ_RING_BUFFER_SIZE );
545 memset ( bp->tx.bd_virt, 0, TX_RING_BUFFER_SIZE );
546 memset ( bp->rx.bd_virt, 0, RX_RING_BUFFER_SIZE );
547 memset ( bp->nq.bd_virt, 0, NQ_RING_BUFFER_SIZE );
548 bp->nq.cons_id = 0;
549 bp->nq.completion_bit = 0x1;
550 bp->nq.epoch = 0;
551 bp->nq.toggle = 0;
552 bp->cq.cons_id = 0;
553 bp->cq.completion_bit = 0x1;
554 bp->cq.epoch = 0;
555 bp->tx.prod_id = 0;
556 bp->tx.cons_id = 0;
557 bp->tx.epoch = 0;
558 bp->rx.cons_id = 0;
559 bp->rx.iob_cnt = 0;
560 bp->rx.epoch = 0;
561
562 bp->mtu = MAX_ETHERNET_PACKET_BUFFER_SIZE;
563 bp->nq.ring_cnt = MAX_NQ_DESC_CNT;
564 bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
565 bp->tx.ring_cnt = MAX_TX_DESC_CNT;
566 bp->rx.ring_cnt = MAX_RX_DESC_CNT;
567 bp->rx.buf_cnt = NUM_RX_BUFFERS;
568}
569
570void bnxt_free_rings_mem ( struct bnxt *bp )
571{
572 DBGP ( "%s\n", __func__ );
573 if ( bp->nq.bd_virt ) {
574 dma_free ( &bp->nq_mapping, bp->nq.bd_virt, NQ_RING_BUFFER_SIZE );
575 bp->nq.bd_virt = NULL;
576 }
577
578 if ( bp->cq.bd_virt ) {
579 dma_free ( &bp->cq_mapping, bp->cq.bd_virt, CQ_RING_BUFFER_SIZE );
580 bp->cq.bd_virt = NULL;
581 }
582
583 if ( bp->rx.bd_virt ) {
584 dma_free ( &bp->rx_mapping, bp->rx.bd_virt, RX_RING_BUFFER_SIZE );
585 bp->rx.bd_virt = NULL;
586 }
587
588 if ( bp->tx.bd_virt ) {
589 dma_free ( &bp->tx_mapping, bp->tx.bd_virt, TX_RING_BUFFER_SIZE );
590 bp->tx.bd_virt = NULL;
591 }
592
593 DBGP ( "- %s ( ): - Done\n", __func__ );
594}
595
596void bnxt_free_hwrm_mem ( struct bnxt *bp )
597{
598 DBGP ( "%s\n", __func__ );
599 if ( bp->hwrm_addr_dma ) {
600 dma_free ( &bp->dma_mapped, bp->hwrm_addr_dma, DMA_BUFFER_SIZE );
601 bp->hwrm_addr_dma = NULL;
602 }
603
604 if ( bp->hwrm_addr_resp ) {
605 dma_free ( &bp->resp_mapping, bp->hwrm_addr_resp, RESP_BUFFER_SIZE );
606 bp->hwrm_addr_resp = NULL;
607 }
608
609 if ( bp->hwrm_addr_req ) {
610 dma_free ( &bp->req_mapping, bp->hwrm_addr_req, REQ_BUFFER_SIZE );
611 bp->hwrm_addr_req = NULL;
612 }
613 DBGP ( "- %s ( ): - Done\n", __func__ );
614}
615
616int bnxt_alloc_hwrm_mem ( struct bnxt *bp )
617{
618 DBGP ( "%s\n", __func__ );
619 bp->hwrm_addr_req = dma_alloc ( bp->dma, &bp->req_mapping,
620 REQ_BUFFER_SIZE, REQ_BUFFER_SIZE );
621 bp->hwrm_addr_resp = dma_alloc ( bp->dma, &bp->resp_mapping,
622 RESP_BUFFER_SIZE, RESP_BUFFER_SIZE );
623 bp->hwrm_addr_dma = dma_alloc ( bp->dma, &bp->dma_mapped,
624 DMA_BUFFER_SIZE, DMA_BUFFER_SIZE);
625
626 if ( bp->hwrm_addr_req && bp->hwrm_addr_resp && bp->hwrm_addr_dma) {
627 bnxt_mm_init_hwrm ( bp, __func__ );
628 return STATUS_SUCCESS;
629 }
630
631 DBGP ( "- %s ( ): Failed\n", __func__ );
632 bnxt_free_hwrm_mem ( bp );
633 return -ENOMEM;
634}
635
636int bnxt_alloc_rings_mem ( struct bnxt *bp )
637{
638 DBGP ( "%s\n", __func__ );
639 bp->tx.bd_virt = dma_alloc ( bp->dma, &bp->tx_mapping,
640 TX_RING_BUFFER_SIZE, DMA_ALIGN_4K );
641 bp->rx.bd_virt = dma_alloc ( bp->dma, &bp->rx_mapping,
642 RX_RING_BUFFER_SIZE, DMA_ALIGN_4K );
643 bp->cq.bd_virt = dma_alloc ( bp->dma, &bp->cq_mapping,
644 CQ_RING_BUFFER_SIZE, BNXT_DMA_ALIGNMENT );
645 bp->nq.bd_virt = dma_alloc ( bp->dma, &bp->nq_mapping,
646 NQ_RING_BUFFER_SIZE, BNXT_DMA_ALIGNMENT );
647 if ( bp->tx.bd_virt && bp->rx.bd_virt &&
648 bp->nq.bd_virt && bp->cq.bd_virt) {
649 bnxt_mm_init_rings ( bp, __func__ );
650 return STATUS_SUCCESS;
651 }
652
653 DBGP ( "- %s ( ): Failed\n", __func__ );
654 bnxt_free_rings_mem ( bp );
655 return -ENOMEM;
656}
657
658static void hwrm_init ( struct bnxt *bp, struct input *req, u16 cmd, u16 len )
659{
660 memset ( req, 0, len );
661 req->req_type = cmd;
662 req->cmpl_ring = ( u16 ) HWRM_NA_SIGNATURE;
663 req->target_id = ( u16 ) HWRM_NA_SIGNATURE;
664 req->resp_addr = RESP_DMA_ADDR ( bp );
665 req->seq_id = bp->seq_id++;
666}
667
668static void hwrm_write_req ( struct bnxt *bp, void *req, u32 cnt )
669{
670 u32 i = 0;
671
672 for ( i = 0; i < cnt; i++ ) {
673 writel ( ( ( u32 * ) req )[i],
674 ( bp->bar0 + GRC_COM_CHAN_BASE + ( i * 4 ) ) );
675 }
676 writel ( 0x1, ( bp->bar0 + GRC_COM_CHAN_BASE + GRC_COM_CHAN_TRIG ) );
677}
678
679static void short_hwrm_cmd_req ( struct bnxt *bp, u16 len )
680{
681 struct hwrm_short_input sreq;
682
683 memset ( &sreq, 0, sizeof ( struct hwrm_short_input ) );
684 sreq.req_type = ( u16 ) ( ( struct input * ) REQ_DMA_ADDR (bp ) )->req_type;
685 sreq.signature = SHORT_REQ_SIGNATURE_SHORT_CMD;
686 sreq.size = len;
687 sreq.req_addr = REQ_DMA_ADDR ( bp );
688 mdelay ( 100 );
689 dbg_short_cmd ( ( u8 * )&sreq, __func__,
690 sizeof ( struct hwrm_short_input ) );
691 hwrm_write_req ( bp, &sreq, sizeof ( struct hwrm_short_input ) / 4 );
692}
693
694static int wait_resp ( struct bnxt *bp, u32 tmo, u16 len, const char *func )
695{
696 struct input *req = ( struct input * ) REQ_DMA_ADDR ( bp );
697 struct output *resp = ( struct output * ) RESP_DMA_ADDR ( bp );
698 u8 *ptr = ( u8 * )resp;
699 u32 idx;
700 u32 wait_cnt = HWRM_CMD_DEFAULT_MULTIPLAYER ( ( u32 )tmo );
701 u16 resp_len = 0;
702 u16 ret = STATUS_TIMEOUT;
703
704 if ( len > bp->hwrm_max_req_len )
705 short_hwrm_cmd_req ( bp, len );
706 else
707 hwrm_write_req ( bp, req, ( u32 ) ( len / 4 ) );
708
709 for ( idx = 0; idx < wait_cnt; idx++ ) {
710 resp_len = resp->resp_len;
711 if ( resp->seq_id == req->seq_id &&
712 resp->req_type == req->req_type &&
713 ptr[resp_len - 1] == 1 ) {
714 bp->last_resp_code = resp->error_code;
715 ret = resp->error_code;
716 break;
717 }
718 udelay ( HWRM_CMD_POLL_WAIT_TIME );
719 }
720 dbg_hw_cmd ( bp, func, len, resp_len, tmo, ret );
721 return ( int )ret;
722}
723
724static int bnxt_hwrm_ver_get ( struct bnxt *bp )
725{
726 u16 cmd_len = ( u16 )sizeof ( struct hwrm_ver_get_input );
727 struct hwrm_ver_get_input *req;
728 struct hwrm_ver_get_output *resp;
729 int rc;
730
731 DBGP ( "%s\n", __func__ );
732 req = ( struct hwrm_ver_get_input * ) REQ_DMA_ADDR ( bp );
733 resp = ( struct hwrm_ver_get_output * ) RESP_DMA_ADDR ( bp );
734 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VER_GET, cmd_len );
735 req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
736 req->hwrm_intf_min = HWRM_VERSION_MINOR;
737 req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
738 rc = wait_resp ( bp, HWRM_CMD_DEFAULT_TIMEOUT, cmd_len, __func__ );
739 if ( rc )
740 return STATUS_FAILURE;
741
742 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
743 resp->hwrm_intf_min_8b << 8 |
744 resp->hwrm_intf_upd_8b;
745 bp->hwrm_cmd_timeout = ( u32 ) resp->def_req_timeout;
746 if ( !bp->hwrm_cmd_timeout )
747 bp->hwrm_cmd_timeout = ( u32 ) HWRM_CMD_DEFAULT_TIMEOUT;
748 if ( resp->hwrm_intf_maj_8b >= 1 )
749 bp->hwrm_max_req_len = resp->max_req_win_len;
750 bp->chip_id = resp->chip_rev << 24 | resp->chip_metal << 16 |
751 resp->chip_bond_id << 8 | resp->chip_platform_type;
752 bp->chip_num = resp->chip_num;
753 if ( ( resp->dev_caps_cfg & SHORT_CMD_SUPPORTED ) &&
754 ( resp->dev_caps_cfg & SHORT_CMD_REQUIRED ) )
755 FLAG_SET ( bp->flags, BNXT_FLAG_HWRM_SHORT_CMD_SUPP );
756 bp->hwrm_max_ext_req_len = resp->max_ext_req_len;
757 if ( ( bp->chip_num == CHIP_NUM_57508 ) ||
758 ( bp->chip_num == CHIP_NUM_57504 ) ||
759 ( bp->chip_num == CHIP_NUM_57502 ) ) {
760 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5 );
761 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS );
762 }
763 if ( bp->chip_num == CHIP_NUM_57608 ) {
764 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P7 );
765 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS );
766 }
767 dbg_fw_ver ( resp, bp->hwrm_cmd_timeout );
768 return STATUS_SUCCESS;
769}
770
771static int bnxt_hwrm_func_resource_qcaps ( struct bnxt *bp )
772{
773 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_resource_qcaps_input );
774 struct hwrm_func_resource_qcaps_input *req;
775 struct hwrm_func_resource_qcaps_output *resp;
776 int rc;
777
778 DBGP ( "%s\n", __func__ );
779 req = ( struct hwrm_func_resource_qcaps_input * ) REQ_DMA_ADDR ( bp );
780 resp = ( struct hwrm_func_resource_qcaps_output * ) RESP_DMA_ADDR ( bp );
781 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_RESOURCE_QCAPS, cmd_len );
782 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
783 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
784 if ( rc != STATUS_SUCCESS )
785 return STATUS_SUCCESS;
786
787 FLAG_SET ( bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT );
788
789 // VFs
790 if ( !bp->vf ) {
791 bp->max_vfs = resp->max_vfs;
792 bp->vf_res_strategy = resp->vf_reservation_strategy;
793 }
794
795 // vNICs
796 bp->min_vnics = resp->min_vnics;
797 bp->max_vnics = resp->max_vnics;
798
799 // MSI-X
800 bp->max_msix = resp->max_msix;
801
802 // Ring Groups
803 bp->min_hw_ring_grps = resp->min_hw_ring_grps;
804 bp->max_hw_ring_grps = resp->max_hw_ring_grps;
805
806 // TX Rings
807 bp->min_tx_rings = resp->min_tx_rings;
808 bp->max_tx_rings = resp->max_tx_rings;
809
810 // RX Rings
811 bp->min_rx_rings = resp->min_rx_rings;
812 bp->max_rx_rings = resp->max_rx_rings;
813
814 // Completion Rings
815 bp->min_cp_rings = resp->min_cmpl_rings;
816 bp->max_cp_rings = resp->max_cmpl_rings;
817
818 // RSS Contexts
819 bp->min_rsscos_ctxs = resp->min_rsscos_ctx;
820 bp->max_rsscos_ctxs = resp->max_rsscos_ctx;
821
822 // L2 Contexts
823 bp->min_l2_ctxs = resp->min_l2_ctxs;
824 bp->max_l2_ctxs = resp->max_l2_ctxs;
825
826 // Statistic Contexts
827 bp->min_stat_ctxs = resp->min_stat_ctx;
828 bp->max_stat_ctxs = resp->max_stat_ctx;
829 dbg_func_resource_qcaps ( bp );
830 return STATUS_SUCCESS;
831}
832
833static u32 bnxt_set_ring_info ( struct bnxt *bp )
834{
835 u32 enables = 0;
836
837 DBGP ( "%s\n", __func__ );
838 bp->num_cmpl_rings = DEFAULT_NUMBER_OF_CMPL_RINGS;
839 bp->num_tx_rings = DEFAULT_NUMBER_OF_TX_RINGS;
840 bp->num_rx_rings = DEFAULT_NUMBER_OF_RX_RINGS;
841 bp->num_hw_ring_grps = DEFAULT_NUMBER_OF_RING_GRPS;
842 bp->num_stat_ctxs = DEFAULT_NUMBER_OF_STAT_CTXS;
843
844 if ( bp->min_cp_rings <= DEFAULT_NUMBER_OF_CMPL_RINGS )
845 bp->num_cmpl_rings = bp->min_cp_rings;
846
847 if ( bp->min_tx_rings <= DEFAULT_NUMBER_OF_TX_RINGS )
848 bp->num_tx_rings = bp->min_tx_rings;
849
850 if ( bp->min_rx_rings <= DEFAULT_NUMBER_OF_RX_RINGS )
851 bp->num_rx_rings = bp->min_rx_rings;
852
853 if ( bp->min_hw_ring_grps <= DEFAULT_NUMBER_OF_RING_GRPS )
854 bp->num_hw_ring_grps = bp->min_hw_ring_grps;
855
856 if ( bp->min_stat_ctxs <= DEFAULT_NUMBER_OF_STAT_CTXS )
857 bp->num_stat_ctxs = bp->min_stat_ctxs;
858
859 dbg_num_rings ( bp );
860 enables = ( FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS |
861 FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS |
862 FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS |
863 FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS |
864 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS );
865 return enables;
866}
867
868static void bnxt_hwrm_assign_resources ( struct bnxt *bp )
869{
870 struct hwrm_func_cfg_input *req;
871 u32 enables = 0;
872
873 DBGP ( "%s\n", __func__ );
874 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_RESOURCE_QCAPS_SUPPORT ) )
875 enables = bnxt_set_ring_info ( bp );
876
877 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
878 req->num_cmpl_rings = bp->num_cmpl_rings;
879 req->num_tx_rings = bp->num_tx_rings;
880 req->num_rx_rings = bp->num_rx_rings;
881 req->num_stat_ctxs = bp->num_stat_ctxs;
882 req->num_hw_ring_grps = bp->num_hw_ring_grps;
883 req->enables = enables;
884}
885
886static int bnxt_hwrm_func_qcaps_req ( struct bnxt *bp )
887{
888 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_qcaps_input );
889 struct hwrm_func_qcaps_input *req;
890 struct hwrm_func_qcaps_output *resp;
891 int rc;
892
893 DBGP ( "%s\n", __func__ );
894 if ( bp->vf )
895 return STATUS_SUCCESS;
896
897 req = ( struct hwrm_func_qcaps_input * ) REQ_DMA_ADDR ( bp );
898 resp = ( struct hwrm_func_qcaps_output * ) RESP_DMA_ADDR ( bp );
899 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_QCAPS, cmd_len );
900 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
901 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
902 if ( rc ) {
903 DBGP ( "- %s ( ): Failed\n", __func__ );
904 return STATUS_FAILURE;
905 }
906
907 bp->fid = resp->fid;
908 bp->port_idx = ( u8 ) resp->port_id;
909
910 if ( resp->flags & FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE ) {
911 bp->err_rcvry_supported = 1;
912 }
913
914 /* Get MAC address for this PF */
915 memcpy ( &bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN );
916 dbg_func_qcaps ( bp );
917
918 return STATUS_SUCCESS;
919}
920
921static int bnxt_hwrm_func_qcfg_req ( struct bnxt *bp )
922{
923 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_qcfg_input );
924 struct hwrm_func_qcfg_input *req;
925 struct hwrm_func_qcfg_output *resp;
926 int rc;
927
928 DBGP ( "%s\n", __func__ );
929 req = ( struct hwrm_func_qcfg_input * ) REQ_DMA_ADDR ( bp );
930 resp = ( struct hwrm_func_qcfg_output * ) RESP_DMA_ADDR ( bp );
931 hwrm_init ( bp, ( void * )req, ( u16 ) HWRM_FUNC_QCFG, cmd_len );
932 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
933 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
934 if ( rc ) {
935 DBGP ( "- %s ( ): Failed\n", __func__ );
936 return STATUS_FAILURE;
937 }
938
939 if ( resp->flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST )
940 FLAG_SET ( bp->flags, BNXT_FLAG_MULTI_HOST );
941
942 if ( resp->port_partition_type &
943 FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 )
944 FLAG_SET ( bp->flags, BNXT_FLAG_NPAR_MODE );
945
946 bp->ordinal_value = ( u8 ) resp->pci_id & 0x0F;
947 bp->stat_ctx_id = resp->stat_ctx_id;
948
949 /* If VF is set to TRUE, then use some data from func_qcfg ( ). */
950 if ( bp->vf ) {
951 bp->fid = resp->fid;
952 bp->port_idx = ( u8 ) resp->port_id;
953 bp->vlan_id = resp->vlan;
954
955 /* Get MAC address for this VF */
956 memcpy ( bp->mac_addr, resp->mac_address, ETH_ALEN );
957 }
958 dbg_func_qcfg ( bp );
959 return STATUS_SUCCESS;
960}
961
962static int bnxt_hwrm_port_phy_qcaps_req ( struct bnxt *bp )
963{
964 u16 cmd_len = ( u16 )sizeof ( struct hwrm_port_phy_qcaps_input );
965 struct hwrm_port_phy_qcaps_input *req;
966 struct hwrm_port_phy_qcaps_output *resp;
967 int rc;
968
969 DBGP ( "%s\n", __func__ );
970
971 req = ( struct hwrm_port_phy_qcaps_input * ) REQ_DMA_ADDR ( bp );
972 resp = ( struct hwrm_port_phy_qcaps_output * ) RESP_DMA_ADDR ( bp );
973 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_QCAPS, cmd_len );
974 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
975 if ( rc ) {
976 DBGP ( "-s %s ( ): Failed\n", __func__ );
977 return STATUS_FAILURE;
978 }
979
980 if ( resp->flags2 & PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED )
981 FLAG_SET ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 );
982
983 return STATUS_SUCCESS;
984}
985
986static int bnxt_hwrm_func_reset_req ( struct bnxt *bp )
987{
988 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_reset_input );
989 struct hwrm_func_reset_input *req;
990
991 DBGP ( "%s\n", __func__ );
992 req = ( struct hwrm_func_reset_input * ) REQ_DMA_ADDR ( bp );
993 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_RESET, cmd_len );
994 if ( !bp->vf )
995 req->func_reset_level = FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME;
996
997 return wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
998}
999
1000static int bnxt_hwrm_func_cfg_req ( struct bnxt *bp )
1001{
1002 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_cfg_input );
1003 struct hwrm_func_cfg_input *req;
1004
1005 DBGP ( "%s\n", __func__ );
1006 if ( bp->vf )
1007 return STATUS_SUCCESS;
1008
1009 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
1010 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_CFG, cmd_len );
1011 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
1012 bnxt_hwrm_assign_resources ( bp );
1013 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
1014 req->enables |= ( FUNC_CFG_REQ_ENABLES_NUM_MSIX |
1015 FUNC_CFG_REQ_ENABLES_NUM_VNICS |
1016 FUNC_CFG_REQ_ENABLES_EVB_MODE );
1017 req->num_msix = 1;
1018 req->num_vnics = 1;
1019 req->evb_mode = FUNC_CFG_REQ_EVB_MODE_NO_EVB;
1020 }
1021 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1022}
1023
1024static int bnxt_hwrm_error_recovery_req ( struct bnxt *bp )
1025{
1026 struct hwrm_error_recovery_qcfg_input *req;
1027 struct hwrm_error_recovery_qcfg_output *resp;
1028 int rc = 0;
1029 u8 i = 0;
1030 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_error_recovery_qcfg_input );
1031
1032 DBGP ( "%s\n", __func__ );
1033 /* Set default error recovery heartbeat polling value (in 100ms)*/
1034 bp->er.drv_poll_freq = 100;
1035 if ( ! ( bp->err_rcvry_supported ) ) {
1036 return STATUS_SUCCESS;
1037 }
1038
1039 req = ( struct hwrm_error_recovery_qcfg_input * ) REQ_DMA_ADDR ( bp );
1040 resp = ( struct hwrm_error_recovery_qcfg_output * ) RESP_DMA_ADDR ( bp );
1041
1042 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_ER_QCFG, cmd_len );
1043
1044 rc = wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
1045 if ( rc ) {
1046 DBGP ( "- %s ( ): Failed\n", __func__ );
1047 return STATUS_FAILURE;
1048 }
1049
1050 bp->er.flags = resp->flags;
1051 bp->er.drv_poll_freq = resp->driver_polling_freq;
1052 bp->er.master_wait_period = resp->master_wait_period;
1053 bp->er.normal_wait_period = resp->normal_wait_period;
1054 bp->er.master_wait_post_rst = resp->master_wait_post_reset;
1055 bp->er.max_bailout_post_rst = resp->max_bailout_time;
1056
1057 bp->er.fw_status_reg = resp->fw_health_status_reg;
1058 bp->er.fw_hb_reg = resp->fw_heartbeat_reg;
1059 bp->er.fw_rst_cnt_reg = resp->fw_reset_cnt_reg;
1060 bp->er.recvry_cnt_reg = resp->err_recovery_cnt_reg;
1061 bp->er.rst_inprg_reg = resp->reset_inprogress_reg;
1062
1063 bp->er.rst_inprg_reg_mask = resp->reset_inprogress_reg_mask;
1064 bp->er.reg_array_cnt = resp->reg_array_cnt;
1065
1066 DBGP ( "flags = 0x%x\n", resp->flags );
1067 DBGP ( "driver_polling_freq = 0x%x\n", resp->driver_polling_freq );
1068 DBGP ( "master_wait_period = 0x%x\n", resp->master_wait_period );
1069 DBGP ( "normal_wait_period = 0x%x\n", resp->normal_wait_period );
1070 DBGP ( "wait_post_reset = 0x%x\n", resp->master_wait_post_reset );
1071 DBGP ( "bailout_post_reset = 0x%x\n", resp->max_bailout_time );
1072 DBGP ( "reg_array_cnt = %x\n", resp->reg_array_cnt );
1073
1074 for ( i = 0; i < resp->reg_array_cnt; i++ ) {
1075 bp->er.rst_reg[i] = resp->reset_reg[i];
1076 bp->er.rst_reg_val[i] = resp->reset_reg_val[i];
1077 bp->er.delay_after_rst[i] = resp->delay_after_reset[i];
1078
1079 DBGP ( "rst_reg = %x ", bp->er.rst_reg[i] );
1080 DBGP ( "rst_reg_val = %x ", bp->er.rst_reg_val[i] );
1081 DBGP ( "rst_after_reset = %x\n", bp->er.delay_after_rst[i] );
1082 }
1083
1084 return STATUS_SUCCESS;
1085}
1086
1087static int bnxt_hwrm_func_drv_rgtr ( struct bnxt *bp )
1088{
1089 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_drv_rgtr_input );
1090 struct hwrm_func_drv_rgtr_input *req;
1091 int rc;
1092
1093 DBGP ( "%s\n", __func__ );
1094 req = ( struct hwrm_func_drv_rgtr_input * ) REQ_DMA_ADDR ( bp );
1095 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_DRV_RGTR, cmd_len );
1096
1097 /* Register with HWRM */
1098 req->enables = FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
1099 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD |
1100 FUNC_DRV_RGTR_REQ_ENABLES_VER;
1101 req->flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
1102
1103 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE;
1104 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE;
1105 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE;
1106 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE;
1107
1108 if ( bp->err_rcvry_supported ) {
1109 req->flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT;
1110 req->flags |= FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
1111 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY;
1112 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY;
1113 }
1114
1115 req->os_type = FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER;
1116 req->ver_maj = IPXE_VERSION_MAJOR;
1117 req->ver_min = IPXE_VERSION_MINOR;
1118 req->ver_upd = IPXE_VERSION_UPDATE;
1119 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1120 if ( rc ) {
1121 DBGP ( "- %s ( ): Failed\n", __func__ );
1122 return STATUS_FAILURE;
1123 }
1124
1125 FLAG_SET ( bp->flag_hwrm, VALID_DRIVER_REG );
1126 return STATUS_SUCCESS;
1127}
1128
1129static int bnxt_hwrm_func_drv_unrgtr ( struct bnxt *bp )
1130{
1131 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_drv_unrgtr_input );
1132 struct hwrm_func_drv_unrgtr_input *req;
1133 int rc;
1134
1135 DBGP ( "%s\n", __func__ );
1136 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_DRIVER_REG ) ) )
1137 return STATUS_SUCCESS;
1138
1139 req = ( struct hwrm_func_drv_unrgtr_input * ) REQ_DMA_ADDR ( bp );
1140 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_DRV_UNRGTR, cmd_len );
1141 req->flags = FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN;
1142 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1143 if ( rc )
1144 return STATUS_FAILURE;
1145
1146 FLAG_RESET ( bp->flag_hwrm, VALID_DRIVER_REG );
1147 return STATUS_SUCCESS;
1148}
1149
1150static int bnxt_hwrm_set_async_event ( struct bnxt *bp )
1151{
1152 int rc;
1153 u16 idx;
1154
1155 DBGP ( "%s\n", __func__ );
1156 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
1157 idx = bp->nq_ring_id;
1158 else
1159 idx = bp->cq_ring_id;
1160 if ( bp->vf ) {
1161 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_vf_cfg_input );
1162 struct hwrm_func_vf_cfg_input *req;
1163
1164 req = ( struct hwrm_func_vf_cfg_input * ) REQ_DMA_ADDR ( bp );
1165 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_VF_CFG,
1166 cmd_len );
1167 req->enables = VF_CFG_ENABLE_FLAGS;
1168 req->async_event_cr = idx;
1169 req->mtu = bp->mtu;
1170 req->guest_vlan = bp->vlan_id;
1171 memcpy ( ( char * ) &req->dflt_mac_addr[0], bp->mac_addr,
1172 ETH_ALEN );
1173 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1174 } else {
1175 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_cfg_input );
1176 struct hwrm_func_cfg_input *req;
1177
1178 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
1179 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_CFG, cmd_len );
1180 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
1181 req->enables = FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR;
1182 req->async_event_cr = idx;
1183 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1184 }
1185 return rc;
1186}
1187
1188static int bnxt_hwrm_cfa_l2_filter_alloc ( struct bnxt *bp )
1189{
1190 u16 cmd_len = ( u16 )sizeof ( struct hwrm_cfa_l2_filter_alloc_input );
1191 struct hwrm_cfa_l2_filter_alloc_input *req;
1192 struct hwrm_cfa_l2_filter_alloc_output *resp;
1193 int rc;
1194 u32 flags = CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX;
1195 u32 enables;
1196
1197 DBGP ( "%s\n", __func__ );
1198 req = ( struct hwrm_cfa_l2_filter_alloc_input * ) REQ_DMA_ADDR ( bp );
1199 resp = ( struct hwrm_cfa_l2_filter_alloc_output * ) RESP_DMA_ADDR ( bp );
1200 if ( bp->vf )
1201 flags |= CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST;
1202 enables = CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
1203 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
1204 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK;
1205
1206 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_FILTER_ALLOC,
1207 cmd_len );
1208 req->flags = flags;
1209 req->enables = enables;
1210 memcpy ( ( char * ) &req->l2_addr[0], ( char * ) &bp->mac_addr[0],
1211 ETH_ALEN );
1212 memset ( ( char * ) &req->l2_addr_mask[0], 0xff, ETH_ALEN );
1213 if ( !bp->vf ) {
1214 memcpy ( ( char * ) &req->t_l2_addr[0], bp->mac_addr, ETH_ALEN );
1215 memset ( ( char * ) &req->t_l2_addr_mask[0], 0xff, ETH_ALEN );
1216 }
1217 req->src_type = CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT;
1218 req->src_id = ( u32 ) bp->port_idx;
1219 req->dst_id = bp->vnic_id;
1220 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1221 if ( rc )
1222 return STATUS_FAILURE;
1223
1224 FLAG_SET ( bp->flag_hwrm, VALID_L2_FILTER );
1225 bp->l2_filter_id = resp->l2_filter_id;
1226 return STATUS_SUCCESS;
1227}
1228
1229static int bnxt_hwrm_cfa_l2_filter_free ( struct bnxt *bp )
1230{
1231 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_cfa_l2_filter_free_input );
1232 struct hwrm_cfa_l2_filter_free_input *req;
1233 int rc;
1234
1235 DBGP ( "%s\n", __func__ );
1236 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_L2_FILTER ) ) )
1237 return STATUS_SUCCESS;
1238
1239 req = ( struct hwrm_cfa_l2_filter_free_input * ) REQ_DMA_ADDR ( bp );
1240 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_FILTER_FREE,
1241 cmd_len );
1242 req->l2_filter_id = bp->l2_filter_id;
1243 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1244 if ( rc ) {
1245 DBGP ( "- %s ( ): Failed\n", __func__ );
1246 return STATUS_FAILURE;
1247 }
1248
1249 FLAG_RESET ( bp->flag_hwrm, VALID_L2_FILTER );
1250 return STATUS_SUCCESS;
1251}
1252
1253u32 set_rx_mask ( u32 rx_mask )
1254{
1255 u32 mask = 0;
1256
1257 if ( !rx_mask )
1258 return mask;
1259
1260 mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
1261 if ( rx_mask != RX_MASK_ACCEPT_NONE ) {
1262 if ( rx_mask & RX_MASK_ACCEPT_MULTICAST )
1263 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
1264 if ( rx_mask & RX_MASK_ACCEPT_ALL_MULTICAST )
1265 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
1266 if ( rx_mask & RX_MASK_PROMISCUOUS_MODE )
1267 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
1268 }
1269 return mask;
1270}
1271
1272static int bnxt_hwrm_set_rx_mask ( struct bnxt *bp, u32 rx_mask )
1273{
1274 u16 cmd_len = ( u16 )sizeof ( struct hwrm_cfa_l2_set_rx_mask_input );
1275 struct hwrm_cfa_l2_set_rx_mask_input *req;
1276 u32 mask = set_rx_mask ( rx_mask );
1277
1278 req = ( struct hwrm_cfa_l2_set_rx_mask_input * ) REQ_DMA_ADDR ( bp );
1279 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_SET_RX_MASK,
1280 cmd_len );
1281 req->vnic_id = bp->vnic_id;
1282 req->mask = mask;
1283
1284 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1285}
1286
1287static int bnxt_hwrm_port_phy_qcfg ( struct bnxt *bp, u16 idx )
1288{
1289 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_phy_qcfg_input );
1290 struct hwrm_port_phy_qcfg_input *req;
1291 struct hwrm_port_phy_qcfg_output *resp;
1292 int rc;
1293
1294 DBGP ( "%s\n", __func__ );
1295 req = ( struct hwrm_port_phy_qcfg_input * ) REQ_DMA_ADDR ( bp );
1296 resp = ( struct hwrm_port_phy_qcfg_output * ) RESP_DMA_ADDR ( bp );
1297 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_QCFG, cmd_len );
1298 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1299 if ( rc ) {
1300 DBGP ( "- %s ( ): Failed\n", __func__ );
1301 return STATUS_FAILURE;
1302 }
1303
1304 if ( idx & SUPPORT_SPEEDS )
1305 bp->support_speeds = resp->support_speeds;
1306
1307 if ( idx & SUPPORT_SPEEDS2 )
1308 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
1309 bp->auto_link_speeds2_mask = resp->auto_link_speeds2;
1310
1311 if ( idx & DETECT_MEDIA )
1312 bp->media_detect = resp->module_status;
1313
1314 if ( idx & PHY_SPEED )
1315 bp->current_link_speed = resp->link_speed;
1316
1317 if ( idx & PHY_STATUS ) {
1318 if ( resp->link == PORT_PHY_QCFG_RESP_LINK_LINK )
1319 bp->link_status = STATUS_LINK_ACTIVE;
1320 else
1321 bp->link_status = STATUS_LINK_DOWN;
1322 }
1323 return STATUS_SUCCESS;
1324}
1325
1326static int bnxt_hwrm_nvm_get_variable_req ( struct bnxt *bp,
1327 u16 data_len, u16 option_num, u16 dimensions, u16 index_0 )
1328{
1329 u16 cmd_len = ( u16 )sizeof ( struct hwrm_nvm_get_variable_input );
1330 struct hwrm_nvm_get_variable_input *req;
1331
1332 DBGP ( "%s\n", __func__ );
1333 req = ( struct hwrm_nvm_get_variable_input * ) REQ_DMA_ADDR ( bp );
1334 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_NVM_GET_VARIABLE, cmd_len );
1335 req->dest_data_addr = DMA_DMA_ADDR ( bp );
1336 req->data_len = data_len;
1337 req->option_num = option_num;
1338 req->dimensions = dimensions;
1339 req->index_0 = index_0;
1340 return wait_resp ( bp,
1341 HWRM_CMD_FLASH_MULTIPLAYER ( bp->hwrm_cmd_timeout ),
1342 cmd_len, __func__ );
1343}
1344
1345static int bnxt_get_link_speed ( struct bnxt *bp )
1346{
1347 u32 *ptr32 = ( u32 * ) DMA_DMA_ADDR ( bp );
1348
1349 DBGP ( "%s\n", __func__ );
1350 if ( ! ( FLAG_TEST (bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) ) {
1351 if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
1352 ( u16 ) LINK_SPEED_DRV_NUM,
1353 1, ( u16 ) bp->port_idx ) != STATUS_SUCCESS )
1354 return STATUS_FAILURE;
1355 bp->link_set = SET_LINK ( *ptr32, SPEED_DRV_MASK, SPEED_DRV_SHIFT );
1356 if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4,
1357 ( u16 ) D3_LINK_SPEED_FW_NUM, 1,
1358 ( u16 ) bp->port_idx ) != STATUS_SUCCESS )
1359 return STATUS_FAILURE;
1360 bp->link_set |= SET_LINK ( *ptr32, D3_SPEED_FW_MASK,
1361 D3_SPEED_FW_SHIFT );
1362 }
1363 if ( bnxt_hwrm_nvm_get_variable_req ( bp, 4, ( u16 ) LINK_SPEED_FW_NUM,
1364 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
1365 return STATUS_FAILURE;
1366 bp->link_set |= SET_LINK ( *ptr32, SPEED_FW_MASK, SPEED_FW_SHIFT );
1367 if ( bnxt_hwrm_nvm_get_variable_req ( bp, 1,
1368 ( u16 ) PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM,
1369 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
1370 return STATUS_FAILURE;
1371 bp->link_set |= SET_LINK ( *ptr32, MEDIA_AUTO_DETECT_MASK,
1372 MEDIA_AUTO_DETECT_SHIFT );
1373
1374 /* Use LINK_SPEED_FW_xxx which is valid for CHIP_P7 and earlier devices */
1375 switch ( bp->link_set & LINK_SPEED_FW_MASK ) {
1376 case LINK_SPEED_FW_1G:
1377 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_1000MBPS );
1378 break;
1379 case LINK_SPEED_FW_2_5G:
1380 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_2500MBPS );
1381 break;
1382 case LINK_SPEED_FW_10G:
1383 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_10GBPS );
1384 break;
1385 case LINK_SPEED_FW_25G:
1386 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_25GBPS );
1387 break;
1388 case LINK_SPEED_FW_40G:
1389 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_40GBPS );
1390 break;
1391 case LINK_SPEED_FW_50G:
1392 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_50GBPS );
1393 break;
1394 case LINK_SPEED_FW_50G_PAM4:
1395 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_50PAM4GBPS );
1396 break;
1397 case LINK_SPEED_FW_100G:
1398 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100GBPS );
1399 break;
1400 case LINK_SPEED_FW_100G_PAM4:
1401 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100PAM4GBPS );
1402 break;
1403 case LINK_SPEED_FW_100G_PAM4_112:
1404 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_100PAM4_112GBPS );
1405 break;
1406 case LINK_SPEED_FW_200G:
1407 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_200GBPS );
1408 break;
1409 case LINK_SPEED_FW_200G_PAM4_112:
1410 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_200PAM4_112GBPS );
1411 break;
1412 case LINK_SPEED_FW_400G_PAM4:
1413 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_400PAM4GBPS );
1414 break;
1415 case LINK_SPEED_FW_400G_PAM4_112:
1416 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_400PAM4_112GBPS );
1417 break;
1418 case LINK_SPEED_FW_AUTONEG:
1419 bp->medium = SET_MEDIUM_SPEED ( bp, MEDIUM_SPEED_AUTONEG );
1420 break;
1421 default:
1422 bp->medium = SET_MEDIUM_DUPLEX ( bp, MEDIUM_FULL_DUPLEX );
1423 break;
1424 }
1425 prn_set_speed ( bp->link_set );
1426 return STATUS_SUCCESS;
1427}
1428
1429static int bnxt_hwrm_backing_store_qcfg ( struct bnxt *bp )
1430{
1431 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_backing_store_qcfg_input );
1432 struct hwrm_func_backing_store_qcfg_input *req;
1433
1434 DBGP ( "%s\n", __func__ );
1435 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) || bp->vf )
1436 return STATUS_SUCCESS;
1437
1438 req = ( struct hwrm_func_backing_store_qcfg_input * ) REQ_DMA_ADDR ( bp );
1439 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_BACKING_STORE_QCFG,
1440 cmd_len );
1441 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1442}
1443
1444static int bnxt_hwrm_backing_store_cfg ( struct bnxt *bp )
1445{
1446 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_backing_store_cfg_input );
1447 struct hwrm_func_backing_store_cfg_input *req;
1448
1449 DBGP ( "%s\n", __func__ );
1450 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) || bp->vf )
1451 return STATUS_SUCCESS;
1452
1453 req = ( struct hwrm_func_backing_store_cfg_input * ) REQ_DMA_ADDR ( bp );
1454 hwrm_init ( bp, ( void * )req, ( u16 )HWRM_FUNC_BACKING_STORE_CFG,
1455 cmd_len );
1456 req->flags = FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE;
1457 req->enables = 0;
1458 return wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
1459}
1460
1461static int bnxt_hwrm_queue_qportcfg ( struct bnxt *bp )
1462{
1463 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_queue_qportcfg_input );
1464 struct hwrm_queue_qportcfg_input *req;
1465 struct hwrm_queue_qportcfg_output *resp;
1466 int rc;
1467
1468 DBGP ( "%s\n", __func__ );
1469
1470 req = ( struct hwrm_queue_qportcfg_input * ) REQ_DMA_ADDR ( bp );
1471 resp = ( struct hwrm_queue_qportcfg_output * ) RESP_DMA_ADDR ( bp );
1472 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_QUEUE_QPORTCFG, cmd_len );
1473 req->flags = 0;
1474 req->port_id = bp->port_idx;
1475 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1476 if ( rc ) {
1477 DBGP ( "- %s ( ): Failed\n", __func__ );
1478 return STATUS_FAILURE;
1479 }
1480
1481 bp->queue_id = resp->queue_id0;
1482 return STATUS_SUCCESS;
1483}
1484
1485static int bnxt_hwrm_port_mac_cfg ( struct bnxt *bp )
1486{
1487 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_mac_cfg_input );
1488 struct hwrm_port_mac_cfg_input *req;
1489
1490 DBGP ( "%s\n", __func__ );
1491 if ( bp->vf )
1492 return STATUS_SUCCESS;
1493
1494 req = ( struct hwrm_port_mac_cfg_input * ) REQ_DMA_ADDR ( bp );
1495 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_MAC_CFG, cmd_len );
1496 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
1497 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1498}
1499
1500static int bnxt_hwrm_port_phy_cfg ( struct bnxt *bp )
1501{
1502 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_phy_cfg_input );
1503 struct hwrm_port_phy_cfg_input *req;
1504 u32 flags;
1505 u32 enables = 0;
1506 u16 force_link_speed = 0;
1507 u16 force_link_speeds2 = 0;
1508 u16 force_pam4_link_speed = 0;
1509 u16 auto_link_speed_mask = 0;
1510 u16 auto_link_speeds2_mask = 0;
1511 u8 auto_mode = 0;
1512 u8 auto_pause = 0;
1513 u8 auto_duplex = 0;
1514
1515 DBGP ( "%s\n", __func__ );
1516 req = ( struct hwrm_port_phy_cfg_input * ) REQ_DMA_ADDR ( bp );
1517 flags = PORT_PHY_CFG_REQ_FLAGS_FORCE |
1518 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY;
1519
1520 switch ( GET_MEDIUM_SPEED ( bp->medium ) ) {
1521 case MEDIUM_SPEED_1000MBPS:
1522 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
1523 break;
1524 case MEDIUM_SPEED_10GBPS:
1525 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1526 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB;
1527 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1528 } else {
1529 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
1530 }
1531 break;
1532 case MEDIUM_SPEED_25GBPS:
1533 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1534 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB;
1535 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1536 } else {
1537 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
1538 }
1539 break;
1540 case MEDIUM_SPEED_40GBPS:
1541 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1542 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB;
1543 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1544 } else {
1545 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
1546 }
1547 break;
1548 case MEDIUM_SPEED_50GBPS:
1549 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1550 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB;
1551 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1552 } else {
1553 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
1554 }
1555 break;
1556 case MEDIUM_SPEED_50PAM4GBPS:
1557 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1558 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56;
1559 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1560 } else {
1561 force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
1562 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
1563 }
1564 break;
1565 case MEDIUM_SPEED_100GBPS:
1566 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1567 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB;
1568 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1569 } else {
1570 force_link_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
1571 }
1572 break;
1573 case MEDIUM_SPEED_100PAM4GBPS:
1574 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1575 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56;
1576 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1577 } else {
1578 force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
1579 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
1580 }
1581 break;
1582 case MEDIUM_SPEED_100PAM4_112GBPS:
1583 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1584 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112;
1585 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1586 }
1587 break;
1588 case MEDIUM_SPEED_200GBPS:
1589 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1590 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56;
1591 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1592 } else {
1593 force_pam4_link_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
1594 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED;
1595 }
1596 break;
1597 case MEDIUM_SPEED_200PAM4_112GBPS:
1598 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1599 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112;
1600 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1601 }
1602 break;
1603 case MEDIUM_SPEED_400PAM4GBPS:
1604 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1605 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56;
1606 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1607 }
1608 break;
1609 case MEDIUM_SPEED_400PAM4_112GBPS:
1610 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1611 force_link_speeds2 = PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112;
1612 enables |= PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2;
1613 }
1614 break;
1615 default:
1616 auto_mode = PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
1617 flags &= ~PORT_PHY_CFG_REQ_FLAGS_FORCE;
1618 enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE |
1619 PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX |
1620 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE;
1621 if ( FLAG_TEST (bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
1622 enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK;
1623 else
1624 enables |= PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK;
1625 auto_pause = PORT_PHY_CFG_REQ_AUTO_PAUSE_TX |
1626 PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
1627 auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH;
1628 auto_link_speed_mask = bp->support_speeds;
1629 auto_link_speeds2_mask = bp->auto_link_speeds2_mask;
1630 break;
1631 }
1632
1633 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_CFG, cmd_len );
1634 req->flags = flags;
1635 req->enables = enables;
1636 req->port_id = bp->port_idx;
1637 req->force_link_speed = force_link_speed;
1638 req->force_pam4_link_speed = force_pam4_link_speed;
1639 req->force_link_speeds2 = force_link_speeds2;
1640 req->auto_mode = auto_mode;
1641 req->auto_duplex = auto_duplex;
1642 req->auto_pause = auto_pause;
1643 req->auto_link_speed_mask = auto_link_speed_mask;
1644 req->auto_link_speeds2_mask = auto_link_speeds2_mask;
1645
1646 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1647}
1648
1649static int bnxt_query_phy_link ( struct bnxt *bp )
1650{
1651 u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
1652
1653 DBGP ( "%s\n", __func__ );
1654 /* Query Link Status */
1655 if ( bnxt_hwrm_port_phy_qcfg ( bp, QCFG_PHY_ALL ) != STATUS_SUCCESS )
1656 return STATUS_FAILURE;
1657
1658 if ( bp->link_status == STATUS_LINK_ACTIVE )
1659 return STATUS_SUCCESS;
1660
1661 /* If VF is set to TRUE, Do not issue the following commands */
1662 if ( bp->vf )
1663 return STATUS_SUCCESS;
1664
1665 /* If multi_host or NPAR, Do not issue bnxt_get_link_speed */
1666 if ( FLAG_TEST ( bp->flags, PORT_PHY_FLAGS ) ) {
1667 dbg_flags ( __func__, bp->flags );
1668 return STATUS_SUCCESS;
1669 }
1670
1671 /* HWRM_NVM_GET_VARIABLE - speed */
1672 if ( bnxt_get_link_speed ( bp ) != STATUS_SUCCESS )
1673 return STATUS_FAILURE;
1674
1675 /* Configure link if it is not up */
1676 bnxt_hwrm_port_phy_cfg ( bp );
1677
1678 /* refresh link speed values after bringing link up */
1679 return bnxt_hwrm_port_phy_qcfg ( bp, flag );
1680}
1681
1682static int bnxt_get_phy_link ( struct bnxt *bp )
1683{
1684 u16 i;
1685 u16 flag = PHY_STATUS | PHY_SPEED | DETECT_MEDIA;
1686
1687 DBGP ( "%s\n", __func__ );
1688 dbg_chip_info ( bp );
1689 for ( i = 0; i < ( bp->wait_link_timeout / 100 ); i++ ) {
1690 if ( bnxt_hwrm_port_phy_qcfg ( bp, flag ) != STATUS_SUCCESS )
1691 break;
1692
1693 if ( bp->link_status == STATUS_LINK_ACTIVE )
1694 break;
1695
1696// if ( bp->media_detect )
1697// break;
1698 mdelay ( LINK_POLL_WAIT_TIME );
1699 }
1700 dbg_link_state ( bp, ( u32 ) ( ( i + 1 ) * 100 ) );
1701 if ( !bp->er.er_rst_on )
1702 bnxt_set_link ( bp );
1703
1704 return STATUS_SUCCESS;
1705}
1706
1707static int bnxt_hwrm_stat_ctx_alloc ( struct bnxt *bp )
1708{
1709 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_stat_ctx_alloc_input );
1710 struct hwrm_stat_ctx_alloc_input *req;
1711 struct hwrm_stat_ctx_alloc_output *resp;
1712 int rc;
1713
1714 DBGP ( "%s\n", __func__ );
1715 req = ( struct hwrm_stat_ctx_alloc_input * ) REQ_DMA_ADDR ( bp );
1716 resp = ( struct hwrm_stat_ctx_alloc_output * ) RESP_DMA_ADDR ( bp );
1717 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_STAT_CTX_ALLOC, cmd_len );
1718 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1719 if ( rc ) {
1720 DBGP ( "- %s ( ): Failed\n", __func__ );
1721 return STATUS_FAILURE;
1722 }
1723
1724 FLAG_SET ( bp->flag_hwrm, VALID_STAT_CTX );
1725 bp->stat_ctx_id = ( u16 )resp->stat_ctx_id;
1726 return STATUS_SUCCESS;
1727}
1728
1729static int bnxt_hwrm_stat_ctx_free ( struct bnxt *bp )
1730{
1731 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_stat_ctx_free_input );
1732 struct hwrm_stat_ctx_free_input *req;
1733 int rc;
1734
1735 DBGP ( "%s\n", __func__ );
1736 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_STAT_CTX ) ) )
1737 return STATUS_SUCCESS;
1738
1739 req = ( struct hwrm_stat_ctx_free_input * ) REQ_DMA_ADDR ( bp );
1740 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_STAT_CTX_FREE, cmd_len );
1741 req->stat_ctx_id = ( u32 ) bp->stat_ctx_id;
1742 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1743 if ( rc ) {
1744 DBGP ( "- %s ( ): Failed\n", __func__ );
1745 return STATUS_FAILURE;
1746 }
1747
1748 FLAG_RESET ( bp->flag_hwrm, VALID_STAT_CTX );
1749 return STATUS_SUCCESS;
1750}
1751
1752static int bnxt_hwrm_ring_free_grp ( struct bnxt *bp )
1753{
1754 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_grp_free_input );
1755 struct hwrm_ring_grp_free_input *req;
1756 int rc;
1757
1758 DBGP ( "%s\n", __func__ );
1759 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_GRP ) ) )
1760 return STATUS_SUCCESS;
1761
1762 req = ( struct hwrm_ring_grp_free_input * ) REQ_DMA_ADDR ( bp );
1763 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_GRP_FREE, cmd_len );
1764 req->ring_group_id = ( u32 ) bp->ring_grp_id;
1765 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1766 if ( rc ) {
1767 DBGP ( "- %s ( ): Failed\n", __func__ );
1768 return STATUS_FAILURE;
1769 }
1770
1771 FLAG_RESET ( bp->flag_hwrm, VALID_RING_GRP );
1772 return STATUS_SUCCESS;
1773}
1774
1775static int bnxt_hwrm_ring_alloc_grp ( struct bnxt *bp )
1776{
1777 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_grp_alloc_input );
1778 struct hwrm_ring_grp_alloc_input *req;
1779 struct hwrm_ring_grp_alloc_output *resp;
1780 int rc;
1781
1782 DBGP ( "%s\n", __func__ );
1783 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
1784 return STATUS_SUCCESS;
1785
1786 req = ( struct hwrm_ring_grp_alloc_input * ) REQ_DMA_ADDR ( bp );
1787 resp = ( struct hwrm_ring_grp_alloc_output * ) RESP_DMA_ADDR ( bp );
1788 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_GRP_ALLOC, cmd_len );
1789 req->cr = bp->cq_ring_id;
1790 req->rr = bp->rx_ring_id;
1791 req->ar = ( u16 )HWRM_NA_SIGNATURE;
1792 if ( bp->vf )
1793 req->sc = bp->stat_ctx_id;
1794
1795 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1796 if ( rc ) {
1797 DBGP ( "- %s ( ): Failed\n", __func__ );
1798 return STATUS_FAILURE;
1799 }
1800
1801 FLAG_SET ( bp->flag_hwrm, VALID_RING_GRP );
1802 bp->ring_grp_id = ( u16 ) resp->ring_group_id;
1803 return STATUS_SUCCESS;
1804}
1805
1806int bnxt_hwrm_ring_free ( struct bnxt *bp, u16 ring_id, u8 ring_type )
1807{
1808 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_free_input );
1809 struct hwrm_ring_free_input *req;
1810
1811 DBGP ( "%s\n", __func__ );
1812 req = ( struct hwrm_ring_free_input * ) REQ_DMA_ADDR ( bp );
1813 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_FREE, cmd_len );
1814 req->ring_type = ring_type;
1815 req->ring_id = ring_id;
1816 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1817}
1818
1819static int bnxt_hwrm_ring_alloc ( struct bnxt *bp, u8 type )
1820{
1821 u16 cmd_len = ( u16 )sizeof ( struct hwrm_ring_alloc_input );
1822 struct hwrm_ring_alloc_input *req;
1823 struct hwrm_ring_alloc_output *resp;
1824 int rc;
1825
1826 DBGP ( "%s\n", __func__ );
1827 req = ( struct hwrm_ring_alloc_input * ) REQ_DMA_ADDR ( bp );
1828 resp = ( struct hwrm_ring_alloc_output * ) RESP_DMA_ADDR ( bp );
1829 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_ALLOC, cmd_len );
1830 req->ring_type = type;
1831 switch ( type ) {
1832 case RING_ALLOC_REQ_RING_TYPE_NQ:
1833 req->page_size = LM_PAGE_BITS ( 12 );
1834 req->int_mode = BNXT_CQ_INTR_MODE ( ( (FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7) ) || bp->vf ) );
1835 req->length = ( u32 ) bp->nq.ring_cnt;
1836 req->logical_id = 0xFFFF; // Required value for Thor FW?
1837 req->page_tbl_addr = NQ_DMA_ADDR ( bp );
1838 break;
1839 case RING_ALLOC_REQ_RING_TYPE_L2_CMPL:
1840 req->page_size = LM_PAGE_BITS ( 8 );
1841 req->int_mode = BNXT_CQ_INTR_MODE ( bp->vf );
1842 req->length = ( u32 ) bp->cq.ring_cnt;
1843 req->page_tbl_addr = CQ_DMA_ADDR ( bp );
1844 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1845 break;
1846 req->enables = RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID;
1847 req->nq_ring_id = bp->nq_ring_id;
1848 req->cq_handle = ( u64 ) bp->nq_ring_id;
1849 break;
1850 case RING_ALLOC_REQ_RING_TYPE_TX:
1851 req->page_size = LM_PAGE_BITS ( 8 );
1852 req->int_mode = RING_ALLOC_REQ_INT_MODE_POLL;
1853 req->length = ( u32 ) bp->tx.ring_cnt;
1854 req->queue_id = ( u16 ) bp->queue_id;
1855 req->stat_ctx_id = ( u32 ) bp->stat_ctx_id;
1856 req->cmpl_ring_id = bp->cq_ring_id;
1857 req->page_tbl_addr = TX_DMA_ADDR ( bp );
1858 break;
1859 case RING_ALLOC_REQ_RING_TYPE_RX:
1860 req->page_size = LM_PAGE_BITS ( 8 );
1861 req->int_mode = RING_ALLOC_REQ_INT_MODE_POLL;
1862 req->length = ( u32 ) bp->rx.ring_cnt;
1863 req->stat_ctx_id = ( u32 ) STAT_CTX_ID;
1864 req->cmpl_ring_id = bp->cq_ring_id;
1865 req->page_tbl_addr = RX_DMA_ADDR ( bp );
1866 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1867 break;
1868 req->queue_id = ( u16 ) RX_RING_QID;
1869 req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE;
1870 req->enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;
1871 break;
1872 default:
1873 return STATUS_SUCCESS;
1874 }
1875 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1876 if ( rc ) {
1877 DBGP ( "- %s ( ): Failed, type = %x\n", __func__, type );
1878 return STATUS_FAILURE;
1879 }
1880
1881 if ( type == RING_ALLOC_REQ_RING_TYPE_L2_CMPL ) {
1882 FLAG_SET ( bp->flag_hwrm, VALID_RING_CQ );
1883 bp->cq_ring_id = resp->ring_id;
1884 } else if ( type == RING_ALLOC_REQ_RING_TYPE_TX ) {
1885 FLAG_SET ( bp->flag_hwrm, VALID_RING_TX );
1886 bp->tx_ring_id = resp->ring_id;
1887 } else if ( type == RING_ALLOC_REQ_RING_TYPE_RX ) {
1888 FLAG_SET ( bp->flag_hwrm, VALID_RING_RX );
1889 bp->rx_ring_id = resp->ring_id;
1890 } else if ( type == RING_ALLOC_REQ_RING_TYPE_NQ ) {
1891 FLAG_SET ( bp->flag_hwrm, VALID_RING_NQ );
1892 bp->nq_ring_id = resp->ring_id;
1893 }
1894 return STATUS_SUCCESS;
1895}
1896
1897static int bnxt_hwrm_ring_alloc_cq ( struct bnxt *bp )
1898{
1899 DBGP ( "%s\n", __func__ );
1900 return bnxt_hwrm_ring_alloc ( bp, RING_ALLOC_REQ_RING_TYPE_L2_CMPL );
1901}
1902
1903static int bnxt_hwrm_ring_alloc_tx ( struct bnxt *bp )
1904{
1905 DBGP ( "%s\n", __func__ );
1906 return bnxt_hwrm_ring_alloc ( bp, RING_ALLOC_REQ_RING_TYPE_TX );
1907}
1908
1909static int bnxt_hwrm_ring_alloc_rx ( struct bnxt *bp )
1910{
1911 DBGP ( "%s\n", __func__ );
1912 return bnxt_hwrm_ring_alloc ( bp, RING_ALLOC_REQ_RING_TYPE_RX );
1913}
1914
1915static int bnxt_hwrm_ring_free_cq ( struct bnxt *bp )
1916{
1917 int ret = STATUS_SUCCESS;
1918
1919 DBGP ( "%s\n", __func__ );
1920 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_CQ ) ) )
1921 return ret;
1922
1923 ret = RING_FREE ( bp, bp->cq_ring_id, RING_FREE_REQ_RING_TYPE_L2_CMPL );
1924 if ( ret == STATUS_SUCCESS )
1925 FLAG_RESET ( bp->flag_hwrm, VALID_RING_CQ );
1926
1927 return ret;
1928}
1929
1930static int bnxt_hwrm_ring_free_tx ( struct bnxt *bp )
1931{
1932 int ret = STATUS_SUCCESS;
1933
1934 DBGP ( "%s\n", __func__ );
1935 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_TX ) ) )
1936 return ret;
1937
1938 ret = RING_FREE ( bp, bp->tx_ring_id, RING_FREE_REQ_RING_TYPE_TX );
1939 if ( ret == STATUS_SUCCESS )
1940 FLAG_RESET ( bp->flag_hwrm, VALID_RING_TX );
1941
1942 return ret;
1943}
1944
1945static int bnxt_hwrm_ring_free_rx ( struct bnxt *bp )
1946{
1947 int ret = STATUS_SUCCESS;
1948
1949 DBGP ( "%s\n", __func__ );
1950 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_RX ) ) )
1951 return ret;
1952
1953 ret = RING_FREE ( bp, bp->rx_ring_id, RING_FREE_REQ_RING_TYPE_RX );
1954 if ( ret == STATUS_SUCCESS )
1955 FLAG_RESET ( bp->flag_hwrm, VALID_RING_RX );
1956
1957 return ret;
1958}
1959
1960static int bnxt_hwrm_ring_alloc_nq ( struct bnxt *bp )
1961{
1962 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1963 return STATUS_SUCCESS;
1964 return bnxt_hwrm_ring_alloc ( bp, RING_ALLOC_REQ_RING_TYPE_NQ );
1965}
1966
1967static int bnxt_hwrm_ring_free_nq ( struct bnxt *bp )
1968{
1969 int ret = STATUS_SUCCESS;
1970
1971 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1972 return STATUS_SUCCESS;
1973
1974 DBGP ( "%s\n", __func__ );
1975 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_NQ ) ) )
1976 return ret;
1977
1978 ret = RING_FREE ( bp, bp->nq_ring_id, RING_FREE_REQ_RING_TYPE_NQ );
1979 if ( ret == STATUS_SUCCESS )
1980 FLAG_RESET ( bp->flag_hwrm, VALID_RING_NQ );
1981
1982 return ret;
1983}
1984
1985static int bnxt_hwrm_vnic_alloc ( struct bnxt *bp )
1986{
1987 u16 cmd_len = ( u16 )sizeof ( struct hwrm_vnic_alloc_input );
1988 struct hwrm_vnic_alloc_input *req;
1989 struct hwrm_vnic_alloc_output *resp;
1990 int rc;
1991
1992 DBGP ( "%s\n", __func__ );
1993 req = ( struct hwrm_vnic_alloc_input * ) REQ_DMA_ADDR ( bp );
1994 resp = ( struct hwrm_vnic_alloc_output * ) RESP_DMA_ADDR ( bp );
1995 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_ALLOC, cmd_len );
1996 req->flags = VNIC_ALLOC_REQ_FLAGS_DEFAULT;
1997 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1998 if ( rc ) {
1999 DBGP ( "- %s ( ): Failed\n", __func__ );
2000 return STATUS_FAILURE;
2001 }
2002
2003 FLAG_SET ( bp->flag_hwrm, VALID_VNIC_ID );
2004 bp->vnic_id = resp->vnic_id;
2005 return STATUS_SUCCESS;
2006}
2007
2008static int bnxt_hwrm_vnic_free ( struct bnxt *bp )
2009{
2010 u16 cmd_len = ( u16 )sizeof ( struct hwrm_vnic_free_input );
2011 struct hwrm_vnic_free_input *req;
2012 int rc;
2013
2014 DBGP ( "%s\n", __func__ );
2015 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_VNIC_ID ) ) )
2016 return STATUS_SUCCESS;
2017
2018 req = ( struct hwrm_vnic_free_input * ) REQ_DMA_ADDR ( bp );
2019 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_FREE, cmd_len );
2020 req->vnic_id = bp->vnic_id;
2021 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
2022 if ( rc ) {
2023 DBGP ( "- %s ( ): Failed\n", __func__ );
2024 return STATUS_FAILURE;
2025 }
2026
2027 FLAG_RESET ( bp->flag_hwrm, VALID_VNIC_ID );
2028 return STATUS_SUCCESS;
2029}
2030
2031static int bnxt_hwrm_vnic_cfg ( struct bnxt *bp )
2032{
2033 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_vnic_cfg_input );
2034 struct hwrm_vnic_cfg_input *req;
2035
2036 DBGP ( "%s\n", __func__ );
2037 req = ( struct hwrm_vnic_cfg_input * ) REQ_DMA_ADDR ( bp );
2038 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_CFG, cmd_len );
2039 req->enables = VNIC_CFG_REQ_ENABLES_MRU;
2040 req->mru = bp->mtu;
2041
2042 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
2043 req->enables |= ( VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
2044 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID );
2045 req->default_rx_ring_id = bp->rx_ring_id;
2046 req->default_cmpl_ring_id = bp->cq_ring_id;
2047 } else {
2048 req->enables |= VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP;
2049 req->dflt_ring_grp = bp->ring_grp_id;
2050 }
2051
2052 req->vnic_id = bp->vnic_id;
2053 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
2054}
2055
2056static int bnxt_set_rx_mask ( struct bnxt *bp )
2057{
2058 return bnxt_hwrm_set_rx_mask ( bp, RX_MASK );
2059}
2060
2061static int bnxt_reset_rx_mask ( struct bnxt *bp )
2062{
2063 return bnxt_hwrm_set_rx_mask ( bp, 0 );
2064}
2065
2066static int bnxt_get_link_state ( struct bnxt *bp )
2067{
2068 int rc = 0;
2069
2070 DBGP ( "%s \n", __func__ );
2071 rc = bnxt_hwrm_port_phy_qcfg ( bp, PHY_STATUS );
2072
2073 return rc;
2074}
2075
2076typedef int ( *hwrm_func_t ) ( struct bnxt *bp );
2077
2078hwrm_func_t bring_up_init[] = {
2079 bnxt_hwrm_ver_get, /* HWRM_VER_GET */
2080 bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
2081 bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
2082 bnxt_get_device_address, /* HW MAC address */
2083 bnxt_get_link_state,
2084 NULL
2085};
2086
2087hwrm_func_t bring_down_chip[] = {
2088 bnxt_hwrm_func_drv_unrgtr, /* HWRM_FUNC_DRV_UNRGTR */
2089 NULL,
2090};
2091
2092hwrm_func_t bring_down_nic[] = {
2093 bnxt_hwrm_cfa_l2_filter_free, /* HWRM_CFA_L2_FILTER_FREE */
2094 bnxt_reset_rx_mask,
2095 bnxt_hwrm_vnic_cfg, /* HWRM_VNIC_CFG */
2096 bnxt_free_rx_iob, /* HWRM_FREE_IOB */
2097 bnxt_hwrm_vnic_free, /* HWRM_VNIC_FREE */
2098 bnxt_hwrm_ring_free_grp, /* HWRM_RING_GRP_FREE */
2099 bnxt_hwrm_ring_free_rx, /* HWRM_RING_FREE - RX Ring */
2100 bnxt_hwrm_ring_free_tx, /* HWRM_RING_FREE - TX Ring */
2101 bnxt_hwrm_stat_ctx_free, /* HWRM_STAT_CTX_FREE */
2102 bnxt_hwrm_ring_free_cq, /* HWRM_RING_FREE - CQ Ring */
2103 bnxt_hwrm_ring_free_nq, /* HWRM_RING_FREE - NQ Ring */
2104 bnxt_hwrm_func_drv_unrgtr, /* HWRM_FUNC_DRV_UNRGTR */
2105 NULL,
2106};
2107hwrm_func_t bring_up_chip[] = {
2108 bnxt_hwrm_ver_get, /* HWRM_VER_GET */
2109 bnxt_hwrm_func_reset_req, /* HWRM_FUNC_RESET */
2110 bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
2111 bnxt_hwrm_func_drv_rgtr, /* HWRM_FUNC_DRV_RGTR */
2112 bnxt_hwrm_error_recovery_req, /* HWRM_ERROR_RECOVERY_REQ */
2113 bnxt_hwrm_backing_store_cfg, /* HWRM_FUNC_BACKING_STORE_CFG */
2114 bnxt_hwrm_backing_store_qcfg, /* HWRM_FUNC_BACKING_STORE_QCFG */
2115 bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */
2116 bnxt_hwrm_port_phy_qcaps_req, /* HWRM_PORT_PHY_QCAPS */
2117 bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
2118 bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */
2119 bnxt_hwrm_func_cfg_req, /* HWRM_FUNC_CFG */
2120 bnxt_query_phy_link, /* HWRM_PORT_PHY_QCFG */
2121 bnxt_get_device_address, /* HW MAC address */
2122 NULL,
2123};
2124
2125hwrm_func_t bring_up_nic[] = {
2126 bnxt_hwrm_stat_ctx_alloc, /* HWRM_STAT_CTX_ALLOC */
2127 bnxt_hwrm_queue_qportcfg, /* HWRM_QUEUE_QPORTCFG */
2128 bnxt_hwrm_ring_alloc_nq, /* HWRM_RING_ALLOC - NQ Ring */
2129 bnxt_hwrm_ring_alloc_cq, /* HWRM_RING_ALLOC - CQ Ring */
2130 bnxt_hwrm_ring_alloc_tx, /* HWRM_RING_ALLOC - TX Ring */
2131 bnxt_hwrm_ring_alloc_rx, /* HWRM_RING_ALLOC - RX Ring */
2132 bnxt_hwrm_ring_alloc_grp, /* HWRM_RING_GRP_ALLOC - Group */
2133 bnxt_hwrm_vnic_alloc, /* HWRM_VNIC_ALLOC */
2134 bnxt_post_rx_buffers, /* Post RX buffers */
2135 bnxt_hwrm_set_async_event, /* ENABLES_ASYNC_EVENT_CR */
2136 bnxt_hwrm_vnic_cfg, /* HWRM_VNIC_CFG */
2137 bnxt_hwrm_cfa_l2_filter_alloc, /* HWRM_CFA_L2_FILTER_ALLOC */
2138 bnxt_get_phy_link, /* HWRM_PORT_PHY_QCFG - PhyLink */
2139 bnxt_set_rx_mask, /* HWRM_CFA_L2_SET_RX_MASK */
2140 NULL,
2141};
2142
2143int bnxt_hwrm_run ( hwrm_func_t cmds[], struct bnxt *bp )
2144{
2145 hwrm_func_t *ptr;
2146 int ret;
2147
2148 for ( ptr = cmds; *ptr; ++ptr ) {
2149 memset ( ( void * ) REQ_DMA_ADDR ( bp ), 0, REQ_BUFFER_SIZE );
2150 memset ( ( void * ) RESP_DMA_ADDR ( bp ), 0, RESP_BUFFER_SIZE );
2151 ret = ( *ptr ) ( bp );
2152 if ( ret ) {
2153 DBGP ( "- %s ( ): Failed\n", __func__ );
2154 return STATUS_FAILURE;
2155 }
2156 }
2157 return STATUS_SUCCESS;
2158}
2159
2160#define bnxt_down_chip( bp ) bnxt_hwrm_run ( bring_down_chip, bp )
2161#define bnxt_up_chip( bp ) bnxt_hwrm_run ( bring_up_chip, bp )
2162#define bnxt_down_nic( bp ) bnxt_hwrm_run ( bring_down_nic, bp )
2163#define bnxt_up_nic( bp ) bnxt_hwrm_run ( bring_up_nic, bp )
2164#define bnxt_up_init( bp ) bnxt_hwrm_run ( bring_up_init, bp )
2165
2166static int bnxt_open ( struct net_device *dev )
2167{
2168 struct bnxt *bp = dev->priv;
2169
2170 DBGP ( "%s\n", __func__ );
2171
2172 /* Allocate and Initialise device specific parameters */
2173 if ( bnxt_alloc_rings_mem ( bp ) != 0 ) {
2174 DBGP ( "- %s ( ): bnxt_alloc_rings_mem Failed\n", __func__ );
2175 return -ENOMEM;
2176 }
2177
2178 bnxt_mm_nic ( bp );
2179
2180 if ( bnxt_up_chip ( bp ) != 0 ) {
2181 DBGP ( "- %s ( ): bnxt_up_chip Failed\n", __func__ );
2182 goto err_bnxt_open;
2183 }
2184
2185 if ( bnxt_up_nic ( bp ) != 0 ) {
2186 DBGP ( "- %s ( ): bnxt_up_nic\n", __func__);
2187 goto err_bnxt_open;
2188 }
2189
2190 return 0;
2191
2192err_bnxt_open:
2193 bnxt_down_nic ( bp );
2194
2195 bnxt_free_rings_mem ( bp );
2196
2197 return -1;
2198}
2199
2200static void bnxt_tx_adjust_pkt ( struct bnxt *bp, struct io_buffer *iob )
2201{
2202 u16 prev_len = iob_len ( iob );
2203
2204 bp->vlan_tx = bnxt_get_pkt_vlan ( ( char * )iob->data );
2205 if ( !bp->vlan_tx && bp->vlan_id )
2206 bnxt_add_vlan ( iob, bp->vlan_id );
2207
2208 dbg_tx_vlan ( bp, ( char * )iob->data, prev_len, iob_len ( iob ) );
2209 if ( iob_len ( iob ) != prev_len )
2210 prev_len = iob_len ( iob );
2211
2212}
2213
2214static int bnxt_tx ( struct net_device *dev, struct io_buffer *iob )
2215{
2216 struct bnxt *bp = dev->priv;
2217 u16 len, entry;
2218 physaddr_t mapping;
2219
2220 if ( bp->er.er_rst_on ) {
2221 /* Error recovery has been initiated */
2222 return -EBUSY;
2223 }
2224
2225 if ( bnxt_tx_avail ( bp ) < 1 ) {
2226 DBGP ( "- %s ( ): Failed no bd's available\n", __func__ );
2227 return -ENOBUFS;
2228 }
2229
2230 mapping = iob_dma ( iob );
2231 bnxt_tx_adjust_pkt ( bp, iob );
2232 entry = bp->tx.prod_id;
2233 len = iob_len ( iob );
2234 bp->tx.iob[entry] = iob;
2235 bnxt_set_txq ( bp, entry, mapping, len );
2236 entry = NEXT_IDX ( entry, bp->tx.ring_cnt );
2237 /* If the ring has wrapped, toggle the epoch bit */
2238 if ( bp->tx.prod_id > entry )
2239 bp->tx.epoch ^= 1;
2240 dump_tx_pkt ( ( u8 * ) iob->data, len, bp->tx.prod_id );
2241 /* Packets are ready, update Tx producer idx local and on card. */
2242 bnxt_db_tx ( bp, ( u32 ) entry );
2243 bp->tx.prod_id = entry;
2244 bp->tx.cnt_req++;
2245 /* memory barrier */
2246 mb ( );
2247 return 0;
2248}
2249
2250static void bnxt_adv_nq_index ( struct bnxt *bp, u16 cnt )
2251{
2252 u16 cons_id;
2253
2254 cons_id = bp->nq.cons_id + cnt;
2255 if ( cons_id >= bp->nq.ring_cnt ) {
2256 /* Toggle completion bit when the ring wraps. */
2257 bp->nq.completion_bit ^= 1;
2258 bp->nq.epoch ^= 1;
2259 cons_id = cons_id - bp->nq.ring_cnt;
2260 }
2261 bp->nq.cons_id = cons_id;
2262}
2263
2264void bnxt_link_evt ( struct bnxt *bp, struct hwrm_async_event_cmpl *evt )
2265{
2266 if ( evt->event_data1 & 0x01 )
2267 bp->link_status = STATUS_LINK_ACTIVE;
2268 else
2269 bp->link_status = STATUS_LINK_DOWN;
2270
2271 bnxt_set_link ( bp );
2272 dbg_link_status ( bp );
2273}
2274
2275#define BNXT_FW_HEALTH_WIN_OFF 0x3000
2276#define BNXT_REG_WINDOW_BASE 0x400
2277#define BNXT_GRC_BASE_MASK 0xfff
2278#define BNXT_GRC_OFFSET_MASK 0xffc
2279
2280u32 bnxt_er_reg_write ( struct bnxt *bp, u32 reg_addr, u32 reg_val)
2281{
2282 u32 reg_base = 0;
2283
2284 reg_base = reg_addr & ~BNXT_GRC_BASE_MASK;
2285
2286 writel ( reg_base, bp->bar0 + BNXT_REG_WINDOW_BASE + 8 );
2287
2288 writel ( reg_val, bp->bar0 + ( BNXT_FW_HEALTH_WIN_OFF +
2289 ( reg_addr & BNXT_GRC_OFFSET_MASK ) ) );
2290
2291 DBGP ("bnxt_er_reg_write: reg_addr = %x, reg_val = %x\n", reg_addr, reg_val);
2292 return reg_val;
2293}
2294
2295u32 bnxt_er_reg_read ( struct bnxt *bp, u32 reg_addr)
2296{
2297 u32 reg_val = 0;
2298 u32 reg_base = 0;
2299
2300 reg_base = reg_addr & ~BNXT_GRC_BASE_MASK;
2301
2302 writel ( reg_base, bp->bar0 + BNXT_REG_WINDOW_BASE + 8 );
2303
2304 reg_val = readl ( bp->bar0 + ( BNXT_FW_HEALTH_WIN_OFF +
2305 ( reg_addr & BNXT_GRC_OFFSET_MASK ) ) );
2306
2307 DBGP ("bnxt_er_reg_read: reg_addr = %x, reg_val = %x\n", reg_addr, reg_val);
2308 return reg_val;
2309}
2310
2311u32 bnxt_er_get_reg_val ( struct bnxt *bp, u32 reg_addr, u32 reg_type, u32 mask )
2312{
2313 u32 reg_val = 0;
2314
2315 switch ( reg_type ) {
2316 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG:
2317 pci_read_config_dword ( bp->pdev, reg_addr & mask, &reg_val );
2318 break;
2319 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC:
2320 reg_val = bnxt_er_reg_read ( bp, reg_addr );
2321 break;
2322 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0:
2323 reg_val = readl ( bp->bar0 + ( reg_addr & mask ) );
2324 break;
2325 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1:
2326 reg_val = readl ( bp->bar1 + ( reg_addr & mask ) );
2327 break;
2328 default:
2329 break;
2330 }
2331 DBGP ( "read_reg_val bp %p addr %x type %x : reg_val = %x\n", bp, reg_addr, reg_type, reg_val );
2332 return reg_val;
2333}
2334
2335void bnxt_rst_reg_val ( struct bnxt *bp, u32 reg_addr, u32 reg_val )
2336{
2337 u32 mask = ER_QCFG_RESET_REG_ADDR_MASK;
2338 u32 reg_type = reg_addr & ER_QCFG_RESET_REG_ADDR_SPACE_MASK;
2339
2340 switch ( reg_type ) {
2341 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG:
2342 pci_write_config_dword ( bp->pdev, reg_addr & mask, reg_val );
2343 break;
2344 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC:
2345 bnxt_er_reg_write ( bp, reg_addr, reg_val );
2346 break;
2347 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0:
2348 writel ( reg_val, bp->bar0 + ( reg_addr & mask ) );
2349 break;
2350 case ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1:
2351 writel ( reg_val, bp->bar1 + ( reg_addr & mask ) );
2352 break;
2353 default:
2354 break;
2355 }
2356}
2357
2358void bnxt_rst_er_registers ( struct bnxt *bp )
2359{
2360 u32 delay_time = 0;
2361 u8 i;
2362
2363 for ( i = 0; i < bp->er.reg_array_cnt; i++ ) {
2364 bnxt_rst_reg_val ( bp, bp->er.rst_reg[i], bp->er.rst_reg_val[i] );
2365
2366 delay_time = bp->er.delay_after_rst[i];
2367 if ( delay_time ) {
2368 udelay ( delay_time * 100000 );
2369 }
2370 }
2371
2372}
2373
2374void bnxt_er_task ( struct bnxt* bp, u8 hb_task )
2375{
2376 u32 present_hb_cnt;
2377 unsigned short pci_command, new_command;
2378 u8 i;
2379
2380 DBGP ( "%s(hb_task: %d)\n", __func__, hb_task );
2381 if ( bp->er.er_rst_on ) {
2382 if ( timer_running ( &bp->wait_timer) ) {
2383 /* Reset already in progress */
2384 return;
2385 }
2386 }
2387
2388 if ( hb_task ) {
2389 present_hb_cnt = bnxt_er_get_reg_val ( bp,
2390 bp->er.fw_hb_reg,
2391 bp->er.fw_hb_reg & ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK,
2392 ER_QCFG_FW_HB_REG_ADDR_MASK ) ;
2393
2394 if ( present_hb_cnt != bp->er.last_fw_hb ) {
2395 bp->er.last_fw_hb = present_hb_cnt;
2396 return;
2397 }
2398 }
2399
2400 /* Heartbeat not incrementing, trigger error recovery */
2401 DBGP ( "%s(): Trigger Error Recovery\n", __func__ );
2402 bp->er.er_rst_on = 1;
2403 /* Set a recovery phase wait timer */
2404 start_timer_fixed ( &bp->wait_timer, BNXT_ER_WAIT_TIMER_INTERVAL ( bp ) );
2405
2406 /* Disable bus master */
2407 pci_read_config_word ( bp->pdev, PCI_COMMAND, &pci_command );
2408 new_command = pci_command & ~PCI_COMMAND_MASTER;
2409 pci_write_config_word ( bp->pdev, PCI_COMMAND, new_command );
2410
2411 /* Free up resources */
2412 bnxt_free_rx_iob ( bp );
2413
2414 /* wait for firmware to be operational */
2415 udelay ( bp->er.rst_min_dsecs * 100000 );
2416
2417 /* Reconfigure the PCI attributes */
2418 pci_write_config_word ( bp->pdev, PCI_COMMAND, pci_command );
2419
2420 if ( hb_task ) {
2421 if ( bp->er.master_pf ) {
2422 /* wait for master func wait period */
2423 udelay ( bp->er.master_wait_period * 100000 );
2424
2425 /* Reset register values */
2426 bnxt_rst_er_registers ( bp );
2427
2428 /* wait for master wait post reset */
2429 udelay ( bp->er.master_wait_post_rst * 100000 );
2430 } else {
2431 /* wait for normal func wait period */
2432 udelay ( bp->er.normal_wait_period * 100000 );
2433 }
2434 }
2435
2436 for ( i = 0; i < bp->er.max_bailout_post_rst; i++ ) {
2437 bp->er.fw_health_status = bnxt_er_get_reg_val ( bp,
2438 bp->er.fw_status_reg,
2439 bp->er.fw_status_reg & ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK,
2440 ER_QCFG_FW_HEALTH_REG_ADDR_MASK );
2441
2442 if ( bp->er.fw_health_status == FW_STATUS_REG_CODE_READY )
2443 break;
2444
2445 /* wait for 1 second */
2446 udelay ( 1000000 );
2447 }
2448
2449 if ( bp->er.fw_health_status == FW_STATUS_REG_CODE_READY ) {
2450 /* Initialize resources */
2451 bnxt_mm_nic ( bp );
2452
2453 /* Get device specific information */
2454 bnxt_up_chip ( bp );
2455
2456 /* Allocate queues */
2457 bnxt_up_nic ( bp );
2458 }
2459
2460 /* Clear Reset in progress flag */
2461 bp->er.er_rst_on = 0;
2462 stop_timer ( &bp->wait_timer );
2463}
2464
2465void bnxt_process_er_event ( struct bnxt *bp,
2466 struct hwrm_async_event_cmpl *evt )
2467{
2468 if ( evt->event_data1 &
2469 ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED ) {
2470 bp->er.driver_initiated_recovery = 1;
2471 start_timer_fixed ( &bp->task_timer, BNXT_ER_TIMER_INTERVAL ( bp ) );
2472
2473 } else {
2474 bp->er.driver_initiated_recovery = 0;
2475 stop_timer ( &bp->task_timer );
2476 }
2477
2478 if ( evt->event_data1 &
2479 ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC ) {
2480 bp->er.master_pf = 1;
2481 } else {
2482 bp->er.master_pf = 0;
2483 }
2484
2485 bp->er.fw_health_status = bnxt_er_get_reg_val ( bp,
2486 bp->er.fw_status_reg,
2487 bp->er.fw_status_reg & ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK,
2488 ER_QCFG_FW_HEALTH_REG_ADDR_MASK );
2489 /* Intialize the last fw heart beat count */
2490 bp->er.last_fw_hb = 0;
2491 bp->er.last_fw_rst_cnt = bnxt_er_get_reg_val ( bp,
2492 bp->er.fw_rst_cnt_reg,
2493 bp->er.fw_rst_cnt_reg & ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK,
2494 ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK );
2495 bp->er.rst_in_progress = bnxt_er_get_reg_val ( bp,
2496 bp->er.rst_inprg_reg,
2497 bp->er.rst_inprg_reg & ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK,
2498 ER_QCFG_RESET_INPRG_REG_ADDR_MASK );
2499 bp->er.err_recovery_cnt = bnxt_er_get_reg_val ( bp,
2500 bp->er.recvry_cnt_reg,
2501 bp->er.recvry_cnt_reg & ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK,
2502 ER_QCFG_RCVRY_CNT_REG_ADDR_MASK );
2503}
2504
2505void bnxt_process_reset_notify_event ( struct bnxt *bp,
2506 struct hwrm_async_event_cmpl *evt )
2507{
2508 DBGP ( "Reset Notify Async event" );
2509 if ( ( ( evt->event_data1 ) &
2510 ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK ) ==
2511 ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL) {
2512 DBGP ( " error recovery initiated\n" );
2513 bp->er.rst_min_dsecs = evt->timestamp_lo;
2514 bp->er.rst_max_dsecs = evt->timestamp_hi;
2515
2516 if ( bp->er.rst_min_dsecs == 0 )
2517 bp->er.rst_min_dsecs = ER_DFLT_FW_RST_MIN_DSECS;
2518
2519 if ( bp->er.rst_max_dsecs == 0 )
2520 bp->er.rst_max_dsecs = ER_DFLT_FW_RST_MAX_DSECS;
2521
2522 // Trigger Error recovery
2523 bp->er.er_initiate = 1;
2524 }
2525}
2526
2527void bnxt_link_speed_evt ( struct bnxt *bp, struct hwrm_async_event_cmpl *evt )
2528{
2529 if ( evt->event_data1 & ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE ) {
2530 DBGP ("bnxt_link_speed_evt: event data = %lx\n",
2531 ( evt->event_data1 & ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK ));
2532 }
2533
2534 if ( bnxt_hwrm_port_phy_qcfg ( bp, QCFG_PHY_ALL ) != STATUS_SUCCESS ) {
2535 return;
2536 }
2537
2538 bnxt_set_link ( bp );
2539 dbg_link_info ( bp );
2540 dbg_link_status ( bp );
2541}
2542
2556
2571
2572static void bnxt_service_cq ( struct net_device *dev )
2573{
2574 struct bnxt *bp = dev->priv;
2575 struct cmpl_base *cmp;
2576 struct tx_cmpl *tx;
2577 u16 old_cid = bp->cq.cons_id;
2578 int done = SERVICE_NEXT_CQ_BD;
2579 u32 cq_type;
2580 struct hwrm_async_event_cmpl *evt;
2581
2582 while ( done == SERVICE_NEXT_CQ_BD ) {
2583 cmp = ( struct cmpl_base * ) BD_NOW ( CQ_DMA_ADDR ( bp ),
2584 bp->cq.cons_id,
2585 sizeof ( struct cmpl_base ) );
2586
2587 if ( ( cmp->info3_v & CMPL_BASE_V ) ^ bp->cq.completion_bit )
2588 break;
2589
2590 cq_type = cmp->type & CMPL_BASE_TYPE_MASK;
2591 dump_evt ( ( u8 * ) cmp, cq_type, bp->cq.cons_id, 0 );
2592 dump_cq ( cmp, bp->cq.cons_id, bp->nq.toggle );
2593
2594 switch ( cq_type ) {
2595 case CMPL_BASE_TYPE_TX_L2:
2596 tx = ( struct tx_cmpl * ) cmp;
2597 bnxt_tx_complete ( dev, ( u16 ) tx->opaque );
2598 /* Fall through */
2599 case CMPL_BASE_TYPE_STAT_EJECT:
2600 bnxt_adv_cq_index ( bp, 1 );
2601 break;
2602 case CMPL_BASE_TYPE_RX_L2:
2603 case CMPL_BASE_TYPE_RX_L2_V3:
2604 done = bnxt_rx_complete ( dev,
2605 ( struct rx_pkt_cmpl * ) cmp );
2606 break;
2607 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2608 evt = ( struct hwrm_async_event_cmpl * ) cmp;
2609 switch ( evt->event_id ) {
2610 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2611 bnxt_link_evt ( bp,
2612 ( struct hwrm_async_event_cmpl * ) cmp );
2613 break;
2614 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2615 bnxt_link_speed_evt ( bp,
2616 ( struct hwrm_async_event_cmpl * ) cmp );
2617 break;
2618 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE:
2619 bnxt_link_speed_chg_evt ( bp,
2620 ( struct hwrm_async_event_cmpl * ) cmp );
2621 break;
2622 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2623 bnxt_port_phy_chg_evt ( bp,
2624 ( struct hwrm_async_event_cmpl * ) cmp );
2625 break;
2626 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY:
2627 bnxt_process_er_event ( bp,
2628 ( struct hwrm_async_event_cmpl * ) cmp );
2629 break;
2630 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY:
2631 bnxt_process_reset_notify_event ( bp,
2632 ( struct hwrm_async_event_cmpl * ) cmp );
2633 break;
2634 default:
2635 break;
2636 }
2637 bnxt_adv_cq_index ( bp, 1 );
2638 break;
2639 default:
2640 done = NO_MORE_CQ_BD_TO_SERVICE;
2641 break;
2642 }
2643 }
2644
2645 if ( bp->cq.cons_id != old_cid )
2646 bnxt_db_cq ( bp );
2647}
2648
2649static void bnxt_service_nq ( struct net_device *dev )
2650{
2651 struct bnxt *bp = dev->priv;
2652 struct nq_base *nqp;
2653 u16 old_cid = bp->nq.cons_id;
2654 int done = SERVICE_NEXT_NQ_BD;
2655 u32 nq_type;
2656 struct hwrm_async_event_cmpl *evt;
2657
2658 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
2659 return;
2660
2661 while ( done == SERVICE_NEXT_NQ_BD ) {
2662 nqp = ( struct nq_base * ) BD_NOW ( NQ_DMA_ADDR ( bp ),
2663 bp->nq.cons_id,
2664 sizeof ( struct nq_base ) );
2665 if ( ( nqp->v & NQ_CN_V ) ^ bp->nq.completion_bit )
2666 break;
2667 nq_type = ( nqp->type & NQ_CN_TYPE_MASK );
2668 bp->nq.toggle = ( ( nqp->type & NQ_CN_TOGGLE_MASK ) >> NQ_CN_TOGGLE_SFT );
2669 dump_evt ( ( u8 * )nqp, nq_type, bp->nq.cons_id, 1 );
2670 dump_nq ( nqp, bp->nq.cons_id );
2671
2672 switch ( nq_type ) {
2673 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2674 evt = ( struct hwrm_async_event_cmpl * ) nqp;
2675 switch ( evt->event_id ) {
2676 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2677 bnxt_link_evt ( bp,
2678 ( struct hwrm_async_event_cmpl * ) nqp );
2679 break;
2680 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
2681 bnxt_link_speed_evt ( bp,
2682 ( struct hwrm_async_event_cmpl * ) nqp );
2683 break;
2684 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE:
2685 bnxt_link_speed_chg_evt ( bp,
2686 ( struct hwrm_async_event_cmpl * ) nqp );
2687 break;
2688 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2689 bnxt_port_phy_chg_evt ( bp,
2690 ( struct hwrm_async_event_cmpl * ) nqp );
2691 break;
2692 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY:
2693 bnxt_process_er_event ( bp,
2694 ( struct hwrm_async_event_cmpl * ) nqp );
2695 break;
2696 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY:
2697 bnxt_process_reset_notify_event ( bp,
2698 ( struct hwrm_async_event_cmpl * ) nqp );
2699 break;
2700 default:
2701 break;
2702 }
2703 bnxt_adv_nq_index ( bp, 1 );
2704 break;
2705 case NQ_CN_TYPE_CQ_NOTIFICATION:
2706 bnxt_adv_nq_index ( bp, 1 );
2707 break;
2708 default:
2709 done = NO_MORE_NQ_BD_TO_SERVICE;
2710 break;
2711 }
2712 }
2713
2714 if ( bp->nq.cons_id != old_cid )
2715 bnxt_db_nq ( bp );
2716}
2717
2718static void bnxt_er_task_timer ( struct retry_timer *timer, int over __unused )
2719{
2720 struct bnxt *bp = container_of ( timer, struct bnxt, task_timer );
2721
2722 /* Restart timer */
2723 start_timer_fixed ( timer, BNXT_ER_TIMER_INTERVAL ( bp ) );
2724 if ( bp->er.driver_initiated_recovery ) {
2725 bnxt_er_task ( bp, 1 );
2726 }
2727}
2728
2729static void bnxt_er_wait_timer ( struct retry_timer *timer, int over __unused )
2730{
2731 struct bnxt *bp = container_of (timer, struct bnxt, wait_timer );
2732 /* The sole function of this timer is to wait for the specified
2733 * amount of time to complete error recovery phase
2734 */
2735 stop_timer ( &bp->wait_timer );
2736 return;
2737}
2738
2739static void bnxt_poll ( struct net_device *dev )
2740{
2741 struct bnxt *bp = dev->priv;
2742
2743 mb ( );
2744 bnxt_service_nq ( dev );
2745 bnxt_service_cq ( dev );
2746
2747 if ( bp->er.er_initiate ) {
2748 bnxt_er_task ( bp, 0 );
2749 bp->er.er_initiate = 0;
2750 }
2751
2752}
2753
2754static void bnxt_close ( struct net_device *dev )
2755{
2756 struct bnxt *bp = dev->priv;
2757
2758 DBGP ( "%s\n", __func__ );
2759 stop_timer ( &bp->task_timer );
2760 stop_timer ( &bp->wait_timer );
2761
2762 bnxt_down_nic ( bp );
2763
2764 bnxt_free_rings_mem ( bp );
2765
2766}
2767
2768static struct net_device_operations bnxt_netdev_ops = {
2769 .open = bnxt_open,
2770 .close = bnxt_close,
2771 .poll = bnxt_poll,
2772 .transmit = bnxt_tx,
2773};
2774
2775static int bnxt_init_one ( struct pci_device *pci )
2776{
2777 struct net_device *netdev;
2778 struct bnxt *bp;
2779 int err = 0;
2780
2781 DBGP ( "%s\n", __func__ );
2782 /* Allocate network device */
2783 netdev = alloc_etherdev ( sizeof ( *bp ) );
2784 if ( !netdev ) {
2785 DBGP ( "- %s ( ): alloc_etherdev Failed\n", __func__ );
2786 err = -ENOMEM;
2787 goto disable_pdev;
2788 }
2789
2790 /* Initialise network device */
2791 netdev_init ( netdev, &bnxt_netdev_ops );
2792
2793 /* Driver private area for this device */
2794 bp = netdev->priv;
2795
2796 /* Set PCI driver private data */
2797 pci_set_drvdata ( pci, netdev );
2798
2799 /* Clear Private area data */
2800 memset ( bp, 0, sizeof ( *bp ) );
2801 bp->pdev = pci;
2802 bp->dev = netdev;
2803 netdev->dev = &pci->dev;
2804
2805 timer_init ( &bp->task_timer, bnxt_er_task_timer, &netdev->refcnt );
2806 timer_init ( &bp->wait_timer, bnxt_er_wait_timer, &netdev->refcnt );
2807
2808 /* Configure DMA */
2809 bp->dma = &pci->dma;
2810 netdev->dma = bp->dma;
2811
2812 /* Enable PCI device */
2813 adjust_pci_device ( pci );
2814
2815 /* Get PCI Information */
2816 bnxt_get_pci_info ( bp );
2817
2818 /* Allocate HWRM memory */
2819 if ( ( err = bnxt_alloc_hwrm_mem ( bp ) ) != 0 )
2820 goto err_alloc_hwrm;
2821
2822 bp->link_status = STATUS_LINK_DOWN;
2823 bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
2824 if ( ( err = bnxt_up_init ( bp ) ) != 0 )
2825 goto err_up_init;
2826
2827 /* Register Network device */
2828 if ( ( err = register_netdev ( netdev ) ) != 0 ) {
2829 DBGP ( "- %s ( ): register_netdev Failed\n", __func__ );
2830 goto err_register_netdev;
2831 }
2832
2833 /* Set Initial Link State */
2834 bnxt_set_link ( bp );
2835
2836 return 0;
2837
2838 unregister_netdev ( netdev );
2839err_register_netdev:
2840err_up_init:
2841 bnxt_free_hwrm_mem ( bp );
2842err_alloc_hwrm:
2843 bnxt_down_pci ( bp );
2844 netdev_nullify ( netdev );
2845 netdev_put ( netdev );
2846disable_pdev:
2847 pci_set_drvdata ( pci, NULL );
2848 return err;
2849}
2850
2851static void bnxt_remove_one ( struct pci_device *pci )
2852{
2853 struct net_device *netdev = pci_get_drvdata ( pci );
2854 struct bnxt *bp = netdev->priv;
2855
2856 DBGP ( "%s\n", __func__ );
2857 /* Unregister network device */
2858 unregister_netdev ( netdev );
2859
2860 /* Free HWRM buffers */
2861 bnxt_free_hwrm_mem ( bp );
2862
2863 /* iounmap PCI BAR ( s ) */
2864 bnxt_down_pci ( bp );
2865
2866 /* Stop network device */
2867 netdev_nullify ( netdev );
2868
2869 /* Drop refernce to network device */
2870 netdev_put ( netdev );
2871 DBGP ( "%s - Done\n", __func__ );
2872}
2873
2874/* Broadcom NXE PCI driver */
2875struct pci_driver bnxt_pci_driver __pci_driver = {
2876 .ids = bnxt_nics,
2877 .id_count = ARRAY_SIZE ( bnxt_nics ),
2878 .probe = bnxt_init_one,
2879 .remove = bnxt_remove_one,
2880};
NULL
#define NULL
NULL pointer (VOID *)
Definition Base.h:322
cmd
struct golan_eqe_cmd cmd
Definition CIB_PRM.h:1
flag
uint32_t flag
Flag number.
Definition aqc1xx.h:2
rc
struct arbelprm_rc_send_wqe rc
Definition arbel.h:3
physaddr_t
unsigned long physaddr_t
Definition stdint.h:20
src
static const void * src
Definition string.h:48
assert
#define assert(condition)
Assert a condition at run-time.
Definition assert.h:50
MAX_TX_DESC_CNT
#define MAX_TX_DESC_CNT
Definition bnx2.h:3881
MAX_RX_DESC_CNT
#define MAX_RX_DESC_CNT
Definition bnx2.h:3885
bnxt_hwrm_set_rx_mask
static int bnxt_hwrm_set_rx_mask(struct bnxt *bp, u32 rx_mask)
Definition bnxt.c:1272
bnxt_hwrm_error_recovery_req
static int bnxt_hwrm_error_recovery_req(struct bnxt *bp)
Definition bnxt.c:1024
bnxt_hwrm_ring_alloc_nq
static int bnxt_hwrm_ring_alloc_nq(struct bnxt *bp)
Definition bnxt.c:1960
bnxt_hwrm_ring_free_grp
static int bnxt_hwrm_ring_free_grp(struct bnxt *bp)
Definition bnxt.c:1752
bnxt_tx_avail
static u32 bnxt_tx_avail(struct bnxt *bp)
Definition bnxt.c:286
bnxt_rst_er_registers
void bnxt_rst_er_registers(struct bnxt *bp)
Definition bnxt.c:2358
bnxt_alloc_rings_mem
int bnxt_alloc_rings_mem(struct bnxt *bp)
Definition bnxt.c:636
bnxt_poll
static void bnxt_poll(struct net_device *dev)
Definition bnxt.c:2739
bnxt_hwrm_stat_ctx_free
static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
Definition bnxt.c:1729
bnxt_hwrm_vnic_alloc
static int bnxt_hwrm_vnic_alloc(struct bnxt *bp)
Definition bnxt.c:1985
bnxt_alloc_rx_iob
static int bnxt_alloc_rx_iob(struct bnxt *bp, u16 cons_id, u16 iob_idx)
Definition bnxt.c:364
bnxt_close
static void bnxt_close(struct net_device *dev)
Definition bnxt.c:2754
bnxt_er_reg_read
u32 bnxt_er_reg_read(struct bnxt *bp, u32 reg_addr)
Definition bnxt.c:2295
bnxt_hwrm_ring_free_cq
static int bnxt_hwrm_ring_free_cq(struct bnxt *bp)
Definition bnxt.c:1915
bring_down_nic
hwrm_func_t bring_down_nic[]
Definition bnxt.c:2092
bnxt_db_nq
static void bnxt_db_nq(struct bnxt *bp)
Definition bnxt.c:216
bnxt_free_rx_iob
int bnxt_free_rx_iob(struct bnxt *bp)
Definition bnxt.c:331
bring_down_chip
hwrm_func_t bring_down_chip[]
Definition bnxt.c:2087
bnxt_hwrm_ring_alloc_grp
static int bnxt_hwrm_ring_alloc_grp(struct bnxt *bp)
Definition bnxt.c:1775
BNXT_FW_HEALTH_WIN_OFF
#define BNXT_FW_HEALTH_WIN_OFF
Definition bnxt.c:2275
bnxt_get_pci_info
static int bnxt_get_pci_info(struct bnxt *bp)
Definition bnxt.c:131
bnxt_open
static int bnxt_open(struct net_device *dev)
Definition bnxt.c:2166
bnxt_db_cq
static void bnxt_db_cq(struct bnxt *bp)
Definition bnxt.c:229
bnxt_hwrm_ring_alloc_rx
static int bnxt_hwrm_ring_alloc_rx(struct bnxt *bp)
Definition bnxt.c:1909
bnxt_tx
static int bnxt_tx(struct net_device *dev, struct io_buffer *iob)
Definition bnxt.c:2214
bnxt_mm_init_hwrm
void bnxt_mm_init_hwrm(struct bnxt *bp, const char *func)
Definition bnxt.c:511
bring_up_chip
hwrm_func_t bring_up_chip[]
Definition bnxt.c:2107
BNXT_GRC_BASE_MASK
#define BNXT_GRC_BASE_MASK
Definition bnxt.c:2277
bnxt_get_link_state
static int bnxt_get_link_state(struct bnxt *bp)
Definition bnxt.c:2066
bnxt_reset_rx_mask
static int bnxt_reset_rx_mask(struct bnxt *bp)
Definition bnxt.c:2061
bnxt_er_task
void bnxt_er_task(struct bnxt *bp, u8 hb_task)
Definition bnxt.c:2374
bnxt_hwrm_cfa_l2_filter_alloc
static int bnxt_hwrm_cfa_l2_filter_alloc(struct bnxt *bp)
Definition bnxt.c:1188
bnxt_service_cq
static void bnxt_service_cq(struct net_device *dev)
Definition bnxt.c:2572
bnxt_tx_adjust_pkt
static void bnxt_tx_adjust_pkt(struct bnxt *bp, struct io_buffer *iob)
Definition bnxt.c:2200
bnxt_set_txq
void bnxt_set_txq(struct bnxt *bp, int entry, physaddr_t mapping, int len)
Definition bnxt.c:298
bnxt_hwrm_func_drv_rgtr
static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
Definition bnxt.c:1087
bnxt_hwrm_func_qcfg_req
static int bnxt_hwrm_func_qcfg_req(struct bnxt *bp)
Definition bnxt.c:921
bnxt_hwrm_queue_qportcfg
static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
Definition bnxt.c:1461
bnxt_hwrm_cfa_l2_filter_free
static int bnxt_hwrm_cfa_l2_filter_free(struct bnxt *bp)
Definition bnxt.c:1229
bring_up_nic
hwrm_func_t bring_up_nic[]
Definition bnxt.c:2125
bnxt_down_pci
static void bnxt_down_pci(struct bnxt *bp)
Definition bnxt.c:105
bnxt_link_speed_evt
void bnxt_link_speed_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2527
bnxt_hwrm_backing_store_qcfg
static int bnxt_hwrm_backing_store_qcfg(struct bnxt *bp)
Definition bnxt.c:1429
bnxt_hwrm_backing_store_cfg
static int bnxt_hwrm_backing_store_cfg(struct bnxt *bp)
Definition bnxt.c:1444
BNXT_GRC_OFFSET_MASK
#define BNXT_GRC_OFFSET_MASK
Definition bnxt.c:2278
bnxt_is_pci_vf
u8 bnxt_is_pci_vf(struct pci_device *pdev)
Check if Virtual Function.
Definition bnxt.c:97
bnxt_hwrm_ring_alloc_tx
static int bnxt_hwrm_ring_alloc_tx(struct bnxt *bp)
Definition bnxt.c:1903
bnxt_hwrm_ver_get
static int bnxt_hwrm_ver_get(struct bnxt *bp)
Definition bnxt.c:724
bnxt_get_link_speed
static int bnxt_get_link_speed(struct bnxt *bp)
Definition bnxt.c:1345
bnxt_hwrm_func_resource_qcaps
static int bnxt_hwrm_func_resource_qcaps(struct bnxt *bp)
Definition bnxt.c:771
bnxt_db_rx
static void bnxt_db_rx(struct bnxt *bp, u32 idx)
Definition bnxt.c:243
bnxt_hwrm_ring_free
int bnxt_hwrm_ring_free(struct bnxt *bp, u16 ring_id, u8 ring_type)
Definition bnxt.c:1806
wait_resp
static int wait_resp(struct bnxt *bp, u32 tmo, u16 len, const char *func)
Definition bnxt.c:694
short_hwrm_cmd_req
static void short_hwrm_cmd_req(struct bnxt *bp, u16 len)
Definition bnxt.c:679
bnxt_er_task_timer
static void bnxt_er_task_timer(struct retry_timer *timer, int over __unused)
Definition bnxt.c:2718
bnxt_hwrm_ring_free_nq
static int bnxt_hwrm_ring_free_nq(struct bnxt *bp)
Definition bnxt.c:1967
bnxt_er_get_reg_val
u32 bnxt_er_get_reg_val(struct bnxt *bp, u32 reg_addr, u32 reg_type, u32 mask)
Definition bnxt.c:2311
bnxt_set_link
static void bnxt_set_link(struct bnxt *bp)
Definition bnxt.c:179
bnxt_set_ring_info
static u32 bnxt_set_ring_info(struct bnxt *bp)
Definition bnxt.c:833
bnxt_post_rx_buffers
int bnxt_post_rx_buffers(struct bnxt *bp)
Definition bnxt.c:381
bnxt_free_rings_mem
void bnxt_free_rings_mem(struct bnxt *bp)
Definition bnxt.c:570
bnxt_hwrm_vnic_free
static int bnxt_hwrm_vnic_free(struct bnxt *bp)
Definition bnxt.c:2008
bnxt_hwrm_port_mac_cfg
static int bnxt_hwrm_port_mac_cfg(struct bnxt *bp)
Definition bnxt.c:1485
bnxt_add_vlan
void bnxt_add_vlan(struct io_buffer *iob, u16 vlan)
Definition bnxt.c:265
bnxt_rst_reg_val
void bnxt_rst_reg_val(struct bnxt *bp, u32 reg_addr, u32 reg_val)
Definition bnxt.c:2335
bnxt_pci_base
static void * bnxt_pci_base(struct pci_device *pdev, unsigned int reg)
Definition bnxt.c:122
bnxt_hwrm_nvm_get_variable_req
static int bnxt_hwrm_nvm_get_variable_req(struct bnxt *bp, u16 data_len, u16 option_num, u16 dimensions, u16 index_0)
Definition bnxt.c:1326
bnxt_db_tx
static void bnxt_db_tx(struct bnxt *bp, u32 idx)
Definition bnxt.c:254
bnxt_link_speed_chg_evt
void bnxt_link_speed_chg_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2543
bnxt_alloc_hwrm_mem
int bnxt_alloc_hwrm_mem(struct bnxt *bp)
Definition bnxt.c:616
bnxt_mm_init_rings
void bnxt_mm_init_rings(struct bnxt *bp, const char *func)
Definition bnxt.c:522
bnxt_nics
static struct pci_device_id bnxt_nics[]
Definition bnxt.c:28
bnxt_up_chip
#define bnxt_up_chip(bp)
Definition bnxt.c:2161
bnxt_set_rx_mask
static int bnxt_set_rx_mask(struct bnxt *bp)
Definition bnxt.c:2056
bnxt_process_er_event
void bnxt_process_er_event(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2465
bnxt_up_init
#define bnxt_up_init(bp)
Definition bnxt.c:2164
bnxt_netdev_ops
static struct net_device_operations bnxt_netdev_ops
Definition bnxt.c:2768
bnxt_set_rx_desc
static void bnxt_set_rx_desc(u8 *buf, struct io_buffer *iob, u16 cid, u32 idx)
Definition bnxt.c:351
bnxt_hwrm_ring_free_tx
static int bnxt_hwrm_ring_free_tx(struct bnxt *bp)
Definition bnxt.c:1930
bnxt_hwrm_assign_resources
static void bnxt_hwrm_assign_resources(struct bnxt *bp)
Definition bnxt.c:868
hwrm_func_t
int(* hwrm_func_t)(struct bnxt *bp)
Definition bnxt.c:2076
bnxt_init_one
static int bnxt_init_one(struct pci_device *pci)
Definition bnxt.c:2775
BNXT_REG_WINDOW_BASE
#define BNXT_REG_WINDOW_BASE
Definition bnxt.c:2276
bring_up_init
hwrm_func_t bring_up_init[]
Definition bnxt.c:2078
bnxt_port_phy_chg_evt
void bnxt_port_phy_chg_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2557
bnxt_adv_nq_index
static void bnxt_adv_nq_index(struct bnxt *bp, u16 cnt)
Definition bnxt.c:2250
bnxt_rx_process
void bnxt_rx_process(struct net_device *dev, struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi)
Definition bnxt.c:466
bnxt_get_device_address
static int bnxt_get_device_address(struct bnxt *bp)
Definition bnxt.c:165
bnxt_down_nic
#define bnxt_down_nic(bp)
Definition bnxt.c:2162
bnxt_hwrm_vnic_cfg
static int bnxt_hwrm_vnic_cfg(struct bnxt *bp)
Definition bnxt.c:2031
bnxt_hwrm_func_drv_unrgtr
static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
Definition bnxt.c:1129
bnxt_hwrm_port_phy_cfg
static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp)
Definition bnxt.c:1500
bnxt_hwrm_func_cfg_req
static int bnxt_hwrm_func_cfg_req(struct bnxt *bp)
Definition bnxt.c:1000
dev_p7_db
static void dev_p7_db(struct bnxt *bp, u32 idx, u32 xid, u32 flag, u32 epoch, u32 toggle)
Definition bnxt.c:202
bnxt_mm_nic
void bnxt_mm_nic(struct bnxt *bp)
Definition bnxt.c:541
bnxt_hwrm_ring_alloc_cq
static int bnxt_hwrm_ring_alloc_cq(struct bnxt *bp)
Definition bnxt.c:1897
bnxt_hwrm_func_qcaps_req
static int bnxt_hwrm_func_qcaps_req(struct bnxt *bp)
Definition bnxt.c:886
bnxt_tx_complete
static void bnxt_tx_complete(struct net_device *dev, u16 hw_idx)
Definition bnxt.c:318
bnxt_link_evt
void bnxt_link_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2264
hwrm_init
static void hwrm_init(struct bnxt *bp, struct input *req, u16 cmd, u16 len)
Definition bnxt.c:658
bnxt_er_wait_timer
static void bnxt_er_wait_timer(struct retry_timer *timer, int over __unused)
Definition bnxt.c:2729
bnxt_up_nic
#define bnxt_up_nic(bp)
Definition bnxt.c:2163
bnxt_hwrm_port_phy_qcaps_req
static int bnxt_hwrm_port_phy_qcaps_req(struct bnxt *bp)
Definition bnxt.c:962
set_rx_mask
u32 set_rx_mask(u32 rx_mask)
Definition bnxt.c:1253
bnxt_hwrm_port_phy_qcfg
static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, u16 idx)
Definition bnxt.c:1287
bnxt_service_nq
static void bnxt_service_nq(struct net_device *dev)
Definition bnxt.c:2649
bnxt_hwrm_set_async_event
static int bnxt_hwrm_set_async_event(struct bnxt *bp)
Definition bnxt.c:1150
bnxt_hwrm_ring_free_rx
static int bnxt_hwrm_ring_free_rx(struct bnxt *bp)
Definition bnxt.c:1945
hwrm_write_req
static void hwrm_write_req(struct bnxt *bp, void *req, u32 cnt)
Definition bnxt.c:668
bnxt_get_phy_link
static int bnxt_get_phy_link(struct bnxt *bp)
Definition bnxt.c:1682
bnxt_rx_complete
static int bnxt_rx_complete(struct net_device *dev, struct rx_pkt_cmpl *rx)
Definition bnxt.c:491
bnxt_hwrm_ring_alloc
static int bnxt_hwrm_ring_alloc(struct bnxt *bp, u8 type)
Definition bnxt.c:1819
bnxt_hwrm_func_reset_req
static int bnxt_hwrm_func_reset_req(struct bnxt *bp)
Definition bnxt.c:986
bnxt_remove_one
static void bnxt_remove_one(struct pci_device *pci)
Definition bnxt.c:2851
bnxt_query_phy_link
static int bnxt_query_phy_link(struct bnxt *bp)
Definition bnxt.c:1649
bnxt_er_reg_write
u32 bnxt_er_reg_write(struct bnxt *bp, u32 reg_addr, u32 reg_val)
Definition bnxt.c:2280
dev_p5_db
static void dev_p5_db(struct bnxt *bp, u32 idx, u32 xid, u32 flag)
Definition bnxt.c:187
bnxt_hwrm_stat_ctx_alloc
static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
Definition bnxt.c:1707
bnxt_adv_cq_index
static void bnxt_adv_cq_index(struct bnxt *bp, u16 cnt)
Definition bnxt.c:452
bnxt_rx_drop
u8 bnxt_rx_drop(struct bnxt *bp, struct io_buffer *iob, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi, u16 rx_len)
Definition bnxt.c:411
bnxt_get_pkt_vlan
static u16 bnxt_get_pkt_vlan(char *src)
Definition bnxt.c:279
bnxt_free_hwrm_mem
void bnxt_free_hwrm_mem(struct bnxt *bp)
Definition bnxt.c:596
bnxt_process_reset_notify_event
void bnxt_process_reset_notify_event(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2505
bnxt_hwrm_run
int bnxt_hwrm_run(hwrm_func_t cmds[], struct bnxt *bp)
Definition bnxt.c:2143
DEFAULT_NUMBER_OF_STAT_CTXS
#define DEFAULT_NUMBER_OF_STAT_CTXS
Definition bnxt.h:145
LINK_SPEED_FW_40G
#define LINK_SPEED_FW_40G
Definition bnxt.h:309
MAX_CQ_DESC_CNT
#define MAX_CQ_DESC_CNT
Definition bnxt.h:149
LINK_SPEED_FW_1G
#define LINK_SPEED_FW_1G
Definition bnxt.h:303
SET_MEDIUM_SPEED
#define SET_MEDIUM_SPEED(bp, s)
Definition bnxt.h:117
STATUS_TIMEOUT
#define STATUS_TIMEOUT
Definition bnxt.h:79
PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM
#define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM
Definition bnxt.h:358
LINK_SPEED_FW_100G_PAM4
#define LINK_SPEED_FW_100G_PAM4
Definition bnxt.h:319
NQ_DMA_ADDR
#define NQ_DMA_ADDR(bp)
Definition bnxt.h:178
NQ_CN_TYPE_MASK
#define NQ_CN_TYPE_MASK
Definition bnxt.h:568
GET_MEDIUM_SPEED
#define GET_MEDIUM_SPEED(m)
Definition bnxt.h:116
MEDIUM_SPEED_25GBPS
#define MEDIUM_SPEED_25GBPS
Definition bnxt.h:101
CMPL_BASE_TYPE_TX_L2
#define CMPL_BASE_TYPE_TX_L2
Definition bnxt.h:522
IPXE_VERSION_UPDATE
#define IPXE_VERSION_UPDATE
Definition bnxt.h:33
STATUS_FAILURE
#define STATUS_FAILURE
Definition bnxt.h:56
VALID_RING_NQ
#define VALID_RING_NQ
Definition bnxt.h:908
RING_FREE
#define RING_FREE(bp, rid, flag)
Definition bnxt.h:1081
ETHERTYPE_VLAN
#define ETHERTYPE_VLAN
Definition bnxt.h:191
MEDIA_AUTO_DETECT_MASK
#define MEDIA_AUTO_DETECT_MASK
Definition bnxt.h:1090
STAT_CTX_ID
#define STAT_CTX_ID
Definition bnxt.h:175
D3_SPEED_FW_SHIFT
#define D3_SPEED_FW_SHIFT
Definition bnxt.h:1089
SET_MEDIUM_DUPLEX
#define SET_MEDIUM_DUPLEX(bp, d)
Definition bnxt.h:122
FW_STATUS_REG_CODE_READY
#define FW_STATUS_REG_CODE_READY
Definition bnxt.h:942
NQ_CN_TOGGLE_MASK
#define NQ_CN_TOGGLE_MASK
Definition bnxt.h:570
HWRM_CMD_DEFAULT_TIMEOUT
#define HWRM_CMD_DEFAULT_TIMEOUT
Definition bnxt.h:134
VALID_RING_GRP
#define VALID_RING_GRP
Definition bnxt.h:904
CHIP_NUM_57608
#define CHIP_NUM_57608
Definition bnxt.h:1106
PORT_PHY_FLAGS
#define PORT_PHY_FLAGS
Definition bnxt.h:1078
MEDIUM_SPEED_400PAM4_112GBPS
#define MEDIUM_SPEED_400PAM4_112GBPS
Definition bnxt.h:111
MEDIUM_SPEED_50PAM4GBPS
#define MEDIUM_SPEED_50PAM4GBPS
Definition bnxt.h:106
CMPL_BASE_TYPE_RX_L2_V3
#define CMPL_BASE_TYPE_RX_L2_V3
Definition bnxt.h:527
TX_RING_BUFFER_SIZE
#define TX_RING_BUFFER_SIZE
Definition bnxt.h:150
SERVICE_NEXT_NQ_BD
#define SERVICE_NEXT_NQ_BD
Definition bnxt.h:186
SHORT_CMD_SUPPORTED
#define SHORT_CMD_SUPPORTED
Definition bnxt.h:1062
RX_MASK
#define RX_MASK
Definition bnxt.h:168
STATUS_LINK_DOWN
#define STATUS_LINK_DOWN
Definition bnxt.h:60
BD_NOW
#define BD_NOW(bd, entry, len)
Definition bnxt.h:162
LINK_SPEED_DRV_NUM
#define LINK_SPEED_DRV_NUM
Definition bnxt.h:220
STATUS_LINK_ACTIVE
#define STATUS_LINK_ACTIVE
Definition bnxt.h:59
DEFAULT_NUMBER_OF_RING_GRPS
#define DEFAULT_NUMBER_OF_RING_GRPS
Definition bnxt.h:144
DB_OFFSET_VF
#define DB_OFFSET_VF
Definition bnxt.h:196
RX_PKT_V3_CMPL_TYPE_RX_L2_V3
#define RX_PKT_V3_CMPL_TYPE_RX_L2_V3
Definition bnxt.h:726
DMA_ALIGN_4K
#define DMA_ALIGN_4K
Definition bnxt.h:155
DEFAULT_NUMBER_OF_TX_RINGS
#define DEFAULT_NUMBER_OF_TX_RINGS
Definition bnxt.h:142
BNXT_CQ_INTR_MODE
#define BNXT_CQ_INTR_MODE(vf)
Definition bnxt.h:163
DBC_DBC_TYPE_SQ
#define DBC_DBC_TYPE_SQ
Definition bnxt.h:432
IPXE_VERSION_MINOR
#define IPXE_VERSION_MINOR
Definition bnxt.h:32
TX_BD_FLAGS
#define TX_BD_FLAGS
Definition bnxt.h:1073
LINK_SPEED_FW_AUTONEG
#define LINK_SPEED_FW_AUTONEG
Definition bnxt.h:301
FLAG_RESET
#define FLAG_RESET(f, b)
Definition bnxt.h:40
TX_BD_SHORT_FLAGS_LHINT_GTE2K
#define TX_BD_SHORT_FLAGS_LHINT_GTE2K
Definition bnxt.h:468
DBC_DBC_TYPE_SRQ
#define DBC_DBC_TYPE_SRQ
Definition bnxt.h:434
FLAG_TEST
#define FLAG_TEST(f, b)
Definition bnxt.h:39
RX_RING_BUFFER_SIZE
#define RX_RING_BUFFER_SIZE
Definition bnxt.h:151
DB_OFFSET_PF
#define DB_OFFSET_PF
Definition bnxt.h:195
MEDIUM_SPEED_200PAM4_112GBPS
#define MEDIUM_SPEED_200PAM4_112GBPS
Definition bnxt.h:109
RESP_BUFFER_SIZE
#define RESP_BUFFER_SIZE
Definition bnxt.h:157
SET_LINK
#define SET_LINK(p, m, s)
Definition bnxt.h:1082
RX_MASK_ACCEPT_ALL_MULTICAST
#define RX_MASK_ACCEPT_ALL_MULTICAST
Definition bnxt.h:86
NQ_RING_BUFFER_SIZE
#define NQ_RING_BUFFER_SIZE
Definition bnxt.h:173
FLAG_SET
#define FLAG_SET(f, b)
Definition bnxt.h:38
BNXT_RX_STD_DMA_SZ
#define BNXT_RX_STD_DMA_SZ
Definition bnxt.h:160
PHY_STATUS
#define PHY_STATUS
Definition bnxt.h:206
DBC_MSG_XID
#define DBC_MSG_XID(xid, flg)
Definition bnxt.h:199
VLAN_HDR_SIZE
#define VLAN_HDR_SIZE
Definition bnxt.h:190
LINK_SPEED_FW_10G
#define LINK_SPEED_FW_10G
Definition bnxt.h:305
TX_DOORBELL_KEY_TX
#define TX_DOORBELL_KEY_TX
Definition bnxt.h:384
MEDIUM_SPEED_100PAM4_112GBPS
#define MEDIUM_SPEED_100PAM4_112GBPS
Definition bnxt.h:108
RX_DMA_ADDR
#define RX_DMA_ADDR(bp)
Definition bnxt.h:181
REQ_BUFFER_SIZE
#define REQ_BUFFER_SIZE
Definition bnxt.h:156
MEDIUM_SPEED_400PAM4GBPS
#define MEDIUM_SPEED_400PAM4GBPS
Definition bnxt.h:110
RX_MASK_ACCEPT_MULTICAST
#define RX_MASK_ACCEPT_MULTICAST
Definition bnxt.h:85
CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
Definition bnxt.h:532
CMPL_BASE_TYPE_MASK
#define CMPL_BASE_TYPE_MASK
Definition bnxt.h:520
BNXT_ER_TIMER_INTERVAL
#define BNXT_ER_TIMER_INTERVAL(x)
Definition bnxt.h:1107
CQ_DOORBELL_KEY_IDX
#define CQ_DOORBELL_KEY_IDX(a)
Definition bnxt.h:1069
LINK_SPEED_FW_50G
#define LINK_SPEED_FW_50G
Definition bnxt.h:311
PCICFG_ME_REGISTER
#define PCICFG_ME_REGISTER
Definition bnxt.h:125
ER_DFLT_FW_RST_MAX_DSECS
#define ER_DFLT_FW_RST_MAX_DSECS
Definition bnxt.h:941
DMA_DMA_ADDR
#define DMA_DMA_ADDR(bp)
Definition bnxt.h:184
CQ_DMA_ADDR
#define CQ_DMA_ADDR(bp)
Definition bnxt.h:179
VALID_STAT_CTX
#define VALID_STAT_CTX
Definition bnxt.h:900
CMPL_BASE_TYPE_RX_L2
#define CMPL_BASE_TYPE_RX_L2
Definition bnxt.h:523
SPEED_DRV_SHIFT
#define SPEED_DRV_SHIFT
Definition bnxt.h:1085
LINK_SPEED_FW_MASK
#define LINK_SPEED_FW_MASK
Definition bnxt.h:299
MAX_ETHERNET_PACKET_BUFFER_SIZE
#define MAX_ETHERNET_PACKET_BUFFER_SIZE
Definition bnxt.h:140
CHIP_NUM_57502
#define CHIP_NUM_57502
Definition bnxt.h:1104
LINK_SPEED_FW_2_5G
#define LINK_SPEED_FW_2_5G
Definition bnxt.h:329
TX_BD_SHORT_FLAGS_LHINT_LT512
#define TX_BD_SHORT_FLAGS_LHINT_LT512
Definition bnxt.h:465
LINK_SPEED_FW_50G_PAM4
#define LINK_SPEED_FW_50G_PAM4
Definition bnxt.h:317
TX_BD_SHORT_FLAGS_LHINT_LT2K
#define TX_BD_SHORT_FLAGS_LHINT_LT2K
Definition bnxt.h:467
NO_MORE_CQ_BD_TO_SERVICE
#define NO_MORE_CQ_BD_TO_SERVICE
Definition bnxt.h:187
DEFAULT_NUMBER_OF_RX_RINGS
#define DEFAULT_NUMBER_OF_RX_RINGS
Definition bnxt.h:143
DETECT_MEDIA
#define DETECT_MEDIA
Definition bnxt.h:208
RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT
Definition bnxt.h:674
DBC_DBC_TYPE_CQ
#define DBC_DBC_TYPE_CQ
Definition bnxt.h:436
NUM_RX_BUFFERS
#define NUM_RX_BUFFERS
Definition bnxt.h:146
VALID_L2_FILTER
#define VALID_L2_FILTER
Definition bnxt.h:907
BNXT_FLAG_IS_CHIP_P5_PLUS
#define BNXT_FLAG_IS_CHIP_P5_PLUS
Definition bnxt.h:50
VALID_RING_RX
#define VALID_RING_RX
Definition bnxt.h:903
D3_LINK_SPEED_FW_NUM
#define D3_LINK_SPEED_FW_NUM
Definition bnxt.h:334
LINK_SPEED_FW_NUM
#define LINK_SPEED_FW_NUM
Definition bnxt.h:298
MEDIUM_SPEED_100GBPS
#define MEDIUM_SPEED_100GBPS
Definition bnxt.h:104
SUPPORT_SPEEDS
#define SUPPORT_SPEEDS
Definition bnxt.h:209
MEDIUM_FULL_DUPLEX
#define MEDIUM_FULL_DUPLEX
Definition bnxt.h:119
MAX_NQ_DESC_CNT
#define MAX_NQ_DESC_CNT
Definition bnxt.h:172
NQ_CN_TYPE_CQ_NOTIFICATION
#define NQ_CN_TYPE_CQ_NOTIFICATION
Definition bnxt.h:573
BNXT_FLAG_NPAR_MODE
#define BNXT_FLAG_NPAR_MODE
Definition bnxt.h:45
NO_MORE_NQ_BD_TO_SERVICE
#define NO_MORE_NQ_BD_TO_SERVICE
Definition bnxt.h:185
MEDIUM_SPEED_40GBPS
#define MEDIUM_SPEED_40GBPS
Definition bnxt.h:102
RX_PKT_CMPL_V2
#define RX_PKT_CMPL_V2
Definition bnxt.h:670
REQ_DMA_ADDR
#define REQ_DMA_ADDR(bp)
Definition bnxt.h:182
NEXT_IDX
#define NEXT_IDX(N, S)
Definition bnxt.h:161
TX_IN_USE
#define TX_IN_USE(a, b, c)
Definition bnxt.h:177
VF_CFG_ENABLE_FLAGS
#define VF_CFG_ENABLE_FLAGS
Definition bnxt.h:1096
LINK_POLL_WAIT_TIME
#define LINK_POLL_WAIT_TIME
Definition bnxt.h:167
DBC_MSG_EPCH
#define DBC_MSG_EPCH(idx)
Definition bnxt.h:202
RX_MASK_PROMISCUOUS_MODE
#define RX_MASK_PROMISCUOUS_MODE
Definition bnxt.h:89
BNXT_FLAG_RESOURCE_QCAPS_SUPPORT
#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT
Definition bnxt.h:43
SERVICE_NEXT_CQ_BD
#define SERVICE_NEXT_CQ_BD
Definition bnxt.h:188
RX_PKT_V3_CMPL_TYPE_MASK
#define RX_PKT_V3_CMPL_TYPE_MASK
Definition bnxt.h:718
VALID_RX_IOB
#define VALID_RX_IOB
Definition bnxt.h:906
SUPPORT_SPEEDS2
#define SUPPORT_SPEEDS2
Definition bnxt.h:210
BYTE_SWAP_S
#define BYTE_SWAP_S(w)
Definition bnxt.h:192
VALID_DRIVER_REG
#define VALID_DRIVER_REG
Definition bnxt.h:899
HWRM_CMD_FLASH_MULTIPLAYER
#define HWRM_CMD_FLASH_MULTIPLAYER(a)
Definition bnxt.h:137
SPEED_FW_SHIFT
#define SPEED_FW_SHIFT
Definition bnxt.h:1087
RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
Definition bnxt.h:870
TX_DMA_ADDR
#define TX_DMA_ADDR(bp)
Definition bnxt.h:180
CHIP_NUM_57504
#define CHIP_NUM_57504
Definition bnxt.h:1103
HWRM_CMD_WAIT
#define HWRM_CMD_WAIT(b)
Definition bnxt.h:139
RESP_DMA_ADDR
#define RESP_DMA_ADDR(bp)
Definition bnxt.h:183
DBC_MSG_TOGGLE
#define DBC_MSG_TOGGLE(idx)
Definition bnxt.h:204
SHORT_CMD_REQUIRED
#define SHORT_CMD_REQUIRED
Definition bnxt.h:1063
VALID_RING_TX
#define VALID_RING_TX
Definition bnxt.h:902
TX_BD_SHORT_FLAGS_LHINT_LT1K
#define TX_BD_SHORT_FLAGS_LHINT_LT1K
Definition bnxt.h:466
RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT
Definition bnxt.h:822
MEDIUM_SPEED_200GBPS
#define MEDIUM_SPEED_200GBPS
Definition bnxt.h:105
MEDIUM_SPEED_100PAM4GBPS
#define MEDIUM_SPEED_100PAM4GBPS
Definition bnxt.h:107
LINK_SPEED_FW_400G_PAM4
#define LINK_SPEED_FW_400G_PAM4
Definition bnxt.h:325
MEDIUM_SPEED_50GBPS
#define MEDIUM_SPEED_50GBPS
Definition bnxt.h:103
D3_SPEED_FW_MASK
#define D3_SPEED_FW_MASK
Definition bnxt.h:1088
HWRM_CMD_POLL_WAIT_TIME
#define HWRM_CMD_POLL_WAIT_TIME
Definition bnxt.h:135
LINK_SPEED_FW_100G
#define LINK_SPEED_FW_100G
Definition bnxt.h:313
LINK_SPEED_FW_200G
#define LINK_SPEED_FW_200G
Definition bnxt.h:315
BNXT_FLAG_PCI_VF
#define BNXT_FLAG_PCI_VF
Definition bnxt.h:47
VALID_VNIC_ID
#define VALID_VNIC_ID
Definition bnxt.h:905
SPEED_DRV_MASK
#define SPEED_DRV_MASK
Definition bnxt.h:1084
LINK_DEFAULT_TIMEOUT
#define LINK_DEFAULT_TIMEOUT
Definition bnxt.h:166
LINK_SPEED_FW_200G_PAM4_112
#define LINK_SPEED_FW_200G_PAM4_112
Definition bnxt.h:323
LINK_SPEED_FW_100G_PAM4_112
#define LINK_SPEED_FW_100G_PAM4_112
Definition bnxt.h:321
PHY_SPEED
#define PHY_SPEED
Definition bnxt.h:207
BNXT_FLAG_IS_CHIP_P5
#define BNXT_FLAG_IS_CHIP_P5
Definition bnxt.h:49
DBC_DBC_TYPE_NQ_ARM
#define DBC_DBC_TYPE_NQ_ARM
Definition bnxt.h:443
CMPL_BASE_V
#define CMPL_BASE_V
Definition bnxt.h:542
CQ_RING_BUFFER_SIZE
#define CQ_RING_BUFFER_SIZE
Definition bnxt.h:153
DMA_BUFFER_SIZE
#define DMA_BUFFER_SIZE
Definition bnxt.h:158
BNXT_FLAG_IS_CHIP_P7
#define BNXT_FLAG_IS_CHIP_P7
Definition bnxt.h:51
CMPL_DOORBELL_KEY_CMPL
#define CMPL_DOORBELL_KEY_CMPL
Definition bnxt.h:406
DBC_MSG_IDX
#define DBC_MSG_IDX(idx)
Definition bnxt.h:197
RX_DOORBELL_KEY_RX
#define RX_DOORBELL_KEY_RX
Definition bnxt.h:394
BNXT_FLAG_LINK_SPEEDS2
#define BNXT_FLAG_LINK_SPEEDS2
Definition bnxt.h:48
CMPL_BASE_TYPE_STAT_EJECT
#define CMPL_BASE_TYPE_STAT_EJECT
Definition bnxt.h:528
MEDIUM_SPEED_1000MBPS
#define MEDIUM_SPEED_1000MBPS
Definition bnxt.h:97
MEDIUM_SPEED_10GBPS
#define MEDIUM_SPEED_10GBPS
Definition bnxt.h:99
BNXT_DMA_ALIGNMENT
#define BNXT_DMA_ALIGNMENT
Definition bnxt.h:154
MEDIUM_SPEED_2500MBPS
#define MEDIUM_SPEED_2500MBPS
Definition bnxt.h:98
BNXT_FLAG_MULTI_HOST
#define BNXT_FLAG_MULTI_HOST
Definition bnxt.h:44
ER_DFLT_FW_RST_MIN_DSECS
#define ER_DFLT_FW_RST_MIN_DSECS
Definition bnxt.h:940
MEDIUM_SPEED_AUTONEG
#define MEDIUM_SPEED_AUTONEG
Definition bnxt.h:93
LINK_SPEED_FW_400G_PAM4_112
#define LINK_SPEED_FW_400G_PAM4_112
Definition bnxt.h:327
GRC_COM_CHAN_BASE
#define GRC_COM_CHAN_BASE
Definition bnxt.h:126
RX_MASK_ACCEPT_NONE
#define RX_MASK_ACCEPT_NONE
Definition bnxt.h:83
NQ_CN_TOGGLE_SFT
#define NQ_CN_TOGGLE_SFT
Definition bnxt.h:571
HWRM_CMD_DEFAULT_MULTIPLAYER
#define HWRM_CMD_DEFAULT_MULTIPLAYER(a)
Definition bnxt.h:136
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition bnxt.h:55
MAC_HDR_SIZE
#define MAC_HDR_SIZE
Definition bnxt.h:189
QCFG_PHY_ALL
#define QCFG_PHY_ALL
Definition bnxt.h:211
VALID_RING_CQ
#define VALID_RING_CQ
Definition bnxt.h:901
BNXT_FLAG_HWRM_SHORT_CMD_SUPP
#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP
Definition bnxt.h:41
LM_PAGE_BITS
#define LM_PAGE_BITS(a)
Definition bnxt.h:159
LINK_SPEED_FW_25G
#define LINK_SPEED_FW_25G
Definition bnxt.h:307
IPXE_VERSION_MAJOR
#define IPXE_VERSION_MAJOR
Definition bnxt.h:31
DEFAULT_NUMBER_OF_CMPL_RINGS
#define DEFAULT_NUMBER_OF_CMPL_RINGS
Definition bnxt.h:141
BNXT_ER_WAIT_TIMER_INTERVAL
#define BNXT_ER_WAIT_TIMER_INTERVAL(x)
Definition bnxt.h:1108
SPEED_FW_MASK
#define SPEED_FW_MASK
Definition bnxt.h:1086
NQ_CN_V
#define NQ_CN_V
Definition bnxt.h:587
TX_AVAIL
#define TX_AVAIL(r)
Definition bnxt.h:176
RX_RING_QID
#define RX_RING_QID
Definition bnxt.h:174
GRC_COM_CHAN_TRIG
#define GRC_COM_CHAN_TRIG
Definition bnxt.h:127
MEDIA_AUTO_DETECT_SHIFT
#define MEDIA_AUTO_DETECT_SHIFT
Definition bnxt.h:1091
CHIP_NUM_57508
#define CHIP_NUM_57508
Definition bnxt.h:1102
bnxt_dbg.h
dbg_rx_cid
#define dbg_rx_cid(idx, cid)
Definition bnxt_dbg.h:463
dump_evt
#define dump_evt(cq, ty, id, ring)
Definition bnxt_dbg.h:660
dbg_alloc_rx_iob_fail
#define dbg_alloc_rx_iob_fail(iob_idx, cons_id)
Definition bnxt_dbg.h:464
dbg_hw_cmd
#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err)
Definition bnxt_dbg.h:378
dbg_pci
#define dbg_pci(bp, func, creg)
Definition bnxt_dbg.h:140
dbg_alloc_rx_iob
#define dbg_alloc_rx_iob(iob, id, cid)
Definition bnxt_dbg.h:462
dbg_tx_avail
#define dbg_tx_avail(bp, a, u)
Definition bnxt_dbg.h:563
dbg_rx_stat
#define dbg_rx_stat(bp)
Definition bnxt_dbg.h:466
dbg_tx_done
#define dbg_tx_done(pkt, len, idx)
Definition bnxt_dbg.h:569
dbg_fw_ver
#define dbg_fw_ver(resp, tmo)
Definition bnxt_dbg.h:319
dbg_func_qcaps
#define dbg_func_qcaps(bp)
Definition bnxt_dbg.h:321
dump_cq
#define dump_cq(cq, id, toggle)
Definition bnxt_dbg.h:508
dbg_link_state
#define dbg_link_state(bp, tmo)
Definition bnxt_dbg.h:663
dbg_tx_vlan
#define dbg_tx_vlan(bp, src, plen, len)
Definition bnxt_dbg.h:564
dbg_func_qcfg
#define dbg_func_qcfg(bp)
Definition bnxt_dbg.h:322
prn_set_speed
#define prn_set_speed(speed)
Definition bnxt_dbg.h:323
dbg_mem
#define dbg_mem(bp, func)
Definition bnxt_dbg.h:175
dbg_rxp
#define dbg_rxp(iob, rx_len, drop)
Definition bnxt_dbg.h:465
dbg_link_info
#define dbg_link_info(bp)
Definition bnxt_dbg.h:662
dbg_flags
#define dbg_flags(func, flags)
Definition bnxt_dbg.h:326
dbg_func_resource_qcaps
#define dbg_func_resource_qcaps(bp)
Definition bnxt_dbg.h:320
dbg_short_cmd
#define dbg_short_cmd(sreq, func, len)
Definition bnxt_dbg.h:398
dbg_link_status
#define dbg_link_status(bp)
Definition bnxt_dbg.h:661
dbg_num_rings
#define dbg_num_rings(bp)
Definition bnxt_dbg.h:325
dump_tx_pkt
#define dump_tx_pkt(pkt, len, idx)
Definition bnxt_dbg.h:567
dump_rx_bd
#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
Definition bnxt_dbg.h:461
dump_tx_stat
#define dump_tx_stat(bp)
Definition bnxt_dbg.h:566
dump_nq
#define dump_nq(nq, id)
Definition bnxt_dbg.h:509
dbg_chip_info
#define dbg_chip_info(bp)
Definition bnxt_dbg.h:324
ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_SUPPORTED_LINK_SPEEDS_CHANGE
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_SUPPORTED_LINK_SPEEDS_CHANGE
Definition bnxt_hsi.h:786
ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC
#define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC
Definition bnxt_hsi.h:588
HWRM_VNIC_FREE
#define HWRM_VNIC_FREE
Definition bnxt_hsi.h:150
VNIC_ALLOC_REQ_FLAGS_DEFAULT
#define VNIC_ALLOC_REQ_FLAGS_DEFAULT
Definition bnxt_hsi.h:5769
ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE
Definition bnxt_hsi.h:664
CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT
Definition bnxt_hsi.h:6562
ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
Definition bnxt_hsi.h:560
PORT_MAC_CFG_REQ_LPBK_NONE
#define PORT_MAC_CFG_REQ_LPBK_NONE
Definition bnxt_hsi.h:3646
PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
Definition bnxt_hsi.h:3110
FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
Definition bnxt_hsi.h:1556
PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB
Definition bnxt_hsi.h:3168
ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY
Definition bnxt_hsi.h:563
HWRM_RING_ALLOC
#define HWRM_RING_ALLOC
Definition bnxt_hsi.h:160
FUNC_CFG_REQ_ENABLES_NUM_MSIX
#define FUNC_CFG_REQ_ENABLES_NUM_MSIX
Definition bnxt_hsi.h:1558
ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1753
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
Definition bnxt_hsi.h:3186
PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2
Definition bnxt_hsi.h:3080
PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
Definition bnxt_hsi.h:3042
ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_FEC_CFG_CHANGE
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_FEC_CFG_CHANGE
Definition bnxt_hsi.h:810
ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1
Definition bnxt_hsi.h:1758
HWRM_RING_FREE
#define HWRM_RING_FREE
Definition bnxt_hsi.h:161
ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG
Definition bnxt_hsi.h:1755
HWRM_VERSION_MINOR
#define HWRM_VERSION_MINOR
Definition bnxt_hsi.h:370
HWRM_MAX_REQ_LEN
#define HWRM_MAX_REQ_LEN
Definition bnxt_hsi.h:364
HWRM_CFA_L2_FILTER_FREE
#define HWRM_CFA_L2_FILTER_FREE
Definition bnxt_hsi.h:173
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
Definition bnxt_hsi.h:3190
PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
Definition bnxt_hsi.h:3068
RING_FREE_REQ_RING_TYPE_NQ
#define RING_FREE_REQ_RING_TYPE_NQ
Definition bnxt_hsi.h:6301
HWRM_PORT_PHY_CFG
#define HWRM_PORT_PHY_CFG
Definition bnxt_hsi.h:119
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
Definition bnxt_hsi.h:3191
CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
Definition bnxt_hsi.h:6683
FUNC_QCFG_RESP_FLAGS_MULTI_HOST
#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST
Definition bnxt_hsi.h:1417
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
Definition bnxt_hsi.h:3188
HWRM_VNIC_ALLOC
#define HWRM_VNIC_ALLOC
Definition bnxt_hsi.h:149
ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE
Definition bnxt_hsi.h:561
ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PAUSE_CFG_CHANGE
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_PAUSE_CFG_CHANGE
Definition bnxt_hsi.h:812
RING_ALLOC_REQ_INT_MODE_POLL
#define RING_ALLOC_REQ_INT_MODE_POLL
Definition bnxt_hsi.h:6270
HWRM_PORT_PHY_QCAPS
#define HWRM_PORT_PHY_QCAPS
Definition bnxt_hsi.h:129
HWRM_VNIC_CFG
#define HWRM_VNIC_CFG
Definition bnxt_hsi.h:151
ER_QCFG_RESET_REG_ADDR_MASK
#define ER_QCFG_RESET_REG_ADDR_MASK
Definition bnxt_hsi.h:1803
RING_ALLOC_REQ_RING_TYPE_RX
#define RING_ALLOC_REQ_RING_TYPE_RX
Definition bnxt_hsi.h:6216
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB
Definition bnxt_hsi.h:3184
ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK
#define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK
Definition bnxt_hsi.h:591
ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
Definition bnxt_hsi.h:562
CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
Definition bnxt_hsi.h:6530
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
Definition bnxt_hsi.h:3187
HWRM_FUNC_RESOURCE_QCAPS
#define HWRM_FUNC_RESOURCE_QCAPS
Definition bnxt_hsi.h:281
VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
Definition bnxt_hsi.h:5821
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB
Definition bnxt_hsi.h:3090
ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED
#define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED
Definition bnxt_hsi.h:589
ER_QCFG_FW_HEALTH_REG_ADDR_MASK
#define ER_QCFG_FW_HEALTH_REG_ADDR_MASK
Definition bnxt_hsi.h:1760
FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS
#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS
Definition bnxt_hsi.h:1542
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB
Definition bnxt_hsi.h:3085
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB
Definition bnxt_hsi.h:3091
PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
Definition bnxt_hsi.h:3111
ER_QCFG_FW_HB_REG_ADDR_MASK
#define ER_QCFG_FW_HB_REG_ADDR_MASK
Definition bnxt_hsi.h:1770
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB
Definition bnxt_hsi.h:3183
HWRM_FUNC_QCAPS
#define HWRM_FUNC_QCAPS
Definition bnxt_hsi.h:108
VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID
#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID
Definition bnxt_hsi.h:5827
RING_FREE_REQ_RING_TYPE_L2_CMPL
#define RING_FREE_REQ_RING_TYPE_L2_CMPL
Definition bnxt_hsi.h:6296
FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT
#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT
Definition bnxt_hsi.h:1835
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
Definition bnxt_hsi.h:3189
SHORT_REQ_SIGNATURE_SHORT_CMD
#define SHORT_REQ_SIGNATURE_SHORT_CMD
Definition bnxt_hsi.h:88
FUNC_CFG_REQ_EVB_MODE_NO_EVB
#define FUNC_CFG_REQ_EVB_MODE_NO_EVB
Definition bnxt_hsi.h:1614
PORT_PHY_QCFG_RESP_LINK_LINK
#define PORT_PHY_QCFG_RESP_LINK_LINK
Definition bnxt_hsi.h:3251
FUNC_DRV_RGTR_REQ_ENABLES_VER
#define FUNC_DRV_RGTR_REQ_ENABLES_VER
Definition bnxt_hsi.h:1838
HWRM_CFA_L2_SET_RX_MASK
#define HWRM_CFA_L2_SET_RX_MASK
Definition bnxt_hsi.h:175
FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN
#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN
Definition bnxt_hsi.h:1889
CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
Definition bnxt_hsi.h:6521
FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE
#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE
Definition bnxt_hsi.h:2162
HWRM_NVM_GET_VARIABLE
#define HWRM_NVM_GET_VARIABLE
Definition bnxt_hsi.h:309
FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME
Definition bnxt_hsi.h:1181
HWRM_FUNC_QCFG
#define HWRM_FUNC_QCFG
Definition bnxt_hsi.h:109
HWRM_FUNC_BACKING_STORE_QCFG
#define HWRM_FUNC_BACKING_STORE_QCFG
Definition bnxt_hsi.h:285
FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
Definition bnxt_hsi.h:1433
HWRM_RING_GRP_ALLOC
#define HWRM_RING_GRP_ALLOC
Definition bnxt_hsi.h:166
CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
Definition bnxt_hsi.h:6681
RING_ALLOC_REQ_RING_TYPE_NQ
#define RING_ALLOC_REQ_RING_TYPE_NQ
Definition bnxt_hsi.h:6219
HWRM_QUEUE_QPORTCFG
#define HWRM_QUEUE_QPORTCFG
Definition bnxt_hsi.h:135
HWRM_FUNC_DRV_UNRGTR
#define HWRM_FUNC_DRV_UNRGTR
Definition bnxt_hsi.h:113
PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
Definition bnxt_hsi.h:3069
HWRM_VER_GET
#define HWRM_VER_GET
Definition bnxt_hsi.h:98
PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
Definition bnxt_hsi.h:3071
PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
Definition bnxt_hsi.h:3067
CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
Definition bnxt_hsi.h:6684
HWRM_FUNC_DRV_RGTR
#define HWRM_FUNC_DRV_RGTR
Definition bnxt_hsi.h:116
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
Definition bnxt_hsi.h:3192
HWRM_PORT_MAC_CFG
#define HWRM_PORT_MAC_CFG
Definition bnxt_hsi.h:120
HWRM_VERSION_MAJOR
#define HWRM_VERSION_MAJOR
Definition bnxt_hsi.h:369
ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EEE_CFG_CHANGE
#define ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EEE_CFG_CHANGE
Definition bnxt_hsi.h:811
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB
Definition bnxt_hsi.h:3093
ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK
#define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1783
RING_FREE_REQ_RING_TYPE_TX
#define RING_FREE_REQ_RING_TYPE_TX
Definition bnxt_hsi.h:6297
RING_ALLOC_REQ_RING_TYPE_TX
#define RING_ALLOC_REQ_RING_TYPE_TX
Definition bnxt_hsi.h:6215
PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
Definition bnxt_hsi.h:3170
FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
Definition bnxt_hsi.h:1841
HWRM_FUNC_VF_CFG
#define HWRM_FUNC_VF_CFG
Definition bnxt_hsi.h:102
FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
Definition bnxt_hsi.h:1551
FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER
#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER
Definition bnxt_hsi.h:1844
CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
Definition bnxt_hsi.h:6517
FUNC_CFG_REQ_ENABLES_EVB_MODE
#define FUNC_CFG_REQ_ENABLES_EVB_MODE
Definition bnxt_hsi.h:1554
ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC
Definition bnxt_hsi.h:1756
FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT
Definition bnxt_hsi.h:1834
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB
Definition bnxt_hsi.h:3181
PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
Definition bnxt_hsi.h:3107
HWRM_VERSION_UPDATE
#define HWRM_VERSION_UPDATE
Definition bnxt_hsi.h:371
RING_ALLOC_REQ_RING_TYPE_L2_CMPL
#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL
Definition bnxt_hsi.h:6214
HWRM_PORT_PHY_QCFG
#define HWRM_PORT_PHY_QCFG
Definition bnxt_hsi.h:126
FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
Definition bnxt_hsi.h:1545
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB
Definition bnxt_hsi.h:3092
HWRM_CFA_L2_FILTER_ALLOC
#define HWRM_CFA_L2_FILTER_ALLOC
Definition bnxt_hsi.h:172
ER_QCFG_RESET_INPRG_REG_ADDR_MASK
#define ER_QCFG_RESET_INPRG_REG_ADDR_MASK
Definition bnxt_hsi.h:1790
HWRM_ER_QCFG
#define HWRM_ER_QCFG
Definition bnxt_hsi.h:99
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB
Definition bnxt_hsi.h:3182
FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE
#define FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE
Definition bnxt_hsi.h:1366
PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK
Definition bnxt_hsi.h:3081
ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK
Definition bnxt_hsi.h:665
ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_ILLEGAL_LINK_SPEED_CFG
#define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_ILLEGAL_LINK_SPEED_CFG
Definition bnxt_hsi.h:787
ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
Definition bnxt_hsi.h:554
HWRM_FUNC_BACKING_STORE_CFG
#define HWRM_FUNC_BACKING_STORE_CFG
Definition bnxt_hsi.h:284
FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE
Definition bnxt_hsi.h:1831
HWRM_NA_SIGNATURE
#define HWRM_NA_SIGNATURE
Definition bnxt_hsi.h:363
VNIC_CFG_REQ_ENABLES_MRU
#define VNIC_CFG_REQ_ENABLES_MRU
Definition bnxt_hsi.h:5825
ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK
#define ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1763
CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
Definition bnxt_hsi.h:6529
VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID
#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID
Definition bnxt_hsi.h:5826
PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
Definition bnxt_hsi.h:3102
PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED
Definition bnxt_hsi.h:3078
CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
Definition bnxt_hsi.h:6682
FUNC_CFG_REQ_ENABLES_NUM_VNICS
#define FUNC_CFG_REQ_ENABLES_NUM_VNICS
Definition bnxt_hsi.h:1544
ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK
#define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1808
PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB
Definition bnxt_hsi.h:3185
ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL
#define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL
Definition bnxt_hsi.h:590
PORT_PHY_CFG_REQ_FLAGS_FORCE
#define PORT_PHY_CFG_REQ_FLAGS_FORCE
Definition bnxt_hsi.h:3044
RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID
Definition bnxt_hsi.h:6211
ER_QCFG_RESET_REG_ADDR_SPACE_MASK
#define ER_QCFG_RESET_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1796
RING_FREE_REQ_RING_TYPE_RX
#define RING_FREE_REQ_RING_TYPE_RX
Definition bnxt_hsi.h:6298
FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
Definition bnxt_hsi.h:1541
ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK
#define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1773
CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
Definition bnxt_hsi.h:6544
HWRM_STAT_CTX_ALLOC
#define HWRM_STAT_CTX_ALLOC
Definition bnxt_hsi.h:191
PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED
#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED
Definition bnxt_hsi.h:4237
FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
Definition bnxt_hsi.h:1540
PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB
Definition bnxt_hsi.h:3169
HWRM_FUNC_RESET
#define HWRM_FUNC_RESET
Definition bnxt_hsi.h:104
ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0
Definition bnxt_hsi.h:1757
ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE
Definition bnxt_hsi.h:556
ER_QCFG_RCVRY_CNT_REG_ADDR_MASK
#define ER_QCFG_RCVRY_CNT_REG_ADDR_MASK
Definition bnxt_hsi.h:1815
HWRM_FUNC_CFG
#define HWRM_FUNC_CFG
Definition bnxt_hsi.h:110
FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
Definition bnxt_hsi.h:1837
HWRM_STAT_CTX_FREE
#define HWRM_STAT_CTX_FREE
Definition bnxt_hsi.h:192
HWRM_RING_GRP_FREE
#define HWRM_RING_GRP_FREE
Definition bnxt_hsi.h:167
ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK
#define ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK
Definition bnxt_hsi.h:1780
RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
Definition bnxt_hsi.h:6212
PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB
Definition bnxt_hsi.h:3088
done
struct bofm_section_header done
Definition bofm_test.c:46
len
ring len
Length.
Definition dwmac.h:226
ARRAY_SIZE
#define ARRAY_SIZE(x)
Definition efx_common.h:43
type
uint32_t type
Operating system type.
Definition ena.h:1
flags
uint8_t flags
Flags.
Definition ena.h:7
desc
struct ena_llq_option desc
Descriptor counts.
Definition ena.h:9
errno.h
Error codes.
alloc_etherdev
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition ethernet.c:265
ethernet.h
Ethernet protocol.
is_valid_ether_addr
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition ethernet.h:78
netdev
static struct net_device * netdev
Definition gdbudp.c:53
__unused
#define __unused
Declare a variable or data structure as unused.
Definition compiler.h:573
DBGP
#define DBGP(...)
Definition compiler.h:532
FILE_LICENCE
#define FILE_LICENCE(_licence)
Declare a particular licence as applying to a file.
Definition compiler.h:896
EINVAL
#define EINVAL
Invalid argument.
Definition errno.h:429
ENOMEM
#define ENOMEM
Not enough space.
Definition errno.h:535
EBUSY
#define EBUSY
Device or resource busy.
Definition errno.h:339
ENOBUFS
#define ENOBUFS
No buffer space available.
Definition errno.h:499
if_ether.h
ETH_ALEN
#define ETH_ALEN
Definition if_ether.h:9
u8
#define u8
Definition igbvf_osdep.h:40
barrier
#define barrier()
Optimisation barrier.
Definition compiler.h:633
mb
void mb(void)
Memory barrier.
writeq
#define writeq(data, io_addr)
Definition io.h:273
iounmap
void iounmap(volatile const void *io_addr)
Unmap I/O address.
pci_read_config_dword
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.
pci_read_config_word
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
pci_ioremap
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
pci_write_config_word
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
pci_read_config_byte
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
pci_write_config_dword
int pci_write_config_dword(struct pci_device *pci, unsigned int where, uint32_t value)
Write 32-bit dword to PCI configuration space.
timer.h
iPXE timers
val
void __asmcall int val
Definition setjmp.h:12
u64
uint64_t u64
Definition stdint.h:26
string.h
String functions.
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
memset
void * memset(void *dest, int character, size_t len) __nonnull
memmove
void * memmove(void *dest, const void *src, size_t len) __nonnull
alloc_rx_iob
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition iobuf.c:188
free_rx_iob
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition iobuf.c:215
iobuf.h
I/O buffers.
iob_put
#define iob_put(iobuf, len)
Definition iobuf.h:125
iob_dma
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition iobuf.h:268
iob_len
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition iobuf.h:160
dma.h
DMA mappings.
dma_free
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.
dma_alloc
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.
malloc.h
Dynamic memory allocation.
mii.h
Media Independent Interface constants.
reg
static unsigned int unsigned int reg
Definition myson.h:162
netdev_link_down
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition netdevice.c:231
netdev_rx
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition netdevice.c:549
unregister_netdev
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition netdevice.c:946
netdev_rx_err
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition netdevice.c:587
register_netdev
int register_netdev(struct net_device *netdev)
Register network device.
Definition netdevice.c:760
netdevice.h
Network device management.
netdev_link_up
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition netdevice.h:792
netdev_init
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition netdevice.h:522
netdev_nullify
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition netdevice.h:535
netdev_put
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition netdevice.h:579
netdev_tx_complete
static void netdev_tx_complete(struct net_device *netdev, struct io_buffer *iobuf)
Complete network transmission.
Definition netdevice.h:770
pci_bar_size
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Get the size of a PCI BAR.
Definition pci.c:164
adjust_pci_device
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition pci.c:241
pci_bar_start
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition pci.c:97
pci.h
PCI bus.
__pci_driver
#define __pci_driver
Declare a PCI driver.
Definition pci.h:278
PCI_SUBSYSTEM_ID
#define PCI_SUBSYSTEM_ID
PCI subsystem ID.
Definition pci.h:79
PCI_COMMAND_MASTER
#define PCI_COMMAND_MASTER
Bus master.
Definition pci.h:29
PCI_BASE_ADDRESS_2
#define PCI_BASE_ADDRESS_2
Definition pci.h:65
pci_set_drvdata
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition pci.h:366
PCI_ROM
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition pci.h:308
PCI_COMMAND_INTX_DISABLE
#define PCI_COMMAND_INTX_DISABLE
Interrupt disable.
Definition pci.h:33
PCI_BASE_ADDRESS_0
#define PCI_BASE_ADDRESS_0
Definition pci.h:63
pci_get_drvdata
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition pci.h:376
PCI_COMMAND
#define PCI_COMMAND
PCI command.
Definition pci.h:26
PCI_BASE_ADDRESS_4
#define PCI_BASE_ADDRESS_4
Definition pci.h:67
PCI_SUBSYSTEM_VENDOR_ID
#define PCI_SUBSYSTEM_VENDOR_ID
PCI subsystem vendor ID.
Definition pci.h:76
bp
uint16_t bp
Definition registers.h:9
start_timer_fixed
void start_timer_fixed(struct retry_timer *timer, unsigned long timeout)
Start timer with a specified timeout.
Definition retry.c:65
stop_timer
void stop_timer(struct retry_timer *timer)
Stop timer.
Definition retry.c:118
container_of
#define container_of(ptr, type, field)
Get containing structure.
Definition stddef.h:36
bnxt
Definition bnxt.h:949
bnxt::wait_timer
struct retry_timer wait_timer
Definition bnxt.h:987
bnxt::dev
struct net_device * dev
Definition bnxt.h:967
bnxt::task_timer
struct retry_timer task_timer
Definition bnxt.h:986
cmpl_base
Definition bnxt.h:518
cmpl_base::type
u16 type
Definition bnxt.h:519
cmpl_base::info3_v
u32 info3_v
Definition bnxt.h:541
hwrm_async_event_cmpl
Definition bnxt_hsi.h:547
hwrm_async_event_cmpl::event_id
__le16 event_id
Definition bnxt_hsi.h:553
hwrm_async_event_cmpl::event_data1
__le32 event_data1
Definition bnxt_hsi.h:587
hwrm_async_event_cmpl::timestamp_hi
__le16 timestamp_hi
Definition bnxt_hsi.h:586
hwrm_async_event_cmpl::timestamp_lo
u8 timestamp_lo
Definition bnxt_hsi.h:585
hwrm_cfa_l2_filter_alloc_input
Definition bnxt_hsi.h:6508
hwrm_cfa_l2_filter_alloc_input::t_l2_addr_mask
u8 t_l2_addr_mask[6]
Definition bnxt_hsi.h:6556
hwrm_cfa_l2_filter_alloc_input::src_type
u8 src_type
Definition bnxt_hsi.h:6561
hwrm_cfa_l2_filter_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:6528
hwrm_cfa_l2_filter_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:6514
hwrm_cfa_l2_filter_alloc_input::t_l2_addr
u8 t_l2_addr[6]
Definition bnxt_hsi.h:6554
hwrm_cfa_l2_filter_alloc_input::dst_id
__le16 dst_id
Definition bnxt_hsi.h:6589
hwrm_cfa_l2_filter_alloc_input::l2_addr
u8 l2_addr[6]
Definition bnxt_hsi.h:6546
hwrm_cfa_l2_filter_alloc_input::src_id
__le32 src_id
Definition bnxt_hsi.h:6572
hwrm_cfa_l2_filter_alloc_input::l2_addr_mask
u8 l2_addr_mask[6]
Definition bnxt_hsi.h:6548
hwrm_cfa_l2_filter_alloc_output
Definition bnxt_hsi.h:6604
hwrm_cfa_l2_filter_alloc_output::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6609
hwrm_cfa_l2_filter_free_input
Definition bnxt_hsi.h:6616
hwrm_cfa_l2_filter_free_input::l2_filter_id
__le64 l2_filter_id
Definition bnxt_hsi.h:6622
hwrm_cfa_l2_set_rx_mask_input
Definition bnxt_hsi.h:6673
hwrm_cfa_l2_set_rx_mask_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:6679
hwrm_cfa_l2_set_rx_mask_input::mask
__le32 mask
Definition bnxt_hsi.h:6680
hwrm_error_recovery_qcfg_input
Definition bnxt_hsi.h:1729
hwrm_error_recovery_qcfg_output
Definition bnxt_hsi.h:1739
hwrm_error_recovery_qcfg_output::reset_inprogress_reg_mask
__le32 reset_inprogress_reg_mask
Definition bnxt_hsi.h:1792
hwrm_error_recovery_qcfg_output::delay_after_reset
u8 delay_after_reset[16]
Definition bnxt_hsi.h:1806
hwrm_error_recovery_qcfg_output::reset_reg_val
__le32 reset_reg_val[16]
Definition bnxt_hsi.h:1805
hwrm_error_recovery_qcfg_output::normal_wait_period
__le32 normal_wait_period
Definition bnxt_hsi.h:1749
hwrm_error_recovery_qcfg_output::master_wait_period
__le32 master_wait_period
Definition bnxt_hsi.h:1748
hwrm_error_recovery_qcfg_output::fw_heartbeat_reg
__le32 fw_heartbeat_reg
Definition bnxt_hsi.h:1762
hwrm_error_recovery_qcfg_output::master_wait_post_reset
__le32 master_wait_post_reset
Definition bnxt_hsi.h:1750
hwrm_error_recovery_qcfg_output::driver_polling_freq
__le32 driver_polling_freq
Definition bnxt_hsi.h:1747
hwrm_error_recovery_qcfg_output::fw_health_status_reg
__le32 fw_health_status_reg
Definition bnxt_hsi.h:1752
hwrm_error_recovery_qcfg_output::fw_reset_cnt_reg
__le32 fw_reset_cnt_reg
Definition bnxt_hsi.h:1772
hwrm_error_recovery_qcfg_output::err_recovery_cnt_reg
__le32 err_recovery_cnt_reg
Definition bnxt_hsi.h:1807
hwrm_error_recovery_qcfg_output::max_bailout_time
__le32 max_bailout_time
Definition bnxt_hsi.h:1751
hwrm_error_recovery_qcfg_output::flags
__le32 flags
Definition bnxt_hsi.h:1744
hwrm_error_recovery_qcfg_output::reset_reg
__le32 reset_reg[16]
Definition bnxt_hsi.h:1795
hwrm_error_recovery_qcfg_output::reg_array_cnt
u8 reg_array_cnt
Definition bnxt_hsi.h:1794
hwrm_error_recovery_qcfg_output::reset_inprogress_reg
__le32 reset_inprogress_reg
Definition bnxt_hsi.h:1782
hwrm_func_backing_store_cfg_input
Definition bnxt_hsi.h:2155
hwrm_func_backing_store_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:2161
hwrm_func_backing_store_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:2163
hwrm_func_backing_store_qcfg_input
Definition bnxt_hsi.h:2494
hwrm_func_cfg_input
Definition bnxt_hsi.h:1509
hwrm_func_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:1536
hwrm_func_cfg_input::fid
__le16 fid
Definition bnxt_hsi.h:1515
hwrm_func_cfg_input::num_tx_rings
__le16 num_tx_rings
Definition bnxt_hsi.h:1564
hwrm_func_cfg_input::num_cmpl_rings
__le16 num_cmpl_rings
Definition bnxt_hsi.h:1563
hwrm_func_cfg_input::num_stat_ctxs
__le16 num_stat_ctxs
Definition bnxt_hsi.h:1568
hwrm_func_cfg_input::num_msix
__le16 num_msix
Definition bnxt_hsi.h:1516
hwrm_func_cfg_input::num_hw_ring_grps
__le16 num_hw_ring_grps
Definition bnxt_hsi.h:1569
hwrm_func_cfg_input::num_vnics
__le16 num_vnics
Definition bnxt_hsi.h:1567
hwrm_func_cfg_input::num_rx_rings
__le16 num_rx_rings
Definition bnxt_hsi.h:1565
hwrm_func_cfg_input::evb_mode
u8 evb_mode
Definition bnxt_hsi.h:1613
hwrm_func_cfg_input::async_event_cr
__le16 async_event_cr
Definition bnxt_hsi.h:1605
hwrm_func_drv_rgtr_input
Definition bnxt_hsi.h:1822
hwrm_func_drv_rgtr_input::flags
__le32 flags
Definition bnxt_hsi.h:1828
hwrm_func_drv_rgtr_input::ver_maj
__le16 ver_maj
Definition bnxt_hsi.h:1863
hwrm_func_drv_rgtr_input::ver_min
__le16 ver_min
Definition bnxt_hsi.h:1864
hwrm_func_drv_rgtr_input::os_type
__le16 os_type
Definition bnxt_hsi.h:1842
hwrm_func_drv_rgtr_input::ver_upd
__le16 ver_upd
Definition bnxt_hsi.h:1865
hwrm_func_drv_rgtr_input::async_event_fwd
__le32 async_event_fwd[8]
Definition bnxt_hsi.h:1862
hwrm_func_drv_rgtr_input::enables
__le32 enables
Definition bnxt_hsi.h:1836
hwrm_func_drv_unrgtr_input
Definition bnxt_hsi.h:1882
hwrm_func_drv_unrgtr_input::flags
__le32 flags
Definition bnxt_hsi.h:1888
hwrm_func_qcaps_input
Definition bnxt_hsi.h:1324
hwrm_func_qcaps_input::fid
__le16 fid
Definition bnxt_hsi.h:1330
hwrm_func_qcaps_output
Definition bnxt_hsi.h:1335
hwrm_func_qcaps_output::fid
__le16 fid
Definition bnxt_hsi.h:1340
hwrm_func_qcaps_output::port_id
__le16 port_id
Definition bnxt_hsi.h:1341
hwrm_func_qcaps_output::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:1367
hwrm_func_qcaps_output::flags
__le32 flags
Definition bnxt_hsi.h:1342
hwrm_func_qcfg_input
Definition bnxt_hsi.h:1392
hwrm_func_qcfg_input::fid
__le16 fid
Definition bnxt_hsi.h:1398
hwrm_func_qcfg_output
Definition bnxt_hsi.h:1403
hwrm_func_qcfg_output::port_id
__le16 port_id
Definition bnxt_hsi.h:1409
hwrm_func_qcfg_output::port_partition_type
u8 port_partition_type
Definition bnxt_hsi.h:1430
hwrm_func_qcfg_output::fid
__le16 fid
Definition bnxt_hsi.h:1408
hwrm_func_qcfg_output::mac_address
u8 mac_address[6]
Definition bnxt_hsi.h:1419
hwrm_func_qcfg_output::stat_ctx_id
__le16 stat_ctx_id
Definition bnxt_hsi.h:1429
hwrm_func_qcfg_output::pci_id
__le16 pci_id
Definition bnxt_hsi.h:1420
hwrm_func_qcfg_output::vlan
__le16 vlan
Definition bnxt_hsi.h:1410
hwrm_func_qcfg_output::flags
__le16 flags
Definition bnxt_hsi.h:1411
hwrm_func_reset_input
Definition bnxt_hsi.h:1170
hwrm_func_reset_input::func_reset_level
u8 func_reset_level
Definition bnxt_hsi.h:1179
hwrm_func_resource_qcaps_input
Definition bnxt_hsi.h:2018
hwrm_func_resource_qcaps_input::fid
__le16 fid
Definition bnxt_hsi.h:2024
hwrm_func_resource_qcaps_output
Definition bnxt_hsi.h:2029
hwrm_func_resource_qcaps_output::min_cmpl_rings
__le16 min_cmpl_rings
Definition bnxt_hsi.h:2043
hwrm_func_resource_qcaps_output::min_rx_rings
__le16 min_rx_rings
Definition bnxt_hsi.h:2047
hwrm_func_resource_qcaps_output::min_tx_rings
__le16 min_tx_rings
Definition bnxt_hsi.h:2045
hwrm_func_resource_qcaps_output::max_vfs
__le16 max_vfs
Definition bnxt_hsi.h:2034
hwrm_func_resource_qcaps_output::max_vnics
__le16 max_vnics
Definition bnxt_hsi.h:2052
hwrm_func_resource_qcaps_output::min_hw_ring_grps
__le16 min_hw_ring_grps
Definition bnxt_hsi.h:2055
hwrm_func_resource_qcaps_output::max_l2_ctxs
__le16 max_l2_ctxs
Definition bnxt_hsi.h:2050
hwrm_func_resource_qcaps_output::min_rsscos_ctx
__le16 min_rsscos_ctx
Definition bnxt_hsi.h:2041
hwrm_func_resource_qcaps_output::min_stat_ctx
__le16 min_stat_ctx
Definition bnxt_hsi.h:2053
hwrm_func_resource_qcaps_output::max_rx_rings
__le16 max_rx_rings
Definition bnxt_hsi.h:2048
hwrm_func_resource_qcaps_output::max_msix
__le16 max_msix
Definition bnxt_hsi.h:2035
hwrm_func_resource_qcaps_output::max_hw_ring_grps
__le16 max_hw_ring_grps
Definition bnxt_hsi.h:2056
hwrm_func_resource_qcaps_output::min_vnics
__le16 min_vnics
Definition bnxt_hsi.h:2051
hwrm_func_resource_qcaps_output::vf_reservation_strategy
__le16 vf_reservation_strategy
Definition bnxt_hsi.h:2036
hwrm_func_resource_qcaps_output::max_cmpl_rings
__le16 max_cmpl_rings
Definition bnxt_hsi.h:2044
hwrm_func_resource_qcaps_output::max_tx_rings
__le16 max_tx_rings
Definition bnxt_hsi.h:2046
hwrm_func_resource_qcaps_output::max_rsscos_ctx
__le16 max_rsscos_ctx
Definition bnxt_hsi.h:2042
hwrm_func_resource_qcaps_output::min_l2_ctxs
__le16 min_l2_ctxs
Definition bnxt_hsi.h:2049
hwrm_func_resource_qcaps_output::max_stat_ctx
__le16 max_stat_ctx
Definition bnxt_hsi.h:2054
hwrm_func_vf_cfg_input
Definition bnxt_hsi.h:1270
hwrm_func_vf_cfg_input::guest_vlan
__le16 guest_vlan
Definition bnxt_hsi.h:1290
hwrm_func_vf_cfg_input::mtu
__le16 mtu
Definition bnxt_hsi.h:1289
hwrm_func_vf_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:1276
hwrm_func_vf_cfg_input::dflt_mac_addr
u8 dflt_mac_addr[6]
Definition bnxt_hsi.h:1292
hwrm_func_vf_cfg_input::async_event_cr
__le16 async_event_cr
Definition bnxt_hsi.h:1291
hwrm_nvm_get_variable_input
Definition bnxt_hsi.h:10299
hwrm_nvm_get_variable_input::data_len
__le16 data_len
Definition bnxt_hsi.h:10306
hwrm_nvm_get_variable_input::index_0
__le16 index_0
Definition bnxt_hsi.h:10312
hwrm_nvm_get_variable_input::dimensions
__le16 dimensions
Definition bnxt_hsi.h:10311
hwrm_nvm_get_variable_input::option_num
__le16 option_num
Definition bnxt_hsi.h:10307
hwrm_nvm_get_variable_input::dest_data_addr
__le64 dest_data_addr
Definition bnxt_hsi.h:10305
hwrm_port_mac_cfg_input
Definition bnxt_hsi.h:3614
hwrm_port_mac_cfg_input::lpbk
u8 lpbk
Definition bnxt_hsi.h:3645
hwrm_port_phy_cfg_input
Definition bnxt_hsi.h:3035
hwrm_port_phy_cfg_input::auto_duplex
u8 auto_duplex
Definition bnxt_hsi.h:3104
hwrm_port_phy_cfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:3082
hwrm_port_phy_cfg_input::flags
__le32 flags
Definition bnxt_hsi.h:3041
hwrm_port_phy_cfg_input::auto_link_speed_mask
__le16 auto_link_speed_mask
Definition bnxt_hsi.h:3128
hwrm_port_phy_cfg_input::auto_link_speeds2_mask
__le16 auto_link_speeds2_mask
Definition bnxt_hsi.h:3194
hwrm_port_phy_cfg_input::auto_mode
u8 auto_mode
Definition bnxt_hsi.h:3097
hwrm_port_phy_cfg_input::force_link_speed
__le16 force_link_speed
Definition bnxt_hsi.h:3083
hwrm_port_phy_cfg_input::auto_pause
u8 auto_pause
Definition bnxt_hsi.h:3109
hwrm_port_phy_cfg_input::force_link_speeds2
__le16 force_link_speeds2
Definition bnxt_hsi.h:3179
hwrm_port_phy_cfg_input::force_pam4_link_speed
__le16 force_pam4_link_speed
Definition bnxt_hsi.h:3167
hwrm_port_phy_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:3066
hwrm_port_phy_qcaps_input
Definition bnxt_hsi.h:4149
hwrm_port_phy_qcaps_output
Definition bnxt_hsi.h:4160
hwrm_port_phy_qcaps_output::flags2
__le16 flags2
Definition bnxt_hsi.h:4233
hwrm_port_phy_qcfg_input
Definition bnxt_hsi.h:3232
hwrm_port_phy_qcfg_output
Definition bnxt_hsi.h:3243
hwrm_port_phy_qcfg_output::link_speed
__le16 link_speed
Definition bnxt_hsi.h:3270
hwrm_port_phy_qcfg_output::link
u8 link
Definition bnxt_hsi.h:3248
hwrm_port_phy_qcfg_output::auto_link_speeds2
__le16 auto_link_speeds2
Definition bnxt_hsi.h:3594
hwrm_port_phy_qcfg_output::module_status
u8 module_status
Definition bnxt_hsi.h:3376
hwrm_port_phy_qcfg_output::support_speeds
__le16 support_speeds
Definition bnxt_hsi.h:3292
hwrm_queue_qportcfg_input
Definition bnxt_hsi.h:4667
hwrm_queue_qportcfg_input::flags
__le32 flags
Definition bnxt_hsi.h:4673
hwrm_queue_qportcfg_input::port_id
__le16 port_id
Definition bnxt_hsi.h:4678
hwrm_queue_qportcfg_output
Definition bnxt_hsi.h:4687
hwrm_queue_qportcfg_output::queue_id0
u8 queue_id0
Definition bnxt_hsi.h:4700
hwrm_ring_alloc_input
Definition bnxt_hsi.h:6200
hwrm_ring_alloc_input::cmpl_ring_id
__le16 cmpl_ring_id
Definition bnxt_hsi.h:6231
hwrm_ring_alloc_input::length
__le32 length
Definition bnxt_hsi.h:6229
hwrm_ring_alloc_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:6248
hwrm_ring_alloc_input::cq_handle
__le64 cq_handle
Definition bnxt_hsi.h:6273
hwrm_ring_alloc_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:6213
hwrm_ring_alloc_input::queue_id
__le16 queue_id
Definition bnxt_hsi.h:6232
hwrm_ring_alloc_input::enables
__le32 enables
Definition bnxt_hsi.h:6206
hwrm_ring_alloc_input::page_tbl_addr
__le64 page_tbl_addr
Definition bnxt_hsi.h:6224
hwrm_ring_alloc_input::rx_buf_size
__le16 rx_buf_size
Definition bnxt_hsi.h:6233
hwrm_ring_alloc_input::logical_id
__le16 logical_id
Definition bnxt_hsi.h:6230
hwrm_ring_alloc_input::int_mode
u8 int_mode
Definition bnxt_hsi.h:6266
hwrm_ring_alloc_input::page_size
u8 page_size
Definition bnxt_hsi.h:6226
hwrm_ring_alloc_input::nq_ring_id
__le16 nq_ring_id
Definition bnxt_hsi.h:6235
hwrm_ring_alloc_output
Definition bnxt_hsi.h:6277
hwrm_ring_alloc_output::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6282
hwrm_ring_free_input
Definition bnxt_hsi.h:6289
hwrm_ring_free_input::ring_id
__le16 ring_id
Definition bnxt_hsi.h:6304
hwrm_ring_free_input::ring_type
u8 ring_type
Definition bnxt_hsi.h:6295
hwrm_ring_grp_alloc_input
Definition bnxt_hsi.h:6463
hwrm_ring_grp_alloc_input::sc
__le16 sc
Definition bnxt_hsi.h:6472
hwrm_ring_grp_alloc_input::ar
__le16 ar
Definition bnxt_hsi.h:6471
hwrm_ring_grp_alloc_input::rr
__le16 rr
Definition bnxt_hsi.h:6470
hwrm_ring_grp_alloc_input::cr
__le16 cr
Definition bnxt_hsi.h:6469
hwrm_ring_grp_alloc_output
Definition bnxt_hsi.h:6476
hwrm_ring_grp_alloc_output::ring_group_id
__le32 ring_group_id
Definition bnxt_hsi.h:6481
hwrm_ring_grp_free_input
Definition bnxt_hsi.h:6487
hwrm_ring_grp_free_input::ring_group_id
__le32 ring_group_id
Definition bnxt_hsi.h:6493
hwrm_short_input
Definition bnxt_hsi.h:85
hwrm_short_input::req_type
__le16 req_type
Definition bnxt_hsi.h:86
hwrm_short_input::signature
__le16 signature
Definition bnxt_hsi.h:87
hwrm_short_input::req_addr
__le64 req_addr
Definition bnxt_hsi.h:92
hwrm_short_input::size
__le16 size
Definition bnxt_hsi.h:91
hwrm_stat_ctx_alloc_input
Definition bnxt_hsi.h:8517
hwrm_stat_ctx_alloc_output
Definition bnxt_hsi.h:8531
hwrm_stat_ctx_alloc_output::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8536
hwrm_stat_ctx_free_input
Definition bnxt_hsi.h:8542
hwrm_stat_ctx_free_input::stat_ctx_id
__le32 stat_ctx_id
Definition bnxt_hsi.h:8548
hwrm_ver_get_input
Definition bnxt_hsi.h:376
hwrm_ver_get_input::hwrm_intf_upd
u8 hwrm_intf_upd
Definition bnxt_hsi.h:384
hwrm_ver_get_input::hwrm_intf_min
u8 hwrm_intf_min
Definition bnxt_hsi.h:383
hwrm_ver_get_input::hwrm_intf_maj
u8 hwrm_intf_maj
Definition bnxt_hsi.h:382
hwrm_ver_get_output
Definition bnxt_hsi.h:389
hwrm_ver_get_output::chip_num
__le16 chip_num
Definition bnxt_hsi.h:430
hwrm_ver_get_output::def_req_timeout
__le16 def_req_timeout
Definition bnxt_hsi.h:441
hwrm_ver_get_output::chip_bond_id
u8 chip_bond_id
Definition bnxt_hsi.h:433
hwrm_ver_get_output::chip_platform_type
u8 chip_platform_type
Definition bnxt_hsi.h:434
hwrm_ver_get_output::hwrm_intf_min_8b
u8 hwrm_intf_min_8b
Definition bnxt_hsi.h:395
hwrm_ver_get_output::max_ext_req_len
__le16 max_ext_req_len
Definition bnxt_hsi.h:467
hwrm_ver_get_output::hwrm_intf_maj_8b
u8 hwrm_intf_maj_8b
Definition bnxt_hsi.h:394
hwrm_ver_get_output::chip_metal
u8 chip_metal
Definition bnxt_hsi.h:432
hwrm_ver_get_output::hwrm_intf_upd_8b
u8 hwrm_intf_upd_8b
Definition bnxt_hsi.h:396
hwrm_ver_get_output::dev_caps_cfg
__le32 dev_caps_cfg
Definition bnxt_hsi.h:410
hwrm_ver_get_output::max_req_win_len
__le16 max_req_win_len
Definition bnxt_hsi.h:439
hwrm_ver_get_output::chip_rev
u8 chip_rev
Definition bnxt_hsi.h:431
hwrm_vnic_alloc_input
Definition bnxt_hsi.h:5762
hwrm_vnic_alloc_input::flags
__le32 flags
Definition bnxt_hsi.h:5768
hwrm_vnic_alloc_output
Definition bnxt_hsi.h:5774
hwrm_vnic_alloc_output::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:5779
hwrm_vnic_cfg_input
Definition bnxt_hsi.h:5806
hwrm_vnic_cfg_input::default_rx_ring_id
__le16 default_rx_ring_id
Definition bnxt_hsi.h:5834
hwrm_vnic_cfg_input::dflt_ring_grp
__le16 dflt_ring_grp
Definition bnxt_hsi.h:5829
hwrm_vnic_cfg_input::vnic_id
__le16 vnic_id
Definition bnxt_hsi.h:5828
hwrm_vnic_cfg_input::default_cmpl_ring_id
__le16 default_cmpl_ring_id
Definition bnxt_hsi.h:5835
hwrm_vnic_cfg_input::enables
__le32 enables
Definition bnxt_hsi.h:5820
hwrm_vnic_cfg_input::mru
__le16 mru
Definition bnxt_hsi.h:5833
hwrm_vnic_free_input
Definition bnxt_hsi.h:5785
hwrm_vnic_free_input::vnic_id
__le32 vnic_id
Definition bnxt_hsi.h:5791
input::seq_id
__le16 seq_id
Definition bnxt_hsi.h:71
input::req_type
__le16 req_type
Definition bnxt_hsi.h:69
input::target_id
__le16 target_id
Definition bnxt_hsi.h:72
input::resp_addr
__le64 resp_addr
Definition bnxt_hsi.h:73
input::cmpl_ring
__le16 cmpl_ring
Definition bnxt_hsi.h:70
io_buffer
A persistent I/O buffer.
Definition iobuf.h:38
io_buffer::data
void * data
Start of data.
Definition iobuf.h:53
net_device_operations
Network device operations.
Definition netdevice.h:214
net_device
A network device.
Definition netdevice.h:353
net_device::priv
void * priv
Driver private data.
Definition netdevice.h:432
net_device::dev
struct device * dev
Underlying hardware device.
Definition netdevice.h:365
nq_base
Definition bnxt.h:559
nq_base::type
u16 type
Definition bnxt.h:560
nq_base::v
u32 v
Definition bnxt.h:581
output::error_code
__le16 error_code
Definition bnxt_hsi.h:78
output::req_type
__le16 req_type
Definition bnxt_hsi.h:79
output::resp_len
__le16 resp_len
Definition bnxt_hsi.h:81
output::seq_id
__le16 seq_id
Definition bnxt_hsi.h:80
pci_device_id
A PCI device ID list entry.
Definition pci.h:175
pci_device_id::driver_data
unsigned long driver_data
Arbitrary driver data.
Definition pci.h:183
pci_device
A PCI device.
Definition pci.h:211
pci_device::dev
struct device dev
Generic device.
Definition pci.h:213
pci_device::id
struct pci_device_id * id
Driver device ID.
Definition pci.h:248
pci_device::dma
struct dma_device dma
DMA device.
Definition pci.h:215
pci_driver
A PCI driver.
Definition pci.h:252
retry_timer
A retry timer.
Definition retry.h:22
rx_pkt_cmpl_hi
Definition bnxt.h:648
rx_pkt_cmpl_hi::errors_v2
u16 errors_v2
Definition bnxt.h:669
rx_pkt_cmpl
Definition bnxt.h:605
rx_pkt_cmpl::opaque
u32 opaque
Definition bnxt.h:635
rx_pkt_cmpl::len
u16 len
Definition bnxt.h:634
rx_pkt_v3_cmpl_hi
Definition bnxt.h:794
rx_pkt_v3_cmpl_hi::errors_v2
u16 errors_v2
Definition bnxt.h:817
rx_pkt_v3_cmpl
Definition bnxt.h:716
rx_pkt_v3_cmpl::flags_type
u16 flags_type
Definition bnxt.h:717
rx_prod_pkt_bd
Definition bnxt.h:866
timer
A timer.
Definition timer.h:29
tx_bd_short
Definition bnxt.h:451
tx_bd_short::dma
physaddr_t dma
Definition bnxt.h:473
tx_bd_short::opaque
u32 opaque
Definition bnxt.h:472
tx_bd_short::len
u16 len
Definition bnxt.h:471
tx_bd_short::flags_type
u16 flags_type
Definition bnxt.h:452
tx_cmpl
Definition bnxt.h:476
mdelay
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition timer.c:79
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition timer.c:61
data_len
uint32_t data_len
Microcode data size (or 0 to indicate 2000 bytes)
Definition ucode.h:15
u16
#define u16
Definition vga.h:20
u32
#define u32
Definition vga.h:21
readl
#define readl
Definition w89c840.c:157
writel
#define writel
Definition w89c840.c:160
tx
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition wpa.h:4
rx
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition wpa.h:1
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