iPXE
bnx2.c
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1 /* bnx2.c: Broadcom NX2 network driver.
2  *
3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  *
9  * Written by: Michael Chan (mchan@broadcom.com)
10  *
11  * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver
12  * version 1.4.40 from linux 2.6.17
13  */
14 
15 FILE_LICENCE ( GPL_ANY );
16 
17 #include "etherboot.h"
18 #include "nic.h"
19 #include <errno.h>
20 #include <ipxe/pci.h>
21 #include <ipxe/ethernet.h>
22 #include "string.h"
23 #include <mii.h>
24 #include "bnx2.h"
25 #include "bnx2_fw.h"
26 
27 #if 0
28 /* Dummy defines for error handling */
29 #define EBUSY 1
30 #define ENODEV 2
31 #define EINVAL 3
32 #define ENOMEM 4
33 #define EIO 5
34 #endif
35 
36 /* The bnx2 seems to be picky about the alignment of the receive buffers
37  * and possibly the status block.
38  */
39 struct bss {
40  struct tx_bd tx_desc_ring[TX_DESC_CNT];
41  struct rx_bd rx_desc_ring[RX_DESC_CNT];
42  unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE];
43  struct status_block status_blk;
44  struct statistics_block stats_blk;
45 };
46 #define bnx2_bss NIC_FAKE_BSS ( struct bss )
47 
48 static struct bnx2 bnx2;
49 
50 static struct flash_spec flash_table[] =
51 {
52  /* Slow EEPROM */
53  {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
54  1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
55  SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
56  "EEPROM - slow"},
57  /* Expansion entry 0001 */
58  {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
59  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
60  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
61  "Entry 0001"},
62  /* Saifun SA25F010 (non-buffered flash) */
63  /* strap, cfg1, & write1 need updates */
64  {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
65  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
66  SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
67  "Non-buffered flash (128kB)"},
68  /* Saifun SA25F020 (non-buffered flash) */
69  /* strap, cfg1, & write1 need updates */
70  {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
71  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
72  SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
73  "Non-buffered flash (256kB)"},
74  /* Expansion entry 0100 */
75  {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
76  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
77  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
78  "Entry 0100"},
79  /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
80  {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
81  0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
82  ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
83  "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
84  /* Entry 0110: ST M45PE20 (non-buffered flash)*/
85  {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
86  0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
87  ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
88  "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
89  /* Saifun SA25F005 (non-buffered flash) */
90  /* strap, cfg1, & write1 need updates */
91  {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
92  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
93  SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
94  "Non-buffered flash (64kB)"},
95  /* Fast EEPROM */
96  {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
97  1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
98  SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
99  "EEPROM - fast"},
100  /* Expansion entry 1001 */
101  {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
102  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
103  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
104  "Entry 1001"},
105  /* Expansion entry 1010 */
106  {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
107  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
108  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
109  "Entry 1010"},
110  /* ATMEL AT45DB011B (buffered flash) */
111  {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
112  1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
113  BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
114  "Buffered flash (128kB)"},
115  /* Expansion entry 1100 */
116  {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
117  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
118  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
119  "Entry 1100"},
120  /* Expansion entry 1101 */
121  {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
122  0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
123  SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
124  "Entry 1101"},
125  /* Ateml Expansion entry 1110 */
126  {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
127  1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
128  BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
129  "Entry 1110 (Atmel)"},
130  /* ATMEL AT45DB021B (buffered flash) */
131  {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
132  1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
133  BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
134  "Buffered flash (256kB)"},
135 };
136 
137 static u32
138 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
139 {
140  REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
141  return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
142 }
143 
144 static void
145 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
146 {
147  REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
148  REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
149 }
150 
151 static void
152 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
153 {
154  offset += cid_addr;
155  REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
156  REG_WR(bp, BNX2_CTX_DATA, val);
157 }
158 
159 static int
160 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
161 {
162  u32 val1;
163  int i, ret;
164 
165  if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
166  val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
167  val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
168 
169  REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
170  REG_RD(bp, BNX2_EMAC_MDIO_MODE);
171 
172  udelay(40);
173  }
174 
175  val1 = (bp->phy_addr << 21) | (reg << 16) |
176  BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
177  BNX2_EMAC_MDIO_COMM_START_BUSY;
178  REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
179 
180  for (i = 0; i < 50; i++) {
181  udelay(10);
182 
183  val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
184  if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
185  udelay(5);
186 
187  val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
188  val1 &= BNX2_EMAC_MDIO_COMM_DATA;
189 
190  break;
191  }
192  }
193 
194  if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
195  *val = 0x0;
196  ret = -EBUSY;
197  }
198  else {
199  *val = val1;
200  ret = 0;
201  }
202 
203  if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
204  val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
205  val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
206 
207  REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
208  REG_RD(bp, BNX2_EMAC_MDIO_MODE);
209 
210  udelay(40);
211  }
212 
213  return ret;
214 }
215 
216 static int
217 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
218 {
219  u32 val1;
220  int i, ret;
221 
222  if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
223  val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
224  val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
225 
226  REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
227  REG_RD(bp, BNX2_EMAC_MDIO_MODE);
228 
229  udelay(40);
230  }
231 
232  val1 = (bp->phy_addr << 21) | (reg << 16) | val |
233  BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
234  BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
235  REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
236 
237  for (i = 0; i < 50; i++) {
238  udelay(10);
239 
240  val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
241  if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
242  udelay(5);
243  break;
244  }
245  }
246 
247  if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
248  ret = -EBUSY;
249  else
250  ret = 0;
251 
252  if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
253  val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
254  val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
255 
256  REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
257  REG_RD(bp, BNX2_EMAC_MDIO_MODE);
258 
259  udelay(40);
260  }
261 
262  return ret;
263 }
264 
265 static void
266 bnx2_disable_int(struct bnx2 *bp)
267 {
268  REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
269  BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
270  REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
271 
272 }
273 
274 static int
275 bnx2_alloc_mem(struct bnx2 *bp)
276 {
277  bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
278  bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
279 
280  bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
281  memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
282  bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
283 
284  memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block));
285  bp->status_blk = &bnx2_bss.status_blk;
286  bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
287 
288  bp->stats_blk = &bnx2_bss.stats_blk;
289  memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block));
290  bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
291 
292  return 0;
293 }
294 
295 static void
296 bnx2_report_fw_link(struct bnx2 *bp)
297 {
298  u32 fw_link_status = 0;
299 
300  if (bp->link_up) {
301  u32 bmsr;
302 
303  switch (bp->line_speed) {
304  case SPEED_10:
305  if (bp->duplex == DUPLEX_HALF)
306  fw_link_status = BNX2_LINK_STATUS_10HALF;
307  else
308  fw_link_status = BNX2_LINK_STATUS_10FULL;
309  break;
310  case SPEED_100:
311  if (bp->duplex == DUPLEX_HALF)
312  fw_link_status = BNX2_LINK_STATUS_100HALF;
313  else
314  fw_link_status = BNX2_LINK_STATUS_100FULL;
315  break;
316  case SPEED_1000:
317  if (bp->duplex == DUPLEX_HALF)
318  fw_link_status = BNX2_LINK_STATUS_1000HALF;
319  else
320  fw_link_status = BNX2_LINK_STATUS_1000FULL;
321  break;
322  case SPEED_2500:
323  if (bp->duplex == DUPLEX_HALF)
324  fw_link_status = BNX2_LINK_STATUS_2500HALF;
325  else
326  fw_link_status = BNX2_LINK_STATUS_2500FULL;
327  break;
328  }
329 
330  fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
331 
332  if (bp->autoneg) {
333  fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
334 
335  bnx2_read_phy(bp, MII_BMSR, &bmsr);
336  bnx2_read_phy(bp, MII_BMSR, &bmsr);
337 
338  if (!(bmsr & BMSR_ANEGCOMPLETE) ||
339  bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
340  fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
341  else
342  fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
343  }
344  }
345  else
346  fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
347 
348  REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
349 }
350 
351 static void
352 bnx2_report_link(struct bnx2 *bp)
353 {
354  if (bp->link_up) {
355  printf("NIC Link is Up, ");
356 
357  printf("%d Mbps ", bp->line_speed);
358 
359  if (bp->duplex == DUPLEX_FULL)
360  printf("full duplex");
361  else
362  printf("half duplex");
363 
364  if (bp->flow_ctrl) {
365  if (bp->flow_ctrl & FLOW_CTRL_RX) {
366  printf(", receive ");
367  if (bp->flow_ctrl & FLOW_CTRL_TX)
368  printf("& transmit ");
369  }
370  else {
371  printf(", transmit ");
372  }
373  printf("flow control ON");
374  }
375  printf("\n");
376  }
377  else {
378  printf("NIC Link is Down\n");
379  }
380 
381  bnx2_report_fw_link(bp);
382 }
383 
384 static void
385 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
386 {
387  u32 local_adv, remote_adv;
388 
389  bp->flow_ctrl = 0;
390  if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
391  (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
392 
393  if (bp->duplex == DUPLEX_FULL) {
394  bp->flow_ctrl = bp->req_flow_ctrl;
395  }
396  return;
397  }
398 
399  if (bp->duplex != DUPLEX_FULL) {
400  return;
401  }
402 
403  if ((bp->phy_flags & PHY_SERDES_FLAG) &&
404  (CHIP_NUM(bp) == CHIP_NUM_5708)) {
405  u32 val;
406 
407  bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
408  if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
409  bp->flow_ctrl |= FLOW_CTRL_TX;
410  if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
411  bp->flow_ctrl |= FLOW_CTRL_RX;
412  return;
413  }
414 
415  bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
416  bnx2_read_phy(bp, MII_LPA, &remote_adv);
417 
418  if (bp->phy_flags & PHY_SERDES_FLAG) {
419  u32 new_local_adv = 0;
420  u32 new_remote_adv = 0;
421 
422  if (local_adv & ADVERTISE_1000XPAUSE)
423  new_local_adv |= ADVERTISE_PAUSE_CAP;
424  if (local_adv & ADVERTISE_1000XPSE_ASYM)
425  new_local_adv |= ADVERTISE_PAUSE_ASYM;
426  if (remote_adv & ADVERTISE_1000XPAUSE)
427  new_remote_adv |= ADVERTISE_PAUSE_CAP;
428  if (remote_adv & ADVERTISE_1000XPSE_ASYM)
429  new_remote_adv |= ADVERTISE_PAUSE_ASYM;
430 
431  local_adv = new_local_adv;
432  remote_adv = new_remote_adv;
433  }
434 
435  /* See Table 28B-3 of 802.3ab-1999 spec. */
436  if (local_adv & ADVERTISE_PAUSE_CAP) {
437  if(local_adv & ADVERTISE_PAUSE_ASYM) {
438  if (remote_adv & ADVERTISE_PAUSE_CAP) {
439  bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
440  }
441  else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
442  bp->flow_ctrl = FLOW_CTRL_RX;
443  }
444  }
445  else {
446  if (remote_adv & ADVERTISE_PAUSE_CAP) {
447  bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
448  }
449  }
450  }
451  else if (local_adv & ADVERTISE_PAUSE_ASYM) {
452  if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
453  (remote_adv & ADVERTISE_PAUSE_ASYM)) {
454 
455  bp->flow_ctrl = FLOW_CTRL_TX;
456  }
457  }
458 }
459 
460 static int
461 bnx2_5708s_linkup(struct bnx2 *bp)
462 {
463  u32 val;
464 
465  bp->link_up = 1;
466  bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
467  switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
468  case BCM5708S_1000X_STAT1_SPEED_10:
469  bp->line_speed = SPEED_10;
470  break;
471  case BCM5708S_1000X_STAT1_SPEED_100:
472  bp->line_speed = SPEED_100;
473  break;
474  case BCM5708S_1000X_STAT1_SPEED_1G:
475  bp->line_speed = SPEED_1000;
476  break;
477  case BCM5708S_1000X_STAT1_SPEED_2G5:
478  bp->line_speed = SPEED_2500;
479  break;
480  }
481  if (val & BCM5708S_1000X_STAT1_FD)
482  bp->duplex = DUPLEX_FULL;
483  else
484  bp->duplex = DUPLEX_HALF;
485 
486  return 0;
487 }
488 
489 static int
490 bnx2_5706s_linkup(struct bnx2 *bp)
491 {
492  u32 bmcr, local_adv, remote_adv, common;
493 
494  bp->link_up = 1;
495  bp->line_speed = SPEED_1000;
496 
497  bnx2_read_phy(bp, MII_BMCR, &bmcr);
498  if (bmcr & BMCR_FULLDPLX) {
499  bp->duplex = DUPLEX_FULL;
500  }
501  else {
502  bp->duplex = DUPLEX_HALF;
503  }
504 
505  if (!(bmcr & BMCR_ANENABLE)) {
506  return 0;
507  }
508 
509  bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
510  bnx2_read_phy(bp, MII_LPA, &remote_adv);
511 
512  common = local_adv & remote_adv;
513  if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
514 
515  if (common & ADVERTISE_1000XFULL) {
516  bp->duplex = DUPLEX_FULL;
517  }
518  else {
519  bp->duplex = DUPLEX_HALF;
520  }
521  }
522 
523  return 0;
524 }
525 
526 static int
527 bnx2_copper_linkup(struct bnx2 *bp)
528 {
529  u32 bmcr;
530 
531  bnx2_read_phy(bp, MII_BMCR, &bmcr);
532  if (bmcr & BMCR_ANENABLE) {
533  u32 local_adv, remote_adv, common;
534 
535  bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
536  bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
537 
538  common = local_adv & (remote_adv >> 2);
539  if (common & ADVERTISE_1000FULL) {
540  bp->line_speed = SPEED_1000;
541  bp->duplex = DUPLEX_FULL;
542  }
543  else if (common & ADVERTISE_1000HALF) {
544  bp->line_speed = SPEED_1000;
545  bp->duplex = DUPLEX_HALF;
546  }
547  else {
548  bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
549  bnx2_read_phy(bp, MII_LPA, &remote_adv);
550 
551  common = local_adv & remote_adv;
552  if (common & ADVERTISE_100FULL) {
553  bp->line_speed = SPEED_100;
554  bp->duplex = DUPLEX_FULL;
555  }
556  else if (common & ADVERTISE_100HALF) {
557  bp->line_speed = SPEED_100;
558  bp->duplex = DUPLEX_HALF;
559  }
560  else if (common & ADVERTISE_10FULL) {
561  bp->line_speed = SPEED_10;
562  bp->duplex = DUPLEX_FULL;
563  }
564  else if (common & ADVERTISE_10HALF) {
565  bp->line_speed = SPEED_10;
566  bp->duplex = DUPLEX_HALF;
567  }
568  else {
569  bp->line_speed = 0;
570  bp->link_up = 0;
571  }
572  }
573  }
574  else {
575  if (bmcr & BMCR_SPEED100) {
576  bp->line_speed = SPEED_100;
577  }
578  else {
579  bp->line_speed = SPEED_10;
580  }
581  if (bmcr & BMCR_FULLDPLX) {
582  bp->duplex = DUPLEX_FULL;
583  }
584  else {
585  bp->duplex = DUPLEX_HALF;
586  }
587  }
588 
589  return 0;
590 }
591 
592 static int
593 bnx2_set_mac_link(struct bnx2 *bp)
594 {
595  u32 val;
596 
597  REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
598  if (bp->link_up && (bp->line_speed == SPEED_1000) &&
599  (bp->duplex == DUPLEX_HALF)) {
600  REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
601  }
602 
603  /* Configure the EMAC mode register. */
604  val = REG_RD(bp, BNX2_EMAC_MODE);
605 
606  val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
607  BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
608  BNX2_EMAC_MODE_25G);
609 
610  if (bp->link_up) {
611  switch (bp->line_speed) {
612  case SPEED_10:
613  if (CHIP_NUM(bp) == CHIP_NUM_5708) {
614  val |= BNX2_EMAC_MODE_PORT_MII_10;
615  break;
616  }
617  /* fall through */
618  case SPEED_100:
619  val |= BNX2_EMAC_MODE_PORT_MII;
620  break;
621  case SPEED_2500:
622  val |= BNX2_EMAC_MODE_25G;
623  /* fall through */
624  case SPEED_1000:
625  val |= BNX2_EMAC_MODE_PORT_GMII;
626  break;
627  }
628  }
629  else {
630  val |= BNX2_EMAC_MODE_PORT_GMII;
631  }
632 
633  /* Set the MAC to operate in the appropriate duplex mode. */
634  if (bp->duplex == DUPLEX_HALF)
635  val |= BNX2_EMAC_MODE_HALF_DUPLEX;
636  REG_WR(bp, BNX2_EMAC_MODE, val);
637 
638  /* Enable/disable rx PAUSE. */
639  bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
640 
641  if (bp->flow_ctrl & FLOW_CTRL_RX)
642  bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
643  REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
644 
645  /* Enable/disable tx PAUSE. */
646  val = REG_RD(bp, BNX2_EMAC_TX_MODE);
647  val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
648 
649  if (bp->flow_ctrl & FLOW_CTRL_TX)
650  val |= BNX2_EMAC_TX_MODE_FLOW_EN;
651  REG_WR(bp, BNX2_EMAC_TX_MODE, val);
652 
653  /* Acknowledge the interrupt. */
654  REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
655 
656  return 0;
657 }
658 
659 static int
660 bnx2_set_link(struct bnx2 *bp)
661 {
662  u32 bmsr;
663  u8 link_up;
664 
665  if (bp->loopback == MAC_LOOPBACK) {
666  bp->link_up = 1;
667  return 0;
668  }
669 
670  link_up = bp->link_up;
671 
672  bnx2_read_phy(bp, MII_BMSR, &bmsr);
673  bnx2_read_phy(bp, MII_BMSR, &bmsr);
674 
675  if ((bp->phy_flags & PHY_SERDES_FLAG) &&
676  (CHIP_NUM(bp) == CHIP_NUM_5706)) {
677  u32 val;
678 
679  val = REG_RD(bp, BNX2_EMAC_STATUS);
680  if (val & BNX2_EMAC_STATUS_LINK)
681  bmsr |= BMSR_LSTATUS;
682  else
683  bmsr &= ~BMSR_LSTATUS;
684  }
685 
686  if (bmsr & BMSR_LSTATUS) {
687  bp->link_up = 1;
688 
689  if (bp->phy_flags & PHY_SERDES_FLAG) {
690  if (CHIP_NUM(bp) == CHIP_NUM_5706)
691  bnx2_5706s_linkup(bp);
692  else if (CHIP_NUM(bp) == CHIP_NUM_5708)
693  bnx2_5708s_linkup(bp);
694  }
695  else {
696  bnx2_copper_linkup(bp);
697  }
698  bnx2_resolve_flow_ctrl(bp);
699  }
700  else {
701  if ((bp->phy_flags & PHY_SERDES_FLAG) &&
702  (bp->autoneg & AUTONEG_SPEED)) {
703 
704  u32 bmcr;
705 
706  bnx2_read_phy(bp, MII_BMCR, &bmcr);
707  if (!(bmcr & BMCR_ANENABLE)) {
708  bnx2_write_phy(bp, MII_BMCR, bmcr |
709  BMCR_ANENABLE);
710  }
711  }
712  bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
713  bp->link_up = 0;
714  }
715 
716  if (bp->link_up != link_up) {
717  bnx2_report_link(bp);
718  }
719 
720  bnx2_set_mac_link(bp);
721 
722  return 0;
723 }
724 
725 static int
726 bnx2_reset_phy(struct bnx2 *bp)
727 {
728  int i;
729  u32 reg;
730 
731  bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
732 
733 #define PHY_RESET_MAX_WAIT 100
734  for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
735  udelay(10);
736 
737  bnx2_read_phy(bp, MII_BMCR, &reg);
738  if (!(reg & BMCR_RESET)) {
739  udelay(20);
740  break;
741  }
742  }
743  if (i == PHY_RESET_MAX_WAIT) {
744  return -EBUSY;
745  }
746  return 0;
747 }
748 
749 static u32
750 bnx2_phy_get_pause_adv(struct bnx2 *bp)
751 {
752  u32 adv = 0;
753 
754  if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
755  (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
756 
757  if (bp->phy_flags & PHY_SERDES_FLAG) {
758  adv = ADVERTISE_1000XPAUSE;
759  }
760  else {
761  adv = ADVERTISE_PAUSE_CAP;
762  }
763  }
764  else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
765  if (bp->phy_flags & PHY_SERDES_FLAG) {
766  adv = ADVERTISE_1000XPSE_ASYM;
767  }
768  else {
769  adv = ADVERTISE_PAUSE_ASYM;
770  }
771  }
772  else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
773  if (bp->phy_flags & PHY_SERDES_FLAG) {
774  adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
775  }
776  else {
777  adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
778  }
779  }
780  return adv;
781 }
782 
783 static int
784 bnx2_setup_serdes_phy(struct bnx2 *bp)
785 {
786  u32 adv, bmcr, up1;
787  u32 new_adv = 0;
788 
789  if (!(bp->autoneg & AUTONEG_SPEED)) {
790  u32 new_bmcr;
791  int force_link_down = 0;
792 
793  if (CHIP_NUM(bp) == CHIP_NUM_5708) {
794  bnx2_read_phy(bp, BCM5708S_UP1, &up1);
795  if (up1 & BCM5708S_UP1_2G5) {
796  up1 &= ~BCM5708S_UP1_2G5;
797  bnx2_write_phy(bp, BCM5708S_UP1, up1);
798  force_link_down = 1;
799  }
800  }
801 
802  bnx2_read_phy(bp, MII_ADVERTISE, &adv);
803  adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
804 
805  bnx2_read_phy(bp, MII_BMCR, &bmcr);
806  new_bmcr = bmcr & ~BMCR_ANENABLE;
807  new_bmcr |= BMCR_SPEED1000;
808  if (bp->req_duplex == DUPLEX_FULL) {
809  adv |= ADVERTISE_1000XFULL;
810  new_bmcr |= BMCR_FULLDPLX;
811  }
812  else {
813  adv |= ADVERTISE_1000XHALF;
814  new_bmcr &= ~BMCR_FULLDPLX;
815  }
816  if ((new_bmcr != bmcr) || (force_link_down)) {
817  /* Force a link down visible on the other side */
818  if (bp->link_up) {
819  bnx2_write_phy(bp, MII_ADVERTISE, adv &
820  ~(ADVERTISE_1000XFULL |
821  ADVERTISE_1000XHALF));
822  bnx2_write_phy(bp, MII_BMCR, bmcr |
823  BMCR_ANRESTART | BMCR_ANENABLE);
824 
825  bp->link_up = 0;
826  bnx2_write_phy(bp, MII_BMCR, new_bmcr);
827  }
828  bnx2_write_phy(bp, MII_ADVERTISE, adv);
829  bnx2_write_phy(bp, MII_BMCR, new_bmcr);
830  }
831  return 0;
832  }
833 
834  if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
835  bnx2_read_phy(bp, BCM5708S_UP1, &up1);
836  up1 |= BCM5708S_UP1_2G5;
837  bnx2_write_phy(bp, BCM5708S_UP1, up1);
838  }
839 
840  if (bp->advertising & ADVERTISED_1000baseT_Full)
841  new_adv |= ADVERTISE_1000XFULL;
842 
843  new_adv |= bnx2_phy_get_pause_adv(bp);
844 
845  bnx2_read_phy(bp, MII_ADVERTISE, &adv);
846  bnx2_read_phy(bp, MII_BMCR, &bmcr);
847 
848  bp->serdes_an_pending = 0;
849  if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
850  /* Force a link down visible on the other side */
851  if (bp->link_up) {
852  int i;
853 
854  bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
855  for (i = 0; i < 110; i++) {
856  udelay(100);
857  }
858  }
859 
860  bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
861  bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
862  BMCR_ANENABLE);
863 #if 0
864  if (CHIP_NUM(bp) == CHIP_NUM_5706) {
865  /* Speed up link-up time when the link partner
866  * does not autonegotiate which is very common
867  * in blade servers. Some blade servers use
868  * IPMI for kerboard input and it's important
869  * to minimize link disruptions. Autoneg. involves
870  * exchanging base pages plus 3 next pages and
871  * normally completes in about 120 msec.
872  */
873  bp->current_interval = SERDES_AN_TIMEOUT;
874  bp->serdes_an_pending = 1;
875  mod_timer(&bp->timer, jiffies + bp->current_interval);
876  }
877 #endif
878  }
879 
880  return 0;
881 }
882 
883 #define ETHTOOL_ALL_FIBRE_SPEED \
884  (ADVERTISED_1000baseT_Full)
885 
886 #define ETHTOOL_ALL_COPPER_SPEED \
887  (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
888  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
889  ADVERTISED_1000baseT_Full)
890 
891 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
892  ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
893 
894 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
895 
896 static int
897 bnx2_setup_copper_phy(struct bnx2 *bp)
898 {
899  u32 bmcr;
900  u32 new_bmcr;
901 
902  bnx2_read_phy(bp, MII_BMCR, &bmcr);
903 
904  if (bp->autoneg & AUTONEG_SPEED) {
905  u32 adv_reg, adv1000_reg;
906  u32 new_adv_reg = 0;
907  u32 new_adv1000_reg = 0;
908 
909  bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
910  adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
911  ADVERTISE_PAUSE_ASYM);
912 
913  bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
914  adv1000_reg &= PHY_ALL_1000_SPEED;
915 
916  if (bp->advertising & ADVERTISED_10baseT_Half)
917  new_adv_reg |= ADVERTISE_10HALF;
918  if (bp->advertising & ADVERTISED_10baseT_Full)
919  new_adv_reg |= ADVERTISE_10FULL;
920  if (bp->advertising & ADVERTISED_100baseT_Half)
921  new_adv_reg |= ADVERTISE_100HALF;
922  if (bp->advertising & ADVERTISED_100baseT_Full)
923  new_adv_reg |= ADVERTISE_100FULL;
924  if (bp->advertising & ADVERTISED_1000baseT_Full)
925  new_adv1000_reg |= ADVERTISE_1000FULL;
926 
927  new_adv_reg |= ADVERTISE_CSMA;
928 
929  new_adv_reg |= bnx2_phy_get_pause_adv(bp);
930 
931  if ((adv1000_reg != new_adv1000_reg) ||
932  (adv_reg != new_adv_reg) ||
933  ((bmcr & BMCR_ANENABLE) == 0)) {
934 
935  bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
936  bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
937  bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
938  BMCR_ANENABLE);
939  }
940  else if (bp->link_up) {
941  /* Flow ctrl may have changed from auto to forced */
942  /* or vice-versa. */
943 
944  bnx2_resolve_flow_ctrl(bp);
945  bnx2_set_mac_link(bp);
946  }
947  return 0;
948  }
949 
950  new_bmcr = 0;
951  if (bp->req_line_speed == SPEED_100) {
952  new_bmcr |= BMCR_SPEED100;
953  }
954  if (bp->req_duplex == DUPLEX_FULL) {
955  new_bmcr |= BMCR_FULLDPLX;
956  }
957  if (new_bmcr != bmcr) {
958  u32 bmsr;
959  int i = 0;
960 
961  bnx2_read_phy(bp, MII_BMSR, &bmsr);
962  bnx2_read_phy(bp, MII_BMSR, &bmsr);
963 
964  if (bmsr & BMSR_LSTATUS) {
965  /* Force link down */
966  bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
967  do {
968  udelay(100);
969  bnx2_read_phy(bp, MII_BMSR, &bmsr);
970  bnx2_read_phy(bp, MII_BMSR, &bmsr);
971  i++;
972  } while ((bmsr & BMSR_LSTATUS) && (i < 620));
973  }
974 
975  bnx2_write_phy(bp, MII_BMCR, new_bmcr);
976 
977  /* Normally, the new speed is setup after the link has
978  * gone down and up again. In some cases, link will not go
979  * down so we need to set up the new speed here.
980  */
981  if (bmsr & BMSR_LSTATUS) {
982  bp->line_speed = bp->req_line_speed;
983  bp->duplex = bp->req_duplex;
984  bnx2_resolve_flow_ctrl(bp);
985  bnx2_set_mac_link(bp);
986  }
987  }
988  return 0;
989 }
990 
991 static int
992 bnx2_setup_phy(struct bnx2 *bp)
993 {
994  if (bp->loopback == MAC_LOOPBACK)
995  return 0;
996 
997  if (bp->phy_flags & PHY_SERDES_FLAG) {
998  return (bnx2_setup_serdes_phy(bp));
999  }
1000  else {
1001  return (bnx2_setup_copper_phy(bp));
1002  }
1003 }
1004 
1005 static int
1006 bnx2_init_5708s_phy(struct bnx2 *bp)
1007 {
1008  u32 val;
1009 
1010  bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1011  bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1012  bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1013 
1014  bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1015  val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1016  bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1017 
1018  bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1019  val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1020  bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1021 
1022  if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1023  bnx2_read_phy(bp, BCM5708S_UP1, &val);
1024  val |= BCM5708S_UP1_2G5;
1025  bnx2_write_phy(bp, BCM5708S_UP1, val);
1026  }
1027 
1028  if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1029  (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1030  (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1031  /* increase tx signal amplitude */
1032  bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1033  BCM5708S_BLK_ADDR_TX_MISC);
1034  bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1035  val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1036  bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1037  bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1038  }
1039 
1040  val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1041  BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1042 
1043  if (val) {
1044  u32 is_backplane;
1045 
1046  is_backplane = REG_RD_IND(bp, bp->shmem_base +
1047  BNX2_SHARED_HW_CFG_CONFIG);
1048  if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1049  bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1050  BCM5708S_BLK_ADDR_TX_MISC);
1051  bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1052  bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1053  BCM5708S_BLK_ADDR_DIG);
1054  }
1055  }
1056  return 0;
1057 }
1058 
1059 static int
1060 bnx2_init_5706s_phy(struct bnx2 *bp)
1061 {
1062  u32 val;
1063 
1064  bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1065 
1066  if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1067  REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1068  }
1069 
1070 
1071  bnx2_write_phy(bp, 0x18, 0x7);
1072  bnx2_read_phy(bp, 0x18, &val);
1073  bnx2_write_phy(bp, 0x18, val & ~0x4007);
1074 
1075  bnx2_write_phy(bp, 0x1c, 0x6c00);
1076  bnx2_read_phy(bp, 0x1c, &val);
1077  bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1078 
1079  return 0;
1080 }
1081 
1082 static int
1083 bnx2_init_copper_phy(struct bnx2 *bp)
1084 {
1085  u32 val;
1086 
1087  bp->phy_flags |= PHY_CRC_FIX_FLAG;
1088 
1089  if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1090  bnx2_write_phy(bp, 0x18, 0x0c00);
1091  bnx2_write_phy(bp, 0x17, 0x000a);
1092  bnx2_write_phy(bp, 0x15, 0x310b);
1093  bnx2_write_phy(bp, 0x17, 0x201f);
1094  bnx2_write_phy(bp, 0x15, 0x9506);
1095  bnx2_write_phy(bp, 0x17, 0x401f);
1096  bnx2_write_phy(bp, 0x15, 0x14e2);
1097  bnx2_write_phy(bp, 0x18, 0x0400);
1098  }
1099 
1100  bnx2_write_phy(bp, 0x18, 0x7);
1101  bnx2_read_phy(bp, 0x18, &val);
1102  bnx2_write_phy(bp, 0x18, val & ~0x4007);
1103 
1104  bnx2_read_phy(bp, 0x10, &val);
1105  bnx2_write_phy(bp, 0x10, val & ~0x1);
1106 
1107  /* ethernet@wirespeed */
1108  bnx2_write_phy(bp, 0x18, 0x7007);
1109  bnx2_read_phy(bp, 0x18, &val);
1110  bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1111  return 0;
1112 }
1113 
1114 static int
1115 bnx2_init_phy(struct bnx2 *bp)
1116 {
1117  u32 val;
1118  int rc = 0;
1119 
1120  bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1121  bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1122 
1123  REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1124 
1125  bnx2_reset_phy(bp);
1126 
1127  bnx2_read_phy(bp, MII_PHYSID1, &val);
1128  bp->phy_id = val << 16;
1129  bnx2_read_phy(bp, MII_PHYSID2, &val);
1130  bp->phy_id |= val & 0xffff;
1131 
1132  if (bp->phy_flags & PHY_SERDES_FLAG) {
1133  if (CHIP_NUM(bp) == CHIP_NUM_5706)
1134  rc = bnx2_init_5706s_phy(bp);
1135  else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1136  rc = bnx2_init_5708s_phy(bp);
1137  }
1138  else {
1139  rc = bnx2_init_copper_phy(bp);
1140  }
1141 
1142  bnx2_setup_phy(bp);
1143 
1144  return rc;
1145 }
1146 
1147 static int
1148 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1149 {
1150  int i;
1151  u32 val;
1152 
1153  bp->fw_wr_seq++;
1154  msg_data |= bp->fw_wr_seq;
1155 
1156  REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1157 
1158  /* wait for an acknowledgement. */
1159  for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) {
1160  mdelay(50);
1161 
1162  val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1163 
1164  if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1165  break;
1166  }
1167  if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1168  return 0;
1169 
1170  /* If we timed out, inform the firmware that this is the case. */
1171  if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1172  if (!silent)
1173  printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data);
1174 
1175  msg_data &= ~BNX2_DRV_MSG_CODE;
1176  msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1177 
1178  REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1179 
1180  return -EBUSY;
1181  }
1182 
1183  if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1184  return -EIO;
1185 
1186  return 0;
1187 }
1188 
1189 static void
1190 bnx2_init_context(struct bnx2 *bp)
1191 {
1192  u32 vcid;
1193 
1194  vcid = 96;
1195  while (vcid) {
1196  u32 vcid_addr, pcid_addr, offset;
1197 
1198  vcid--;
1199 
1200  if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1201  u32 new_vcid;
1202 
1203  vcid_addr = GET_PCID_ADDR(vcid);
1204  if (vcid & 0x8) {
1205  new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1206  }
1207  else {
1208  new_vcid = vcid;
1209  }
1210  pcid_addr = GET_PCID_ADDR(new_vcid);
1211  }
1212  else {
1213  vcid_addr = GET_CID_ADDR(vcid);
1214  pcid_addr = vcid_addr;
1215  }
1216 
1217  REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1218  REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1219 
1220  /* Zero out the context. */
1221  for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1222  CTX_WR(bp, 0x00, offset, 0);
1223  }
1224 
1225  REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1226  REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1227  }
1228 }
1229 
1230 static int
1231 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1232 {
1233  u16 good_mbuf[512];
1234  u32 good_mbuf_cnt;
1235  u32 val;
1236 
1237  REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1238  BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1239 
1240  good_mbuf_cnt = 0;
1241 
1242  /* Allocate a bunch of mbufs and save the good ones in an array. */
1243  val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1244  while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1245  REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1246 
1247  val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1248 
1249  val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1250 
1251  /* The addresses with Bit 9 set are bad memory blocks. */
1252  if (!(val & (1 << 9))) {
1253  good_mbuf[good_mbuf_cnt] = (u16) val;
1254  good_mbuf_cnt++;
1255  }
1256 
1257  val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1258  }
1259 
1260  /* Free the good ones back to the mbuf pool thus discarding
1261  * all the bad ones. */
1262  while (good_mbuf_cnt) {
1263  good_mbuf_cnt--;
1264 
1265  val = good_mbuf[good_mbuf_cnt];
1266  val = (val << 9) | val | 1;
1267 
1268  REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1269  }
1270  return 0;
1271 }
1272 
1273 static void
1274 bnx2_set_mac_addr(struct bnx2 *bp)
1275 {
1276  u32 val;
1277  u8 *mac_addr = bp->nic->node_addr;
1278 
1279  val = (mac_addr[0] << 8) | mac_addr[1];
1280 
1281  REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1282 
1283  val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1284  (mac_addr[4] << 8) | mac_addr[5];
1285 
1286  REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1287 }
1288 
1289 static void
1290 bnx2_set_rx_mode(struct nic *nic __unused)
1291 {
1292  struct bnx2 *bp = &bnx2;
1293  u32 rx_mode, sort_mode;
1294  int i;
1295 
1296  rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1297  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1298  sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1299 
1300  if (!(bp->flags & ASF_ENABLE_FLAG)) {
1301  rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1302  }
1303 
1304  /* Accept all multicasts */
1305  for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1306  REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1307  0xffffffff);
1308  }
1309  sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1310 
1311  if (rx_mode != bp->rx_mode) {
1312  bp->rx_mode = rx_mode;
1313  REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1314  }
1315 
1316  REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1317  REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1318  REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1319 }
1320 
1321 static void
1322 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
1323 {
1324  unsigned int i;
1325  u32 val;
1326 
1327 
1328  for (i = 0; i < rv2p_code_len; i += 8) {
1329  REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1330  rv2p_code++;
1331  REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1332  rv2p_code++;
1333 
1334  if (rv2p_proc == RV2P_PROC1) {
1335  val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1336  REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1337  }
1338  else {
1339  val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1340  REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1341  }
1342  }
1343 
1344  /* Reset the processor, un-stall is done later. */
1345  if (rv2p_proc == RV2P_PROC1) {
1346  REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1347  }
1348  else {
1349  REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1350  }
1351 }
1352 
1353 static void
1354 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1355 {
1356  u32 offset;
1357  u32 val;
1358 
1359  /* Halt the CPU. */
1360  val = REG_RD_IND(bp, cpu_reg->mode);
1361  val |= cpu_reg->mode_value_halt;
1362  REG_WR_IND(bp, cpu_reg->mode, val);
1363  REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1364 
1365  /* Load the Text area. */
1366  offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1367  if (fw->text) {
1368  unsigned int j;
1369 
1370  for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1371  REG_WR_IND(bp, offset, fw->text[j]);
1372  }
1373  }
1374 
1375  /* Load the Data area. */
1376  offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1377  if (fw->data) {
1378  unsigned int j;
1379 
1380  for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1381  REG_WR_IND(bp, offset, fw->data[j]);
1382  }
1383  }
1384 
1385  /* Load the SBSS area. */
1386  offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1387  if (fw->sbss) {
1388  unsigned int j;
1389 
1390  for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1391  REG_WR_IND(bp, offset, fw->sbss[j]);
1392  }
1393  }
1394 
1395  /* Load the BSS area. */
1396  offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1397  if (fw->bss) {
1398  unsigned int j;
1399 
1400  for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1401  REG_WR_IND(bp, offset, fw->bss[j]);
1402  }
1403  }
1404 
1405  /* Load the Read-Only area. */
1406  offset = cpu_reg->spad_base +
1407  (fw->rodata_addr - cpu_reg->mips_view_base);
1408  if (fw->rodata) {
1409  unsigned int j;
1410 
1411  for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1412  REG_WR_IND(bp, offset, fw->rodata[j]);
1413  }
1414  }
1415 
1416  /* Clear the pre-fetch instruction. */
1417  REG_WR_IND(bp, cpu_reg->inst, 0);
1418  REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1419 
1420  /* Start the CPU. */
1421  val = REG_RD_IND(bp, cpu_reg->mode);
1422  val &= ~cpu_reg->mode_value_halt;
1423  REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1424  REG_WR_IND(bp, cpu_reg->mode, val);
1425 }
1426 
1427 static void
1428 bnx2_init_cpus(struct bnx2 *bp)
1429 {
1430  struct cpu_reg cpu_reg;
1431  struct fw_info fw;
1432 
1433  /* Unfortunately, it looks like we need to load the firmware
1434  * before the card will work properly. That means this driver
1435  * will be huge by Etherboot standards (approx. 50K compressed).
1436  */
1437 
1438  /* Initialize the RV2P processor. */
1439  load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1440  load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1441 
1442  /* Initialize the RX Processor. */
1443  cpu_reg.mode = BNX2_RXP_CPU_MODE;
1444  cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1445  cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1446  cpu_reg.state = BNX2_RXP_CPU_STATE;
1447  cpu_reg.state_value_clear = 0xffffff;
1448  cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1449  cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1450  cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1451  cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1452  cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1453  cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1454  cpu_reg.mips_view_base = 0x8000000;
1455 
1456  fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1457  fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1458  fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1459  fw.start_addr = bnx2_RXP_b06FwStartAddr;
1460 
1461  fw.text_addr = bnx2_RXP_b06FwTextAddr;
1462  fw.text_len = bnx2_RXP_b06FwTextLen;
1463  fw.text_index = 0;
1464  fw.text = bnx2_RXP_b06FwText;
1465 
1466  fw.data_addr = bnx2_RXP_b06FwDataAddr;
1467  fw.data_len = bnx2_RXP_b06FwDataLen;
1468  fw.data_index = 0;
1469  fw.data = bnx2_RXP_b06FwData;
1470 
1471  fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1472  fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1473  fw.sbss_index = 0;
1474  fw.sbss = bnx2_RXP_b06FwSbss;
1475 
1476  fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1477  fw.bss_len = bnx2_RXP_b06FwBssLen;
1478  fw.bss_index = 0;
1479  fw.bss = bnx2_RXP_b06FwBss;
1480 
1481  fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1482  fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1483  fw.rodata_index = 0;
1484  fw.rodata = bnx2_RXP_b06FwRodata;
1485 
1486  load_cpu_fw(bp, &cpu_reg, &fw);
1487 
1488  /* Initialize the TX Processor. */
1489  cpu_reg.mode = BNX2_TXP_CPU_MODE;
1490  cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1491  cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1492  cpu_reg.state = BNX2_TXP_CPU_STATE;
1493  cpu_reg.state_value_clear = 0xffffff;
1494  cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1495  cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1496  cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1497  cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1498  cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1499  cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1500  cpu_reg.mips_view_base = 0x8000000;
1501 
1502  fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1503  fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1504  fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1505  fw.start_addr = bnx2_TXP_b06FwStartAddr;
1506 
1507  fw.text_addr = bnx2_TXP_b06FwTextAddr;
1508  fw.text_len = bnx2_TXP_b06FwTextLen;
1509  fw.text_index = 0;
1510  fw.text = bnx2_TXP_b06FwText;
1511 
1512  fw.data_addr = bnx2_TXP_b06FwDataAddr;
1513  fw.data_len = bnx2_TXP_b06FwDataLen;
1514  fw.data_index = 0;
1515  fw.data = bnx2_TXP_b06FwData;
1516 
1517  fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1518  fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1519  fw.sbss_index = 0;
1520  fw.sbss = bnx2_TXP_b06FwSbss;
1521 
1522  fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1523  fw.bss_len = bnx2_TXP_b06FwBssLen;
1524  fw.bss_index = 0;
1525  fw.bss = bnx2_TXP_b06FwBss;
1526 
1527  fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1528  fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1529  fw.rodata_index = 0;
1530  fw.rodata = bnx2_TXP_b06FwRodata;
1531 
1532  load_cpu_fw(bp, &cpu_reg, &fw);
1533 
1534  /* Initialize the TX Patch-up Processor. */
1535  cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1536  cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1537  cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1538  cpu_reg.state = BNX2_TPAT_CPU_STATE;
1539  cpu_reg.state_value_clear = 0xffffff;
1540  cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1541  cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1542  cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1543  cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1544  cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1545  cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1546  cpu_reg.mips_view_base = 0x8000000;
1547 
1548  fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1549  fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1550  fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1551  fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1552 
1553  fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1554  fw.text_len = bnx2_TPAT_b06FwTextLen;
1555  fw.text_index = 0;
1556  fw.text = bnx2_TPAT_b06FwText;
1557 
1558  fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1559  fw.data_len = bnx2_TPAT_b06FwDataLen;
1560  fw.data_index = 0;
1561  fw.data = bnx2_TPAT_b06FwData;
1562 
1563  fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1564  fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1565  fw.sbss_index = 0;
1566  fw.sbss = bnx2_TPAT_b06FwSbss;
1567 
1568  fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1569  fw.bss_len = bnx2_TPAT_b06FwBssLen;
1570  fw.bss_index = 0;
1571  fw.bss = bnx2_TPAT_b06FwBss;
1572 
1573  fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1574  fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1575  fw.rodata_index = 0;
1576  fw.rodata = bnx2_TPAT_b06FwRodata;
1577 
1578  load_cpu_fw(bp, &cpu_reg, &fw);
1579 
1580  /* Initialize the Completion Processor. */
1581  cpu_reg.mode = BNX2_COM_CPU_MODE;
1582  cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1583  cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1584  cpu_reg.state = BNX2_COM_CPU_STATE;
1585  cpu_reg.state_value_clear = 0xffffff;
1586  cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1587  cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1588  cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1589  cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1590  cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1591  cpu_reg.spad_base = BNX2_COM_SCRATCH;
1592  cpu_reg.mips_view_base = 0x8000000;
1593 
1594  fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1595  fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1596  fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1597  fw.start_addr = bnx2_COM_b06FwStartAddr;
1598 
1599  fw.text_addr = bnx2_COM_b06FwTextAddr;
1600  fw.text_len = bnx2_COM_b06FwTextLen;
1601  fw.text_index = 0;
1602  fw.text = bnx2_COM_b06FwText;
1603 
1604  fw.data_addr = bnx2_COM_b06FwDataAddr;
1605  fw.data_len = bnx2_COM_b06FwDataLen;
1606  fw.data_index = 0;
1607  fw.data = bnx2_COM_b06FwData;
1608 
1609  fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1610  fw.sbss_len = bnx2_COM_b06FwSbssLen;
1611  fw.sbss_index = 0;
1612  fw.sbss = bnx2_COM_b06FwSbss;
1613 
1614  fw.bss_addr = bnx2_COM_b06FwBssAddr;
1615  fw.bss_len = bnx2_COM_b06FwBssLen;
1616  fw.bss_index = 0;
1617  fw.bss = bnx2_COM_b06FwBss;
1618 
1619  fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1620  fw.rodata_len = bnx2_COM_b06FwRodataLen;
1621  fw.rodata_index = 0;
1622  fw.rodata = bnx2_COM_b06FwRodata;
1623 
1624  load_cpu_fw(bp, &cpu_reg, &fw);
1625 
1626 }
1627 
1628 static int
1629 bnx2_set_power_state_0(struct bnx2 *bp)
1630 {
1631  u16 pmcsr;
1632  u32 val;
1633 
1634  pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
1635 
1636  pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
1637  (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
1638  PCI_PM_CTRL_PME_STATUS);
1639 
1640  if (pmcsr & PCI_PM_CTRL_STATE_MASK)
1641  /* delay required during transition out of D3hot */
1642  mdelay(20);
1643 
1644  val = REG_RD(bp, BNX2_EMAC_MODE);
1645  val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
1646  val &= ~BNX2_EMAC_MODE_MPKT;
1647  REG_WR(bp, BNX2_EMAC_MODE, val);
1648 
1649  val = REG_RD(bp, BNX2_RPM_CONFIG);
1650  val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
1651  REG_WR(bp, BNX2_RPM_CONFIG, val);
1652 
1653  return 0;
1654 }
1655 
1656 static void
1657 bnx2_enable_nvram_access(struct bnx2 *bp)
1658 {
1659  u32 val;
1660 
1661  val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1662  /* Enable both bits, even on read. */
1663  REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1664  val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
1665 }
1666 
1667 static void
1668 bnx2_disable_nvram_access(struct bnx2 *bp)
1669 {
1670  u32 val;
1671 
1672  val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
1673  /* Disable both bits, even after read. */
1674  REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
1675  val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
1676  BNX2_NVM_ACCESS_ENABLE_WR_EN));
1677 }
1678 
1679 static int
1680 bnx2_init_nvram(struct bnx2 *bp)
1681 {
1682  u32 val;
1683  int j, entry_count, rc;
1684  struct flash_spec *flash;
1685 
1686  /* Determine the selected interface. */
1687  val = REG_RD(bp, BNX2_NVM_CFG1);
1688 
1689  entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1690 
1691  rc = 0;
1692  if (val & 0x40000000) {
1693  /* Flash interface has been reconfigured */
1694  for (j = 0, flash = &flash_table[0]; j < entry_count;
1695  j++, flash++) {
1696  if ((val & FLASH_BACKUP_STRAP_MASK) ==
1697  (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1698  bp->flash_info = flash;
1699  break;
1700  }
1701  }
1702  }
1703  else {
1704  u32 mask;
1705  /* Not yet been reconfigured */
1706 
1707  if (val & (1 << 23))
1708  mask = FLASH_BACKUP_STRAP_MASK;
1709  else
1710  mask = FLASH_STRAP_MASK;
1711 
1712  for (j = 0, flash = &flash_table[0]; j < entry_count;
1713  j++, flash++) {
1714 
1715  if ((val & mask) == (flash->strapping & mask)) {
1716  bp->flash_info = flash;
1717 
1718  /* Enable access to flash interface */
1719  bnx2_enable_nvram_access(bp);
1720 
1721  /* Reconfigure the flash interface */
1722  REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
1723  REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
1724  REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
1725  REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
1726 
1727  /* Disable access to flash interface */
1728  bnx2_disable_nvram_access(bp);
1729 
1730  break;
1731  }
1732  }
1733  } /* if (val & 0x40000000) */
1734 
1735  if (j == entry_count) {
1736  bp->flash_info = NULL;
1737  printf("Unknown flash/EEPROM type.\n");
1738  return -ENODEV;
1739  }
1740 
1741  val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
1742  val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
1743  if (val) {
1744  bp->flash_size = val;
1745  }
1746  else {
1747  bp->flash_size = bp->flash_info->total_size;
1748  }
1749 
1750  return rc;
1751 }
1752 
1753 static int
1754 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
1755 {
1756  u32 val;
1757  int i, rc = 0;
1758 
1759  /* Wait for the current PCI transaction to complete before
1760  * issuing a reset. */
1761  REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
1762  BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
1763  BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
1764  BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
1765  BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
1766  val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
1767  udelay(5);
1768 
1769 
1770  /* Wait for the firmware to tell us it is ok to issue a reset. */
1771  bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
1772 
1773  /* Deposit a driver reset signature so the firmware knows that
1774  * this is a soft reset. */
1775  REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
1776  BNX2_DRV_RESET_SIGNATURE_MAGIC);
1777 
1778  /* Do a dummy read to force the chip to complete all current transaction
1779  * before we issue a reset. */
1780  val = REG_RD(bp, BNX2_MISC_ID);
1781 
1782  val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1783  BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1784  BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
1785 
1786  /* Chip reset. */
1787  REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
1788 
1789  if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
1790  (CHIP_ID(bp) == CHIP_ID_5706_A1))
1791  mdelay(15);
1792 
1793  /* Reset takes approximate 30 usec */
1794  for (i = 0; i < 10; i++) {
1795  val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
1796  if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1797  BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
1798  break;
1799  }
1800  udelay(10);
1801  }
1802 
1803  if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
1804  BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
1805  printf("Chip reset did not complete\n");
1806  return -EBUSY;
1807  }
1808 
1809  /* Make sure byte swapping is properly configured. */
1810  val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
1811  if (val != 0x01020304) {
1812  printf("Chip not in correct endian mode\n");
1813  return -ENODEV;
1814  }
1815 
1816  /* Wait for the firmware to finish its initialization. */
1817  rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
1818  if (rc) {
1819  return rc;
1820  }
1821 
1822  if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1823  /* Adjust the voltage regular to two steps lower. The default
1824  * of this register is 0x0000000e. */
1825  REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
1826 
1827  /* Remove bad rbuf memory from the free pool. */
1828  rc = bnx2_alloc_bad_rbuf(bp);
1829  }
1830 
1831  return rc;
1832 }
1833 
1834 static void
1835 bnx2_disable(struct nic *nic __unused)
1836 {
1837  struct bnx2* bp = &bnx2;
1838 
1839  if (bp->regview) {
1840  bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
1841  iounmap(bp->regview);
1842  }
1843 }
1844 
1845 static int
1846 bnx2_init_chip(struct bnx2 *bp)
1847 {
1848  u32 val;
1849  int rc;
1850 
1851  /* Make sure the interrupt is not active. */
1852  REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1853 
1854  val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
1855  BNX2_DMA_CONFIG_DATA_WORD_SWAP |
1856 #if __BYTE_ORDER == __BIG_ENDIAN
1857  BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
1858 #endif
1859  BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
1860  DMA_READ_CHANS << 12 |
1861  DMA_WRITE_CHANS << 16;
1862 
1863  val |= (0x2 << 20) | (1 << 11);
1864 
1865  if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
1866  val |= (1 << 23);
1867 
1868  if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
1869  (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
1870  val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
1871 
1872  REG_WR(bp, BNX2_DMA_CONFIG, val);
1873 
1874  if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1875  val = REG_RD(bp, BNX2_TDMA_CONFIG);
1876  val |= BNX2_TDMA_CONFIG_ONE_DMA;
1877  REG_WR(bp, BNX2_TDMA_CONFIG, val);
1878  }
1879 
1880  if (bp->flags & PCIX_FLAG) {
1881  u16 val16;
1882 
1883  pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1884  &val16);
1885  pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
1886  val16 & ~PCI_X_CMD_ERO);
1887  }
1888 
1889  REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1890  BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
1891  BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
1892  BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
1893 
1894  /* Initialize context mapping and zero out the quick contexts. The
1895  * context block must have already been enabled. */
1896  bnx2_init_context(bp);
1897 
1898  bnx2_init_nvram(bp);
1899  bnx2_init_cpus(bp);
1900 
1901  bnx2_set_mac_addr(bp);
1902 
1903  val = REG_RD(bp, BNX2_MQ_CONFIG);
1904  val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
1905  val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
1906  REG_WR(bp, BNX2_MQ_CONFIG, val);
1907 
1908  val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
1909  REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
1910  REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
1911 
1912  val = (BCM_PAGE_BITS - 8) << 24;
1913  REG_WR(bp, BNX2_RV2P_CONFIG, val);
1914 
1915  /* Configure page size. */
1916  val = REG_RD(bp, BNX2_TBDR_CONFIG);
1917  val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
1918  val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
1919  REG_WR(bp, BNX2_TBDR_CONFIG, val);
1920 
1921  val = bp->mac_addr[0] +
1922  (bp->mac_addr[1] << 8) +
1923  (bp->mac_addr[2] << 16) +
1924  bp->mac_addr[3] +
1925  (bp->mac_addr[4] << 8) +
1926  (bp->mac_addr[5] << 16);
1927  REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
1928 
1929  /* Program the MTU. Also include 4 bytes for CRC32. */
1930  val = ETH_MAX_MTU + ETH_HLEN + 4;
1931  if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
1932  val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
1933  REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
1934 
1935  bp->last_status_idx = 0;
1936  bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
1937 
1938  /* Set up how to generate a link change interrupt. */
1939  REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1940 
1941  REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
1942  (u64) bp->status_blk_mapping & 0xffffffff);
1943  REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
1944 
1945  REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
1946  (u64) bp->stats_blk_mapping & 0xffffffff);
1947  REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
1948  (u64) bp->stats_blk_mapping >> 32);
1949 
1950  REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
1951  (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
1952 
1953  REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
1954  (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
1955 
1956  REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
1957  (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
1958 
1959  REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
1960 
1961  REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
1962 
1963  REG_WR(bp, BNX2_HC_COM_TICKS,
1964  (bp->com_ticks_int << 16) | bp->com_ticks);
1965 
1966  REG_WR(bp, BNX2_HC_CMD_TICKS,
1967  (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
1968 
1969  REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
1970  REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
1971 
1972  if (CHIP_ID(bp) == CHIP_ID_5706_A1)
1973  REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
1974  else {
1975  REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
1976  BNX2_HC_CONFIG_TX_TMR_MODE |
1977  BNX2_HC_CONFIG_COLLECT_STATS);
1978  }
1979 
1980  /* Clear internal stats counters. */
1981  REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
1982 
1983  REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
1984 
1985  if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
1986  BNX2_PORT_FEATURE_ASF_ENABLED)
1987  bp->flags |= ASF_ENABLE_FLAG;
1988 
1989  /* Initialize the receive filter. */
1990  bnx2_set_rx_mode(bp->nic);
1991 
1992  rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
1993  0);
1994 
1995  REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
1996  REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
1997 
1998  udelay(20);
1999 
2000  bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
2001 
2002  return rc;
2003 }
2004 
2005 static void
2006 bnx2_init_tx_ring(struct bnx2 *bp)
2007 {
2008  struct tx_bd *txbd;
2009  u32 val;
2010 
2011  txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2012 
2013  /* Etherboot lives below 4GB, so hi is always 0 */
2014  txbd->tx_bd_haddr_hi = 0;
2015  txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
2016 
2017  bp->tx_prod = 0;
2018  bp->tx_cons = 0;
2019  bp->hw_tx_cons = 0;
2020  bp->tx_prod_bseq = 0;
2021 
2022  val = BNX2_L2CTX_TYPE_TYPE_L2;
2023  val |= BNX2_L2CTX_TYPE_SIZE_L2;
2024  CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2025 
2026  val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2027  val |= 8 << 16;
2028  CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2029 
2030  /* Etherboot lives below 4GB, so hi is always 0 */
2031  CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
2032 
2033  val = (u64) bp->tx_desc_mapping & 0xffffffff;
2034  CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2035 }
2036 
2037 static void
2038 bnx2_init_rx_ring(struct bnx2 *bp)
2039 {
2040  struct rx_bd *rxbd;
2041  unsigned int i;
2042  u16 prod, ring_prod;
2043  u32 val;
2044 
2045  bp->rx_buf_use_size = RX_BUF_USE_SIZE;
2046  bp->rx_buf_size = RX_BUF_SIZE;
2047 
2048  ring_prod = prod = bp->rx_prod = 0;
2049  bp->rx_cons = 0;
2050  bp->hw_rx_cons = 0;
2051  bp->rx_prod_bseq = 0;
2052 
2053  memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf));
2054 
2055  rxbd = &bp->rx_desc_ring[0];
2056  for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2057  rxbd->rx_bd_len = bp->rx_buf_use_size;
2058  rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
2059  }
2060  rxbd->rx_bd_haddr_hi = 0;
2061  rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
2062 
2063  val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
2064  val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
2065  val |= 0x02 << 8;
2066  CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
2067 
2068  /* Etherboot doesn't use memory above 4GB, so this is always 0 */
2069  CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
2070 
2071  val = bp->rx_desc_mapping & 0xffffffff;
2072  CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
2073 
2074  for (i = 0; (int) i < bp->rx_ring_size; i++) {
2075  rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
2076  rxbd->rx_bd_haddr_hi = 0;
2077  rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
2078  bp->rx_prod_bseq += bp->rx_buf_use_size;
2079  prod = NEXT_RX_BD(prod);
2080  ring_prod = RX_RING_IDX(prod);
2081  }
2082  bp->rx_prod = prod;
2083 
2084  REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2085 
2086  REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2087 }
2088 
2089 static int
2090 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
2091 {
2092  int rc;
2093 
2094  rc = bnx2_reset_chip(bp, reset_code);
2095  if (rc) {
2096  return rc;
2097  }
2098 
2099  bnx2_init_chip(bp);
2100  bnx2_init_tx_ring(bp);
2101  bnx2_init_rx_ring(bp);
2102  return 0;
2103 }
2104 
2105 static int
2106 bnx2_init_nic(struct bnx2 *bp)
2107 {
2108  int rc;
2109 
2110  if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
2111  return rc;
2112 
2113  bnx2_init_phy(bp);
2114  bnx2_set_link(bp);
2115  return 0;
2116 }
2117 
2118 static int
2119 bnx2_init_board(struct pci_device *pdev, struct nic *nic)
2120 {
2121  unsigned long bnx2reg_base, bnx2reg_len;
2122  struct bnx2 *bp = &bnx2;
2123  int rc;
2124  u32 reg;
2125 
2126  bp->flags = 0;
2127  bp->phy_flags = 0;
2128 
2129  /* enable device (incl. PCI PM wakeup), and bus-mastering */
2130  adjust_pci_device(pdev);
2131 
2132  nic->ioaddr = pdev->ioaddr & ~3;
2133  nic->irqno = 0;
2134 
2135  rc = 0;
2136  bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2137  if (bp->pm_cap == 0) {
2138  printf("Cannot find power management capability, aborting.\n");
2139  rc = -EIO;
2140  goto err_out_disable;
2141  }
2142 
2143  bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
2144  if (bp->pcix_cap == 0) {
2145  printf("Cannot find PCIX capability, aborting.\n");
2146  rc = -EIO;
2147  goto err_out_disable;
2148  }
2149 
2150  bp->pdev = pdev;
2151  bp->nic = nic;
2152 
2153  bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
2154  bnx2reg_len = MB_GET_CID_ADDR(17);
2155 
2156  bp->regview = pci_ioremap(pdev, bnx2reg_base, bnx2reg_len);
2157 
2158  if (!bp->regview) {
2159  printf("Cannot map register space, aborting.\n");
2160  rc = -EIO;
2161  goto err_out_disable;
2162  }
2163 
2164  /* Configure byte swap and enable write to the reg_window registers.
2165  * Rely on CPU to do target byte swapping on big endian systems
2166  * The chip's target access swapping will not swap all accesses
2167  */
2168  pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
2169  BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2170  BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
2171 
2172  bnx2_set_power_state_0(bp);
2173 
2174  bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
2175 
2176  /* Get bus information. */
2177  reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
2178  if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
2179  u32 clkreg;
2180 
2181  bp->flags |= PCIX_FLAG;
2182 
2183  clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
2184 
2185  clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
2186  switch (clkreg) {
2187  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
2188  bp->bus_speed_mhz = 133;
2189  break;
2190 
2191  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
2192  bp->bus_speed_mhz = 100;
2193  break;
2194 
2195  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
2196  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
2197  bp->bus_speed_mhz = 66;
2198  break;
2199 
2200  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
2201  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
2202  bp->bus_speed_mhz = 50;
2203  break;
2204 
2205  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
2206  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
2207  case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
2208  bp->bus_speed_mhz = 33;
2209  break;
2210  }
2211  }
2212  else {
2213  if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
2214  bp->bus_speed_mhz = 66;
2215  else
2216  bp->bus_speed_mhz = 33;
2217  }
2218 
2219  if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
2220  bp->flags |= PCI_32BIT_FLAG;
2221 
2222  /* 5706A0 may falsely detect SERR and PERR. */
2223  if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2224  reg = REG_RD(bp, PCI_COMMAND);
2225  reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2226  REG_WR(bp, PCI_COMMAND, reg);
2227  }
2228  else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
2229  !(bp->flags & PCIX_FLAG)) {
2230 
2231  printf("5706 A1 can only be used in a PCIX bus, aborting.\n");
2232  goto err_out_disable;
2233  }
2234 
2235  bnx2_init_nvram(bp);
2236 
2237  reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
2238 
2239  if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
2240  BNX2_SHM_HDR_SIGNATURE_SIG)
2241  bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
2242  else
2243  bp->shmem_base = HOST_VIEW_SHMEM_BASE;
2244 
2245  /* Get the permanent MAC address. First we need to make sure the
2246  * firmware is actually running.
2247  */
2248  reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
2249 
2250  if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
2251  BNX2_DEV_INFO_SIGNATURE_MAGIC) {
2252  printf("Firmware not running, aborting.\n");
2253  rc = -ENODEV;
2254  goto err_out_disable;
2255  }
2256 
2257  bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
2258 
2259  reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
2260  bp->mac_addr[0] = (u8) (reg >> 8);
2261  bp->mac_addr[1] = (u8) reg;
2262 
2263  reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
2264  bp->mac_addr[2] = (u8) (reg >> 24);
2265  bp->mac_addr[3] = (u8) (reg >> 16);
2266  bp->mac_addr[4] = (u8) (reg >> 8);
2267  bp->mac_addr[5] = (u8) reg;
2268 
2269  bp->tx_ring_size = MAX_TX_DESC_CNT;
2270  bp->rx_ring_size = RX_BUF_CNT;
2271  bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
2272 
2273  bp->rx_offset = RX_OFFSET;
2274 
2275  bp->tx_quick_cons_trip_int = 20;
2276  bp->tx_quick_cons_trip = 20;
2277  bp->tx_ticks_int = 80;
2278  bp->tx_ticks = 80;
2279 
2280  bp->rx_quick_cons_trip_int = 6;
2281  bp->rx_quick_cons_trip = 6;
2282  bp->rx_ticks_int = 18;
2283  bp->rx_ticks = 18;
2284 
2285  bp->stats_ticks = 1000000 & 0xffff00;
2286 
2287  bp->phy_addr = 1;
2288 
2289  /* No need for WOL support in Etherboot */
2290  bp->flags |= NO_WOL_FLAG;
2291 
2292  /* Disable WOL support if we are running on a SERDES chip. */
2293  if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
2294  bp->phy_flags |= PHY_SERDES_FLAG;
2295  if (CHIP_NUM(bp) == CHIP_NUM_5708) {
2296  bp->phy_addr = 2;
2297  reg = REG_RD_IND(bp, bp->shmem_base +
2298  BNX2_SHARED_HW_CFG_CONFIG);
2299  if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
2300  bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
2301  }
2302  }
2303 
2304  if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2305  bp->tx_quick_cons_trip_int =
2306  bp->tx_quick_cons_trip;
2307  bp->tx_ticks_int = bp->tx_ticks;
2308  bp->rx_quick_cons_trip_int =
2309  bp->rx_quick_cons_trip;
2310  bp->rx_ticks_int = bp->rx_ticks;
2311  bp->comp_prod_trip_int = bp->comp_prod_trip;
2312  bp->com_ticks_int = bp->com_ticks;
2313  bp->cmd_ticks_int = bp->cmd_ticks;
2314  }
2315 
2316  bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
2317  bp->req_line_speed = 0;
2318  if (bp->phy_flags & PHY_SERDES_FLAG) {
2319  bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
2320 
2321  reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
2322  reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
2323  if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
2324  bp->autoneg = 0;
2325  bp->req_line_speed = bp->line_speed = SPEED_1000;
2326  bp->req_duplex = DUPLEX_FULL;
2327  }
2328  }
2329  else {
2330  bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
2331  }
2332 
2333  bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
2334 
2335  /* Disable driver heartbeat checking */
2336  REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
2337  BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE);
2338  REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
2339 
2340  return 0;
2341 
2342 err_out_disable:
2343  bnx2_disable(nic);
2344 
2345  return rc;
2346 }
2347 
2348 static void
2349 bnx2_transmit(struct nic *nic, const char *dst_addr,
2350  unsigned int type, unsigned int size, const char *packet)
2351 {
2352  /* Sometimes the nic will be behind by a frame. Using two transmit
2353  * buffers prevents us from timing out in that case.
2354  */
2355  static struct eth_frame {
2356  uint8_t dst_addr[ETH_ALEN];
2357  uint8_t src_addr[ETH_ALEN];
2358  uint16_t type;
2359  uint8_t data [ETH_FRAME_LEN - ETH_HLEN];
2360  } frame[2];
2361  static int frame_idx = 0;
2362 
2363  /* send the packet to destination */
2364  struct tx_bd *txbd;
2365  struct bnx2 *bp = &bnx2;
2366  u16 prod, ring_prod;
2367  u16 hw_cons;
2368  int i = 0;
2369 
2370  prod = bp->tx_prod;
2371  ring_prod = TX_RING_IDX(prod);
2372  hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
2373  if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2374  hw_cons++;
2375  }
2376 
2377  while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) {
2378  mdelay(10); /* give the nic a chance */
2379  //poll_interruptions();
2380  if (++i > 500) { /* timeout 5s for transmit */
2381  printf("transmit timed out\n");
2382  bnx2_disable(bp->nic);
2383  bnx2_init_board(bp->pdev, bp->nic);
2384  return;
2385  }
2386  }
2387  if (i != 0) {
2388  printf("#");
2389  }
2390 
2391  /* Copy the packet to the our local buffer */
2392  memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
2393  memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
2394  frame[frame_idx].type = htons(type);
2395  memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
2396  memcpy(&frame[frame_idx].data, packet, size);
2397 
2398  /* Setup the ring buffer entry to transmit */
2399  txbd = &bp->tx_desc_ring[ring_prod];
2400  txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2401  txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]);
2402  txbd->tx_bd_mss_nbytes = (size + ETH_HLEN);
2403  txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
2404 
2405  /* Advance to the next entry */
2406  prod = NEXT_TX_BD(prod);
2407  frame_idx ^= 1;
2408 
2409  bp->tx_prod_bseq += (size + ETH_HLEN);
2410 
2411  REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
2412  REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
2413 
2414  wmb();
2415 
2416  bp->tx_prod = prod;
2417 }
2418 
2419 static int
2420 bnx2_poll_link(struct bnx2 *bp)
2421 {
2422  u32 new_link_state, old_link_state, emac_status;
2423 
2424  new_link_state = bp->status_blk->status_attn_bits &
2425  STATUS_ATTN_BITS_LINK_STATE;
2426 
2427  old_link_state = bp->status_blk->status_attn_bits_ack &
2428  STATUS_ATTN_BITS_LINK_STATE;
2429 
2430  if (!new_link_state && !old_link_state) {
2431  /* For some reason the card doesn't always update the link
2432  * status bits properly. Kick the stupid thing and try again.
2433  */
2434  u32 bmsr;
2435 
2436  bnx2_read_phy(bp, MII_BMSR, &bmsr);
2437  bnx2_read_phy(bp, MII_BMSR, &bmsr);
2438 
2439  if ((bp->phy_flags & PHY_SERDES_FLAG) &&
2440  (CHIP_NUM(bp) == CHIP_NUM_5706)) {
2441  REG_RD(bp, BNX2_EMAC_STATUS);
2442  }
2443 
2444  new_link_state = bp->status_blk->status_attn_bits &
2445  STATUS_ATTN_BITS_LINK_STATE;
2446 
2447  old_link_state = bp->status_blk->status_attn_bits_ack &
2448  STATUS_ATTN_BITS_LINK_STATE;
2449 
2450  /* Okay, for some reason the above doesn't work with some
2451  * switches (like HP ProCurve). If the above doesn't work,
2452  * check the MAC directly to see if we have a link. Perhaps we
2453  * should always check the MAC instead probing the MII.
2454  */
2455  if (!new_link_state && !old_link_state) {
2456  emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
2457  if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) {
2458  /* Acknowledge the link change */
2459  REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
2460  } else if (emac_status & BNX2_EMAC_STATUS_LINK) {
2461  new_link_state = !old_link_state;
2462  }
2463  }
2464 
2465  }
2466 
2467  if (new_link_state != old_link_state) {
2468  if (new_link_state) {
2469  REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
2470  STATUS_ATTN_BITS_LINK_STATE);
2471  }
2472  else {
2473  REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
2474  STATUS_ATTN_BITS_LINK_STATE);
2475  }
2476 
2477  bnx2_set_link(bp);
2478 
2479  /* This is needed to take care of transient status
2480  * during link changes.
2481  */
2482 
2483  REG_WR(bp, BNX2_HC_COMMAND,
2484  bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2485  REG_RD(bp, BNX2_HC_COMMAND);
2486 
2487  }
2488 
2489  return bp->link_up;
2490 }
2491 
2492 static int
2493 bnx2_poll(struct nic* nic, int retrieve)
2494 {
2495  struct bnx2 *bp = &bnx2;
2496  struct rx_bd *cons_bd, *prod_bd;
2497  u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2498  struct l2_fhdr *rx_hdr;
2499  int result = 0;
2500  unsigned int len;
2501  unsigned char *data;
2502  u32 status;
2503 
2504 #if 0
2505  if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2506  (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2507  BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) {
2508 
2509  bp->last_status_idx = bp->status_blk->status_idx;
2510  REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2511  BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2512  BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2513  bp->last_status_idx);
2514  return 0;
2515  }
2516 #endif
2517 
2518  if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
2519  return 1;
2520 
2521  if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
2522 
2523  hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
2524  if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2525  hw_cons++;
2526  }
2527  sw_cons = bp->rx_cons;
2528  sw_prod = bp->rx_prod;
2529 
2530  rmb();
2531  if (sw_cons != hw_cons) {
2532 
2533  sw_ring_cons = RX_RING_IDX(sw_cons);
2534  sw_ring_prod = RX_RING_IDX(sw_prod);
2535 
2536  data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
2537 
2538  rx_hdr = (struct l2_fhdr *)data;
2539  len = rx_hdr->l2_fhdr_pkt_len - 4;
2540  if ((len > (ETH_MAX_MTU + ETH_HLEN)) ||
2541  ((status = rx_hdr->l2_fhdr_status) &
2542  (L2_FHDR_ERRORS_BAD_CRC |
2543  L2_FHDR_ERRORS_PHY_DECODE |
2544  L2_FHDR_ERRORS_ALIGNMENT |
2545  L2_FHDR_ERRORS_TOO_SHORT |
2546  L2_FHDR_ERRORS_GIANT_FRAME))) {
2547  result = 0;
2548  }
2549  else
2550  {
2551  nic->packetlen = len;
2552  memcpy(nic->packet, data + bp->rx_offset, len);
2553  result = 1;
2554  }
2555 
2556  /* Reuse the buffer */
2557  bp->rx_prod_bseq += bp->rx_buf_use_size;
2558  if (sw_cons != sw_prod) {
2559  cons_bd = &bp->rx_desc_ring[sw_ring_cons];
2560  prod_bd = &bp->rx_desc_ring[sw_ring_prod];
2561  prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
2562  prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2563  }
2564 
2565  sw_cons = NEXT_RX_BD(sw_cons);
2566  sw_prod = NEXT_RX_BD(sw_prod);
2567 
2568  }
2569 
2570  bp->rx_cons = sw_cons;
2571  bp->rx_prod = sw_prod;
2572 
2573  REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
2574 
2575  REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2576 
2577  wmb();
2578 
2579  }
2580 
2581  bnx2_poll_link(bp);
2582 
2583 #if 0
2584  bp->last_status_idx = bp->status_blk->status_idx;
2585  rmb();
2586 
2587  REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2588  BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2589  BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2590  bp->last_status_idx);
2591 
2592  REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2593 #endif
2594 
2595  return result;
2596 }
2597 
2598 static void
2599 bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
2600 {
2601  switch ( action ) {
2602  case DISABLE: break;
2603  case ENABLE: break;
2604  case FORCE: break;
2605  }
2606 }
2607 
2608 static struct nic_operations bnx2_operations = {
2609  .connect = dummy_connect,
2610  .poll = bnx2_poll,
2611  .transmit = bnx2_transmit,
2612  .irq = bnx2_irq,
2613 };
2614 
2615 static int
2616 bnx2_probe(struct nic *nic, struct pci_device *pdev)
2617 {
2618  struct bnx2 *bp = &bnx2;
2619  int i, rc;
2620 
2621  memset(bp, 0, sizeof(*bp));
2622 
2623  rc = bnx2_init_board(pdev, nic);
2624  if (rc < 0) {
2625  return 0;
2626  }
2627 
2628  /*
2629  nic->disable = bnx2_disable;
2630  nic->transmit = bnx2_transmit;
2631  nic->poll = bnx2_poll;
2632  nic->irq = bnx2_irq;
2633  */
2634 
2635  nic->nic_op = &bnx2_operations;
2636 
2637  memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
2638  printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
2639  printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
2640  (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
2641  (int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
2642  ((bp->flags & PCIX_FLAG) ? "-X" : ""),
2643  ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
2644  bp->bus_speed_mhz);
2645 
2646  bnx2_set_power_state_0(bp);
2647  bnx2_disable_int(bp);
2648 
2649  bnx2_alloc_mem(bp);
2650 
2651  rc = bnx2_init_nic(bp);
2652  if (rc) {
2653  return 0;
2654  }
2655 
2656  bnx2_poll_link(bp);
2657  for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
2658  mdelay(1);
2659  bnx2_poll_link(bp);
2660  }
2661 #if 1
2662  if (!bp->link_up){
2663  printf("Valid link not established\n");
2664  goto err_out_disable;
2665  }
2666 #endif
2667 
2668  return 1;
2669 
2670 err_out_disable:
2671  bnx2_disable(nic);
2672  return 0;
2673 }
2674 
2675 static void
2676 bnx2_remove(struct nic *nic, void *hwdev __unused)
2677 {
2678  bnx2_disable(nic);
2679 }
2680 
2681 static struct pci_device_id bnx2_nics[] = {
2682  PCI_ROM(0x14e4, 0x164a, "bnx2-5706", "Broadcom NetXtreme II BCM5706", 0),
2683  PCI_ROM(0x14e4, 0x164c, "bnx2-5708", "Broadcom NetXtreme II BCM5708", 0),
2684  PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S", "Broadcom NetXtreme II BCM5706S", 0),
2685  PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S", "Broadcom NetXtreme II BCM5708S", 0),
2686 };
2687 
2688 PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS );
2689 
2690 DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver,
2691  bnx2_probe, bnx2_remove, bnx2_bss );
2692 
2693 /*
2694 static struct pci_driver bnx2_driver __pci_driver = {
2695  .type = NIC_DRIVER,
2696  .name = "BNX2",
2697  .probe = bnx2_probe,
2698  .ids = bnx2_nics,
2699  .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]),
2700  .class = 0,
2701 };
2702 */
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L2_FHDR_ERRORS_ALIGNMENT
#define L2_FHDR_ERRORS_ALIGNMENT
Definition: bnx2.h:382
rc
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
BNX2_HC_RX_TICKS
#define BNX2_HC_RX_TICKS
Definition: bnx2.h:2893
bnx2_disable
static void bnx2_disable(struct nic *nic __unused)
Definition: bnx2.c:1835
bnx2_RXP_b06FwSbssAddr
static u32 bnx2_RXP_b06FwSbssAddr
Definition: bnx2_fw.h:990
uint16_t
unsigned short uint16_t
Definition: stdint.h:11
BNX2_EMAC_MULTICAST_HASH0
#define BNX2_EMAC_MULTICAST_HASH0
Definition: bnx2.h:1707
SEEPROM_BYTE_ADDR_MASK
#define SEEPROM_BYTE_ADDR_MASK
Definition: bnx2.h:3945
BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
Definition: bnx2.h:512
BNX2_NVM_ACCESS_ENABLE_EN
#define BNX2_NVM_ACCESS_ENABLE_EN
Definition: bnx2.h:1240
BNX2_RBUF_COMMAND
#define BNX2_RBUF_COMMAND
Definition: bnx2.h:2388
wmb
wmb()
BNX2_FW_MSG_STATUS_MASK
#define BNX2_FW_MSG_STATUS_MASK
Definition: bnx2.h:4312
BNX2_RBUF_FW_BUF_ALLOC
#define BNX2_RBUF_FW_BUF_ALLOC
Definition: bnx2.h:2406
BCM5708S_1000X_STAT1_SPEED_10
#define BCM5708S_1000X_STAT1_SPEED_10
Definition: bnx2.h:3849
BNX2_RBUF_STATUS1
#define BNX2_RBUF_STATUS1
Definition: bnx2.h:2395
bnx2_TPAT_b06FwTextAddr
static const u32 bnx2_TPAT_b06FwTextAddr
Definition: bnx2_fw.h:2332
BNX2_EMAC_MODE_MPKT
#define BNX2_EMAC_MODE_MPKT
Definition: bnx2.h:1544
eth_frame::type
u16 type
Definition: amd8111e.c:85
fw_info::data_addr
u32 data_addr
Definition: bnx2.h:4246
BNX2_RXP_CPU_MODE
#define BNX2_RXP_CPU_MODE
Definition: bnx2.h:3363
bss
Definition: bnx2.c:39
fw_info::sbss_addr
u32 sbss_addr
Definition: bnx2.h:4252
bnx2_TPAT_b06FwTextLen
static const int bnx2_TPAT_b06FwTextLen
Definition: bnx2_fw.h:2333
printf
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
fw_info::sbss_len
u32 sbss_len
Definition: bnx2.h:4253
BNX2_DMA_CONFIG
#define BNX2_DMA_CONFIG
Definition: bnx2.h:1270
TX_RING_IDX
#define TX_RING_IDX(x)
Definition: bnx2.h:3896
cpu_reg::state_value_clear
u32 state_value_clear
Definition: bnx2.h:4219
BCM5708S_1000X_STAT1_TX_PAUSE
#define BCM5708S_1000X_STAT1_TX_PAUSE
Definition: bnx2.h:3853
ADVERTISE_1000FULL
#define ADVERTISE_1000FULL
Definition: mii.h:133
bnx2_poll_link
static int bnx2_poll_link(struct bnx2 *bp)
Definition: bnx2.c:2420
BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
Definition: bnx2.h:459
BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
Definition: bnx2.h:456
pci_driver
A PCI driver.
Definition: pci.h:251
BNX2_RV2P_PROC1_ADDR_CMD
#define BNX2_RV2P_PROC1_ADDR_CMD
Definition: bnx2.h:2505
EBUSY
#define EBUSY
Device or resource busy.
Definition: errno.h:338
BNX2_LINK_STATUS_1000HALF
#define BNX2_LINK_STATUS_1000HALF
Definition: bnx2.h:4327
DRIVER
DRIVER("BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_remove, bnx2_bss)
bnx2_TXP_b06FwSbssLen
static const int bnx2_TXP_b06FwSbssLen
Definition: bnx2_fw.h:2556
tx_bd::tx_bd_vlan_tag_flags
u32 tx_bd_vlan_tag_flags
Definition: bnx2.h:154
BCM5708S_1000X_CTL1_AUTODET_EN
#define BCM5708S_1000X_CTL1_AUTODET_EN
Definition: bnx2.h:3837
reg
static unsigned int unsigned int reg
Definition: myson.h:162
BNX2_TPAT_CPU_MODE
#define BNX2_TPAT_CPU_MODE
Definition: bnx2.h:3268
ADVERTISE_1000XPAUSE
#define ADVERTISE_1000XPAUSE
Definition: mii.h:79
l2_fhdr
Definition: bnx2.h:367
fw_info::start_addr
u32 start_addr
Definition: bnx2.h:4237
BNX2_LINK_STATUS_AN_ENABLED
#define BNX2_LINK_STATUS_AN_ENABLED
Definition: bnx2.h:4331
BNX2_TPAT_CPU_INSTRUCTION
#define BNX2_TPAT_CPU_INSTRUCTION
Definition: bnx2.h:3311
BNX2_RPM_CONFIG
#define BNX2_RPM_CONFIG
Definition: bnx2.h:2032
BNX2_COM_CPU_MODE_SOFT_HALT
#define BNX2_COM_CPU_MODE_SOFT_HALT
Definition: bnx2.h:3486
val
void __asmcall int val
Definition: setjmp.h:12
bnx2_5708s_linkup
static int bnx2_5708s_linkup(struct bnx2 *bp)
Definition: bnx2.c:461
BNX2_COM_CPU_MODE_STEP_ENA
#define BNX2_COM_CPU_MODE_STEP_ENA
Definition: bnx2.h:3481
ADVERTISE_10FULL
#define ADVERTISE_10FULL
Definition: mii.h:76
bss::rx_buf
unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE]
Definition: bnx2.c:42
BUFFERED_FLASH_PAGE_SIZE
#define BUFFERED_FLASH_PAGE_SIZE
Definition: bnx2.h:3952
bnx2_RXP_b06FwRodataLen
static int bnx2_RXP_b06FwRodataLen
Definition: bnx2_fw.h:987
pci_find_capability
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:38
SEEPROM_PAGE_SIZE
#define SEEPROM_PAGE_SIZE
Definition: bnx2.h:3946
bnx2_reset_chip
static int bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
Definition: bnx2.c:1754
RX_BUF_SIZE
#define RX_BUF_SIZE
Definition: 3c90x.h:269
PHY_ALL_1000_SPEED
#define PHY_ALL_1000_SPEED
Definition: bnx2.c:894
bnx2_nics
static struct pci_device_id bnx2_nics[]
Definition: bnx2.c:2681
bnx2_set_link
static int bnx2_set_link(struct bnx2 *bp)
Definition: bnx2.c:660
VALID_LINK_TIMEOUT
#define VALID_LINK_TIMEOUT
Definition: etherboot.h:34
pci_device::ioaddr
unsigned long ioaddr
I/O address.
Definition: pci.h:225
bnx2_COM_b06FwRodata
static u32 bnx2_COM_b06FwRodata[(0x58/4)+1]
Definition: bnx2_fw.h:970
errno.h
Error codes.
bss::stats_blk
struct statistics_block stats_blk
Definition: bnx2.c:44
bnx2_COM_b06FwRodataLen
static const int bnx2_COM_b06FwRodataLen
Definition: bnx2_fw.h:26
fw_info::ver_minor
u32 ver_minor
Definition: bnx2.h:4234
BNX2_LINK_STATUS_10FULL
#define BNX2_LINK_STATUS_10FULL
Definition: bnx2.h:4323
BNX2_RXP_CPU_INSTRUCTION
#define BNX2_RXP_CPU_INSTRUCTION
Definition: bnx2.h:3406
bnx2_COM_b06FwRodataAddr
static const u32 bnx2_COM_b06FwRodataAddr
Definition: bnx2_fw.h:25
MB_TX_CID_ADDR
#define MB_TX_CID_ADDR
Definition: bnx2.h:3932
eth_frame
Definition: amd8111e.c:82
BCM5708S_BLK_ADDR_DIG
#define BCM5708S_BLK_ADDR_DIG
Definition: bnx2.h:3829
BNX2_DRV_MSG_CODE_RESET
#define BNX2_DRV_MSG_CODE_RESET
Definition: bnx2.h:4293
BNX2_DRV_MSG_CODE
#define BNX2_DRV_MSG_CODE
Definition: bnx2.h:4292
BNX2_CTX_DATA
#define BNX2_CTX_DATA
Definition: bnx2.h:1482
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
Definition: bnx2.h:486
cpu_reg
Definition: bnx2.h:4213
BNX2_RV2P_PROC1_ADDR_CMD_RDWR
#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR
Definition: bnx2.h:2507
BNX2_DRV_MSG_DATA_WAIT0
#define BNX2_DRV_MSG_DATA_WAIT0
Definition: bnx2.h:4303
PCI_PM_CTRL_PME_STATUS
#define PCI_PM_CTRL_PME_STATUS
PME pin status.
Definition: pci.h:108
BNX2_DRV_MSG_DATA_WAIT1
#define BNX2_DRV_MSG_DATA_WAIT1
Definition: bnx2.h:4304
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
Definition: bnx2.h:483
ADVERTISED_100baseT_Half
#define ADVERTISED_100baseT_Half
Definition: bnx2.h:44
bnx2_init_chip
static int bnx2_init_chip(struct bnx2 *bp)
Definition: bnx2.c:1846
BNX2_TXP_CPU_REG_FILE
#define BNX2_TXP_CPU_REG_FILE
Definition: bnx2.h:3239
type
uint32_t type
Operating system type.
Definition: ena.h:12
bnx2_RXP_b06FwTextLen
static int bnx2_RXP_b06FwTextLen
Definition: bnx2_fw.h:983
pci_write_config_word
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
bnx2_setup_phy
static int bnx2_setup_phy(struct bnx2 *bp)
Definition: bnx2.c:992
PCI_CAP_ID_PM
#define PCI_CAP_ID_PM
Power management.
Definition: pci.h:94
BNX2_TXP_CPU_MODE
#define BNX2_TXP_CPU_MODE
Definition: bnx2.h:3173
fw_info::rodata_index
u32 rodata_index
Definition: bnx2.h:4266
BNX2_EMAC_TX_MODE
#define BNX2_EMAC_TX_MODE
Definition: bnx2.h:1668
bnx2_COM_b06FwReleaseMajor
static const int bnx2_COM_b06FwReleaseMajor
Definition: bnx2_fw.h:17
BNX2_EMAC_RX_MODE
#define BNX2_EMAC_RX_MODE
Definition: bnx2.h:1688
bnx2_COM_b06FwStartAddr
static const u32 bnx2_COM_b06FwStartAddr
Definition: bnx2_fw.h:20
size
uint16_t size
Buffer size.
Definition: dwmac.h:14
bnx2_transmit
static void bnx2_transmit(struct nic *nic, const char *dst_addr, unsigned int type, unsigned int size, const char *packet)
Definition: bnx2.c:2349
BNX2_EMAC_MODE_PORT_MII
#define BNX2_EMAC_MODE_PORT_MII
Definition: bnx2.h:1534
REG_WR
#define REG_WR(bp, offset, val)
Definition: bnx2.h:4194
BNX2_HC_TX_QUICK_CONS_TRIP
#define BNX2_HC_TX_QUICK_CONS_TRIP
Definition: bnx2.h:2881
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
Definition: bnx2.h:481
BNX2_NVM_ACCESS_ENABLE
#define BNX2_NVM_ACCESS_ENABLE
Definition: bnx2.h:1239
bnx2_TPAT_b06FwReleaseFix
static const int bnx2_TPAT_b06FwReleaseFix
Definition: bnx2_fw.h:2330
PHY_2_5G_CAPABLE_FLAG
#define PHY_2_5G_CAPABLE_FLAG
Definition: bnx2.h:4064
BNX2_EMAC_RX_MODE_FLOW_EN
#define BNX2_EMAC_RX_MODE_FLOW_EN
Definition: bnx2.h:1690
bnx2_fw.h
BNX2_L2CTX_TBDR_BHADDR_LO
#define BNX2_L2CTX_TBDR_BHADDR_LO
Definition: bnx2.h:425
BNX2_RXP_CPU_EVENT_MASK
#define BNX2_RXP_CPU_EVENT_MASK
Definition: bnx2.h:3392
fw_info::ver_major
u32 ver_major
Definition: bnx2.h:4233
BNX2_EMAC_BACKOFF_SEED
#define BNX2_EMAC_BACKOFF_SEED
Definition: bnx2.h:1609
bss::status_blk
struct status_block status_blk
Definition: bnx2.c:43
bnx2_COM_b06FwBssAddr
static const u32 bnx2_COM_b06FwBssAddr
Definition: bnx2_fw.h:27
fw_info::text_len
u32 text_len
Definition: bnx2.h:4241
l2_fhdr::l2_fhdr_status
u32 l2_fhdr_status
Definition: bnx2.h:368
BMCR_ANRESTART
#define BMCR_ANRESTART
Definition: mii.h:46
bp
uint16_t bp
Definition: registers.h:23
BNX2_PCICFG_MISC_STATUS
#define BNX2_PCICFG_MISC_STATUS
Definition: bnx2.h:466
bnx2_copper_linkup
static int bnx2_copper_linkup(struct bnx2 *bp)
Definition: bnx2.c:527
ADVERTISE_100FULL
#define ADVERTISE_100FULL
Definition: mii.h:80
BNX2_PCICFG_MISC_CONFIG
#define BNX2_PCICFG_MISC_CONFIG
Definition: bnx2.h:454
PHY_INT_MODE_MASK_FLAG
#define PHY_INT_MODE_MASK_FLAG
Definition: bnx2.h:4065
PCI_BASE_ADDRESS_0
#define PCI_BASE_ADDRESS_0
Definition: pci.h:62
BNX2_EMAC_RX_MODE_PROMISCUOUS
#define BNX2_EMAC_RX_MODE_PROMISCUOUS
Definition: bnx2.h:1696
bnx2_TPAT_b06FwBss
static u32 bnx2_TPAT_b06FwBss[(0x250/4)+1]
Definition: bnx2_fw.h:2540
tx_bd::tx_bd_mss_nbytes
u32 tx_bd_mss_nbytes
Definition: bnx2.h:153
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
Definition: bnx2.h:478
pci_read_config_word
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
bnx2_COM_b06FwTextAddr
static const u32 bnx2_COM_b06FwTextAddr
Definition: bnx2_fw.h:21
ETH_MAX_MTU
#define ETH_MAX_MTU
Definition: if_ether.h:14
BNX2_RV2P_COMMAND_PROC2_RESET
#define BNX2_RV2P_COMMAND_PROC2_RESET
Definition: bnx2.h:2447
MAC_LOOPBACK
#define MAC_LOOPBACK
Definition: bnx2.h:4165
bss::rx_desc_ring
struct rx_bd rx_desc_ring[RX_DESC_CNT]
Definition: bnx2.c:41
PCI_COMMAND
#define PCI_COMMAND
PCI command.
Definition: pci.h:25
bnx2_TXP_b06FwDataAddr
static const u32 bnx2_TXP_b06FwDataAddr
Definition: bnx2_fw.h:2549
BNX2_EMAC_MODE_PORT_GMII
#define BNX2_EMAC_MODE_PORT_GMII
Definition: bnx2.h:1535
BNX2_HC_TX_TICKS
#define BNX2_HC_TX_TICKS
Definition: bnx2.h:2897
HOST_VIEW_SHMEM_BASE
#define HOST_VIEW_SHMEM_BASE
Definition: bnx2.h:4578
BNX2_RBUF_FW_BUF_ALLOC_VALUE
#define BNX2_RBUF_FW_BUF_ALLOC_VALUE
Definition: bnx2.h:2407
bnx2_RXP_b06FwDataLen
static int bnx2_RXP_b06FwDataLen
Definition: bnx2_fw.h:985
bnx2_setup_serdes_phy
static int bnx2_setup_serdes_phy(struct bnx2 *bp)
Definition: bnx2.c:784
BNX2_DEV_INFO_BC_REV
#define BNX2_DEV_INFO_BC_REV
Definition: bnx2.h:4390
bnx2_init_5708s_phy
static int bnx2_init_5708s_phy(struct bnx2 *bp)
Definition: bnx2.c:1006
CHIP_ID_5706_A0
#define CHIP_ID_5706_A0
Definition: bnx2.h:4084
BNX2_PORT_HW_CFG_MAC_UPPER
#define BNX2_PORT_HW_CFG_MAC_UPPER
Definition: bnx2.h:4392
bnx2_bss
#define bnx2_bss
Definition: bnx2.c:46
BNX2_L2CTX_CTX_TYPE
#define BNX2_L2CTX_CTX_TYPE
Definition: bnx2.h:436
SPEED_10
#define SPEED_10
Definition: atl1e.h:50
BNX2_DRV_PULSE_MB
#define BNX2_DRV_PULSE_MB
Definition: bnx2.h:4350
PREV_TX_BD
#define PREV_TX_BD(x)
Definition: bnx2.h:3892
BNX2_RXP_CPU_MODE_SOFT_HALT
#define BNX2_RXP_CPU_MODE_SOFT_HALT
Definition: bnx2.h:3370
fw_info::rodata
u32 * rodata
Definition: bnx2.h:4267
CHIP_NUM_5708
#define CHIP_NUM_5708
Definition: bnx2.h:4073
fw_info::text_addr
u32 text_addr
Definition: bnx2.h:4240
BNX2_RPM_SORT_USER0_BC_EN
#define BNX2_RPM_SORT_USER0_BC_EN
Definition: bnx2.h:2054
bnx2_remove
static void bnx2_remove(struct nic *nic, void *hwdev __unused)
Definition: bnx2.c:2676
BNX2_TPAT_CPU_HW_BREAKPOINT
#define BNX2_TPAT_CPU_HW_BREAKPOINT
Definition: bnx2.h:3316
BNX2_CTX_PAGE_TBL
#define BNX2_CTX_PAGE_TBL
Definition: bnx2.h:1476
adjust_pci_device
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:240
fw_info::sbss_index
u32 sbss_index
Definition: bnx2.h:4254
BNX2_EMAC_STATUS
#define BNX2_EMAC_STATUS
Definition: bnx2.h:1548
BNX2_NVM_ACCESS_ENABLE_WR_EN
#define BNX2_NVM_ACCESS_ENABLE_WR_EN
Definition: bnx2.h:1241
BNX2_EMAC_MDIO_COMM_COMMAND_WRITE
#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE
Definition: bnx2.h:1644
BUFFERED_FLASH_BYTE_ADDR_MASK
#define BUFFERED_FLASH_BYTE_ADDR_MASK
Definition: bnx2.h:3951
FILE_LICENCE
FILE_LICENCE(GPL_ANY)
load_cpu_fw
static void load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
Definition: bnx2.c:1354
BNX2_SHARED_HW_CFG_PHY_2_5G
#define BNX2_SHARED_HW_CFG_PHY_2_5G
Definition: bnx2.h:4379
ETHTOOL_ALL_COPPER_SPEED
#define ETHTOOL_ALL_COPPER_SPEED
Definition: bnx2.c:886
BNX2_RV2P_PROC2_ADDR_CMD
#define BNX2_RV2P_PROC2_ADDR_CMD
Definition: bnx2.h:2509
BCM5708S_1000X_CTL2_PLLEL_DET_EN
#define BCM5708S_1000X_CTL2_PLLEL_DET_EN
Definition: bnx2.h:3841
SAIFUN_FLASH_PAGE_BITS
#define SAIFUN_FLASH_PAGE_BITS
Definition: bnx2.h:3955
BNX2_L2CTX_CTX_TYPE_SIZE_L2
#define BNX2_L2CTX_CTX_TYPE_SIZE_L2
Definition: bnx2.h:437
BNX2_LINK_STATUS_AN_COMPLETE
#define BNX2_LINK_STATUS_AN_COMPLETE
Definition: bnx2.h:4332
ASF_ENABLE_FLAG
#define ASF_ENABLE_FLAG
Definition: bnx2.h:4011
dummy_connect
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:175
cpu_reg::mode
u32 mode
Definition: bnx2.h:4214
BNX2_L2CTX_TX_HOST_BSEQ
#define BNX2_L2CTX_TX_HOST_BSEQ
Definition: bnx2.h:419
tx_bd::tx_bd_haddr_lo
u32 tx_bd_haddr_lo
Definition: bnx2.h:152
BNX2_TPAT_CPU_MODE_SOFT_HALT
#define BNX2_TPAT_CPU_MODE_SOFT_HALT
Definition: bnx2.h:3275
rx_bd::rx_bd_haddr_lo
u32 rx_bd_haddr_lo
Definition: bnx2.h:176
bnx2_RXP_b06FwTextAddr
static u32 bnx2_RXP_b06FwTextAddr
Definition: bnx2_fw.h:982
BMCR_LOOPBACK
#define BMCR_LOOPBACK
Definition: mii.h:51
BNX2_NVM_CFG1
#define BNX2_NVM_CFG1
Definition: bnx2.h:1196
bnx2_TPAT_b06FwSbssLen
static const int bnx2_TPAT_b06FwSbssLen
Definition: bnx2_fw.h:2341
BNX2_PCICFG_STATUS_BIT_CLEAR_CMD
#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD
Definition: bnx2.h:517
BNX2_SHM_HDR_SIGNATURE
#define BNX2_SHM_HDR_SIGNATURE
Definition: bnx2.h:3802
FLOW_CTRL_TX
#define FLOW_CTRL_TX
Definition: bnx2.h:4152
BNX2_NVM_CFG2
#define BNX2_NVM_CFG2
Definition: bnx2.h:1210
BNX2_PORT_FEATURE_ASF_ENABLED
#define BNX2_PORT_FEATURE_ASF_ENABLED
Definition: bnx2.h:4423
BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
Definition: bnx2.h:4388
BNX2_EMAC_RX_MODE_SORT_MODE
#define BNX2_EMAC_RX_MODE_SORT_MODE
Definition: bnx2.h:1700
bnx2_COM_b06FwSbssAddr
static const u32 bnx2_COM_b06FwSbssAddr
Definition: bnx2_fw.h:29
L2_FHDR_ERRORS_BAD_CRC
#define L2_FHDR_ERRORS_BAD_CRC
Definition: bnx2.h:380
bus_to_virt
static __always_inline void * bus_to_virt(unsigned long bus_addr)
Convert bus address to a virtual address.
Definition: io.h:195
bnx2_TXP_b06FwRodata
static u32 bnx2_TXP_b06FwRodata[(0x0/4)+1]
Definition: bnx2_fw.h:3492
PCI_DRIVER
PCI_DRIVER(bnx2_driver, bnx2_nics, PCI_NO_CLASS)
BNX2_TXP_CPU_EVENT_MASK
#define BNX2_TXP_CPU_EVENT_MASK
Definition: bnx2.h:3202
BNX2_HC_STATUS_ADDR_H
#define BNX2_HC_STATUS_ADDR_H
Definition: bnx2.h:2878
BNX2_SHM_HDR_ADDR_0
#define BNX2_SHM_HDR_ADDR_0
Definition: bnx2.h:3808
bnx2_COM_b06FwReleaseMinor
static const int bnx2_COM_b06FwReleaseMinor
Definition: bnx2_fw.h:18
BNX2_EMAC_MDIO_COMM_START_BUSY
#define BNX2_EMAC_MDIO_COMM_START_BUSY
Definition: bnx2.h:1648
MB_KERNEL_CTX_SIZE
#define MB_KERNEL_CTX_SIZE
Definition: bnx2.h:3921
BMCR_SPEED1000
#define BMCR_SPEED1000
Definition: mii.h:43
REG_RD_IND
#define REG_RD_IND(bp, offset)
Definition: bnx2.h:4200
BNX2_RV2P_INSTR_HIGH
#define BNX2_RV2P_INSTR_HIGH
Definition: bnx2.h:2501
SPEED_100
#define SPEED_100
Definition: atl1e.h:51
bnx2_COM_b06FwBssLen
static const int bnx2_COM_b06FwBssLen
Definition: bnx2_fw.h:28
SEEPROM_TOTAL_SIZE
#define SEEPROM_TOTAL_SIZE
Definition: bnx2.h:3947
bnx2_TPAT_b06FwRodata
static u32 bnx2_TPAT_b06FwRodata[(0x0/4)+1]
Definition: bnx2_fw.h:2539
fw_info::ver_fix
u32 ver_fix
Definition: bnx2.h:4235
MB_RX_CID_ADDR
#define MB_RX_CID_ADDR
Definition: bnx2.h:3933
bnx2_read_phy
static int bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
Definition: bnx2.c:160
bnx2_TXP_b06FwSbss
static u32 bnx2_TXP_b06FwSbss[(0x38/4)+1]
Definition: bnx2_fw.h:3494
bnx2_TPAT_b06FwDataAddr
static const u32 bnx2_TPAT_b06FwDataAddr
Definition: bnx2_fw.h:2334
bnx2_reset_phy
static int bnx2_reset_phy(struct bnx2 *bp)
Definition: bnx2.c:726
BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE
#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE
Definition: bnx2.h:440
frame
unsigned long frame
Definition: xengrant.h:179
DMA_READ_CHANS
#define DMA_READ_CHANS
Definition: bnx2.h:3874
BNX2_EMAC_STATUS_LINK
#define BNX2_EMAC_STATUS_LINK
Definition: bnx2.h:1549
rmb
#define rmb()
Definition: io.h:544
ADVERTISE_1000XHALF
#define ADVERTISE_1000XHALF
Definition: mii.h:77
BNX2_RV2P_PROC2_ADDR_CMD_RDWR
#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR
Definition: bnx2.h:2511
bnx2_set_mac_addr
static void bnx2_set_mac_addr(struct bnx2 *bp)
Definition: bnx2.c:1274
BCM5708S_1000X_CTL1
#define BCM5708S_1000X_CTL1
Definition: bnx2.h:3834
bnx2_RXP_b06FwSbssLen
static int bnx2_RXP_b06FwSbssLen
Definition: bnx2_fw.h:991
RX_OFFSET
#define RX_OFFSET
Definition: bnx2.h:4586
memcpy
void * memcpy(void *dest, const void *src, size_t len) __nonnull
PCI_32BIT_FLAG
#define PCI_32BIT_FLAG
Definition: bnx2.h:4006
nic::ioaddr
unsigned int ioaddr
Definition: nic.h:55
bnx2_COM_b06FwTextLen
static const int bnx2_COM_b06FwTextLen
Definition: bnx2_fw.h:22
BNX2_L2CTX_HOST_BDIDX
#define BNX2_L2CTX_HOST_BDIDX
Definition: bnx2.h:442
bnx2_TPAT_b06FwBssAddr
static const u32 bnx2_TPAT_b06FwBssAddr
Definition: bnx2_fw.h:2338
BNX2_HC_CMD_TICKS
#define BNX2_HC_CMD_TICKS
Definition: bnx2.h:2905
virt_to_bus
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
BNX2_MQ_KNL_BYP_WIND_START
#define BNX2_MQ_KNL_BYP_WIND_START
Definition: bnx2.h:2625
PHY_ALL_10_100_SPEED
#define PHY_ALL_10_100_SPEED
Definition: bnx2.c:891
PCI_PM_CTRL_STATE_MASK
#define PCI_PM_CTRL_STATE_MASK
Current power state.
Definition: pci.h:106
BNX2_TPAT_CPU_MODE_STEP_ENA
#define BNX2_TPAT_CPU_MODE_STEP_ENA
Definition: bnx2.h:3270
bnx2_TXP_b06FwBss
static u32 bnx2_TXP_b06FwBss[(0x1c4/4)+1]
Definition: bnx2_fw.h:3493
PCI_X_CMD_ERO
#define PCI_X_CMD_ERO
Definition: bnx2.h:37
MAX_RX_DESC_CNT
#define MAX_RX_DESC_CNT
Definition: bnx2.h:3885
BNX2_LINK_STATUS_2500FULL
#define BNX2_LINK_STATUS_2500FULL
Definition: bnx2.h:4330
bnx2::rx_mode
u32 rx_mode
Definition: bnx2.h:4140
ETH_HLEN
#define ETH_HLEN
Definition: if_ether.h:9
BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
Definition: bnx2.h:1273
bnx2_enable_nvram_access
static void bnx2_enable_nvram_access(struct bnx2 *bp)
Definition: bnx2.c:1657
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
Definition: bnx2.h:484
STATUS_ATTN_BITS_LINK_STATE
#define STATUS_ATTN_BITS_LINK_STATE
Definition: bnx2.h:192
BNX2_SHARED_HW_CFG_CONFIG
#define BNX2_SHARED_HW_CFG_CONFIG
Definition: bnx2.h:4374
bnx2_set_power_state_0
static int bnx2_set_power_state_0(struct bnx2 *bp)
Definition: bnx2.c:1629
ethernet.h
Ethernet protocol.
BNX2_HC_COMP_PROD_TRIP
#define BNX2_HC_COMP_PROD_TRIP
Definition: bnx2.h:2885
BNX2_TXP_CPU_INSTRUCTION
#define BNX2_TXP_CPU_INSTRUCTION
Definition: bnx2.h:3216
BNX2_RXP_SCRATCH
#define BNX2_RXP_SCRATCH
Definition: bnx2.h:3472
RX_BD_FLAGS_END
#define RX_BD_FLAGS_END
Definition: bnx2.h:181
bnx2_TXP_b06FwText
static u32 bnx2_TXP_b06FwText[(0x5748/4)+1]
Definition: bnx2_fw.h:2557
BNX2_RV2P_CONFIG
#define BNX2_RV2P_CONFIG
Definition: bnx2.h:2459
ETH_FRAME_LEN
#define ETH_FRAME_LEN
Definition: if_ether.h:11
BNX2_COM_CPU_STATE
#define BNX2_COM_CPU_STATE
Definition: bnx2.h:3492
tx_bd
Definition: bnx2.h:150
PHY_INT_MODE_LINK_READY_FLAG
#define PHY_INT_MODE_LINK_READY_FLAG
Definition: bnx2.h:4067
fw_info::bss_index
u32 bss_index
Definition: bnx2.h:4260
BCM5708S_UP1_2G5
#define BCM5708S_UP1_2G5
Definition: bnx2.h:3825
MAX_CID_CNT
#define MAX_CID_CNT
Definition: bnx2.h:3925
ADVERTISED_Autoneg
#define ADVERTISED_Autoneg
Definition: bnx2.h:48
BCM5708S_TX_ACTL1_DRIVER_VCM
#define BCM5708S_TX_ACTL1_DRIVER_VCM
Definition: bnx2.h:3864
bnx2_RXP_b06FwRodataAddr
static u32 bnx2_RXP_b06FwRodataAddr
Definition: bnx2_fw.h:986
BNX2_L2CTX_TBDR_BHADDR_HI
#define BNX2_L2CTX_TBDR_BHADDR_HI
Definition: bnx2.h:424
__unused
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
bnx2_5706s_linkup
static int bnx2_5706s_linkup(struct bnx2 *bp)
Definition: bnx2.c:490
SAIFUN_FLASH_BYTE_ADDR_MASK
#define SAIFUN_FLASH_BYTE_ADDR_MASK
Definition: bnx2.h:3957
BNX2_RV2P_INSTR_LOW
#define BNX2_RV2P_INSTR_LOW
Definition: bnx2.h:2504
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
Definition: bnx2.h:2607
BNX2_PCICFG_MISC_STATUS_32BIT_DET
#define BNX2_PCICFG_MISC_STATUS_32BIT_DET
Definition: bnx2.h:468
BNX2_DMA_CONFIG_DATA_BYTE_SWAP
#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP
Definition: bnx2.h:1271
CHIP_NUM
#define CHIP_NUM(bp)
Definition: bnx2.h:4071
bnx2_alloc_bad_rbuf
static int bnx2_alloc_bad_rbuf(struct bnx2 *bp)
Definition: bnx2.c:1231
len
ring len
Length.
Definition: dwmac.h:231
bnx2_reset_nic
static int bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
Definition: bnx2.c:2090
TX_BD_FLAGS_START
#define TX_BD_FLAGS_START
Definition: bnx2.h:162
TX_DESC_CNT
#define TX_DESC_CNT
Definition: bnx2.h:3880
SPEED_2500
#define SPEED_2500
Definition: bnx2.h:105
RX_DESC_CNT
#define RX_DESC_CNT
Definition: bnx2.h:3884
BNX2_DRV_MSG_DATA_WAIT2
#define BNX2_DRV_MSG_DATA_WAIT2
Definition: bnx2.h:4305
BNX2_COM_CPU_INSTRUCTION
#define BNX2_COM_CPU_INSTRUCTION
Definition: bnx2.h:3522
BNX2_L2CTX_NX_BDHADDR_HI
#define BNX2_L2CTX_NX_BDHADDR_HI
Definition: bnx2.h:445
udelay
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
BMSR_ANEGCOMPLETE
#define BMSR_ANEGCOMPLETE
Definition: mii.h:60
BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
Definition: bnx2.h:826
bnx2_operations
static struct nic_operations bnx2_operations
Definition: bnx2.c:2608
bnx2_init_board
static int bnx2_init_board(struct pci_device *pdev, struct nic *nic)
Definition: bnx2.c:2119
DUPLEX_FULL
#define DUPLEX_FULL
Definition: bnx2.h:111
u64
uint64_t u64
Definition: stdint.h:25
DMA_WRITE_CHANS
#define DMA_WRITE_CHANS
Definition: bnx2.h:3875
BNX2_LINK_STATUS_10HALF
#define BNX2_LINK_STATUS_10HALF
Definition: bnx2.h:4322
BNX2_NVM_WRITE1
#define BNX2_NVM_WRITE1
Definition: bnx2.h:1243
u8
#define u8
Definition: igbvf_osdep.h:40
BNX2_L2CTX_TYPE
#define BNX2_L2CTX_TYPE
Definition: bnx2.h:406
cpu_reg::inst
u32 inst
Definition: bnx2.h:4224
fw_info::text_index
u32 text_index
Definition: bnx2.h:4242
pci_bar_start
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
cpu_reg::pc
u32 pc
Definition: bnx2.h:4223
irq_action_t
irq_action_t
Definition: nic.h:34
MAX_ETHERNET_PACKET_SIZE
#define MAX_ETHERNET_PACKET_SIZE
Definition: bnx2.h:3869
BNX2_HC_STATISTICS_ADDR_H
#define BNX2_HC_STATISTICS_ADDR_H
Definition: bnx2.h:2880
BCM5708S_BLK_ADDR_TX_MISC
#define BCM5708S_BLK_ADDR_TX_MISC
Definition: bnx2.h:3831
bnx2_ctx_wr
static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
Definition: bnx2.c:152
bnx2_TPAT_b06FwBssLen
static const int bnx2_TPAT_b06FwBssLen
Definition: bnx2_fw.h:2339
BNX2_MISC_ENABLE_CLR_BITS
#define BNX2_MISC_ENABLE_CLR_BITS
Definition: bnx2.h:799
BNX2_EMAC_ATTENTION_ENA_LINK
#define BNX2_EMAC_ATTENTION_ENA_LINK
Definition: bnx2.h:1557
BNX2_RXP_CPU_PROGRAM_COUNTER
#define BNX2_RXP_CPU_PROGRAM_COUNTER
Definition: bnx2.h:3405
BNX2_EMAC_MAC_MATCH1
#define BNX2_EMAC_MAC_MATCH1
Definition: bnx2.h:1578
bnx2_TPAT_b06FwReleaseMajor
static const int bnx2_TPAT_b06FwReleaseMajor
Definition: bnx2_fw.h:2328
BNX2_EMAC_MODE_PORT_MII_10
#define BNX2_EMAC_MODE_PORT_MII_10
Definition: bnx2.h:1536
MII_CTRL1000
#define MII_CTRL1000
Definition: mii.h:24
BNX2_TPAT_CPU_STATE
#define BNX2_TPAT_CPU_STATE
Definition: bnx2.h:3281
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
Definition: bnx2.h:480
BCM5708S_BLK_ADDR
#define BCM5708S_BLK_ADDR
Definition: bnx2.h:3827
BNX2_LINK_STATUS_100FULL
#define BNX2_LINK_STATUS_100FULL
Definition: bnx2.h:4326
BNX2_HC_STATS_TICKS
#define BNX2_HC_STATS_TICKS
Definition: bnx2.h:2915
RV2P_PROC1
#define RV2P_PROC1
Definition: bnx2.h:4270
BUFFERED_FLASH_TOTAL_SIZE
#define BUFFERED_FLASH_TOTAL_SIZE
Definition: bnx2.h:3953
ADVERTISE_1000XPSE_ASYM
#define ADVERTISE_1000XPSE_ASYM
Definition: mii.h:81
BCM5708S_1000X_STAT1_SPEED_MASK
#define BCM5708S_1000X_STAT1_SPEED_MASK
Definition: bnx2.h:3848
BNX2_MISC_UNUSED0
#define BNX2_MISC_UNUSED0
Definition: bnx2.h:1141
fw_info::bss_len
u32 bss_len
Definition: bnx2.h:4259
bnx2_init_phy
static int bnx2_init_phy(struct bnx2 *bp)
Definition: bnx2.c:1115
BNX2_HC_STATISTICS_ADDR_L
#define BNX2_HC_STATISTICS_ADDR_L
Definition: bnx2.h:2879
cpu_reg::evmask
u32 evmask
Definition: bnx2.h:4222
bnx2_disable_nvram_access
static void bnx2_disable_nvram_access(struct bnx2 *bp)
Definition: bnx2.c:1668
BNX2_RV2P_COMMAND_PROC1_RESET
#define BNX2_RV2P_COMMAND_PROC1_RESET
Definition: bnx2.h:2446
nic::packetlen
unsigned int packetlen
Definition: nic.h:54
BNX2_PCICFG_MISC_STATUS_PCIX_DET
#define BNX2_PCICFG_MISC_STATUS_PCIX_DET
Definition: bnx2.h:470
fw_info::data_index
u32 data_index
Definition: bnx2.h:4248
rx_bd
Definition: bnx2.h:174
BNX2_COM_CPU_REG_FILE
#define BNX2_COM_CPU_REG_FILE
Definition: bnx2.h:3545
PCI_CAP_ID_PCIX
#define PCI_CAP_ID_PCIX
Definition: bnx2.h:35
BNX2_HC_CONFIG_TX_TMR_MODE
#define BNX2_HC_CONFIG_TX_TMR_MODE
Definition: bnx2.h:2869
BNX2_EMAC_MAC_MATCH0
#define BNX2_EMAC_MAC_MATCH0
Definition: bnx2.h:1577
BNX2_PCICFG_STATUS_BIT_SET_CMD
#define BNX2_PCICFG_STATUS_BIT_SET_CMD
Definition: bnx2.h:516
BNX2_EMAC_MDIO_COMM_COMMAND_READ
#define BNX2_EMAC_MDIO_COMM_COMMAND_READ
Definition: bnx2.h:1645
BNX2_DRV_MSG_DATA
#define BNX2_DRV_MSG_DATA
Definition: bnx2.h:4302
bnx2_TXP_b06FwDataLen
static const int bnx2_TXP_b06FwDataLen
Definition: bnx2_fw.h:2550
bnx2_init_cpus
static void bnx2_init_cpus(struct bnx2 *bp)
Definition: bnx2.c:1428
ADVERTISE_PAUSE_ASYM
#define ADVERTISE_PAUSE_ASYM
Definition: mii.h:84
AUTONEG_FLOW_CTRL
#define AUTONEG_FLOW_CTRL
Definition: bnx2.h:4162
FLASH_BACKUP_STRAP_MASK
#define FLASH_BACKUP_STRAP_MASK
Definition: bnx2.h:3975
bnx2_phy_get_pause_adv
static u32 bnx2_phy_get_pause_adv(struct bnx2 *bp)
Definition: bnx2.c:750
bnx2_init_nic
static int bnx2_init_nic(struct bnx2 *bp)
Definition: bnx2.c:2106
bnx2_COM_b06FwBss
static u32 bnx2_COM_b06FwBss[(0x88/4)+1]
Definition: bnx2_fw.h:975
PCI_PM_CTRL
#define PCI_PM_CTRL
Power management control and status.
Definition: pci.h:105
BMSR_LSTATUS
#define BMSR_LSTATUS
Definition: mii.h:57
BNX2_HC_RX_QUICK_CONS_TRIP
#define BNX2_HC_RX_QUICK_CONS_TRIP
Definition: bnx2.h:2889
PHY_SERDES_FLAG
#define PHY_SERDES_FLAG
Definition: bnx2.h:4061
bnx2_TXP_b06FwData
static u32 bnx2_TXP_b06FwData[(0x0/4)+1]
Definition: bnx2_fw.h:3491
BCM5708S_1000X_STAT1_FD
#define BCM5708S_1000X_STAT1_FD
Definition: bnx2.h:3847
BCM5708S_1000X_CTL1_FIBER_MODE
#define BCM5708S_1000X_CTL1_FIBER_MODE
Definition: bnx2.h:3836
bss::tx_desc_ring
struct tx_bd tx_desc_ring[TX_DESC_CNT]
Definition: bnx2.c:40
l2_fhdr::l2_fhdr_pkt_len
u16 l2_fhdr_pkt_len
Definition: bnx2.h:390
bnx2_TXP_b06FwRodataLen
static const int bnx2_TXP_b06FwRodataLen
Definition: bnx2_fw.h:2552
BNX2_EMAC_STATUS_LINK_CHANGE
#define BNX2_EMAC_STATUS_LINK_CHANGE
Definition: bnx2.h:1550
NUM_MC_HASH_REGISTERS
#define NUM_MC_HASH_REGISTERS
Definition: bnx2.h:3812
BNX2_TXP_CPU_HW_BREAKPOINT
#define BNX2_TXP_CPU_HW_BREAKPOINT
Definition: bnx2.h:3221
BNX2_COM_SCRATCH
#define BNX2_COM_SCRATCH
Definition: bnx2.h:3609
pci.h
PCI bus.
bnx2_RXP_b06FwSbss
static u32 bnx2_RXP_b06FwSbss[(0x1c/4)+1]
Definition: bnx2_fw.h:1944
REG_RD
#define REG_RD(bp, offset)
Definition: bnx2.h:4191
bnx2_COM_b06FwDataLen
static const int bnx2_COM_b06FwDataLen
Definition: bnx2_fw.h:24
BCM5708S_BLK_ADDR_DIG3
#define BCM5708S_BLK_ADDR_DIG3
Definition: bnx2.h:3830
pci_device
A PCI device.
Definition: pci.h:210
BNX2_PCICFG_MISC_STATUS_M66EN
#define BNX2_PCICFG_MISC_STATUS_M66EN
Definition: bnx2.h:469
eth_ntoa
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
NEXT_TX_BD
#define NEXT_TX_BD(x)
Definition: bnx2.h:3888
bnx2_RXP_b06FwReleaseMajor
static int bnx2_RXP_b06FwReleaseMajor
Definition: bnx2_fw.h:978
BNX2_TXP_CPU_MODE_STEP_ENA
#define BNX2_TXP_CPU_MODE_STEP_ENA
Definition: bnx2.h:3175
BNX2_HC_COM_TICKS
#define BNX2_HC_COM_TICKS
Definition: bnx2.h:2901
bnx2_TPAT_b06FwRodataLen
static const int bnx2_TPAT_b06FwRodataLen
Definition: bnx2_fw.h:2337
fw_info
Definition: bnx2.h:4232
BNX2_DRV_RESET_SIGNATURE
#define BNX2_DRV_RESET_SIGNATURE
Definition: bnx2.h:4287
BNX2_TPAT_CPU_EVENT_MASK
#define BNX2_TPAT_CPU_EVENT_MASK
Definition: bnx2.h:3297
BNX2_NVM_CFG3
#define BNX2_NVM_CFG3
Definition: bnx2.h:1215
BNX2_HC_COMMAND_CLR_STAT_NOW
#define BNX2_HC_COMMAND_CLR_STAT_NOW
Definition: bnx2.h:2852
rx_bd::rx_bd_haddr_hi
u32 rx_bd_haddr_hi
Definition: bnx2.h:175
BNX2_EMAC_MODE_FORCE_LINK
#define BNX2_EMAC_MODE_FORCE_LINK
Definition: bnx2.h:1543
BNX2_PORT_FEATURE
#define BNX2_PORT_FEATURE
Definition: bnx2.h:4419
bnx2_TXP_b06FwRodataAddr
static const u32 bnx2_TXP_b06FwRodataAddr
Definition: bnx2_fw.h:2551
bnx2_init_rx_ring
static void bnx2_init_rx_ring(struct bnx2 *bp)
Definition: bnx2.c:2038
BNX2_PCICFG_INT_ACK_CMD_MASK_INT
#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT
Definition: bnx2.h:514
fw_info::bss
u32 * bss
Definition: bnx2.h:4261
BCM5708S_TX_ACTL3
#define BCM5708S_TX_ACTL3
Definition: bnx2.h:3866
GET_PCID_ADDR
#define GET_PCID_ADDR(_pcid)
Definition: bnx2.h:3917
bnx2_setup_copper_phy
static int bnx2_setup_copper_phy(struct bnx2 *bp)
Definition: bnx2.c:897
BNX2_PCICFG_REG_WINDOW
#define BNX2_PCICFG_REG_WINDOW
Definition: bnx2.h:509
bnx2_fw_sync
static int bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
Definition: bnx2.c:1148
ENODEV
#define ENODEV
No such device.
Definition: errno.h:509
fw_info::data_len
u32 data_len
Definition: bnx2.h:4247
BNX2_EMAC_TX_MODE_FLOW_EN
#define BNX2_EMAC_TX_MODE_FLOW_EN
Definition: bnx2.h:1671
BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
Definition: bnx2.h:461
GET_CID_ADDR
#define GET_CID_ADDR(_cid)
Definition: bnx2.h:3911
uint8_t
unsigned char uint8_t
Definition: stdint.h:10
RX_BD_FLAGS_START
#define RX_BD_FLAGS_START
Definition: bnx2.h:182
bnx2::pdev
struct pci_device * pdev
Definition: bnx2.h:3997
NO_WOL_FLAG
#define NO_WOL_FLAG
Definition: bnx2.h:4008
BNX2_TXP_CPU_PROGRAM_COUNTER
#define BNX2_TXP_CPU_PROGRAM_COUNTER
Definition: bnx2.h:3215
cpu_reg::gpr0
u32 gpr0
Definition: bnx2.h:4221
bnx2_RXP_b06FwRodata
static u32 bnx2_RXP_b06FwRodata[(0x28/4)+1]
Definition: bnx2_fw.h:1940
CHIP_ID_5708_B0
#define CHIP_ID_5708_B0
Definition: bnx2.h:4088
bnx2_RXP_b06FwBssAddr
static u32 bnx2_RXP_b06FwBssAddr
Definition: bnx2_fw.h:988
MII_BMCR
#define MII_BMCR
Definition: atl1e.h:871
bnx2::nic
struct nic * nic
Definition: bnx2.h:3996
L2_FHDR_ERRORS_GIANT_FRAME
#define L2_FHDR_ERRORS_GIANT_FRAME
Definition: bnx2.h:384
BNX2_SHM_HDR_SIGNATURE_SIG
#define BNX2_SHM_HDR_SIGNATURE_SIG
Definition: bnx2.h:3804
bnx2
Definition: bnx2.h:3991
BNX2_SHM_HDR_SIGNATURE_SIG_MASK
#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK
Definition: bnx2.h:3803
SERDES_AN_TIMEOUT
#define SERDES_AN_TIMEOUT
Definition: bnx2.h:4169
statistics_block
Definition: bnx2.h:280
SAIFUN_FLASH_BASE_TOTAL_SIZE
#define SAIFUN_FLASH_BASE_TOTAL_SIZE
Definition: bnx2.h:3959
bnx2_COM_b06FwSbss
static u32 bnx2_COM_b06FwSbss[(0x1c/4)+1]
Definition: bnx2_fw.h:976
BNX2_L2CTX_CMD_TYPE
#define BNX2_L2CTX_CMD_TYPE
Definition: bnx2.h:414
BNX2_HC_STATUS_ADDR_L
#define BNX2_HC_STATUS_ADDR_L
Definition: bnx2.h:2877
BNX2_EMAC_MODE_ACPI_RCVD
#define BNX2_EMAC_MODE_ACPI_RCVD
Definition: bnx2.h:1546
ETH_ALEN
#define ETH_ALEN
Definition: if_ether.h:8
BNX2_DMA_CONFIG_DATA_WORD_SWAP
#define BNX2_DMA_CONFIG_DATA_WORD_SWAP
Definition: bnx2.h:1272
FLOW_CTRL_RX
#define FLOW_CTRL_RX
Definition: bnx2.h:4153
RX_RING_IDX
#define RX_RING_IDX(x)
Definition: bnx2.h:3902
pci_device_id
A PCI device ID list entry.
Definition: pci.h:174
ADVERTISE_1000HALF
#define ADVERTISE_1000HALF
Definition: mii.h:134
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
Definition: bnx2.h:487
FORCE
Definition: nic.h:37
BNX2_DRV_MSG_CODE_FW_TIMEOUT
#define BNX2_DRV_MSG_CODE_FW_TIMEOUT
Definition: bnx2.h:4297
BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
Definition: bnx2.h:4360
nic
Definition: nic.h:49
bnx2_TXP_b06FwBssAddr
static const u32 bnx2_TXP_b06FwBssAddr
Definition: bnx2_fw.h:2553
common
struct ib_cm_common common
Definition: ib_mad.h:11
PCI_COMMAND_SERR
#define PCI_COMMAND_SERR
SERR# enable.
Definition: pci.h:31
ADVERTISE_CSMA
#define ADVERTISE_CSMA
Definition: mii.h:73
bnx2_rv2p_proc1
static u32 bnx2_rv2p_proc1[]
Definition: bnx2_fw.h:1946
BNX2_TDMA_CONFIG_ONE_DMA
#define BNX2_TDMA_CONFIG_ONE_DMA
Definition: bnx2.h:2764
BNX2_DRV_MSG_SEQ
#define BNX2_DRV_MSG_SEQ
Definition: bnx2.h:4308
BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
Definition: bnx2.h:460
BNX2_CTX_VIRT_ADDR
#define BNX2_CTX_VIRT_ADDR
Definition: bnx2.h:1473
bnx2_COM_b06FwReleaseFix
static const int bnx2_COM_b06FwReleaseFix
Definition: bnx2_fw.h:19
cpu_reg::state
u32 state
Definition: bnx2.h:4218
BNX2_DRV_MSG_CODE_UNLOAD
#define BNX2_DRV_MSG_CODE_UNLOAD
Definition: bnx2.h:4294
BNX2_SHARED_HW_CFG_PHY_BACKPLANE
#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE
Definition: bnx2.h:4380
bnx2_TPAT_b06FwReleaseMinor
static const int bnx2_TPAT_b06FwReleaseMinor
Definition: bnx2_fw.h:2329
status
uint8_t status
Status.
Definition: ena.h:16
BNX2_L2CTX_TX_HOST_BIDX
#define BNX2_L2CTX_TX_HOST_BIDX
Definition: bnx2.h:412
load_rv2p_fw
static void load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
Definition: bnx2.c:1322
eth_frame::data
u8 data[ETH_FRAME_LEN - ETH_HLEN]
Definition: amd8111e.c:86
BNX2_LINK_STATUS_PARALLEL_DET
#define BNX2_LINK_STATUS_PARALLEL_DET
Definition: bnx2.h:4333
BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
Definition: bnx2.h:819
CHIP_BOND_ID
#define CHIP_BOND_ID(bp)
Definition: bnx2.h:4091
BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
Definition: bnx2.h:1698
BNX2_HC_COMMAND
#define BNX2_HC_COMMAND
Definition: bnx2.h:2841
bnx2_init_copper_phy
static int bnx2_init_copper_phy(struct bnx2 *bp)
Definition: bnx2.c:1083
BNX2_HC_COMMAND_COAL_NOW_WO_INT
#define BNX2_HC_COMMAND_COAL_NOW_WO_INT
Definition: bnx2.h:2845
bnx2_disable_int
static void bnx2_disable_int(struct bnx2 *bp)
Definition: bnx2.c:266
status_block
Definition: bnx2.h:190
result
uint16_t result
Definition: hyperv.h:33
TX_CID
#define TX_CID
Definition: bnx2.h:3929
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
Definition: bnx2.h:482
bnx2_COM_b06FwSbssLen
static const int bnx2_COM_b06FwSbssLen
Definition: bnx2_fw.h:30
bnx2_init_5706s_phy
static int bnx2_init_5706s_phy(struct bnx2 *bp)
Definition: bnx2.c:1060
bnx2_init_context
static void bnx2_init_context(struct bnx2 *bp)
Definition: bnx2.c:1190
bnx2_irq
static void bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
Definition: bnx2.c:2599
BNX2_RPM_CONFIG_ACPI_ENA
#define BNX2_RPM_CONFIG_ACPI_ENA
Definition: bnx2.h:2034
ENABLE
Definition: nic.h:36
BNX2_SHARED_HW_CFG_CONFIG2
#define BNX2_SHARED_HW_CFG_CONFIG2
Definition: bnx2.h:4387
nic::packet
unsigned char * packet
Definition: nic.h:53
bnx2_write_phy
static int bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
Definition: bnx2.c:217
MAX_TX_DESC_CNT
#define MAX_TX_DESC_CNT
Definition: bnx2.h:3881
REG_WR16
#define REG_WR16(bp, offset, val)
Definition: bnx2.h:4197
BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
Definition: bnx2.h:804
BNX2_EMAC_MODE
#define BNX2_EMAC_MODE
Definition: bnx2.h:1529
mdelay
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
BNX2_LINK_STATUS_LINK_UP
#define BNX2_LINK_STATUS_LINK_UP
Definition: bnx2.h:4318
BCM5708S_1000X_STAT1_RX_PAUSE
#define BCM5708S_1000X_STAT1_RX_PAUSE
Definition: bnx2.h:3854
BNX2_DRV_MB
#define BNX2_DRV_MB
Definition: bnx2.h:4291
CTX_WR
#define CTX_WR(bp, cid_addr, offset, val)
Definition: bnx2.h:4210
bnx2_report_fw_link
static void bnx2_report_fw_link(struct bnx2 *bp)
Definition: bnx2.c:296
BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE
#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE
Definition: bnx2.h:755
bnx2_probe
static int bnx2_probe(struct nic *nic, struct pci_device *pdev)
Definition: bnx2.c:2616
nic::node_addr
unsigned char * node_addr
Definition: nic.h:52
bnx2_init_tx_ring
static void bnx2_init_tx_ring(struct bnx2 *bp)
Definition: bnx2.c:2006
bnx2_RXP_b06FwStartAddr
static u32 bnx2_RXP_b06FwStartAddr
Definition: bnx2_fw.h:981
BNX2_EMAC_MDIO_COMM
#define BNX2_EMAC_MDIO_COMM
Definition: bnx2.h:1638
RX_BUF_CNT
#define RX_BUF_CNT
Definition: bnx2.h:4588
BNX2_EMAC_MODE_PORT
#define BNX2_EMAC_MODE_PORT
Definition: bnx2.h:1532
L2_FHDR_ERRORS_TOO_SHORT
#define L2_FHDR_ERRORS_TOO_SHORT
Definition: bnx2.h:383
bnx2_rv2p_proc2
static u32 bnx2_rv2p_proc2[]
Definition: bnx2_fw.h:2071
CHIP_NUM_5706
#define CHIP_NUM_5706
Definition: bnx2.h:4072
TX_BD_FLAGS_END
#define TX_BD_FLAGS_END
Definition: bnx2.h:161
BNX2_PCICFG_REG_WINDOW_ADDRESS
#define BNX2_PCICFG_REG_WINDOW_ADDRESS
Definition: bnx2.h:508
BNX2_TXP_SCRATCH
#define BNX2_TXP_SCRATCH
Definition: bnx2.h:3261
bnx2_COM_b06FwText
static u32 bnx2_COM_b06FwText[(0x57bc/4)+1]
Definition: bnx2_fw.h:31
PCI_X_CMD
#define PCI_X_CMD
Definition: bnx2.h:36
mii.h
Media Independent Interface constants.
BNX2_TPAT_CPU_REG_FILE
#define BNX2_TPAT_CPU_REG_FILE
Definition: bnx2.h:3334
BNX2_EMAC_TX_LENGTHS
#define BNX2_EMAC_TX_LENGTHS
Definition: bnx2.h:1683
RX_CID
#define RX_CID
Definition: bnx2.h:3930
BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE
#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE
Definition: bnx2.h:789
cpu_reg::mode_value_sstep
u32 mode_value_sstep
Definition: bnx2.h:4216
BNX2_RXP_CPU_HW_BREAKPOINT
#define BNX2_RXP_CPU_HW_BREAKPOINT
Definition: bnx2.h:3411
BNX2_HC_CONFIG_COLLECT_STATS
#define BNX2_HC_CONFIG_COLLECT_STATS
Definition: bnx2.h:2867
MII_PHYSID2
#define MII_PHYSID2
Definition: atl1e.h:874
RV2P_PROC2
#define RV2P_PROC2
Definition: bnx2.h:4271
BNX2_CTX_DATA_ADR
#define BNX2_CTX_DATA_ADR
Definition: bnx2.h:1479
ADVERTISE_10HALF
#define ADVERTISE_10HALF
Definition: mii.h:74
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK
Definition: bnx2.h:4398
FW_ACK_TIME_OUT_MS
#define FW_ACK_TIME_OUT_MS
Definition: bnx2.h:4284
bnx2
static struct bnx2 bnx2
Definition: bnx2.c:48
PCI_COMMAND_PARITY
#define PCI_COMMAND_PARITY
Parity error response.
Definition: pci.h:30
rx_bd::rx_bd_len
u32 rx_bd_len
Definition: bnx2.h:177
EIO
#define EIO
Input/output error.
Definition: errno.h:433
BNX2_L2CTX_HOST_BSEQ
#define BNX2_L2CTX_HOST_BSEQ
Definition: bnx2.h:443
ST_MICRO_FLASH_BASE_TOTAL_SIZE
#define ST_MICRO_FLASH_BASE_TOTAL_SIZE
Definition: bnx2.h:3965
BNX2_TXP_CPU_STATE
#define BNX2_TXP_CPU_STATE
Definition: bnx2.h:3186
BNX2_EMAC_MDIO_MODE_AUTO_POLL
#define BNX2_EMAC_MDIO_MODE_AUTO_POLL
Definition: bnx2.h:1657
pci_write_config_dword
int pci_write_config_dword(struct pci_device *pci, unsigned int where, uint32_t value)
Write 32-bit dword to PCI configuration space.
bnx2_RXP_b06FwData
static u32 bnx2_RXP_b06FwData[(0x0/4)+1]
Definition: bnx2_fw.h:1939
MB_GET_CID_ADDR
#define MB_GET_CID_ADDR(_cid)
Definition: bnx2.h:3923
ST_MICRO_FLASH_PAGE_SIZE
#define ST_MICRO_FLASH_PAGE_SIZE
Definition: bnx2.h:3964
BUFFERED_FLASH_PAGE_BITS
#define BUFFERED_FLASH_PAGE_BITS
Definition: bnx2.h:3949
bnx2_set_mac_link
static int bnx2_set_mac_link(struct bnx2 *bp)
Definition: bnx2.c:593
BNX2_PCICFG_INT_ACK_CMD
#define BNX2_PCICFG_INT_ACK_CMD
Definition: bnx2.h:510
BNX2_TPAT_SCRATCH
#define BNX2_TPAT_SCRATCH
Definition: bnx2.h:3356
bnx2_TXP_b06FwReleaseFix
static const int bnx2_TXP_b06FwReleaseFix
Definition: bnx2_fw.h:2545
flash
int flash(void)
bnx2_RXP_b06FwBss
static u32 bnx2_RXP_b06FwBss[(0x13a4/4)+1]
Definition: bnx2_fw.h:1943
iounmap
void iounmap(volatile const void *io_addr)
Unmap I/O address.
BNX2_FW_MB
#define BNX2_FW_MB
Definition: bnx2.h:4310
BNX2_PCICFG_MISC_STATUS_INTA_VALUE
#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE
Definition: bnx2.h:467
BCM_PAGE_BITS
#define BCM_PAGE_BITS
Definition: bnx2.h:3877
data
uint8_t data[48]
Additional event data.
Definition: ena.h:22
BNX2_RBUF_COMMAND_ALLOC_REQ
#define BNX2_RBUF_COMMAND_ALLOC_REQ
Definition: bnx2.h:2393
eth_frame::src_addr
u8 src_addr[ETH_ALEN]
Definition: amd8111e.c:84
fw_info::rodata_len
u32 rodata_len
Definition: bnx2.h:4265
BMCR_RESET
#define BMCR_RESET
Definition: mii.h:52
ADVERTISED_10baseT_Full
#define ADVERTISED_10baseT_Full
Definition: bnx2.h:43
BNX2_L2CTX_CMD_TYPE_TYPE_L2
#define BNX2_L2CTX_CMD_TYPE_TYPE_L2
Definition: bnx2.h:416
BNX2_EMAC_RX_MTU_SIZE
#define BNX2_EMAC_RX_MTU_SIZE
Definition: bnx2.h:1612
BNX2_DRV_RESET_SIGNATURE_MAGIC
#define BNX2_DRV_RESET_SIGNATURE_MAGIC
Definition: bnx2.h:4288
fw_info::rodata_addr
u32 rodata_addr
Definition: bnx2.h:4264
cpu_reg::bp
u32 bp
Definition: bnx2.h:4225
BNX2_EMAC_MODE_MPKT_RCVD
#define BNX2_EMAC_MODE_MPKT_RCVD
Definition: bnx2.h:1545
BNX2_MQ_CONFIG
#define BNX2_MQ_CONFIG
Definition: bnx2.h:2604
BNX2_MISC_ENABLE_SET_BITS
#define BNX2_MISC_ENABLE_SET_BITS
Definition: bnx2.h:769
BCM5708S_1000X_STAT1_SPEED_100
#define BCM5708S_1000X_STAT1_SPEED_100
Definition: bnx2.h:3850
BNX2_PORT_HW_CFG_MAC_LOWER
#define BNX2_PORT_HW_CFG_MAC_LOWER
Definition: bnx2.h:4395
BNX2_EMAC_ATTENTION_ENA
#define BNX2_EMAC_ATTENTION_ENA
Definition: bnx2.h:1556
BCM5708S_DIG_3_0
#define BCM5708S_DIG_3_0
Definition: bnx2.h:3857
BNX2_RPM_SORT_USER0_ENA
#define BNX2_RPM_SORT_USER0_ENA
Definition: bnx2.h:2060
BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE
#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE
Definition: bnx2.h:782
BNX2_FW_MSG_ACK
#define BNX2_FW_MSG_ACK
Definition: bnx2.h:4311
BNX2_FW_MSG_STATUS_OK
#define BNX2_FW_MSG_STATUS_OK
Definition: bnx2.h:4313
REG_WR_IND
#define REG_WR_IND(bp, offset, val)
Definition: bnx2.h:4203
BNX2_RV2P_COMMAND
#define BNX2_RV2P_COMMAND
Definition: bnx2.h:2436
bnx2_TXP_b06FwSbssAddr
static const u32 bnx2_TXP_b06FwSbssAddr
Definition: bnx2_fw.h:2555
BNX2_COM_CPU_MODE
#define BNX2_COM_CPU_MODE
Definition: bnx2.h:3479
PHY_PARALLEL_DETECT_FLAG
#define PHY_PARALLEL_DETECT_FLAG
Definition: bnx2.h:4063
BNX2_LINK_STATUS_100HALF
#define BNX2_LINK_STATUS_100HALF
Definition: bnx2.h:4324
BNX2_LINK_STATUS_1000FULL
#define BNX2_LINK_STATUS_1000FULL
Definition: bnx2.h:4328
bnx2_TPAT_b06FwText
static u32 bnx2_TPAT_b06FwText[(0x122c/4)+1]
Definition: bnx2_fw.h:2342
BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA
#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA
Definition: bnx2.h:1278
BNX2_L2CTX_TYPE_SIZE_L2
#define BNX2_L2CTX_TYPE_SIZE_L2
Definition: bnx2.h:407
BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256
#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256
Definition: bnx2.h:2608
BNX2_MQ_KNL_WIND_END
#define BNX2_MQ_KNL_WIND_END
Definition: bnx2.h:2628
bnx2_TXP_b06FwReleaseMinor
static const int bnx2_TXP_b06FwReleaseMinor
Definition: bnx2_fw.h:2544
cpu_reg::spad_base
u32 spad_base
Definition: bnx2.h:4227
BNX2_RBUF_STATUS1_FREE_COUNT
#define BNX2_RBUF_STATUS1_FREE_COUNT
Definition: bnx2.h:2396
BNX2_EMAC_MODE_HALF_DUPLEX
#define BNX2_EMAC_MODE_HALF_DUPLEX
Definition: bnx2.h:1531
ADVERTISE_PAUSE_CAP
#define ADVERTISE_PAUSE_CAP
Definition: mii.h:83
BNX2_COM_CPU_EVENT_MASK
#define BNX2_COM_CPU_EVENT_MASK
Definition: bnx2.h:3508
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
Definition: bnx2.h:479
BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G
#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G
Definition: bnx2.h:4400
bnx2_resolve_flow_ctrl
static void bnx2_resolve_flow_ctrl(struct bnx2 *bp)
Definition: bnx2.c:385
ADVERTISE_100HALF
#define ADVERTISE_100HALF
Definition: mii.h:78
BNX2_MISC_VREG_CONTROL
#define BNX2_MISC_VREG_CONTROL
Definition: bnx2.h:1134
BNX2_L2CTX_TYPE_TYPE_L2
#define BNX2_L2CTX_TYPE_TYPE_L2
Definition: bnx2.h:410
fw_info::sbss
u32 * sbss
Definition: bnx2.h:4255
BNX2_EMAC_MDIO_MODE
#define BNX2_EMAC_MDIO_MODE
Definition: bnx2.h:1655
bnx2_TXP_b06FwBssLen
static const int bnx2_TXP_b06FwBssLen
Definition: bnx2_fw.h:2554
ETHTOOL_ALL_FIBRE_SPEED
#define ETHTOOL_ALL_FIBRE_SPEED
Definition: bnx2.c:883
RX_BUF_USE_SIZE
#define RX_BUF_USE_SIZE
Definition: bnx2.h:4591
flash_table
static struct flash_spec flash_table[]
Definition: bnx2.c:50
ST_MICRO_FLASH_PAGE_BITS
#define ST_MICRO_FLASH_PAGE_BITS
Definition: bnx2.h:3961
offset
uint16_t offset
Offset to command line.
Definition: bzimage.h:8
BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK
#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK
Definition: bnx2.h:4397
PHY_CTX_SIZE
#define PHY_CTX_SIZE
Definition: bnx2.h:3915
fw_info::data
u32 * data
Definition: bnx2.h:4249
CHIP_ID_5706_A1
#define CHIP_ID_5706_A1
Definition: bnx2.h:4085
BCM5708S_UP1
#define BCM5708S_UP1
Definition: bnx2.h:3823
BNX2_HC_CONFIG_RX_TMR_MODE
#define BNX2_HC_CONFIG_RX_TMR_MODE
Definition: bnx2.h:2868
BNX2_RXP_CPU_STATE
#define BNX2_RXP_CPU_STATE
Definition: bnx2.h:3376
BNX2_LINK_STATUS_LINK_DOWN
#define BNX2_LINK_STATUS_LINK_DOWN
Definition: bnx2.h:4319
BNX2_DEV_INFO_SIGNATURE
#define BNX2_DEV_INFO_SIGNATURE
Definition: bnx2.h:4358
bnx2_RXP_b06FwDataAddr
static u32 bnx2_RXP_b06FwDataAddr
Definition: bnx2_fw.h:984
BNX2_DEV_INFO_SIGNATURE_MAGIC
#define BNX2_DEV_INFO_SIGNATURE_MAGIC
Definition: bnx2.h:4359
CHIP_ID
#define CHIP_ID(bp)
Definition: bnx2.h:4083
nic::nic_op
struct nic_operations * nic_op
Definition: nic.h:50
FLASH_STRAP_MASK
#define FLASH_STRAP_MASK
Definition: bnx2.h:3970
BMCR_ANENABLE
#define BMCR_ANENABLE
Definition: mii.h:49
BNX2_EMAC_MDIO_COMM_DISEXT
#define BNX2_EMAC_MDIO_COMM_DISEXT
Definition: bnx2.h:1649
pci_ioremap
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
BNX2_EMAC_MDIO_COMM_DATA
#define BNX2_EMAC_MDIO_COMM_DATA
Definition: bnx2.h:1639
MII_BMSR
#define MII_BMSR
Definition: atl1e.h:872
MII_PHYSID1
#define MII_PHYSID1
Definition: atl1e.h:873
bnx2_RXP_b06FwReleaseMinor
static int bnx2_RXP_b06FwReleaseMinor
Definition: bnx2_fw.h:979
BNX2_EMAC_MODE_25G
#define BNX2_EMAC_MODE_25G
Definition: bnx2.h:1538
bnx2_TPAT_b06FwStartAddr
static const u32 bnx2_TPAT_b06FwStartAddr
Definition: bnx2_fw.h:2331
AUTONEG_SPEED
#define AUTONEG_SPEED
Definition: bnx2.h:4161
bnx2_init_nvram
static int bnx2_init_nvram(struct bnx2 *bp)
Definition: bnx2.c:1680
BNX2_LINK_STATUS_2500HALF
#define BNX2_LINK_STATUS_2500HALF
Definition: bnx2.h:4329
bnx2_reg_wr_ind
static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
Definition: bnx2.c:145
BCM5708S_1000X_STAT1_SPEED_2G5
#define BCM5708S_1000X_STAT1_SPEED_2G5
Definition: bnx2.h:3852
BNX2_RPM_SORT_USER0
#define BNX2_RPM_SORT_USER0
Definition: bnx2.h:2052
BNX2_RXP_CPU_REG_FILE
#define BNX2_RXP_CPU_REG_FILE
Definition: bnx2.h:3429
cpu_reg::mode_value_halt
u32 mode_value_halt
Definition: bnx2.h:4215
BCM5708S_TX_ACTL1
#define BCM5708S_TX_ACTL1
Definition: bnx2.h:3862
ADVERTISED_1000baseT_Full
#define ADVERTISED_1000baseT_Full
Definition: bnx2.h:47
BMCR_SPEED100
#define BMCR_SPEED100
Definition: mii.h:50
bnx2_TXP_b06FwTextLen
static const int bnx2_TXP_b06FwTextLen
Definition: bnx2_fw.h:2548
bnx2_TPAT_b06FwRodataAddr
static const u32 bnx2_TPAT_b06FwRodataAddr
Definition: bnx2_fw.h:2336
bnx2_TPAT_b06FwSbssAddr
static const u32 bnx2_TPAT_b06FwSbssAddr
Definition: bnx2_fw.h:2340
fw_info::bss_addr
u32 bss_addr
Definition: bnx2.h:4258
nic_operations::connect
int(* connect)(struct nic *)
Definition: nic.h:69
BNX2_LINK_STATUS
#define BNX2_LINK_STATUS
Definition: bnx2.h:4316
BNX2_COM_CPU_HW_BREAKPOINT
#define BNX2_COM_CPU_HW_BREAKPOINT
Definition: bnx2.h:3527
NULL
#define NULL
NULL pointer (VOID *)
Definition: Base.h:321
L2_FHDR_ERRORS_PHY_DECODE
#define L2_FHDR_ERRORS_PHY_DECODE
Definition: bnx2.h:381
BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
Definition: bnx2.h:817
ADVERTISED_100baseT_Full
#define ADVERTISED_100baseT_Full
Definition: bnx2.h:45
bnx2_alloc_mem
static int bnx2_alloc_mem(struct bnx2 *bp)
Definition: bnx2.c:275
SAIFUN_FLASH_PAGE_SIZE
#define SAIFUN_FLASH_PAGE_SIZE
Definition: bnx2.h:3958
bnx2_RXP_b06FwReleaseFix
static int bnx2_RXP_b06FwReleaseFix
Definition: bnx2_fw.h:980
bnx2_poll
static int bnx2_poll(struct nic *nic, int retrieve)
Definition: bnx2.c:2493
string.h
String functions.
BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE
#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE
Definition: bnx2.h:4356
PCI_ROM
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:307
BNX2_RBUF_FW_BUF_FREE
#define BNX2_RBUF_FW_BUF_FREE
Definition: bnx2.h:2409
bnx2_TPAT_b06FwData
static u32 bnx2_TPAT_b06FwData[(0x0/4)+1]
Definition: bnx2_fw.h:2538
PHY_INT_MODE_AUTO_POLLING_FLAG
#define PHY_INT_MODE_AUTO_POLLING_FLAG
Definition: bnx2.h:4066
flash_spec
Definition: bnx2.h:3977
htons
#define htons(value)
Definition: byteswap.h:135
PHY_CRC_FIX_FLAG
#define PHY_CRC_FIX_FLAG
Definition: bnx2.h:4062
BNX2_RXP_CPU_MODE_STEP_ENA
#define BNX2_RXP_CPU_MODE_STEP_ENA
Definition: bnx2.h:3365
BCM5708S_DIG_3_0_USE_IEEE
#define BCM5708S_DIG_3_0_USE_IEEE
Definition: bnx2.h:3859
CHIP_ID_5708_A0
#define CHIP_ID_5708_A0
Definition: bnx2.h:4087
BNX2_TXP_CPU_MODE_SOFT_HALT
#define BNX2_TXP_CPU_MODE_SOFT_HALT
Definition: bnx2.h:3180
ADVERTISED_10baseT_Half
#define ADVERTISED_10baseT_Half
Definition: bnx2.h:42
BNX2_MISC_ID
#define BNX2_MISC_ID
Definition: bnx2.h:733
bnx2_RXP_b06FwText
static u32 bnx2_RXP_b06FwText[(0x588c/4)+1]
Definition: bnx2_fw.h:992
u8
uint8_t u8
Definition: stdint.h:19
BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE
#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE
Definition: bnx2.h:761
SEEPROM_PAGE_BITS
#define SEEPROM_PAGE_BITS
Definition: bnx2.h:3943
bnx2_RXP_b06FwBssLen
static int bnx2_RXP_b06FwBssLen
Definition: bnx2_fw.h:989
BNX2_PORT_HW_CFG_CONFIG
#define BNX2_PORT_HW_CFG_CONFIG
Definition: bnx2.h:4396
u32
uint32_t u32
Definition: stdint.h:23
bnx2_TPAT_b06FwDataLen
static const int bnx2_TPAT_b06FwDataLen
Definition: bnx2_fw.h:2335
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
Definition: bnx2.h:485
BCM5708S_1000X_STAT1_SPEED_1G
#define BCM5708S_1000X_STAT1_SPEED_1G
Definition: bnx2.h:3851
cpu_reg::mips_view_base
u32 mips_view_base
Definition: bnx2.h:4229
CHIP_BOND_ID_SERDES_BIT
#define CHIP_BOND_ID_SERDES_BIT
Definition: bnx2.h:4094
bnx2_set_rx_mode
static void bnx2_set_rx_mode(struct nic *nic __unused)
Definition: bnx2.c:1290
BNX2_TDMA_CONFIG
#define BNX2_TDMA_CONFIG
Definition: bnx2.h:2763
eth_frame::dst_addr
u8 dst_addr[ETH_ALEN]
Definition: amd8111e.c:83
BMCR_FULLDPLX
#define BMCR_FULLDPLX
Definition: mii.h:45
BNX2_L2CTX_NX_BDHADDR_LO
#define BNX2_L2CTX_NX_BDHADDR_LO
Definition: bnx2.h:446
BNX2_HC_STAT_COLLECT_TICKS
#define BNX2_HC_STAT_COLLECT_TICKS
Definition: bnx2.h:2912
bnx2_COM_b06FwData
static u32 bnx2_COM_b06FwData[(0x0/4)+1]
Definition: bnx2_fw.h:969
BNX2_HC_ATTN_BITS_ENABLE
#define BNX2_HC_ATTN_BITS_ENABLE
Definition: bnx2.h:2876
bnx2_TPAT_b06FwSbss
static u32 bnx2_TPAT_b06FwSbss[(0x34/4)+1]
Definition: bnx2_fw.h:2541
BNX2_DMA_CONFIG_CNTL_WORD_SWAP
#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP
Definition: bnx2.h:1274
tx_bd::tx_bd_haddr_hi
u32 tx_bd_haddr_hi
Definition: bnx2.h:151
BNX2_EMAC_MODE_MAC_LOOP
#define BNX2_EMAC_MODE_MAC_LOOP
Definition: bnx2.h:1537
bnx2_TXP_b06FwStartAddr
static const u32 bnx2_TXP_b06FwStartAddr
Definition: bnx2_fw.h:2546
ADVERTISE_1000XFULL
#define ADVERTISE_1000XFULL
Definition: mii.h:75
BNX2_PCI_SWAP_DIAG0
#define BNX2_PCI_SWAP_DIAG0
Definition: bnx2.h:619
BNX2_TBDR_CONFIG_PAGE_SIZE
#define BNX2_TBDR_CONFIG_PAGE_SIZE
Definition: bnx2.h:2700
DUPLEX_HALF
#define DUPLEX_HALF
Definition: bnx2.h:110
bnx2_TXP_b06FwTextAddr
static const u32 bnx2_TXP_b06FwTextAddr
Definition: bnx2_fw.h:2547
BNX2_COM_CPU_PROGRAM_COUNTER
#define BNX2_COM_CPU_PROGRAM_COUNTER
Definition: bnx2.h:3521
ST_MICRO_FLASH_BYTE_ADDR_MASK
#define ST_MICRO_FLASH_BYTE_ADDR_MASK
Definition: bnx2.h:3963
NEXT_RX_BD
#define NEXT_RX_BD(x)
Definition: bnx2.h:3898
MII_STAT1000
#define MII_STAT1000
Definition: mii.h:25
memset
void * memset(void *dest, int character, size_t len) __nonnull
BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS
#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS
Definition: bnx2.h:477
BNX2_HC_CONFIG
#define BNX2_HC_CONFIG
Definition: bnx2.h:2866
nic_operations
Definition: nic.h:68
BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
Definition: bnx2.h:1614
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