iPXE
Defines | Typedefs | Functions | Variables
ath9k_ar9003_eeprom.c File Reference
#include <ipxe/io.h>
#include <ipxe/malloc.h>
#include "hw.h"
#include "ar9003_phy.h"
#include "ar9003_eeprom.h"

Go to the source code of this file.

Defines

#define COMP_HDR_LEN   4
#define COMP_CKSUM_LEN   2
#define AR_CH0_TOP   (0x00016288)
#define AR_CH0_TOP_XPABIASLVL   (0x300)
#define AR_CH0_TOP_XPABIASLVL_S   (8)
#define AR_CH0_THERM   (0x00016290)
#define AR_CH0_THERM_XPABIASLVL_MSB   0x3
#define AR_CH0_THERM_XPABIASLVL_MSB_S   0
#define AR_CH0_THERM_XPASHORT2GND   0x4
#define AR_CH0_THERM_XPASHORT2GND_S   2
#define AR_SWITCH_TABLE_COM_ALL   (0xffff)
#define AR_SWITCH_TABLE_COM_ALL_S   (0)
#define AR_SWITCH_TABLE_COM2_ALL   (0xffffff)
#define AR_SWITCH_TABLE_COM2_ALL_S   (0)
#define AR_SWITCH_TABLE_ALL   (0xfff)
#define AR_SWITCH_TABLE_ALL_S   (0)
#define LE16(x)   (uint16_t)(x)
#define LE32(x)   (uint32_t)(x)
#define EXT_ADDITIVE   (0x8000)
#define CTL_11A_EXT   (CTL_11A | EXT_ADDITIVE)
#define CTL_11G_EXT   (CTL_11G | EXT_ADDITIVE)
#define CTL_11B_EXT   (CTL_11B | EXT_ADDITIVE)
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN   6 /* 10*log10(2)*2 */
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
#define PWRINCR_3_TO_1_CHAIN   9 /* 10*log(3)*2 */
#define PWRINCR_3_TO_2_CHAIN   3 /* floor(10*log(3/2)*2) */
#define PWRINCR_2_TO_1_CHAIN   6 /* 10*log(2)*2 */
#define SUB_NUM_CTL_MODES_AT_5G_40   2 /* excluding HT40, EXT-OFDM */
#define SUB_NUM_CTL_MODES_AT_2G_40   3 /* excluding HT40, EXT-OFDM, EXT-CCK */
#define CTL(_tpower, _flag)   ((_tpower) | ((_flag) << 6))
#define EEPROM_DATA_LEN_9485   1088
#define N_LOOP   (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
#define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
#define MDEFAULT   15
#define MSTATE   100
#define POW_SM(_r, _s)   (((_r) & 0x3f) << (_s))

Typedefs

typedef int(* eeprom_read_op )(struct ath_hw *ah, int address, u8 *buffer, int count)

Functions

static int ar9003_hw_power_interpolate (int32_t x, int32_t *px, int32_t *py, uint16_t np)
static struct ar9300_eepromar9003_eeprom_struct_find_by_id (int id)
static u16 ath9k_hw_fbin2freq (u8 fbin, int is2GHz)
static int ath9k_hw_ar9300_check_eeprom (struct ath_hw *ah __unused)
static int interpolate (int x, int xa, int xb, int ya, int yb)
static u32 ath9k_hw_ar9300_get_eeprom (struct ath_hw *ah, enum eeprom_param param)
static int ar9300_eeprom_read_byte (struct ath_common *common, int address, u8 *buffer)
static int ar9300_eeprom_read_word (struct ath_common *common, int address, u8 *buffer)
static int ar9300_read_eeprom (struct ath_hw *ah, int address, u8 *buffer, int count)
static int ar9300_otp_read_word (struct ath_hw *ah, int addr, u32 *data)
static int ar9300_read_otp (struct ath_hw *ah, int address, u8 *buffer, int count)
static void ar9300_comp_hdr_unpack (u8 *best, int *code, int *reference, int *length, int *major, int *minor)
static u16 ar9300_comp_cksum (u8 *data, int dsize)
static int ar9300_uncompress_block (struct ath_hw *ah __unused, u8 *mptr, int mdataSize, u8 *block, int size)
static int ar9300_compress_decision (struct ath_hw *ah, int it, int code, int reference, u8 *mptr, u8 *word, int length, int mdata_size)
static int ar9300_check_header (void *data)
static int ar9300_check_eeprom_header (struct ath_hw *ah, eeprom_read_op read, int base_addr)
static int ar9300_eeprom_restore_flash (struct ath_hw *ah, u8 *mptr, int mdata_size)
static int ar9300_eeprom_restore_internal (struct ath_hw *ah, u8 *mptr, int mdata_size)
static int ath9k_hw_ar9300_fill_eeprom (struct ath_hw *ah)
static int ath9k_hw_ar9300_get_eeprom_ver (struct ath_hw *ah)
static int ath9k_hw_ar9300_get_eeprom_rev (struct ath_hw *ah __unused)
static s32 ar9003_hw_xpa_bias_level_get (struct ath_hw *ah, int is2ghz)
static void ar9003_hw_xpa_bias_level_apply (struct ath_hw *ah, int is2ghz)
static u32 ar9003_hw_ant_ctrl_common_get (struct ath_hw *ah, int is2ghz)
static u32 ar9003_hw_ant_ctrl_common_2_get (struct ath_hw *ah, int is2ghz)
static u16 ar9003_hw_ant_ctrl_chain_get (struct ath_hw *ah, int chain, int is2ghz)
static void ar9003_hw_ant_ctrl_apply (struct ath_hw *ah, int is2ghz)
static void ar9003_hw_drive_strength_apply (struct ath_hw *ah)
static u16 ar9003_hw_atten_chain_get (struct ath_hw *ah, int chain, struct ath9k_channel *chan)
static u16 ar9003_hw_atten_chain_get_margin (struct ath_hw *ah, int chain, struct ath9k_channel *chan)
static void ar9003_hw_atten_apply (struct ath_hw *ah, struct ath9k_channel *chan)
static int is_pmu_set (struct ath_hw *ah, u32 pmu_reg, int pmu_set)
static void ar9003_hw_internal_regulator_apply (struct ath_hw *ah)
static void ar9003_hw_apply_tuning_caps (struct ath_hw *ah)
static void ath9k_hw_ar9300_set_board_values (struct ath_hw *ah, struct ath9k_channel *chan)
static void ath9k_hw_ar9300_set_addac (struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
static u8 ar9003_hw_eeprom_get_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq)
static int ar9003_hw_tx_power_regwrite (struct ath_hw *ah, u8 *pPwrArray)
static void ar9003_hw_set_target_power_eeprom (struct ath_hw *ah, u16 freq, u8 *targetPowerValT2)
static int ar9003_hw_cal_pier_get (struct ath_hw *ah, int mode, int ipier, int ichain, int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage)
static int ar9003_hw_power_control_override (struct ath_hw *ah, int frequency, int *correction, int *voltage __unused, int *temperature)
static int ar9003_hw_calibration_apply (struct ath_hw *ah, int frequency)
static u16 ar9003_hw_get_direct_edge_power (struct ar9300_eeprom *eep, int idx, int edge, int is2GHz)
static u16 ar9003_hw_get_indirect_edge_power (struct ar9300_eeprom *eep, int idx, unsigned int edge, u16 freq, int is2GHz)
static u16 ar9003_hw_get_max_edge_power (struct ar9300_eeprom *eep, u16 freq, int idx, int is2GHz)
static void ar9003_hw_set_power_per_rate_table (struct ath_hw *ah, struct ath9k_channel *chan, u8 *pPwrArray, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u16 powerLimit)
static u8 mcsidx_to_tgtpwridx (unsigned int mcs_idx, u8 base_pwridx)
static void ath9k_hw_ar9300_set_txpower (struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
static u16 ath9k_hw_ar9300_get_spur_channel (struct ath_hw *ah __unused, u16 i __unused, int is2GHz __unused)
s32 ar9003_hw_get_tx_gain_idx (struct ath_hw *ah)
s32 ar9003_hw_get_rx_gain_idx (struct ath_hw *ah)
u8ar9003_get_spur_chan_ptr (struct ath_hw *ah, int is_2ghz)
unsigned int ar9003_get_paprd_scale_factor (struct ath_hw *ah, struct ath9k_channel *chan)

Variables

static struct ar9300_eeprom ar9300_default
static struct ar9300_eeprom ar9300_x113
static struct ar9300_eeprom ar9300_h112
static struct ar9300_eeprom ar9300_x112
static struct ar9300_eeprom ar9300_h116
static struct ar9300_eepromar9300_eep_templates []
struct eeprom_ops eep_ar9300_ops

Define Documentation

#define COMP_HDR_LEN   4
#define COMP_CKSUM_LEN   2

Definition at line 28 of file ath9k_ar9003_eeprom.c.

Referenced by ar9300_eeprom_restore_internal().

#define AR_CH0_TOP   (0x00016288)

Definition at line 30 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_xpa_bias_level_apply().

#define AR_CH0_TOP_XPABIASLVL   (0x300)

Definition at line 31 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_xpa_bias_level_apply().

#define AR_CH0_TOP_XPABIASLVL_S   (8)

Definition at line 32 of file ath9k_ar9003_eeprom.c.

#define AR_CH0_THERM   (0x00016290)

Definition at line 34 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_xpa_bias_level_apply().

#define AR_CH0_THERM_XPABIASLVL_MSB   0x3

Definition at line 35 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_xpa_bias_level_apply().

Definition at line 36 of file ath9k_ar9003_eeprom.c.

#define AR_CH0_THERM_XPASHORT2GND   0x4

Definition at line 37 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_xpa_bias_level_apply().

Definition at line 38 of file ath9k_ar9003_eeprom.c.

#define AR_SWITCH_TABLE_COM_ALL   (0xffff)

Definition at line 40 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_ant_ctrl_apply().

#define AR_SWITCH_TABLE_COM_ALL_S   (0)

Definition at line 41 of file ath9k_ar9003_eeprom.c.

#define AR_SWITCH_TABLE_COM2_ALL   (0xffffff)

Definition at line 43 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_ant_ctrl_apply().

#define AR_SWITCH_TABLE_COM2_ALL_S   (0)

Definition at line 44 of file ath9k_ar9003_eeprom.c.

#define AR_SWITCH_TABLE_ALL   (0xfff)

Definition at line 46 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_ant_ctrl_apply().

#define AR_SWITCH_TABLE_ALL_S   (0)

Definition at line 47 of file ath9k_ar9003_eeprom.c.

#define LE16 (   x)    (uint16_t)(x)

Definition at line 49 of file ath9k_ar9003_eeprom.c.

#define LE32 (   x)    (uint32_t)(x)

Definition at line 50 of file ath9k_ar9003_eeprom.c.

#define EXT_ADDITIVE   (0x8000)
#define CTL_11A_EXT   (CTL_11A | EXT_ADDITIVE)
#define CTL_11G_EXT   (CTL_11G | EXT_ADDITIVE)
#define CTL_11B_EXT   (CTL_11B | EXT_ADDITIVE)
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN   6 /* 10*log10(2)*2 */
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
#define PWRINCR_3_TO_1_CHAIN   9 /* 10*log(3)*2 */

Definition at line 59 of file ath9k_ar9003_eeprom.c.

#define PWRINCR_3_TO_2_CHAIN   3 /* floor(10*log(3/2)*2) */

Definition at line 60 of file ath9k_ar9003_eeprom.c.

#define PWRINCR_2_TO_1_CHAIN   6 /* 10*log(2)*2 */

Definition at line 61 of file ath9k_ar9003_eeprom.c.

#define SUB_NUM_CTL_MODES_AT_5G_40   2 /* excluding HT40, EXT-OFDM */
#define SUB_NUM_CTL_MODES_AT_2G_40   3 /* excluding HT40, EXT-OFDM, EXT-CCK */
#define CTL (   _tpower,
  _flag 
)    ((_tpower) | ((_flag) << 6))

Definition at line 66 of file ath9k_ar9003_eeprom.c.

#define EEPROM_DATA_LEN_9485   1088

Definition at line 68 of file ath9k_ar9003_eeprom.c.

Referenced by ar9300_eeprom_restore_internal().

#define N_LOOP   (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
#define MDEFAULT   15
#define MSTATE   100
#define POW_SM (   _r,
  _s 
)    (((_r) & 0x3f) << (_s))

Typedef Documentation

typedef int(* eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, int count)

Definition at line 3265 of file ath9k_ar9003_eeprom.c.


Function Documentation

static int ar9003_hw_power_interpolate ( int32_t  x,
int32_t px,
int32_t py,
uint16_t  np 
) [static]

Definition at line 3821 of file ath9k_ar9003_eeprom.c.

References dx, interpolate(), and ip.

Referenced by ar9003_hw_atten_chain_get(), ar9003_hw_atten_chain_get_margin(), ar9003_hw_eeprom_get_cck_tgt_pwr(), ar9003_hw_eeprom_get_ht20_tgt_pwr(), ar9003_hw_eeprom_get_ht40_tgt_pwr(), ar9003_hw_eeprom_get_tgt_pwr(), and ar9003_hw_power_control_override().

{
        int ip = 0;
        int lx = 0, ly = 0, lhave = 0;
        int hx = 0, hy = 0, hhave = 0;
        int dx = 0;
        int y = 0;

        lhave = 0;
        hhave = 0;

        /* identify best lower and higher x calibration measurement */
        for (ip = 0; ip < np; ip++) {
                dx = x - px[ip];

                /* this measurement is higher than our desired x */
                if (dx <= 0) {
                        if (!hhave || dx > (x - hx)) {
                                /* new best higher x measurement */
                                hx = px[ip];
                                hy = py[ip];
                                hhave = 1;
                        }
                }
                /* this measurement is lower than our desired x */
                if (dx >= 0) {
                        if (!lhave || dx < (x - lx)) {
                                /* new best lower x measurement */
                                lx = px[ip];
                                ly = py[ip];
                                lhave = 1;
                        }
                }
        }

        /* the low x is good */
        if (lhave) {
                /* so is the high x */
                if (hhave) {
                        /* they're the same, so just pick one */
                        if (hx == lx)
                                y = ly;
                        else    /* interpolate  */
                                y = interpolate(x, lx, hx, ly, hy);
                } else          /* only low is good, use it */
                        y = ly;
        } else if (hhave)       /* only high is good, use it */
                y = hy;
        else /* nothing is good,this should never happen unless np=0, ???? */
                y = -(1 << 30);
        return y;
}
static struct ar9300_eeprom* ar9003_eeprom_struct_find_by_id ( int  id) [static, read]

Definition at line 2971 of file ath9k_ar9003_eeprom.c.

References N_LOOP, NULL, and templateVersion.

Referenced by ar9300_compress_decision().

{
#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
        unsigned int it;

        for (it = 0; it < N_LOOP; it++)
                if (ar9300_eep_templates[it]->templateVersion == id)
                        return ar9300_eep_templates[it];
        return NULL;
#undef N_LOOP
}
static u16 ath9k_hw_fbin2freq ( u8  fbin,
int  is2GHz 
) [static]

Definition at line 2984 of file ath9k_ar9003_eeprom.c.

References AR5416_BCHAN_UNUSED.

Referenced by ar9003_hw_get_indirect_edge_power(), and ar9003_hw_get_max_edge_power().

{
        if (fbin == AR5416_BCHAN_UNUSED)
                return fbin;

        return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
}
static int ath9k_hw_ar9300_check_eeprom ( struct ath_hw *ah  __unused) [static]

Definition at line 2992 of file ath9k_ar9003_eeprom.c.

{
        return 0;
}
static int interpolate ( int  x,
int  xa,
int  xb,
int  ya,
int  yb 
) [static]

Definition at line 2997 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_hw_calibration_apply(), and ar9003_hw_power_interpolate().

{
        int bf, factor, plus;

        bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
        factor = bf / 2;
        plus = bf % 2;
        return ya + factor + plus;
}
static u32 ath9k_hw_ar9300_get_eeprom ( struct ath_hw ah,
enum eeprom_param  param 
) [static]

Definition at line 3007 of file ath9k_ar9003_eeprom.c.

References ar9300_BaseExtension_1::ant_div_control, ath_hw::ar9300_eep, AR9300_EEP_BASE_DRIV_STRENGTH, ar9300_eeprom::base_ext1, ar9300_eeprom::baseEepHeader, BIT, ar9300_base_eep_hdr::deviceCap, EEP_ANT_DIV_CTL1, EEP_CHAIN_MASK_REDUCE, EEP_DRIVE_STRENGTH, EEP_INTERNAL_REGULATOR, EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW, EEP_OP_CAP, EEP_OP_MODE, EEP_PAPRD, EEP_REG_0, EEP_REG_1, EEP_RF_SILENT, EEP_RX_MASK, EEP_SWREG, EEP_TX_MASK, ath_hw::eeprom, ar9300_base_eep_hdr::featureEnable, ar9300_eeprom::macAddr, ar9300_base_eep_hdr::miscConfiguration, ar9300_base_eep_hdr::opCapFlags, eepFlags::opFlags, ar9300_base_eep_hdr::regDmn, ar9300_base_eep_hdr::rfSilent, ar9300_base_eep_hdr::swreg, and ar9300_base_eep_hdr::txrxMask.

Referenced by ar9003_hw_ant_ctrl_apply(), ar9003_hw_drive_strength_apply(), and ar9003_hw_internal_regulator_apply().

{
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;

        switch (param) {
        case EEP_MAC_LSW:
                return eep->macAddr[0] << 8 | eep->macAddr[1];
        case EEP_MAC_MID:
                return eep->macAddr[2] << 8 | eep->macAddr[3];
        case EEP_MAC_MSW:
                return eep->macAddr[4] << 8 | eep->macAddr[5];
        case EEP_REG_0:
                return (uint16_t)(pBase->regDmn[0]);
        case EEP_REG_1:
                return (uint16_t)(pBase->regDmn[1]);
        case EEP_OP_CAP:
                return pBase->deviceCap;
        case EEP_OP_MODE:
                return pBase->opCapFlags.opFlags;
        case EEP_RF_SILENT:
                return pBase->rfSilent;
        case EEP_TX_MASK:
                return (pBase->txrxMask >> 4) & 0xf;
        case EEP_RX_MASK:
                return pBase->txrxMask & 0xf;
        case EEP_DRIVE_STRENGTH:
#define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
                return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
        case EEP_INTERNAL_REGULATOR:
                /* Bit 4 is internal regulator flag */
                return (pBase->featureEnable & 0x10) >> 4;
        case EEP_SWREG:
                return (uint32_t)(pBase->swreg);
        case EEP_PAPRD:
                return !!(pBase->featureEnable & BIT(5));
        case EEP_CHAIN_MASK_REDUCE:
                return (pBase->miscConfiguration >> 0x3) & 0x1;
        case EEP_ANT_DIV_CTL1:
                return (uint32_t)(eep->base_ext1.ant_div_control);
        default:
                return 0;
        }
}
static int ar9300_eeprom_read_byte ( struct ath_common common,
int  address,
u8 buffer 
) [static]

Definition at line 3053 of file ath9k_ar9003_eeprom.c.

References ath9k_hw_nvram_read(), and val.

Referenced by ar9300_read_eeprom().

{
        u16 val;

        if (!ath9k_hw_nvram_read(common, address / 2, &val))
                return 0;

        *buffer = (val >> (8 * (address % 2))) & 0xff;
        return 1;
}
static int ar9300_eeprom_read_word ( struct ath_common common,
int  address,
u8 buffer 
) [static]

Definition at line 3065 of file ath9k_ar9003_eeprom.c.

References ath9k_hw_nvram_read(), and val.

Referenced by ar9300_read_eeprom().

{
        u16 val;

        if (!ath9k_hw_nvram_read(common, address / 2, &val))
                return 0;

        buffer[0] = val >> 8;
        buffer[1] = val & 0xff;

        return 1;
}
static int ar9300_read_eeprom ( struct ath_hw ah,
int  address,
u8 buffer,
int  count 
) [static]

Definition at line 3079 of file ath9k_ar9003_eeprom.c.

References ar9300_eeprom_read_byte(), ar9300_eeprom_read_word(), AR9300_EEPROM_SIZE, ath9k_hw_common(), common, DBG, and error.

Referenced by ar9300_eeprom_restore_internal().

{
        struct ath_common *common = ath9k_hw_common(ah);
        int i;

        if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
                DBG("ath9k: "
                        "eeprom address not in range\n");
                return 0;
        }

        /*
         * Since we're reading the bytes in reverse order from a little-endian
         * word stream, an even address means we only use the lower half of
         * the 16-bit word at that address
         */
        if (address % 2 == 0) {
                if (!ar9300_eeprom_read_byte(common, address--, buffer++))
                        goto error;

                count--;
        }

        for (i = 0; i < count / 2; i++) {
                if (!ar9300_eeprom_read_word(common, address, buffer))
                        goto error;

                address -= 2;
                buffer += 2;
        }

        if (count % 2)
                if (!ar9300_eeprom_read_byte(common, address, buffer))
                        goto error;

        return 1;

error:
        DBG("ath9k: "
                "unable to read eeprom region at offset %d\n", address);
        return 0;
}
static int ar9300_otp_read_word ( struct ath_hw ah,
int  addr,
u32 data 
) [static]
static int ar9300_read_otp ( struct ath_hw ah,
int  address,
u8 buffer,
int  count 
) [static]

Definition at line 3135 of file ath9k_ar9003_eeprom.c.

References ar9300_otp_read_word(), count, data, and offset.

Referenced by ar9300_eeprom_restore_internal().

{
        u32 data;
        int i;

        for (i = 0; i < count; i++) {
                int offset = 8 * ((address - i) % 4);
                if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
                        return 0;

                buffer[i] = (data >> offset) & 0xff;
        }

        return 1;
}
static void ar9300_comp_hdr_unpack ( u8 best,
int *  code,
int *  reference,
int *  length,
int *  major,
int *  minor 
) [static]

Definition at line 3153 of file ath9k_ar9003_eeprom.c.

References value.

Referenced by ar9300_eeprom_restore_internal().

{
        unsigned long value[4];

        value[0] = best[0];
        value[1] = best[1];
        value[2] = best[2];
        value[3] = best[3];
        *code = ((value[0] >> 5) & 0x0007);
        *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
        *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
        *major = (value[2] & 0x000f);
        *minor = (value[3] & 0x00ff);
}
static u16 ar9300_comp_cksum ( u8 data,
int  dsize 
) [static]

Definition at line 3169 of file ath9k_ar9003_eeprom.c.

References checksum.

Referenced by ar9300_eeprom_restore_internal().

{
        int it, checksum = 0;

        for (it = 0; it < dsize; it++) {
                checksum += data[it];
                checksum &= 0xffff;
        }

        return checksum;
}
static int ar9300_uncompress_block ( struct ath_hw *ah  __unused,
u8 mptr,
int  mdataSize,
u8 block,
int  size 
) [static]

Definition at line 3181 of file ath9k_ar9003_eeprom.c.

References DBG, DBG2, length, memcpy(), offset, and size.

Referenced by ar9300_compress_decision().

{
        int it;
        int spot;
        int offset;
        int length;

        spot = 0;

        for (it = 0; it < size; it += (length+2)) {
                offset = block[it];
                offset &= 0xff;
                spot += offset;
                length = block[it+1];
                length &= 0xff;

                if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
                        DBG2("ath9k: "
                                "Restore at %d: spot=%d offset=%d length=%d\n",
                                it, spot, offset, length);
                        memcpy(&mptr[spot], &block[it+2], length);
                        spot += length;
                } else if (length > 0) {
                        DBG("ath9k: "
                                "Bad restore at %d: spot=%d offset=%d length=%d\n",
                                it, spot, offset, length);
                        return 0;
                }
        }
        return 1;
}
static int ar9300_compress_decision ( struct ath_hw ah,
int  it,
int  code,
int  reference,
u8 mptr,
u8 word,
int  length,
int  mdata_size 
) [static]

Definition at line 3217 of file ath9k_ar9003_eeprom.c.

References _CompressBlock, _CompressNone, ar9003_eeprom_struct_find_by_id(), ar9300_uncompress_block(), COMP_HDR_LEN, DBG, DBG2, memcpy(), and NULL.

Referenced by ar9300_eeprom_restore_internal().

{
        const struct ar9300_eeprom *eep = NULL;

        switch (code) {
        case _CompressNone:
                if (length != mdata_size) {
                        DBG("ath9k: "
                                "EEPROM structure size mismatch memory=%d eeprom=%d\n",
                                mdata_size, length);
                        return -1;
                }
                memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
                DBG2("ath9k: "
                        "restored eeprom %d: uncompressed, length %d\n",
                        it, length);
                break;
        case _CompressBlock:
                if (reference == 0) {
                } else {
                        eep = ar9003_eeprom_struct_find_by_id(reference);
                        if (eep == NULL) {
                                DBG("ath9k: "
                                        "can't find reference eeprom struct %d\n",
                                        reference);
                                return -1;
                        }
                        memcpy(mptr, eep, mdata_size);
                }
                DBG2("ath9k: "
                        "restore eeprom %d: block, reference %d, length %d\n",
                        it, reference, length);
                ar9300_uncompress_block(ah, mptr, mdata_size,
                                        (u8 *) (word + COMP_HDR_LEN), length);
                break;
        default:
                DBG("ath9k: "
                        "unknown compression code %d\n", code);
                return -1;
        }
        return 0;
}
static int ar9300_check_header ( void *  data) [static]

Definition at line 3268 of file ath9k_ar9003_eeprom.c.

References data.

Referenced by ar9300_check_eeprom_header(), and ar9300_eeprom_restore_internal().

{
        u32 *word = data;
        return !(*word == 0 || *word == (unsigned int)~0);
}
static int ar9300_check_eeprom_header ( struct ath_hw ah,
eeprom_read_op  read,
int  base_addr 
) [static]

Definition at line 3274 of file ath9k_ar9003_eeprom.c.

References ar9300_check_header(), and header.

Referenced by ar9300_eeprom_restore_internal().

{
        u8 header[4];

        if (!read(ah, base_addr, header, 4))
                return 0;

        return ar9300_check_header(header);
}
static int ar9300_eeprom_restore_flash ( struct ath_hw ah,
u8 mptr,
int  mdata_size 
) [static]

Definition at line 3285 of file ath9k_ar9003_eeprom.c.

References ath9k_hw_common(), ath9k_hw_nvram_read(), common, and data.

Referenced by ar9300_eeprom_restore_internal().

{
        struct ath_common *common = ath9k_hw_common(ah);
        u16 *data = (u16 *) mptr;
        int i;

        for (i = 0; i < mdata_size / 2; i++, data++)
                ath9k_hw_nvram_read(common, i, data);

        return 0;
}
static int ar9300_eeprom_restore_internal ( struct ath_hw ah,
u8 mptr,
int  mdata_size 
) [static]

Definition at line 3304 of file ath9k_ar9003_eeprom.c.

References AR9300_BASE_ADDR, AR9300_BASE_ADDR_4K, AR9300_BASE_ADDR_512, ar9300_check_eeprom_header(), ar9300_check_header(), ar9300_comp_cksum(), ar9300_comp_hdr_unpack(), ar9300_compress_decision(), ar9300_eeprom_restore_flash(), ar9300_read_eeprom(), ar9300_read_otp(), AR_SREV_9485, ath9k_hw_use_flash, checksum, code, COMP_CKSUM_LEN, COMP_HDR_LEN, DBG2, EEPROM_DATA_LEN_9485, free, length, major, memcpy(), minor, MSTATE, and zalloc().

Referenced by ath9k_hw_ar9300_fill_eeprom().

{
#define MDEFAULT 15
#define MSTATE 100
        int cptr;
        u8 *word;
        int code;
        int reference, length, major, minor;
        int osize;
        int it;
        u16 checksum, mchecksum;
        eeprom_read_op read;

        if (ath9k_hw_use_flash(ah))
                return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);

        word = zalloc(2048);
        if (!word)
                return -1;

        memcpy(mptr, &ar9300_default, mdata_size);

        read = ar9300_read_eeprom;
        if (AR_SREV_9485(ah))
                cptr = AR9300_BASE_ADDR_4K;
        else
                cptr = AR9300_BASE_ADDR;
        DBG2("ath9k: "
                "Trying EEPROM access at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;

        cptr = AR9300_BASE_ADDR_512;
        DBG2("ath9k: "
                "Trying EEPROM access at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;

        read = ar9300_read_otp;
        cptr = AR9300_BASE_ADDR;
        DBG2("ath9k: "
                "Trying OTP access at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;

        cptr = AR9300_BASE_ADDR_512;
        DBG2("ath9k: "
                "Trying OTP access at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;

        goto fail;

found:
        DBG2("ath9k: Found valid EEPROM data\n");

        for (it = 0; it < MSTATE; it++) {
                if (!read(ah, cptr, word, COMP_HDR_LEN))
                        goto fail;

                if (!ar9300_check_header(word))
                        break;

                ar9300_comp_hdr_unpack(word, &code, &reference,
                                       &length, &major, &minor);
                DBG2("ath9k: "
                        "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
                        cptr, code, reference, length, major, minor);
                if ((!AR_SREV_9485(ah) && length >= 1024) ||
                    (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
                        DBG2("ath9k: "
                                "Skipping bad header\n");
                        cptr -= COMP_HDR_LEN;
                        continue;
                }

                osize = length;
                read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                mchecksum = word[COMP_HDR_LEN + osize] |
                    (word[COMP_HDR_LEN + osize + 1] << 8);
                DBG2("ath9k: "
                        "checksum %x %x\n", checksum, mchecksum);
                if (checksum == mchecksum) {
                        ar9300_compress_decision(ah, it, code, reference, mptr,
                                                 word, length, mdata_size);
                } else {
                        DBG2("ath9k: "
                                "skipping block with bad checksum\n");
                }
                cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
        }

        free(word);
        return cptr;

fail:
        free(word);
        return -1;
}
static int ath9k_hw_ar9300_fill_eeprom ( struct ath_hw ah) [static]

Definition at line 3411 of file ath9k_ar9003_eeprom.c.

References ath_hw::ar9300_eep, ar9300_eeprom_restore_internal(), and ath_hw::eeprom.

{
        u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;

        if (ar9300_eeprom_restore_internal(ah, mptr,
                        sizeof(struct ar9300_eeprom)) < 0)
                return 0;

        return 1;
}
static int ath9k_hw_ar9300_get_eeprom_ver ( struct ath_hw ah) [static]
static int ath9k_hw_ar9300_get_eeprom_rev ( struct ath_hw *ah  __unused) [static]

Definition at line 3429 of file ath9k_ar9003_eeprom.c.

{
        return 0;
}
static s32 ar9003_hw_xpa_bias_level_get ( struct ath_hw ah,
int  is2ghz 
) [static]
static void ar9003_hw_xpa_bias_level_apply ( struct ath_hw ah,
int  is2ghz 
) [static]
static u32 ar9003_hw_ant_ctrl_common_get ( struct ath_hw ah,
int  is2ghz 
) [static]
static u32 ar9003_hw_ant_ctrl_common_2_get ( struct ath_hw ah,
int  is2ghz 
) [static]
static u16 ar9003_hw_ant_ctrl_chain_get ( struct ath_hw ah,
int  chain,
int  is2ghz 
) [static]

Definition at line 3484 of file ath9k_ar9003_eeprom.c.

References ar9300_modal_eep_header::antCtrlChain, ath_hw::ar9300_eep, AR9300_MAX_CHAINS, ath_hw::eeprom, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and val.

Referenced by ar9003_hw_ant_ctrl_apply().

{
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        uint16_t val = 0;

        if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
                if (is2ghz)
                        val = eep->modalHeader2G.antCtrlChain[chain];
                else
                        val = eep->modalHeader5G.antCtrlChain[chain];
        }

        return (uint16_t)(val);
}
static void ar9003_hw_ant_ctrl_apply ( struct ath_hw ah,
int  is2ghz 
) [static]

Definition at line 3501 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_ant_ctrl_chain_get(), ar9003_hw_ant_ctrl_common_2_get(), ar9003_hw_ant_ctrl_common_get(), AR9300_MAX_CHAINS, AR_ANT_DIV_CTRL_ALL, AR_ANT_DIV_CTRL_ALL_S, AR_FAST_DIV_ENABLE, AR_FAST_DIV_ENABLE_S, AR_PHY_9485_ANT_DIV_ALT_GAINTB, AR_PHY_9485_ANT_DIV_ALT_LNACONF, AR_PHY_9485_ANT_DIV_ALT_LNACONF_S, AR_PHY_9485_ANT_DIV_LNA1, AR_PHY_9485_ANT_DIV_LNA2, AR_PHY_9485_ANT_DIV_LNADIV, AR_PHY_9485_ANT_DIV_LNADIV_S, AR_PHY_9485_ANT_DIV_MAIN_GAINTB, AR_PHY_9485_ANT_DIV_MAIN_LNACONF, AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S, AR_PHY_CCK_DETECT, AR_PHY_MC_GAIN_CTRL, AR_PHY_SWITCH_CHAIN_0, AR_PHY_SWITCH_CHAIN_1, AR_PHY_SWITCH_CHAIN_2, AR_PHY_SWITCH_COM, AR_PHY_SWITCH_COM_2, AR_SREV_9485, AR_SWITCH_TABLE_ALL, AR_SWITCH_TABLE_COM2_ALL, AR_SWITCH_TABLE_COM_ALL, ath9k_hw_ar9300_get_eeprom(), BIT, EEP_ANT_DIV_CTL1, ath_hw::eep_ops, eeprom_ops::get_eeprom, REG_READ, REG_RMW_FIELD, REG_WRITE, ath_hw::rxchainmask, ath_hw::txchainmask, and value.

Referenced by ath9k_hw_ar9300_set_board_values().

{
        int chain;
        u32 regval;
        u32 ant_div_ctl1;
        static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
                        AR_PHY_SWITCH_CHAIN_0,
                        AR_PHY_SWITCH_CHAIN_1,
                        AR_PHY_SWITCH_CHAIN_2,
        };

        u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);

        REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);

        value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);

        for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
                if ((ah->rxchainmask & BIT(chain)) ||
                    (ah->txchainmask & BIT(chain))) {
                        value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
                                                             is2ghz);
                        REG_RMW_FIELD(ah, switch_chain_reg[chain],
                                      AR_SWITCH_TABLE_ALL, value);
                }
        }

        if (AR_SREV_9485(ah)) {
                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /*
                 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
                 * are the fields present
                 */
                regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
                regval &= (~AR_ANT_DIV_CTRL_ALL);
                regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
                /* enable_lnadiv */
                regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
                regval |= ((value >> 6) & 0x1) <<
                                AR_PHY_9485_ANT_DIV_LNADIV_S;
                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

                /*enable fast_div */
                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
                regval &= (~AR_FAST_DIV_ENABLE);
                regval |= ((value >> 7) & 0x1) <<
                                AR_FAST_DIV_ENABLE_S;
                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
                ant_div_ctl1 =
                        ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
                /* check whether antenna diversity is enabled */
                if ((ant_div_ctl1 >> 0x6) == 0x3) {
                        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
                        /*
                         * clear bits 25-30 main_lnaconf, alt_lnaconf,
                         * main_tb, alt_tb
                         */
                        regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF |
                                        AR_PHY_9485_ANT_DIV_ALT_GAINTB |
                                        AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
                        /* by default use LNA1 for the main antenna */
                        regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
                        regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
                                        AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
                        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
                }


        }

}
static void ar9003_hw_drive_strength_apply ( struct ath_hw ah) [static]

Definition at line 3576 of file ath9k_ar9003_eeprom.c.

References AR_PHY_65NM_CH0_BIAS1, AR_PHY_65NM_CH0_BIAS2, AR_PHY_65NM_CH0_BIAS4, ath9k_hw_ar9300_get_eeprom(), EEP_DRIVE_STRENGTH, reg, REG_READ, and REG_WRITE.

Referenced by ath9k_hw_ar9300_set_board_values().

{
        int drive_strength;
        unsigned long reg;

        drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);

        if (!drive_strength)
                return;

        reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
        reg &= ~0x00ffffc0;
        reg |= 0x5 << 21;
        reg |= 0x5 << 18;
        reg |= 0x5 << 15;
        reg |= 0x5 << 12;
        reg |= 0x5 << 9;
        reg |= 0x5 << 6;
        REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);

        reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
        reg &= ~0xffffffe0;
        reg |= 0x5 << 29;
        reg |= 0x5 << 26;
        reg |= 0x5 << 23;
        reg |= 0x5 << 20;
        reg |= 0x5 << 17;
        reg |= 0x5 << 14;
        reg |= 0x5 << 11;
        reg |= 0x5 << 8;
        reg |= 0x5 << 5;
        REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);

        reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
        reg &= ~0xff800000;
        reg |= 0x5 << 29;
        reg |= 0x5 << 26;
        reg |= 0x5 << 23;
        REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
}
static u16 ar9003_hw_atten_chain_get ( struct ath_hw ah,
int  chain,
struct ath9k_channel chan 
) [static]

Definition at line 3617 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, ar9300_eeprom::base_ext2, ath9k_channel::channel, ath_hw::eeprom, IS_CHAN_2GHZ, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, value, ar9300_modal_eep_header::xatten1DB, ar9300_BaseExtension_2::xatten1DBHigh, and ar9300_BaseExtension_2::xatten1DBLow.

Referenced by ar9003_hw_atten_apply().

{
        int f[3], t[3];
        u16 value;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        if (chain >= 0 && chain < 3) {
                if (IS_CHAN_2GHZ(chan))
                        return eep->modalHeader2G.xatten1DB[chain];
                else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
                        t[0] = eep->base_ext2.xatten1DBLow[chain];
                        f[0] = 5180;
                        t[1] = eep->modalHeader5G.xatten1DB[chain];
                        f[1] = 5500;
                        t[2] = eep->base_ext2.xatten1DBHigh[chain];
                        f[2] = 5785;
                        value = ar9003_hw_power_interpolate((s32) chan->channel,
                                                            f, t, 3);
                        return value;
                } else
                        return eep->modalHeader5G.xatten1DB[chain];
        }

        return 0;
}
static u16 ar9003_hw_atten_chain_get_margin ( struct ath_hw ah,
int  chain,
struct ath9k_channel chan 
) [static]

Definition at line 3645 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, ar9300_eeprom::base_ext2, ath9k_channel::channel, ath_hw::eeprom, IS_CHAN_2GHZ, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, value, ar9300_modal_eep_header::xatten1Margin, ar9300_BaseExtension_2::xatten1MarginHigh, and ar9300_BaseExtension_2::xatten1MarginLow.

Referenced by ar9003_hw_atten_apply().

{
        int f[3], t[3];
        u16 value;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        if (chain >= 0 && chain < 3) {
                if (IS_CHAN_2GHZ(chan))
                        return eep->modalHeader2G.xatten1Margin[chain];
                else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
                        t[0] = eep->base_ext2.xatten1MarginLow[chain];
                        f[0] = 5180;
                        t[1] = eep->modalHeader5G.xatten1Margin[chain];
                        f[1] = 5500;
                        t[2] = eep->base_ext2.xatten1MarginHigh[chain];
                        f[2] = 5785;
                        value = ar9003_hw_power_interpolate((s32) chan->channel,
                                                            f, t, 3);
                        return value;
                } else
                        return eep->modalHeader5G.xatten1Margin[chain];
        }

        return 0;
}
static void ar9003_hw_atten_apply ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]

Definition at line 3672 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_atten_chain_get(), ar9003_hw_atten_chain_get_margin(), AR_PHY_EXT_ATTEN_CTL_0, AR_PHY_EXT_ATTEN_CTL_1, AR_PHY_EXT_ATTEN_CTL_2, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, BIT, REG_RMW_FIELD, ath_hw::txchainmask, and value.

Referenced by ath9k_hw_ar9300_set_board_values().

{
        int i;
        u16 value;
        unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
                                          AR_PHY_EXT_ATTEN_CTL_1,
                                          AR_PHY_EXT_ATTEN_CTL_2,
                                         };

        /* Test value. if 0 then attenuation is unused. Don't load anything. */
        for (i = 0; i < 3; i++) {
                if (ah->txchainmask & BIT(i)) {
                        value = ar9003_hw_atten_chain_get(ah, i, chan);
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);

                        value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
                        REG_RMW_FIELD(ah, ext_atten_reg[i],
                                      AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
                                      value);
                }
        }
}
static int is_pmu_set ( struct ath_hw ah,
u32  pmu_reg,
int  pmu_set 
) [static]

Definition at line 3696 of file ath9k_ar9003_eeprom.c.

References REG_READ, REG_WRITE, timeout(), and udelay().

Referenced by ar9003_hw_internal_regulator_apply().

{
        int timeout = 100;

        while ((unsigned int)pmu_set != REG_READ(ah, pmu_reg)) {
                if (timeout-- == 0)
                        return 0;
                REG_WRITE(ah, pmu_reg, pmu_set);
                udelay(10);
        }

        return 1;
}
static void ar9003_hw_internal_regulator_apply ( struct ath_hw ah) [static]

Definition at line 3710 of file ath9k_ar9003_eeprom.c.

References AR_PHY_PMU1, AR_PHY_PMU1_PWD, AR_PHY_PMU2, AR_PHY_PMU2_PGM, AR_RTC_FORCE_SWREG_PRD, AR_RTC_REG_CONTROL0, AR_RTC_REG_CONTROL1, AR_RTC_REG_CONTROL1_SWREG_PROGRAM, AR_RTC_SLEEP_CLK, AR_SREV_9485, ath9k_hw_ar9300_get_eeprom(), EEP_INTERNAL_REGULATOR, EEP_SWREG, is_pmu_set(), REG_READ, REG_READ_FIELD, REG_RMW_FIELD, REG_WRITE, swreg, and udelay().

Referenced by ath9k_hw_ar9300_set_board_values().

{
        int internal_regulator =
                ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);

        if (internal_regulator) {
                if (AR_SREV_9485(ah)) {
                        int reg_pmu_set;

                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
                                return;

                        reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
                                      (2 << 14) | (6 << 17) | (1 << 20) |
                                      (3 << 24) | (1 << 28);

                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
                                return;

                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
                                        | (4 << 26);
                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
                                return;

                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
                                        | (1 << 21);
                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
                                return;
                } else {
                        /* Internal regulator is ON. Write swreg register. */
                        int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
                                  REG_READ(ah, AR_RTC_REG_CONTROL1) &
                                  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
                        REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
                        /* Set REG_CONTROL1.SWREG_PROGRAM */
                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
                                  REG_READ(ah,
                                           AR_RTC_REG_CONTROL1) |
                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
                }
        } else {
                if (AR_SREV_9485(ah)) {
                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
                                              AR_PHY_PMU2_PGM))
                                udelay(10);

                        REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
                        while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
                                               AR_PHY_PMU1_PWD))
                                udelay(10);
                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
                        while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
                                              AR_PHY_PMU2_PGM))
                                udelay(10);
                } else
                        REG_WRITE(ah, AR_RTC_SLEEP_CLK,
                                  (REG_READ(ah,
                                   AR_RTC_SLEEP_CLK) |
                                   AR_RTC_FORCE_SWREG_PRD));
        }

}
static void ar9003_hw_apply_tuning_caps ( struct ath_hw ah) [static]
static void ath9k_hw_ar9300_set_board_values ( struct ath_hw ah,
struct ath9k_channel chan 
) [static]
static void ath9k_hw_ar9300_set_addac ( struct ath_hw *ah  __unused,
struct ath9k_channel *chan  __unused 
) [static]

Definition at line 3807 of file ath9k_ar9003_eeprom.c.

{
}
static u8 ar9003_hw_eeprom_get_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
) [static]

Definition at line 3875 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, AR9300_NUM_2G_20_TARGET_POWERS, AR9300_NUM_5G_20_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2G, ar9300_eeprom::calTarget_freqbin_5G, ar9300_eeprom::calTargetPower2G, ar9300_eeprom::calTargetPower5G, ath_hw::eeprom, FBIN2FREQ, and cal_tgt_pow_legacy::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

{
        u16 numPiers, i;
        s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
        s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct cal_tgt_pow_legacy *pEepromTargetPwr;
        u8 *pFreqBin;

        if (is2GHz) {
                numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower2G;
                pFreqBin = eep->calTarget_freqbin_2G;
        } else {
                numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower5G;
                pFreqBin = eep->calTarget_freqbin_5G;
        }

        /*
         * create array of channels and targetpower from
         * targetpower piers stored on eeprom
         */
        for (i = 0; i < numPiers; i++) {
                freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
                targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
        }

        /* interpolate to get target power for given frequency */
        return (u8) ar9003_hw_power_interpolate((s32) freq,
                                                 freqArray,
                                                 targetPowerArray, numPiers);
}
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
) [static]

Definition at line 3910 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, AR9300_NUM_2G_20_TARGET_POWERS, AR9300_NUM_5G_20_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2GHT20, ar9300_eeprom::calTarget_freqbin_5GHT20, ar9300_eeprom::calTargetPower2GHT20, ar9300_eeprom::calTargetPower5GHT20, ath_hw::eeprom, FBIN2FREQ, and cal_tgt_pow_ht::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

{
        u16 numPiers, i;
        s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
        s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct cal_tgt_pow_ht *pEepromTargetPwr;
        u8 *pFreqBin;

        if (is2GHz) {
                numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower2GHT20;
                pFreqBin = eep->calTarget_freqbin_2GHT20;
        } else {
                numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower5GHT20;
                pFreqBin = eep->calTarget_freqbin_5GHT20;
        }

        /*
         * create array of channels and targetpower
         * from targetpower piers stored on eeprom
         */
        for (i = 0; i < numPiers; i++) {
                freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
                targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
        }

        /* interpolate to get target power for given frequency */
        return (u8) ar9003_hw_power_interpolate((s32) freq,
                                                 freqArray,
                                                 targetPowerArray, numPiers);
}
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
) [static]

Definition at line 3946 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, AR9300_NUM_2G_40_TARGET_POWERS, AR9300_NUM_5G_40_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2GHT40, ar9300_eeprom::calTarget_freqbin_5GHT40, ar9300_eeprom::calTargetPower2GHT40, ar9300_eeprom::calTargetPower5GHT40, ath_hw::eeprom, FBIN2FREQ, and cal_tgt_pow_ht::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

{
        u16 numPiers, i;
        s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
        s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct cal_tgt_pow_ht *pEepromTargetPwr;
        u8 *pFreqBin;

        if (is2GHz) {
                numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower2GHT40;
                pFreqBin = eep->calTarget_freqbin_2GHT40;
        } else {
                numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
                pEepromTargetPwr = eep->calTargetPower5GHT40;
                pFreqBin = eep->calTarget_freqbin_5GHT40;
        }

        /*
         * create array of channels and targetpower from
         * targetpower piers stored on eeprom
         */
        for (i = 0; i < numPiers; i++) {
                freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
                targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
        }

        /* interpolate to get target power for given frequency */
        return (u8) ar9003_hw_power_interpolate((s32) freq,
                                                 freqArray,
                                                 targetPowerArray, numPiers);
}
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq 
) [static]

Definition at line 3982 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, AR9300_NUM_2G_CCK_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_Cck, ar9300_eeprom::calTargetPowerCck, ath_hw::eeprom, FBIN2FREQ, and cal_tgt_pow_legacy::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

{
        u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
        s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
        s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
        u8 *pFreqBin = eep->calTarget_freqbin_Cck;

        /*
         * create array of channels and targetpower from
         * targetpower piers stored on eeprom
         */
        for (i = 0; i < numPiers; i++) {
                freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
                targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
        }

        /* interpolate to get target power for given frequency */
        return (u8) ar9003_hw_power_interpolate((s32) freq,
                                                 freqArray,
                                                 targetPowerArray, numPiers);
}
static int ar9003_hw_tx_power_regwrite ( struct ath_hw ah,
u8 pPwrArray 
) [static]

Definition at line 4008 of file ath9k_ar9003_eeprom.c.

References ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_12, ALL_TARGET_HT20_13, ALL_TARGET_HT20_14, ALL_TARGET_HT20_15, ALL_TARGET_HT20_1_3_9_11_17_19, ALL_TARGET_HT20_20, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT20_4, ALL_TARGET_HT20_5, ALL_TARGET_HT20_6, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_12, ALL_TARGET_HT40_13, ALL_TARGET_HT40_14, ALL_TARGET_HT40_15, ALL_TARGET_HT40_1_3_9_11_17_19, ALL_TARGET_HT40_20, ALL_TARGET_HT40_21, ALL_TARGET_HT40_22, ALL_TARGET_HT40_23, ALL_TARGET_HT40_4, ALL_TARGET_HT40_5, ALL_TARGET_HT40_6, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_11L, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_36, ALL_TARGET_LEGACY_48, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_5S, ALL_TARGET_LEGACY_6_24, AR_PHY_POWER_TX_RATE, AR_PHY_TX_FORCED_GAIN, POW_SM, and REG_WRITE.

Referenced by ath9k_hw_ar9300_set_txpower().

{
#define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
        /* make sure forced gain is not set */
        REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);

        /* Write the OFDM power per rate set */

        /* 6 (LSB), 9, 12, 18 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));

        /* 24 (LSB), 36, 48, 54 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));

        /* Write the CCK power per rate set */

        /* 1L (LSB), reserved, 2L, 2S (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
                  /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));

        /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
            );

        /* Write the power for duplicated frames - HT40 */

        /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
        REG_WRITE(ah, 0xa3e0,
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
                  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
            );

        /* Write the HT20 power per rate set */

        /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
                  POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
            );

        /* 6 (LSB), 7, 12, 13 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
                  POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
            );

        /* 14 (LSB), 15, 20, 21 */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
                  POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
            );

        /* Mixed HT20 and HT40 rates */

        /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
                  POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
            );

        /*
         * Write the HT40 power per rate set
         * correct PAR difference between HT40 and HT20/LEGACY
         * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
         */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
                  POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
            );

        /* 6 (LSB), 7, 12, 13 (MSB) */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
                  POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
            );

        /* 14 (LSB), 15, 20, 21 */
        REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
                  POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
                  POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
            );

        return 0;
#undef POW_SM
}
static void ar9003_hw_set_target_power_eeprom ( struct ath_hw ah,
u16  freq,
u8 targetPowerValT2 
) [static]

Definition at line 4125 of file ath9k_ar9003_eeprom.c.

References ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_12, ALL_TARGET_HT20_13, ALL_TARGET_HT20_14, ALL_TARGET_HT20_15, ALL_TARGET_HT20_1_3_9_11_17_19, ALL_TARGET_HT20_20, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT20_4, ALL_TARGET_HT20_5, ALL_TARGET_HT20_6, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_12, ALL_TARGET_HT40_13, ALL_TARGET_HT40_14, ALL_TARGET_HT40_15, ALL_TARGET_HT40_1_3_9_11_17_19, ALL_TARGET_HT40_20, ALL_TARGET_HT40_21, ALL_TARGET_HT40_22, ALL_TARGET_HT40_23, ALL_TARGET_HT40_4, ALL_TARGET_HT40_5, ALL_TARGET_HT40_6, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_11L, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_36, ALL_TARGET_LEGACY_48, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_5S, ALL_TARGET_LEGACY_6_24, ar9003_hw_eeprom_get_cck_tgt_pwr(), ar9003_hw_eeprom_get_ht20_tgt_pwr(), ar9003_hw_eeprom_get_ht40_tgt_pwr(), ar9003_hw_eeprom_get_tgt_pwr(), ar9300RateSize, DBG2, HT_TARGET_RATE_0_8_16, HT_TARGET_RATE_12, HT_TARGET_RATE_13, HT_TARGET_RATE_14, HT_TARGET_RATE_15, HT_TARGET_RATE_1_3_9_11_17_19, HT_TARGET_RATE_20, HT_TARGET_RATE_21, HT_TARGET_RATE_22, HT_TARGET_RATE_23, HT_TARGET_RATE_4, HT_TARGET_RATE_5, HT_TARGET_RATE_6, HT_TARGET_RATE_7, LEGACY_TARGET_RATE_11L, LEGACY_TARGET_RATE_11S, LEGACY_TARGET_RATE_1L_5L, LEGACY_TARGET_RATE_36, LEGACY_TARGET_RATE_48, LEGACY_TARGET_RATE_54, LEGACY_TARGET_RATE_5S, and LEGACY_TARGET_RATE_6_24.

Referenced by ath9k_hw_ar9300_set_txpower().

{
        /* XXX: hard code for now, need to get from eeprom struct */
        u8 ht40PowerIncForPdadc = 0;
        int is2GHz = 0;
        unsigned int i = 0;

        if (freq < 4000)
                is2GHz = 1;

        targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
            ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
                                         is2GHz);
        targetPowerValT2[ALL_TARGET_LEGACY_36] =
            ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
                                         is2GHz);
        targetPowerValT2[ALL_TARGET_LEGACY_48] =
            ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
                                         is2GHz);
        targetPowerValT2[ALL_TARGET_LEGACY_54] =
            ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
                                         is2GHz);
        targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
            ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
                                             freq);
        targetPowerValT2[ALL_TARGET_LEGACY_5S] =
            ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
        targetPowerValT2[ALL_TARGET_LEGACY_11L] =
            ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
        targetPowerValT2[ALL_TARGET_LEGACY_11S] =
            ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
        targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
                                              freq, is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_4] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_5] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_6] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_7] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_12] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_13] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_14] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_15] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_20] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_21] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_22] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT20_23] =
            ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                              is2GHz);
        targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
                                              freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_4] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_5] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_6] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_7] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_12] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_13] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_14] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_15] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_20] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_21] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_22] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
        targetPowerValT2[ALL_TARGET_HT40_23] =
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                              is2GHz) + ht40PowerIncForPdadc;

        for (i = 0; i < ar9300RateSize; i++) {
                DBG2("ath9k: "
                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
        }
}
static int ar9003_hw_cal_pier_get ( struct ath_hw ah,
int  mode,
int  ipier,
int  ichain,
int *  pfrequency,
int *  pcorrection,
int *  ptemperature,
int *  pvoltage 
) [static]

Definition at line 4249 of file ath9k_ar9003_eeprom.c.

References ath_hw::ar9300_eep, AR9300_MAX_CHAINS, AR9300_NUM_2G_CAL_PIERS, AR9300_NUM_5G_CAL_PIERS, ar9300_eeprom::calFreqPier2G, ar9300_eeprom::calFreqPier5G, ar9300_eeprom::calPierData2G, ar9300_eeprom::calPierData5G, DBG, ath_hw::eeprom, FBIN2FREQ, ar9300_cal_data_per_freq_op_loop::refPower, ar9300_cal_data_per_freq_op_loop::tempMeas, and ar9300_cal_data_per_freq_op_loop::voltMeas.

Referenced by ar9003_hw_calibration_apply().

{
        u8 *pCalPier;
        struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
        int is2GHz;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        if (ichain >= AR9300_MAX_CHAINS) {
                DBG("ath9k: "
                        "Invalid chain index, must be less than %d\n",
                        AR9300_MAX_CHAINS);
                return -1;
        }

        if (mode) {             /* 5GHz */
                if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
                        DBG("ath9k: "
                                "Invalid 5GHz cal pier index, must be less than %d\n",
                                AR9300_NUM_5G_CAL_PIERS);
                        return -1;
                }
                pCalPier = &(eep->calFreqPier5G[ipier]);
                pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
                is2GHz = 0;
        } else {
                if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
                        DBG("ath9k: "
                                "Invalid 2GHz cal pier index, must be less than %d\n",
                                AR9300_NUM_2G_CAL_PIERS);
                        return -1;
                }

                pCalPier = &(eep->calFreqPier2G[ipier]);
                pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
                is2GHz = 1;
        }

        *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
        *pcorrection = pCalPierStruct->refPower;
        *ptemperature = pCalPierStruct->tempMeas;
        *pvoltage = pCalPierStruct->voltMeas;

        return 0;
}
static int ar9003_hw_power_control_override ( struct ath_hw ah,
int  frequency,
int *  correction,
int *voltage  __unused,
int *  temperature 
) [static]

Definition at line 4300 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_power_interpolate(), ath_hw::ar9300_eep, AR_PHY_TPC_11_B0, AR_PHY_TPC_11_B1, AR_PHY_TPC_11_B2, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_6_B0, AR_PHY_TPC_6_B1, AR_PHY_TPC_6_B2, AR_PHY_TPC_6_ERROR_EST_MODE, AR_PHY_TPC_6_ERROR_EST_MODE_S, AR_PHY_TPC_OLPC_GAIN_DELTA, AR_PHY_TPC_OLPC_GAIN_DELTA_S, ar9300_eeprom::base_ext2, BIT, ath_hw::caps, ath_hw::eeprom, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, REG_RMW, REG_RMW_FIELD, ar9300_modal_eep_header::tempSlope, tempSlope, ar9300_BaseExtension_2::tempSlopeHigh, ar9300_BaseExtension_2::tempSlopeLow, and ath9k_hw_capabilities::tx_chainmask.

Referenced by ar9003_hw_calibration_apply().

{
        int tempSlope = 0;
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        int f[3], t[3];

        REG_RMW(ah, AR_PHY_TPC_11_B0,
                (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                AR_PHY_TPC_OLPC_GAIN_DELTA);
        if (ah->caps.tx_chainmask & BIT(1))
                REG_RMW(ah, AR_PHY_TPC_11_B1,
                        (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                        AR_PHY_TPC_OLPC_GAIN_DELTA);
        if (ah->caps.tx_chainmask & BIT(2))
                REG_RMW(ah, AR_PHY_TPC_11_B2,
                        (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                        AR_PHY_TPC_OLPC_GAIN_DELTA);

        /* enable open loop power control on chip */
        REG_RMW(ah, AR_PHY_TPC_6_B0,
                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                AR_PHY_TPC_6_ERROR_EST_MODE);
        if (ah->caps.tx_chainmask & BIT(1))
                REG_RMW(ah, AR_PHY_TPC_6_B1,
                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                        AR_PHY_TPC_6_ERROR_EST_MODE);
        if (ah->caps.tx_chainmask & BIT(2))
                REG_RMW(ah, AR_PHY_TPC_6_B2,
                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                        AR_PHY_TPC_6_ERROR_EST_MODE);

        /*
         * enable temperature compensation
         * Need to use register names
         */
        if (frequency < 4000)
                tempSlope = eep->modalHeader2G.tempSlope;
        else if (eep->base_ext2.tempSlopeLow != 0) {
                t[0] = eep->base_ext2.tempSlopeLow;
                f[0] = 5180;
                t[1] = eep->modalHeader5G.tempSlope;
                f[1] = 5500;
                t[2] = eep->base_ext2.tempSlopeHigh;
                f[2] = 5785;
                tempSlope = ar9003_hw_power_interpolate((s32) frequency,
                                                        f, t, 3);
        } else
                tempSlope = eep->modalHeader5G.tempSlope;

        REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
        REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
                      temperature[0]);

        return 0;
}
static int ar9003_hw_calibration_apply ( struct ath_hw ah,
int  frequency 
) [static]

Definition at line 4360 of file ath9k_ar9003_eeprom.c.

References ar9003_hw_cal_pier_get(), ar9003_hw_power_control_override(), AR9300_MAX_CHAINS, AR9300_NUM_2G_CAL_PIERS, AR9300_NUM_5G_CAL_PIERS, DBG2, and interpolate().

Referenced by ath9k_hw_ar9300_set_txpower().

{
        int ichain, ipier, npier;
        int mode;
        int lfrequency[AR9300_MAX_CHAINS],
            lcorrection[AR9300_MAX_CHAINS],
            ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
        int hfrequency[AR9300_MAX_CHAINS],
            hcorrection[AR9300_MAX_CHAINS],
            htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
        int fdiff;
        int correction[AR9300_MAX_CHAINS],
            voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
        int pfrequency, pcorrection, ptemperature, pvoltage;

        mode = (frequency >= 4000);
        if (mode)
                npier = AR9300_NUM_5G_CAL_PIERS;
        else
                npier = AR9300_NUM_2G_CAL_PIERS;

        for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
                lfrequency[ichain] = 0;
                hfrequency[ichain] = 100000;
        }
        /* identify best lower and higher frequency calibration measurement */
        for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
                for (ipier = 0; ipier < npier; ipier++) {
                        if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
                                                    &pfrequency, &pcorrection,
                                                    &ptemperature, &pvoltage)) {
                                fdiff = frequency - pfrequency;

                                /*
                                 * this measurement is higher than
                                 * our desired frequency
                                 */
                                if (fdiff <= 0) {
                                        if (hfrequency[ichain] <= 0 ||
                                            hfrequency[ichain] >= 100000 ||
                                            fdiff >
                                            (frequency - hfrequency[ichain])) {
                                                /*
                                                 * new best higher
                                                 * frequency measurement
                                                 */
                                                hfrequency[ichain] = pfrequency;
                                                hcorrection[ichain] =
                                                    pcorrection;
                                                htemperature[ichain] =
                                                    ptemperature;
                                                hvoltage[ichain] = pvoltage;
                                        }
                                }
                                if (fdiff >= 0) {
                                        if (lfrequency[ichain] <= 0
                                            || fdiff <
                                            (frequency - lfrequency[ichain])) {
                                                /*
                                                 * new best lower
                                                 * frequency measurement
                                                 */
                                                lfrequency[ichain] = pfrequency;
                                                lcorrection[ichain] =
                                                    pcorrection;
                                                ltemperature[ichain] =
                                                    ptemperature;
                                                lvoltage[ichain] = pvoltage;
                                        }
                                }
                        }
                }
        }

        /* interpolate  */
        for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
                DBG2("ath9k: "
                        "ch=%d f=%d low=%d %d h=%d %d\n",
                        ichain, frequency, lfrequency[ichain],
                        lcorrection[ichain], hfrequency[ichain],
                        hcorrection[ichain]);
                /* they're the same, so just pick one */
                if (hfrequency[ichain] == lfrequency[ichain]) {
                        correction[ichain] = lcorrection[ichain];
                        voltage[ichain] = lvoltage[ichain];
                        temperature[ichain] = ltemperature[ichain];
                }
                /* the low frequency is good */
                else if (frequency - lfrequency[ichain] < 1000) {
                        /* so is the high frequency, interpolate */
                        if (hfrequency[ichain] - frequency < 1000) {

                                correction[ichain] = interpolate(frequency,
                                                lfrequency[ichain],
                                                hfrequency[ichain],
                                                lcorrection[ichain],
                                                hcorrection[ichain]);

                                temperature[ichain] = interpolate(frequency,
                                                lfrequency[ichain],
                                                hfrequency[ichain],
                                                ltemperature[ichain],
                                                htemperature[ichain]);

                                voltage[ichain] = interpolate(frequency,
                                                lfrequency[ichain],
                                                hfrequency[ichain],
                                                lvoltage[ichain],
                                                hvoltage[ichain]);
                        }
                        /* only low is good, use it */
                        else {
                                correction[ichain] = lcorrection[ichain];
                                temperature[ichain] = ltemperature[ichain];
                                voltage[ichain] = lvoltage[ichain];
                        }
                }
                /* only high is good, use it */
                else if (hfrequency[ichain] - frequency < 1000) {
                        correction[ichain] = hcorrection[ichain];
                        temperature[ichain] = htemperature[ichain];
                        voltage[ichain] = hvoltage[ichain];
                } else {        /* nothing is good, presume 0???? */
                        correction[ichain] = 0;
                        temperature[ichain] = 0;
                        voltage[ichain] = 0;
                }
        }

        ar9003_hw_power_control_override(ah, frequency, correction, voltage,
                                         temperature);

        DBG2("ath9k: "
                "for frequency=%d, calibration correction = %d %d %d\n",
                frequency, correction[0], correction[1], correction[2]);

        return 0;
}
static u16 ar9003_hw_get_direct_edge_power ( struct ar9300_eeprom eep,
int  idx,
int  edge,
int  is2GHz 
) [static]

Definition at line 4499 of file ath9k_ar9003_eeprom.c.

References CTL_EDGE_TPOWER, ctlEdges, ar9300_eeprom::ctlPowerData_2G, and ar9300_eeprom::ctlPowerData_5G.

Referenced by ar9003_hw_get_max_edge_power().

{
        struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
        struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;

        if (is2GHz)
                return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
        else
                return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
}
static u16 ar9003_hw_get_indirect_edge_power ( struct ar9300_eeprom eep,
int  idx,
unsigned int  edge,
u16  freq,
int  is2GHz 
) [static]

Definition at line 4513 of file ath9k_ar9003_eeprom.c.

References ath9k_hw_fbin2freq(), CTL_EDGE_FLAGS, CTL_EDGE_TPOWER, ar9300_eeprom::ctl_freqbin_2G, ar9300_eeprom::ctl_freqbin_5G, ctlEdges, ar9300_eeprom::ctlPowerData_2G, ar9300_eeprom::ctlPowerData_5G, and MAX_RATE_POWER.

Referenced by ar9003_hw_get_max_edge_power().

{
        struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
        struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;

        u8 *ctl_freqbin = is2GHz ?
                &eep->ctl_freqbin_2G[idx][0] :
                &eep->ctl_freqbin_5G[idx][0];

        if (is2GHz) {
                if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
                    CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
                        return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
        } else {
                if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
                    CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
                        return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
        }

        return MAX_RATE_POWER;
}
static u16 ar9003_hw_get_max_edge_power ( struct ar9300_eeprom eep,
u16  freq,
int  idx,
int  is2GHz 
) [static]

Definition at line 4542 of file ath9k_ar9003_eeprom.c.

References AR5416_BCHAN_UNUSED, ar9003_hw_get_direct_edge_power(), ar9003_hw_get_indirect_edge_power(), AR9300_NUM_BAND_EDGES_2G, AR9300_NUM_BAND_EDGES_5G, ath9k_hw_fbin2freq(), ar9300_eeprom::ctl_freqbin_2G, ar9300_eeprom::ctl_freqbin_5G, and MAX_RATE_POWER.

Referenced by ar9003_hw_set_power_per_rate_table().

{
        u16 twiceMaxEdgePower = MAX_RATE_POWER;
        u8 *ctl_freqbin = is2GHz ?
                &eep->ctl_freqbin_2G[idx][0] :
                &eep->ctl_freqbin_5G[idx][0];
        u16 num_edges = is2GHz ?
                AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
        unsigned int edge;

        /* Get the edge power */
        for (edge = 0;
             (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
             edge++) {
                /*
                 * If there's an exact channel match or an inband flag set
                 * on the lower channel use the given rdEdgePower
                 */
                if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
                        twiceMaxEdgePower =
                                ar9003_hw_get_direct_edge_power(eep, idx,
                                                                edge, is2GHz);
                        break;
                } else if ((edge > 0) &&
                           (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
                                                      is2GHz))) {
                        twiceMaxEdgePower =
                                ar9003_hw_get_indirect_edge_power(eep, idx,
                                                                  edge, freq,
                                                                  is2GHz);
                        /*
                         * Leave loop - no more affecting edges possible in
                         * this monotonic increasing list
                         */
                        break;
                }
        }
        return twiceMaxEdgePower;
}
static void ar9003_hw_set_power_per_rate_table ( struct ath_hw ah,
struct ath9k_channel chan,
u8 pPwrArray,
u16  cfgCtl,
u8  twiceAntennaReduction,
u8  twiceMaxRegulatoryPower,
u16  powerLimit 
) [static]

Definition at line 4583 of file ath9k_ar9003_eeprom.c.

References ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_23, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_6_24, ar9300_modal_eep_header::antennaGain, ar5416_get_ntxchains, ar9003_hw_get_max_edge_power(), ath_hw::ar9300_eep, AR9300_NUM_CTLS_2G, AR9300_NUM_CTLS_5G, ARRAY_SIZE, ath9k_hw_get_channel_centers(), ath9k_hw_regulatory(), ATH9K_TP_SCALE_MAX, ath9k_channel::channel, CTL_11A, CTL_11A_EXT, CTL_11B, CTL_11B_EXT, CTL_11G, CTL_11G_EXT, CTL_2GHT20, CTL_2GHT40, CTL_5GHT20, CTL_5GHT40, chan_centers::ctl_center, CTL_MODE_M, ar9300_eeprom::ctlIndex_2G, ar9300_eeprom::ctlIndex_5G, DBG2, ath_hw::eeprom, EXT_ADDITIVE, chan_centers::ext_center, IS_CHAN_2GHZ, IS_CHAN_HT40, max, MAX_RATE_POWER, min, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, REDUCE_SCALED_POWER_BY_THREE_CHAIN, REDUCE_SCALED_POWER_BY_TWO_CHAIN, SD_NO_CTL, SUB_NUM_CTL_MODES_AT_2G_40, SUB_NUM_CTL_MODES_AT_5G_40, chan_centers::synth_center, ath_regulatory::tp_scale, and ath_hw::txchainmask.

Referenced by ath9k_hw_ar9300_set_txpower().

{
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
        u16 twiceMaxEdgePower = MAX_RATE_POWER;
        static const u16 tpScaleReductionTable[5] = {
                0, 3, 6, 9, MAX_RATE_POWER
        };
        int i;
        int16_t  twiceLargestAntenna;
        u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
        static const u16 ctlModesFor11a[] = {
                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
        };
        static const u16 ctlModesFor11g[] = {
                CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
                CTL_11G_EXT, CTL_2GHT40
        };
        u16 numCtlModes;
        const u16 *pCtlMode;
        u16 ctlMode, freq;
        struct chan_centers centers;
        u8 *ctlIndex;
        u8 ctlNum;
        u16 twiceMinEdgePower;
        int is2ghz = IS_CHAN_2GHZ(chan);

        ath9k_hw_get_channel_centers(ah, chan, &centers);

        /* Compute TxPower reduction due to Antenna Gain */
        if (is2ghz)
                twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
        else
                twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;

        twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
                                twiceLargestAntenna, 0);

        /*
         * scaledPower is the minimum of the user input power level
         * and the regulatory allowed power level
         */
        maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;

        if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
                maxRegAllowedPower -=
                        (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
        }

        scaledPower = min(powerLimit, maxRegAllowedPower);

        /*
         * Reduce scaled Power by number of chains active to get
         * to per chain tx power level
         */
        switch (ar5416_get_ntxchains(ah->txchainmask)) {
        case 1:
                break;
        case 2:
                if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
                        scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
                else
                        scaledPower = 0;
                break;
        case 3:
                if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
                        scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
                else
                        scaledPower = 0;
                break;
        }

        scaledPower = max((u16)0, scaledPower);

        /*
         * Get target powers from EEPROM - our baseline for TX Power
         */
        if (is2ghz) {
                /* Setup for CTL modes */
                /* CTL_11B, CTL_11G, CTL_2GHT20 */
                numCtlModes =
                        ARRAY_SIZE(ctlModesFor11g) -
                                   SUB_NUM_CTL_MODES_AT_2G_40;
                pCtlMode = ctlModesFor11g;
                if (IS_CHAN_HT40(chan))
                        /* All 2G CTL's */
                        numCtlModes = ARRAY_SIZE(ctlModesFor11g);
        } else {
                /* Setup for CTL modes */
                /* CTL_11A, CTL_5GHT20 */
                numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
                                         SUB_NUM_CTL_MODES_AT_5G_40;
                pCtlMode = ctlModesFor11a;
                if (IS_CHAN_HT40(chan))
                        /* All 5G CTL's */
                        numCtlModes = ARRAY_SIZE(ctlModesFor11a);
        }

        /*
         * For MIMO, need to apply regulatory caps individually across
         * dynamically running modes: CCK, OFDM, HT20, HT40
         *
         * The outer loop walks through each possible applicable runtime mode.
         * The inner loop walks through each ctlIndex entry in EEPROM.
         * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
         */
        for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
                int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
                        (pCtlMode[ctlMode] == CTL_2GHT40);
                if (isHt40CtlMode)
                        freq = centers.synth_center;
                else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
                        freq = centers.ext_center;
                else
                        freq = centers.ctl_center;

                DBG2("ath9k: "
                        "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
                        ctlMode, numCtlModes, isHt40CtlMode,
                        (pCtlMode[ctlMode] & EXT_ADDITIVE));

                /* walk through each CTL index stored in EEPROM */
                if (is2ghz) {
                        ctlIndex = pEepData->ctlIndex_2G;
                        ctlNum = AR9300_NUM_CTLS_2G;
                } else {
                        ctlIndex = pEepData->ctlIndex_5G;
                        ctlNum = AR9300_NUM_CTLS_5G;
                }

                for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
                        DBG2("ath9k: "
                                "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
                                i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
                                chan->channel);

                                /*
                                 * compare test group from regulatory
                                 * channel list with test mode from pCtlMode
                                 * list
                                 */
                                if ((((cfgCtl & ~CTL_MODE_M) |
                                       (pCtlMode[ctlMode] & CTL_MODE_M)) ==
                                        ctlIndex[i]) ||
                                    (((cfgCtl & ~CTL_MODE_M) |
                                       (pCtlMode[ctlMode] & CTL_MODE_M)) ==
                                     ((ctlIndex[i] & CTL_MODE_M) |
                                       SD_NO_CTL))) {
                                        twiceMinEdgePower =
                                          ar9003_hw_get_max_edge_power(pEepData,
                                                                       freq, i,
                                                                       is2ghz);

                                        if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
                                                /*
                                                 * Find the minimum of all CTL
                                                 * edge powers that apply to
                                                 * this channel
                                                 */
                                                twiceMaxEdgePower =
                                                        min(twiceMaxEdgePower,
                                                            twiceMinEdgePower);
                                                else {
                                                        /* specific */
                                                        twiceMaxEdgePower =
                                                          twiceMinEdgePower;
                                                        break;
                                                }
                                }
                        }

                        minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);

                        DBG2("ath9k: "
                                "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
                                ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
                                scaledPower, minCtlPower);

                        /* Apply ctl mode to correct target power set */
                        switch (pCtlMode[ctlMode]) {
                        case CTL_11B:
                                for (i = ALL_TARGET_LEGACY_1L_5L;
                                     i <= ALL_TARGET_LEGACY_11S; i++)
                                        pPwrArray[i] =
                                          (u8)min((u16)pPwrArray[i],
                                                  minCtlPower);
                                break;
                        case CTL_11A:
                        case CTL_11G:
                                for (i = ALL_TARGET_LEGACY_6_24;
                                     i <= ALL_TARGET_LEGACY_54; i++)
                                        pPwrArray[i] =
                                          (u8)min((u16)pPwrArray[i],
                                                  minCtlPower);
                                break;
                        case CTL_5GHT20:
                        case CTL_2GHT20:
                                for (i = ALL_TARGET_HT20_0_8_16;
                                     i <= ALL_TARGET_HT20_21; i++)
                                        pPwrArray[i] =
                                          (u8)min((u16)pPwrArray[i],
                                                  minCtlPower);
                                pPwrArray[ALL_TARGET_HT20_22] =
                                  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
                                          minCtlPower);
                                pPwrArray[ALL_TARGET_HT20_23] =
                                  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
                                           minCtlPower);
                                break;
                        case CTL_5GHT40:
                        case CTL_2GHT40:
                                for (i = ALL_TARGET_HT40_0_8_16;
                                     i <= ALL_TARGET_HT40_23; i++)
                                        pPwrArray[i] =
                                          (u8)min((u16)pPwrArray[i],
                                                  minCtlPower);
                                break;
                        default:
                            break;
                        }
        } /* end ctl mode checking */
}
static u8 mcsidx_to_tgtpwridx ( unsigned int  mcs_idx,
u8  base_pwridx 
) [inline, static]

Definition at line 4811 of file ath9k_ar9003_eeprom.c.

Referenced by ath9k_hw_ar9300_set_txpower().

{
        u8 mod_idx = mcs_idx % 8;

        if (mod_idx <= 3)
                return mod_idx ? (base_pwridx + 1) : base_pwridx;
        else
                return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
}
static void ath9k_hw_ar9300_set_txpower ( struct ath_hw ah,
struct ath9k_channel chan,
u16  cfgCtl,
u8  twiceAntennaReduction,
u8  twiceMaxRegulatoryPower,
u8  powerLimit,
int  test 
) [static]

Definition at line 4821 of file ath9k_ar9003_eeprom.c.

References abs, ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_6_24, ar9003_get_paprd_scale_factor(), ar9003_hw_calibration_apply(), ar9003_hw_set_power_per_rate_table(), ar9003_hw_set_target_power_eeprom(), ar9003_hw_tx_power_regwrite(), ath_hw::ar9300_eep, AR9300_PAPRD_RATE_MASK, ar9300RateSize, ath9k_hw_regulatory(), ath9k_channel::channel, DBG2, ath_hw::eep_ops, EEP_PAPRD, ath_hw::eeprom, eeprom_ops::get_eeprom, IS_CHAN_2GHZ, IS_CHAN_HT20, IS_CHAN_HT40, ath_regulatory::max_power_level, mcsidx_to_tgtpwridx(), memcpy(), ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, ar9300_modal_eep_header::papdRateMaskHt20, ar9300_modal_eep_header::papdRateMaskHt40, ath_hw::paprd_ratemask, ath_hw::paprd_ratemask_ht40, ath_hw::paprd_table_write_done, ath_hw::paprd_target_power, and ath_hw::txpower_limit.

{
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
        struct ar9300_modal_eep_header *modal_hdr;
        u8 targetPowerValT2[ar9300RateSize];
        u8 target_power_val_t2_eep[ar9300RateSize];
        unsigned int i = 0, paprd_scale_factor = 0;
        u8 pwr_idx, min_pwridx = 0;

        ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);

        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
                if (IS_CHAN_2GHZ(chan))
                        modal_hdr = &eep->modalHeader2G;
                else
                        modal_hdr = &eep->modalHeader5G;

                ah->paprd_ratemask =
                                (uint32_t)(modal_hdr->papdRateMaskHt20) &
                        AR9300_PAPRD_RATE_MASK;

                ah->paprd_ratemask_ht40 =
                                (uint32_t)(modal_hdr->papdRateMaskHt40) &
                        AR9300_PAPRD_RATE_MASK;

                paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
                min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
                                                  ALL_TARGET_HT20_0_8_16;

                if (!ah->paprd_table_write_done) {
                        memcpy(target_power_val_t2_eep, targetPowerValT2,
                               sizeof(targetPowerValT2));
                        for (i = 0; i < 24; i++) {
                                pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
                                if (ah->paprd_ratemask & (1 << i)) {
                                        if (targetPowerValT2[pwr_idx] &&
                                            targetPowerValT2[pwr_idx] ==
                                            target_power_val_t2_eep[pwr_idx])
                                                targetPowerValT2[pwr_idx] -=
                                                        paprd_scale_factor;
                                }
                        }
                }
                memcpy(target_power_val_t2_eep, targetPowerValT2,
                       sizeof(targetPowerValT2));
        }

        ar9003_hw_set_power_per_rate_table(ah, chan,
                                           targetPowerValT2, cfgCtl,
                                           twiceAntennaReduction,
                                           twiceMaxRegulatoryPower,
                                           powerLimit);

        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
                for (i = 0; i < ar9300RateSize; i++) {
                        if ((ah->paprd_ratemask & (1 << i)) &&
                            ((unsigned int)abs(targetPowerValT2[i] -
                                target_power_val_t2_eep[i]) >
                            paprd_scale_factor)) {
                                ah->paprd_ratemask &= ~(1 << i);
                                DBG2("ath9k: "
                                        "paprd disabled for mcs %d\n", i);
                        }
                }
        }

        regulatory->max_power_level = 0;
        for (i = 0; i < ar9300RateSize; i++) {
                if (targetPowerValT2[i] > regulatory->max_power_level)
                        regulatory->max_power_level = targetPowerValT2[i];
        }

        if (test)
                return;

        for (i = 0; i < ar9300RateSize; i++) {
                DBG2("ath9k: "
                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
        }

        /*
         * This is the TX power we send back to driver core,
         * and it can use to pass to userspace to display our
         * currently configured TX power setting.
         *
         * Since power is rate dependent, use one of the indices
         * from the AR9300_Rates enum to select an entry from
         * targetPowerValT2[] to report. Currently returns the
         * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
         * as CCK power is less interesting (?).
         */
        i = ALL_TARGET_LEGACY_6_24; /* legacy */
        if (IS_CHAN_HT40(chan))
                i = ALL_TARGET_HT40_0_8_16; /* ht40 */
        else if (IS_CHAN_HT20(chan))
                i = ALL_TARGET_HT20_0_8_16; /* ht20 */

        ah->txpower_limit = targetPowerValT2[i];
        regulatory->max_power_level = targetPowerValT2[i];

        /* Write target power array to registers */
        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
        ar9003_hw_calibration_apply(ah, chan->channel);

        if (IS_CHAN_2GHZ(chan)) {
                if (IS_CHAN_HT40(chan))
                        i = ALL_TARGET_HT40_0_8_16;
                else
                        i = ALL_TARGET_HT20_0_8_16;
        } else {
                if (IS_CHAN_HT40(chan))
                        i = ALL_TARGET_HT40_7;
                else
                        i = ALL_TARGET_HT20_7;
        }
        ah->paprd_target_power = targetPowerValT2[i];
}
static u16 ath9k_hw_ar9300_get_spur_channel ( struct ath_hw *ah  __unused,
u16 __unused,
int is2GHz  __unused 
) [static]

Definition at line 4944 of file ath9k_ar9003_eeprom.c.

References AR_NO_SPUR.

{
        return AR_NO_SPUR;
}

Definition at line 4950 of file ath9k_ar9003_eeprom.c.

References ath_hw::ar9300_eep, ar9300_eeprom::baseEepHeader, ath_hw::eeprom, and ar9300_base_eep_hdr::txrxgain.

Referenced by ar9003_tx_gain_table_apply().

{
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
}

Definition at line 4957 of file ath9k_ar9003_eeprom.c.

References ath_hw::ar9300_eep, ar9300_eeprom::baseEepHeader, ath_hw::eeprom, and ar9300_base_eep_hdr::txrxgain.

Referenced by ar9003_rx_gain_table_apply().

{
        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;

        return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
}
u8* ar9003_get_spur_chan_ptr ( struct ath_hw ah,
int  is_2ghz 
)
unsigned int ar9003_get_paprd_scale_factor ( struct ath_hw ah,
struct ath9k_channel chan 
)

Variable Documentation

struct ar9300_eeprom ar9300_default [static]

Definition at line 74 of file ath9k_ar9003_eeprom.c.

struct ar9300_eeprom ar9300_x113 [static]

Definition at line 652 of file ath9k_ar9003_eeprom.c.

struct ar9300_eeprom ar9300_h112 [static]

Definition at line 1230 of file ath9k_ar9003_eeprom.c.

struct ar9300_eeprom ar9300_x112 [static]

Definition at line 1808 of file ath9k_ar9003_eeprom.c.

struct ar9300_eeprom ar9300_h116 [static]

Definition at line 2385 of file ath9k_ar9003_eeprom.c.

struct ar9300_eeprom* ar9300_eep_templates[] [static]
Initial value:

Definition at line 2963 of file ath9k_ar9003_eeprom.c.

Initial value:

Definition at line 4995 of file ath9k_ar9003_eeprom.c.

Referenced by ath9k_hw_eeprom_init().