iPXE
amd8111e.c
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1 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
2  * Copyright (C) 2004 Advanced Micro Devices
3  * Copyright (C) 2005 Liu Tao <liutao1980@gmail.com> [etherboot port]
4  *
5  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
6  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
7  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
8  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
9  * Copyright 1993 United States Government as represented by the
10  * Director, National Security Agency.[ pcnet32.c ]
11  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
12  * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
13  *
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
28  * 02110-1301, USA.
29  * USA
30  */
31 
32 FILE_LICENCE ( GPL2_OR_LATER );
33 
34 #include "etherboot.h"
35 #include "nic.h"
36 #include "mii.h"
37 #include <ipxe/pci.h>
38 #include <ipxe/ethernet.h>
39 #include "string.h"
40 #include "stdint.h"
41 #include "amd8111e.h"
42 
43 
44 /* driver definitions */
45 #define NUM_TX_SLOTS 2
46 #define NUM_RX_SLOTS 4
47 #define TX_SLOTS_MASK 1
48 #define RX_SLOTS_MASK 3
49 
50 #define TX_BUF_LEN 1536
51 #define RX_BUF_LEN 1536
52 
53 #define TX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN)
54 #define RX_PKT_LEN_MIN 60
55 #define RX_PKT_LEN_MAX ETH_FRAME_LEN
56 
57 #define TX_TIMEOUT 3000
58 #define TX_PROCESS_TIME 10
59 #define TX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME)
60 
61 #define PHY_RW_RETRY 10
62 
63 
71 };
72 
80 };
81 
82 struct eth_frame {
87 } __attribute__((packed));
88 
89 struct amd8111e_priv {
92  unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN];
93  unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN];
94  unsigned long tx_idx, rx_idx;
96 
97  char opened;
98  char link;
99  char speed;
100  char duplex;
103 
104  struct pci_device *pdev;
105  struct nic *nic;
106  void *mmio;
107 };
108 
109 static struct amd8111e_priv amd8111e;
110 
111 
112 /********************************************************
113  * locale functions *
114  ********************************************************/
115 static void amd8111e_init_hw_default(struct amd8111e_priv *lp);
116 static int amd8111e_start(struct amd8111e_priv *lp);
117 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val);
118 #if 0
119 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val);
120 #endif
121 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp);
122 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp);
123 static void amd8111e_enable_interrupt(struct amd8111e_priv *lp);
124 static void amd8111e_force_interrupt(struct amd8111e_priv *lp);
125 static int amd8111e_get_mac_address(struct amd8111e_priv *lp);
126 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp);
127 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp);
128 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index);
129 static void amd8111e_wait_link(struct amd8111e_priv *lp);
130 static void amd8111e_poll_link(struct amd8111e_priv *lp);
131 static void amd8111e_restart(struct amd8111e_priv *lp);
132 
133 
134 /*
135  * This function clears necessary the device registers.
136  */
138 {
139  unsigned int reg_val;
140  void *mmio = lp->mmio;
141 
142  /* stop the chip */
143  writel(RUN, mmio + CMD0);
144 
145  /* Clear RCV_RING_BASE_ADDR */
147 
148  /* Clear XMT_RING_BASE_ADDR */
153 
154  /* Clear CMD0 */
156 
157  /* Clear CMD2 */
159 
160  /* Clear CMD7 */
162 
163  /* Clear DLY_INT_A and DLY_INT_B */
164  writel(0x0, mmio + DLY_INT_A);
165  writel(0x0, mmio + DLY_INT_B);
166 
167  /* Clear FLOW_CONTROL */
168  writel(0x0, mmio + FLOW_CONTROL);
169 
170  /* Clear INT0 write 1 to clear register */
171  reg_val = readl(mmio + INT0);
172  writel(reg_val, mmio + INT0);
173 
174  /* Clear STVAL */
175  writel(0x0, mmio + STVAL);
176 
177  /* Clear INTEN0 */
179 
180  /* Clear LADRF */
181  writel(0x0, mmio + LADRF);
182 
183  /* Set SRAM_SIZE & SRAM_BOUNDARY registers */
184  writel(0x80010, mmio + SRAM_SIZE);
185 
186  /* Clear RCV_RING0_LEN */
187  writel(0x0, mmio + RCV_RING_LEN0);
188 
189  /* Clear XMT_RING0/1/2/3_LEN */
190  writel(0x0, mmio + XMT_RING_LEN0);
191  writel(0x0, mmio + XMT_RING_LEN1);
192  writel(0x0, mmio + XMT_RING_LEN2);
193  writel(0x0, mmio + XMT_RING_LEN3);
194 
195  /* Clear XMT_RING_LIMIT */
196  writel(0x0, mmio + XMT_RING_LIMIT);
197 
198  /* Clear MIB */
200 
201  /* Clear LARF */
202  writel( 0, mmio + LADRF);
203  writel( 0, mmio + LADRF + 4);
204 
205  /* SRAM_SIZE register */
206  reg_val = readl(mmio + SRAM_SIZE);
207 
208  /* Set default value to CTRL1 Register */
210 
211  /* To avoid PCI posting bug */
212  readl(mmio + CMD2);
213 }
214 
215 /*
216  * This function initializes the device registers and starts the device.
217  */
218 static int amd8111e_start(struct amd8111e_priv *lp)
219 {
220  struct nic *nic = lp->nic;
221  void *mmio = lp->mmio;
222  int i, reg_val;
223 
224  /* stop the chip */
225  writel(RUN, mmio + CMD0);
226 
227  /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
228  writew(0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
229 
230  /* enable the port manager and set auto negotiation always */
231  writel(VAL1 | EN_PMGR, mmio + CMD3 );
232  writel(XPHYANE | XPHYRST, mmio + CTRL2);
233 
234  /* set control registers */
235  reg_val = readl(mmio + CTRL1);
236  reg_val &= ~XMTSP_MASK;
237  writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
238 
239  /* initialize tx and rx ring base addresses */
246 
247  /* set default IPG to 96 */
248  writew(DEFAULT_IPG, mmio + IPG);
249  writew(DEFAULT_IPG - IFS1_DELTA, mmio + IFS1);
250 
251  /* AutoPAD transmit, Retransmit on Underflow */
252  writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
253 
254  /* JUMBO disabled */
255  writel(JUMBO, mmio + CMD3);
256 
257  /* Setting the MAC address to the device */
258  for(i = 0; i < ETH_ALEN; i++)
259  writeb(nic->node_addr[i], mmio + PADR + i);
260 
261  /* set RUN bit to start the chip, interrupt not enabled */
262  writel(VAL2 | RDMD0 | VAL0 | RUN, mmio + CMD0);
263 
264  /* To avoid PCI posting bug */
265  readl(mmio + CMD0);
266  return 0;
267 }
268 
269 /*
270 This function will read the PHY registers.
271 */
272 static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
273 {
274  void *mmio = lp->mmio;
275  unsigned int reg_val;
276  unsigned int retry = PHY_RW_RETRY;
277 
278  reg_val = readl(mmio + PHY_ACCESS);
279  while (reg_val & PHY_CMD_ACTIVE)
280  reg_val = readl(mmio + PHY_ACCESS);
281 
282  writel(PHY_RD_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16),
283  mmio + PHY_ACCESS);
284  do {
285  reg_val = readl(mmio + PHY_ACCESS);
286  udelay(30); /* It takes 30 us to read/write data */
287  } while (--retry && (reg_val & PHY_CMD_ACTIVE));
288 
289  if (reg_val & PHY_RD_ERR) {
290  *val = 0;
291  return -1;
292  }
293 
294  *val = reg_val & 0xffff;
295  return 0;
296 }
297 
298 /*
299 This function will write into PHY registers.
300 */
301 #if 0
302 static int amd8111e_write_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 val)
303 {
304  void *mmio = lp->mmio;
305  unsigned int reg_val;
306  unsigned int retry = PHY_RW_RETRY;
307 
308  reg_val = readl(mmio + PHY_ACCESS);
309  while (reg_val & PHY_CMD_ACTIVE)
310  reg_val = readl(mmio + PHY_ACCESS);
311 
312  writel(PHY_WR_CMD | ((phy_addr & 0x1f) << 21) | ((reg & 0x1f) << 16) | val,
313  mmio + PHY_ACCESS);
314  do {
315  reg_val = readl(mmio + PHY_ACCESS);
316  udelay(30); /* It takes 30 us to read/write the data */
317  } while (--retry && (reg_val & PHY_CMD_ACTIVE));
318 
319  if(reg_val & PHY_RD_ERR)
320  return -1;
321 
322  return 0;
323 }
324 #endif
325 
326 static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
327 {
328  int i;
329 
330  lp->ext_phy_id = 0;
331  lp->ext_phy_addr = 1;
332 
333  for (i = 0x1e; i >= 0; i--) {
334  u32 id1, id2;
335 
336  if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
337  continue;
338  if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
339  continue;
340  lp->ext_phy_id = (id1 << 16) | id2;
341  lp->ext_phy_addr = i;
342  break;
343  }
344 
345  if (lp->ext_phy_id)
346  printf("Found MII PHY ID 0x%08x at address 0x%02x\n",
347  (unsigned int) lp->ext_phy_id, lp->ext_phy_addr);
348  else
349  printf("Couldn't detect MII PHY, assuming address 0x01\n");
350 }
351 
353 {
354  void *mmio = lp->mmio;
355  unsigned int int0;
356 
357  writel(INTREN, mmio + CMD0);
358  writel(INTEN0_CLEAR, mmio + INTEN0);
359  int0 = readl(mmio + INT0);
360  writel(int0, mmio + INT0);
361  readl(mmio + INT0);
362 }
363 
365 {
366  void *mmio = lp->mmio;
367 
368  writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
369  writel(VAL0 | INTREN, mmio + CMD0);
370  readl(mmio + CMD0);
371 }
372 
374 {
375  void *mmio = lp->mmio;
376 
377  writel(VAL0 | UINTCMD, mmio + CMD0);
378  readl(mmio + CMD0);
379 }
380 
382 {
383  struct nic *nic = lp->nic;
384  void *mmio = lp->mmio;
385  int i;
386 
387  /* BIOS should have set mac address to PADR register,
388  * so we read PADR to get it.
389  */
390  for (i = 0; i < ETH_ALEN; i++)
391  nic->node_addr[i] = readb(mmio + PADR + i);
392 
393  DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) );
394 
395  return 0;
396 }
397 
398 static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
399 {
400  int i;
401 
402  lp->rx_idx = 0;
403 
404  /* Initilaizing receive descriptors */
405  for (i = 0; i < NUM_RX_SLOTS; i++) {
408  wmb();
410  }
411 
412  return 0;
413 }
414 
415 static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
416 {
417  int i;
418 
419  lp->tx_idx = 0;
420  lp->tx_consistent = 1;
421 
422  /* Initializing transmit descriptors */
423  for (i = 0; i < NUM_TX_SLOTS; i++) {
424  lp->tx_ring[i].tx_flags = 0;
425  lp->tx_ring[i].buf_phy_addr = 0;
426  lp->tx_ring[i].buf_len = 0;
427  }
428 
429  return 0;
430 }
431 
432 static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
433 {
434  volatile u16 status;
435  int retry = TX_RETRY;
436 
438  while (--retry && (status & OWN_BIT)) {
441  }
442  if (status & OWN_BIT) {
443  printf("Error: tx slot %d timeout, stat = 0x%x\n", index, status);
444  amd8111e_restart(lp);
445  return -1;
446  }
447 
448  return 0;
449 }
450 
451 static void amd8111e_wait_link(struct amd8111e_priv *lp)
452 {
453  unsigned int status;
454  u32 reg_val;
455 
456  do {
457  /* read phy to update STAT0 register */
458  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
459  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
460  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
461  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
462  status = readl(lp->mmio + STAT0);
463  } while (!(status & AUTONEG_COMPLETE) || !(status & LINK_STATS));
464 }
465 
466 static void amd8111e_poll_link(struct amd8111e_priv *lp)
467 {
468  unsigned int status, speed;
469  u32 reg_val;
470 
471  if (!lp->link) {
472  /* read phy to update STAT0 register */
473  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMCR, &reg_val);
474  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_BMSR, &reg_val);
475  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_ADVERTISE, &reg_val);
476  amd8111e_read_phy(lp, lp->ext_phy_addr, MII_LPA, &reg_val);
477  status = readl(lp->mmio + STAT0);
478 
479  if (status & LINK_STATS) {
480  lp->link = 1;
481  speed = (status & SPEED_MASK) >> 7;
482  if (speed == PHY_SPEED_100)
483  lp->speed = 1;
484  else
485  lp->speed = 0;
486  if (status & FULL_DPLX)
487  lp->duplex = 1;
488  else
489  lp->duplex = 0;
490 
491  printf("Link is up: %s Mbps %s duplex\n",
492  lp->speed ? "100" : "10", lp->duplex ? "full" : "half");
493  }
494  } else {
495  status = readl(lp->mmio + STAT0);
496  if (!(status & LINK_STATS)) {
497  lp->link = 0;
498  printf("Link is down\n");
499  }
500  }
501 }
502 
503 static void amd8111e_restart(struct amd8111e_priv *lp)
504 {
505  printf("\nStarting nic...\n");
510  amd8111e_start(lp);
511 
512  printf("Waiting link up...\n");
513  lp->link = 0;
514  amd8111e_wait_link(lp);
515  amd8111e_poll_link(lp);
516 }
517 
518 
519 /********************************************************
520  * Interface Functions *
521  ********************************************************/
522 
523 static void amd8111e_transmit(struct nic *nic, const char *dst_addr,
524  unsigned int type, unsigned int size, const char *packet)
525 {
526  struct amd8111e_priv *lp = nic->priv_data;
527  struct eth_frame *frame;
528  unsigned int index;
529 
530  /* check packet size */
531  if (size > TX_PKT_LEN_MAX) {
532  printf("amd8111e_transmit(): too large packet, drop\n");
533  return;
534  }
535 
536  /* get tx slot */
537  index = lp->tx_idx;
538  if (amd8111e_wait_tx_ring(lp, index))
539  return;
540 
541  /* fill frame */
542  frame = (struct eth_frame *)lp->tx_buf[index];
543  memset(frame->data, 0, TX_PKT_LEN_MAX);
544  memcpy(frame->dst_addr, dst_addr, ETH_ALEN);
545  memcpy(frame->src_addr, nic->node_addr, ETH_ALEN);
546  frame->type = htons(type);
547  memcpy(frame->data, packet, size);
548 
549  /* start xmit */
552  wmb();
553  lp->tx_ring[index].tx_flags =
555  writel(VAL1 | TDMD0, lp->mmio + CMD0);
556  readl(lp->mmio + CMD0);
557 
558  /* update slot pointer */
559  lp->tx_idx = (lp->tx_idx + 1) & TX_SLOTS_MASK;
560 }
561 
562 static int amd8111e_poll(struct nic *nic, int retrieve)
563 {
564  /* return true if there's an ethernet packet ready to read */
565  /* nic->packet should contain data on return */
566  /* nic->packetlen should contain length of data */
567 
568  struct amd8111e_priv *lp = nic->priv_data;
569  u16 status, pkt_len;
570  unsigned int index, pkt_ok;
571 
572  amd8111e_poll_link(lp);
573 
574  index = lp->rx_idx;
576  pkt_len = le16_to_cpu(lp->rx_ring[index].msg_len) - 4; /* remove 4bytes FCS */
577 
578  if (status & OWN_BIT)
579  return 0;
580 
581  if (status & ERR_BIT)
582  pkt_ok = 0;
583  else if (!(status & STP_BIT))
584  pkt_ok = 0;
585  else if (!(status & ENP_BIT))
586  pkt_ok = 0;
587  else if (pkt_len < RX_PKT_LEN_MIN)
588  pkt_ok = 0;
589  else if (pkt_len > RX_PKT_LEN_MAX)
590  pkt_ok = 0;
591  else
592  pkt_ok = 1;
593 
594  if (pkt_ok) {
595  if (!retrieve)
596  return 1;
597  nic->packetlen = pkt_len;
599  }
600 
603  wmb();
605  writel(VAL2 | RDMD0, lp->mmio + CMD0);
606  readl(lp->mmio + CMD0);
607 
608  lp->rx_idx = (lp->rx_idx + 1) & RX_SLOTS_MASK;
609  return pkt_ok;
610 }
611 
612 static void amd8111e_disable(struct nic *nic)
613 {
614  struct amd8111e_priv *lp = nic->priv_data;
615 
616  /* disable interrupt */
618 
619  /* stop chip */
621 
622  /* unmap mmio */
623  iounmap(lp->mmio);
624 
625  /* update status */
626  lp->opened = 0;
627 }
628 
629 static void amd8111e_irq(struct nic *nic, irq_action_t action)
630 {
631  struct amd8111e_priv *lp = nic->priv_data;
632 
633  switch (action) {
634  case DISABLE:
636  break;
637  case ENABLE:
639  break;
640  case FORCE:
642  break;
643  }
644 }
645 
648  .poll = amd8111e_poll,
649  .transmit = amd8111e_transmit,
650  .irq = amd8111e_irq,
651 };
652 
653 static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
654 {
655  struct amd8111e_priv *lp = &amd8111e;
656  unsigned long mmio_start, mmio_len;
657 
658  nic->ioaddr = pdev->ioaddr;
659  nic->irqno = pdev->irq;
660 
661  mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
662  mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0);
663 
664  memset(lp, 0, sizeof(*lp));
665  lp->pdev = pdev;
666  lp->nic = nic;
667  lp->mmio = ioremap(mmio_start, mmio_len);
668  lp->opened = 1;
670 
671  nic->priv_data = lp;
672 
673  amd8111e_restart(lp);
674 
676  return 1;
677 }
678 
679 static struct pci_device_id amd8111e_nics[] = {
680  PCI_ROM(0x1022, 0x7462, "amd8111e", "AMD8111E", 0),
681 };
682 
683 PCI_DRIVER ( amd8111e_driver, amd8111e_nics, PCI_NO_CLASS );
684 
685 DRIVER ( "AMD8111E", nic_driver, pci_driver, amd8111e_driver,
687 
688 /*
689  * Local variables:
690  * c-basic-offset: 8
691  * c-indent-level: 8
692  * tab-width: 8
693  * End:
694  */
unsigned char irqno
Definition: nic.h:56
#define MII_ADVERTISE
Definition: atl1e.h:875
uint16_t u16
Definition: stdint.h:21
static void amd8111e_force_interrupt(struct amd8111e_priv *lp)
Definition: amd8111e.c:373
#define __attribute__(x)
Definition: compiler.h:10
Definition: nic.h:35
#define MII_LPA
Definition: atl1e.h:876
uint8_t irq
Interrupt number.
Definition: pci.h:208
Definition: amd8111e.h:195
wmb()
uint8_t readb(volatile uint8_t *io_addr)
Read byte from memory-mapped device.
#define XMT_RING_LEN2
Definition: amd8111e.h:106
u16 type
Definition: amd8111e.c:85
#define PADR
Definition: amd8111e.h:116
int printf(const char *fmt,...)
Write a formatted string to the console.
Definition: vsprintf.c:464
Definition: epic100.h:31
A PCI driver.
Definition: pci.h:224
void * mmio
Definition: amd8111e.c:106
#define DLY_INT_A
Definition: amd8111e.h:84
unsigned long ioaddr
I/O address.
Definition: pci.h:200
#define XMT_RING_BASE_ADDR2
Definition: amd8111e.h:94
static struct pci_device_id amd8111e_nics[]
Definition: amd8111e.c:679
uint8_t type
Type.
Definition: ena.h:16
char speed
Definition: amd8111e.c:99
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
#define CMD0
Definition: amd8111e.h:66
#define TX_BUF_LEN
Definition: amd8111e.c:50
#define DLY_INT_B
Definition: amd8111e.h:85
static int amd8111e_poll(struct nic *nic, int retrieve)
Definition: amd8111e.c:562
Definition: amd8111e.h:248
#define PHY_SPEED_100
Definition: amd8111e.h:161
#define PCI_BASE_ADDRESS_0
Definition: pci.h:61
#define IFS1
Definition: amd8111e.h:118
static void amd8111e_irq(struct nic *nic, irq_action_t action)
Definition: amd8111e.c:629
#define XMT_RING_LIMIT
Definition: amd8111e.h:74
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:149
Definition: amd8111e.h:198
Definition: amd8111e.h:196
int dummy_connect(struct nic *nic __unused)
Definition: legacy.c:151
struct amd8111e_tx_desc tx_ring[NUM_TX_SLOTS]
Definition: amd8111e.c:90
void writeb(uint8_t data, volatile uint8_t *io_addr)
Write byte to memory-mapped device.
#define SRAM_SIZE
Definition: amd8111e.h:111
struct pci_device * pdev
Definition: amd8111e.c:104
static int amd8111e_read_phy(struct amd8111e_priv *lp, int phy_addr, int reg, u32 *val)
Definition: amd8111e.c:272
#define RX_PKT_LEN_MIN
Definition: amd8111e.c:54
DRIVER("AMD8111E", nic_driver, pci_driver, amd8111e_driver, amd8111e_probe, amd8111e_disable)
static int amd8111e_get_mac_address(struct amd8111e_priv *lp)
Definition: amd8111e.c:381
uint8_t status
Status.
Definition: ena.h:16
#define INT0
Definition: amd8111e.h:64
unsigned long frame
Definition: xengrant.h:178
void * memcpy(void *dest, const void *src, size_t len) __nonnull
unsigned int ioaddr
Definition: nic.h:55
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
#define ETH_HLEN
Definition: if_ether.h:9
Ethernet protocol.
static void amd8111e_poll_link(struct amd8111e_priv *lp)
Definition: amd8111e.c:466
#define ETH_FRAME_LEN
Definition: if_ether.h:11
#define PHY_ACCESS
Definition: amd8111e.h:88
unsigned long rx_idx
Definition: amd8111e.c:94
static void amd8111e_disable(struct nic *nic)
Definition: amd8111e.c:612
#define XMT_RING_BASE_ADDR0
Definition: amd8111e.h:92
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
unsigned char tx_buf[NUM_TX_SLOTS][TX_BUF_LEN]
Definition: amd8111e.c:92
#define RCV_RING_BASE_ADDR0
Definition: amd8111e.h:97
void * priv_data
Definition: nic.h:59
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition: pci.c:96
irq_action_t
Definition: nic.h:34
#define CTRL2
Definition: amd8111e.h:72
#define RCV_RING_LEN0
Definition: amd8111e.h:109
static int amd8111e_start(struct amd8111e_priv *lp)
Definition: amd8111e.c:218
struct nic * nic
Definition: amd8111e.c:105
static int amd8111e_init_tx_ring(struct amd8111e_priv *lp)
Definition: amd8111e.c:415
#define cpu_to_le32(value)
Definition: byteswap.h:107
char opened
Definition: amd8111e.c:97
#define CMD2
Definition: amd8111e.h:67
static void amd8111e_wait_link(struct amd8111e_priv *lp)
Definition: amd8111e.c:451
unsigned int packetlen
Definition: nic.h:54
static struct nic_operations amd8111e_operations
Definition: amd8111e.c:646
static void amd8111e_probe_ext_phy(struct amd8111e_priv *lp)
Definition: amd8111e.c:326
static void amd8111e_enable_interrupt(struct amd8111e_priv *lp)
Definition: amd8111e.c:364
#define CMD3
Definition: amd8111e.h:68
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Find the size of a PCI BAR.
Definition: pciextra.c:90
static unsigned int unsigned int reg
Definition: intel.h:245
#define XMT_RING_LEN3
Definition: amd8111e.h:107
PCI bus.
#define RX_PKT_LEN_MAX
Definition: amd8111e.c:55
A PCI device.
Definition: pci.h:187
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:175
#define IFS1_DELTA
Definition: amd8111e.h:572
unsigned long tx_idx
Definition: amd8111e.c:94
#define NUM_TX_SLOTS
Definition: amd8111e.c:45
static int amd8111e_probe(struct nic *nic, struct pci_device *pdev)
Definition: amd8111e.c:653
#define TX_SLOTS_MASK
Definition: amd8111e.c:47
#define STVAL
Definition: amd8111e.h:90
#define MII_BMCR
Definition: atl1e.h:871
int ext_phy_addr
Definition: amd8111e.c:101
#define ETH_ALEN
Definition: if_ether.h:8
A PCI device ID list entry.
Definition: pci.h:151
Definition: nic.h:37
#define le16_to_cpu(value)
Definition: byteswap.h:112
#define LADRF
Definition: amd8111e.h:123
Definition: nic.h:49
#define TX_RETRY
Definition: amd8111e.c:59
void __asmcall int val
Definition: setjmp.h:28
u8 data[ETH_FRAME_LEN - ETH_HLEN]
Definition: amd8111e.c:86
static void amd8111e_restart(struct amd8111e_priv *lp)
Definition: amd8111e.c:503
static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
Definition: amd8111e.c:137
static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
Definition: amd8111e.c:352
Definition: nic.h:36
unsigned char * packet
Definition: nic.h:53
#define NUM_RX_SLOTS
Definition: amd8111e.c:46
Definition: amd8111e.h:197
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:78
unsigned char * node_addr
Definition: nic.h:52
static int amd8111e_init_rx_ring(struct amd8111e_priv *lp)
Definition: amd8111e.c:398
Media Independent Interface constants.
PCI_DRIVER(amd8111e_driver, amd8111e_nics, PCI_NO_CLASS)
#define MIB_ADDR
Definition: amd8111e.h:62
#define writew
Definition: w89c840.c:159
#define MII_PHYSID2
Definition: atl1e.h:874
#define TX_PKT_LEN_MAX
Definition: amd8111e.c:53
static struct amd8111e_priv amd8111e
Definition: amd8111e.c:109
#define cpu_to_le16(value)
Definition: byteswap.h:106
#define TX_PROCESS_TIME
Definition: amd8111e.c:58
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
void iounmap(volatile const void *io_addr)
Unmap I/O address.
u8 src_addr[ETH_ALEN]
Definition: amd8111e.c:84
FILE_LICENCE(GPL2_OR_LATER)
#define RX_SLOTS_MASK
Definition: amd8111e.c:48
#define XMT_RING_LEN1
Definition: amd8111e.h:105
int tx_consistent
Definition: amd8111e.c:95
#define CTRL1
Definition: amd8111e.h:71
#define PHY_RW_RETRY
Definition: amd8111e.c:61
#define CMD7
Definition: amd8111e.h:69
#define RX_BUF_LEN
Definition: amd8111e.c:51
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
void * ioremap(unsigned long bus_addr, size_t len)
Map bus address as an I/O address.
struct nic_operations * nic_op
Definition: nic.h:50
unsigned char rx_buf[NUM_RX_SLOTS][RX_BUF_LEN]
Definition: amd8111e.c:93
#define MII_BMSR
Definition: atl1e.h:872
#define MII_PHYSID1
Definition: atl1e.h:873
struct nic nic
Definition: legacy.c:22
#define FLOW_CONTROL
Definition: amd8111e.h:87
uint64_t index
Index of the first segment within the content.
Definition: pccrc.h:21
#define DEFAULT_IPG
Definition: amd8111e.h:571
int(* connect)(struct nic *)
Definition: nic.h:63
u32 ext_phy_id
Definition: amd8111e.c:102
#define XMT_RING_LEN0
Definition: amd8111e.h:104
String functions.
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:283
#define XMT_RING_BASE_ADDR3
Definition: amd8111e.h:95
#define STAT0
Definition: amd8111e.h:63
#define htons(value)
Definition: byteswap.h:135
static void amd8111e_transmit(struct nic *nic, const char *dst_addr, unsigned int type, unsigned int size, const char *packet)
Definition: amd8111e.c:523
#define AUTOPOLL0
Definition: amd8111e.h:76
uint8_t u8
Definition: stdint.h:19
static int amd8111e_wait_tx_ring(struct amd8111e_priv *lp, unsigned int index)
Definition: amd8111e.c:432
uint32_t u32
Definition: stdint.h:23
u8 dst_addr[ETH_ALEN]
Definition: amd8111e.c:83
#define XMT_RING_BASE_ADDR1
Definition: amd8111e.h:93
#define INTEN0
Definition: amd8111e.h:65
void * memset(void *dest, int character, size_t len) __nonnull
struct amd8111e_rx_desc rx_ring[NUM_RX_SLOTS]
Definition: amd8111e.c:91