iPXE
Functions | Variables
ice.c File Reference

Intel 100 Gigabit Ethernet network card driver. More...

#include <stdint.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/iobuf.h>
#include <ipxe/pci.h>
#include "ice.h"

Go to the source code of this file.

Functions

 FILE_LICENCE (GPL2_OR_LATER_OR_UBDL)
 
 FILE_SECBOOT (PERMITTED)
 
static int ice_admin_version (struct intelxl_nic *intelxl)
 Get firmware version. More...
 
static int ice_admin_mac_read (struct net_device *netdev)
 Get MAC address. More...
 
static int ice_admin_mac_write (struct net_device *netdev)
 Set MAC address. More...
 
static int ice_admin_switch (struct intelxl_nic *intelxl)
 Get switch configuration. More...
 
static int ice_admin_rules (struct intelxl_nic *intelxl, uint8_t *mac)
 Add switch rules. More...
 
static struct ice_admin_schedule_nodeice_admin_schedule_is_parent (struct ice_admin_schedule_branch *branch, struct ice_admin_schedule_node *node)
 Check if scheduler node is a parent (i.e. More...
 
static int ice_admin_schedule (struct intelxl_nic *intelxl)
 Query default scheduling tree topology. More...
 
static int ice_admin_autoneg (struct intelxl_nic *intelxl)
 Restart autonegotiation. More...
 
static int ice_admin_link (struct net_device *netdev)
 Get link status. More...
 
static void ice_admin_event (struct net_device *netdev, struct intelxl_admin_descriptor *xlevt, union intelxl_admin_buffer *xlbuf __unused)
 Handle admin event. More...
 
static int ice_admin_add_txq (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Add transmit queue. More...
 
static int ice_admin_disable_txq (struct intelxl_nic *intelxl)
 Disable transmit queue. More...
 
static void ice_dump_tx (struct intelxl_nic *intelxl)
 Dump transmit queue context (for debugging) More...
 
static void ice_dump_rx (struct intelxl_nic *intelxl)
 Dump receive queue context (for debugging) More...
 
static int ice_create_tx (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Create transmit queue. More...
 
static void ice_destroy_tx (struct intelxl_nic *intelxl, struct intelxl_ring *ring)
 Destroy transmit queue. More...
 
static int ice_context_rx (struct intelxl_nic *intelxl, physaddr_t address)
 Program receive queue context. More...
 
static int ice_open (struct net_device *netdev)
 Open network device. More...
 
static void ice_close (struct net_device *netdev)
 Close network device. More...
 
static int ice_probe (struct pci_device *pci)
 Probe PCI device. More...
 
static void ice_remove (struct pci_device *pci)
 Remove PCI device. More...
 

Variables

static uint8_t ice_magic_mac [ETH_HLEN] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 }
 Magic MAC address. More...
 
static struct net_device_operations ice_operations
 Network device operations. More...
 
static struct pci_device_id ice_nics []
 PCI device IDs. More...
 
struct pci_driver ice_driver __pci_driver
 PCI driver. More...
 

Detailed Description

Intel 100 Gigabit Ethernet network card driver.

Definition in file ice.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL  )

◆ FILE_SECBOOT()

FILE_SECBOOT ( PERMITTED  )

◆ ice_admin_version()

static int ice_admin_version ( struct intelxl_nic intelxl)
static

Get firmware version.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 66 of file ice.c.

66  {
67  struct ice_admin_descriptor *cmd;
69  unsigned int api;
70  int rc;
71 
72  /* Populate descriptor */
73  cmd = ice_admin_command_descriptor ( intelxl );
75  version = &cmd->params.version;
76 
77  /* Issue command */
78  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
79  return rc;
80  api = version->api.major;
81  DBGC ( intelxl, "ICE %p firmware v%d/%d.%d.%d API v%d/%d.%d.%d\n",
82  intelxl, version->firmware.branch, version->firmware.major,
83  version->firmware.minor, version->firmware.patch,
84  version->api.branch, version->api.major, version->api.minor,
85  version->api.patch );
86 
87  /* Check for API compatibility */
88  if ( api > INTELXL_ADMIN_API_MAJOR ) {
89  DBGC ( intelxl, "ICE %p unsupported API v%d\n", intelxl, api );
90  return -ENOTSUP;
91  }
92 
93  return 0;
94 }
Admin queue Get Version command parameters.
Definition: ice.h:123
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct pci_api * api
API for this bus:dev.fn address.
Definition: pcicloud.c:42
#define DBGC(...)
Definition: compiler.h:505
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
#define ENOTSUP
Operation not supported.
Definition: errno.h:590
u32 version
Driver version.
Definition: ath9k_hw.c:1985
#define INTELXL_ADMIN_VERSION
Admin queue Get Version command.
Definition: intelxl.h:88
#define INTELXL_ADMIN_API_MAJOR
Admin queue API major version.
Definition: intelxl.h:490
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References api, cmd, cpu_to_le16, DBGC, ENOTSUP, ice_admin_command_descriptor(), INTELXL_ADMIN_API_MAJOR, intelxl_admin_command(), INTELXL_ADMIN_VERSION, rc, and version.

◆ ice_admin_mac_read()

static int ice_admin_mac_read ( struct net_device netdev)
static

Get MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 102 of file ice.c.

102  {
103  struct intelxl_nic *intelxl = netdev->priv;
104  struct ice_admin_descriptor *cmd;
107  union ice_admin_buffer *buf;
108  unsigned int i;
109  int rc;
110 
111  /* Populate descriptor */
112  cmd = ice_admin_command_descriptor ( intelxl );
113  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_MAC_READ );
114  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
115  cmd->len = cpu_to_le16 ( sizeof ( buf->mac_read ) );
116  read = &cmd->params.mac_read;
117  buf = ice_admin_command_buffer ( intelxl );
118 
119  /* Issue command */
120  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
121  return rc;
122 
123  /* Check that MAC address is present in response */
124  if ( ! ( read->valid & INTELXL_ADMIN_MAC_READ_VALID_LAN ) ) {
125  DBGC ( intelxl, "ICE %p has no MAC address\n", intelxl );
126  return -ENOENT;
127  }
128 
129  /* Identify MAC address */
130  for ( i = 0 ; i < read->count ; i++ ) {
131 
132  /* Check for a LAN MAC address */
133  mac = &buf->mac_read.mac[i];
134  if ( mac->type != ICE_ADMIN_MAC_READ_TYPE_LAN )
135  continue;
136 
137  /* Check that address is valid */
138  if ( ! is_valid_ether_addr ( mac->mac ) ) {
139  DBGC ( intelxl, "ICE %p has invalid MAC address "
140  "(%s)\n", intelxl, eth_ntoa ( mac->mac ) );
141  return -EINVAL;
142  }
143 
144  /* Copy MAC address */
145  DBGC ( intelxl, "ICE %p has MAC address %s\n",
146  intelxl, eth_ntoa ( mac->mac ) );
147  memcpy ( netdev->hw_addr, mac->mac, ETH_ALEN );
148 
149  return 0;
150  }
151 
152  /* Missing LAN MAC address */
153  DBGC ( intelxl, "ICE %p has no LAN MAC address\n",
154  intelxl );
155  return -ENOENT;
156 }
Admin queue data buffer.
Definition: ice.h:459
#define EINVAL
Invalid argument.
Definition: errno.h:429
struct option_descriptor read[1]
Definition: nvo_cmd.c:116
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
MAC Address description.
Definition: ice.h:147
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:515
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
#define INTELXL_ADMIN_MAC_READ_VALID_LAN
LAN MAC address is valid.
Definition: intelxl.h:161
void * memcpy(void *dest, const void *src, size_t len) __nonnull
struct ice_admin_mac_read_buffer mac_read
Manage MAC Address Read data buffer.
Definition: ice.h:463
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
Admin queue Manage MAC Address Read command parameters.
Definition: ice.h:135
#define INTELXL_ADMIN_MAC_READ
Admin queue Manage MAC Address Read command.
Definition: intelxl.h:150
const char * eth_ntoa(const void *ll_addr)
Transcribe Ethernet address.
Definition: ethernet.c:176
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define ETH_ALEN
Definition: if_ether.h:9
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition: ethernet.h:78
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
#define ICE_ADMIN_MAC_READ_TYPE_LAN
LAN MAC address type.
Definition: ice.h:157
struct ice_admin_mac_read_address mac[4]
MAC addresses.
Definition: ice.h:162
#define cpu_to_le16(value)
Definition: byteswap.h:107
uint8_t hw_addr[MAX_HW_ADDR_LEN]
Hardware address.
Definition: netdevice.h:382
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, EINVAL, ENOENT, ETH_ALEN, eth_ntoa(), net_device::hw_addr, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_ADMIN_MAC_READ_TYPE_LAN, intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_MAC_READ, INTELXL_ADMIN_MAC_READ_VALID_LAN, is_valid_ether_addr(), mac, ice_admin_mac_read_buffer::mac, ice_admin_buffer::mac_read, memcpy(), netdev, net_device::priv, rc, and read.

Referenced by ice_probe().

◆ ice_admin_mac_write()

static int ice_admin_mac_write ( struct net_device netdev)
static

Set MAC address.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 164 of file ice.c.

164  {
165  struct intelxl_nic *intelxl = netdev->priv;
166  struct ice_admin_descriptor *cmd;
168  int rc;
169 
170  /* Populate descriptor */
171  cmd = ice_admin_command_descriptor ( intelxl );
173  write = &cmd->params.mac_write;
174  memcpy ( write->mac, netdev->ll_addr, ETH_ALEN );
175 
176  /* Issue command */
177  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
178  return rc;
179 
180  return 0;
181 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
void * memcpy(void *dest, const void *src, size_t len) __nonnull
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
device nvs write
Definition: threewire.h:61
Admin queue Manage MAC Address Write command parameters.
Definition: ice.h:166
#define INTELXL_ADMIN_MAC_WRITE
Admin queue Manage MAC Address Write command.
Definition: intelxl.h:176
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define ETH_ALEN
Definition: if_ether.h:9
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
#define cpu_to_le16(value)
Definition: byteswap.h:107
uint8_t ll_addr[MAX_LL_ADDR_LEN]
Link-layer address.
Definition: netdevice.h:388
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, ETH_ALEN, ice_admin_command_descriptor(), intelxl_admin_command(), INTELXL_ADMIN_MAC_WRITE, net_device::ll_addr, memcpy(), netdev, net_device::priv, rc, and write.

Referenced by ice_open().

◆ ice_admin_switch()

static int ice_admin_switch ( struct intelxl_nic intelxl)
static

Get switch configuration.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 189 of file ice.c.

189  {
190  struct ice_admin_descriptor *cmd;
191  struct ice_admin_switch_params *sw;
192  union ice_admin_buffer *buf;
193  uint16_t next = 0;
194  uint16_t seid;
195  uint16_t type;
196  int rc;
197 
198  /* Get each configuration in turn */
199  do {
200  /* Populate descriptor */
201  cmd = ice_admin_command_descriptor ( intelxl );
202  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
203  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
204  cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
205  sw = &cmd->params.sw;
206  sw->next = next;
207  buf = ice_admin_command_buffer ( intelxl );
208 
209  /* Issue command */
210  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
211  return rc;
212  seid = le16_to_cpu ( buf->sw.cfg[0].seid );
213 
214  /* Dump raw configuration */
215  DBGC2 ( intelxl, "ICE %p SEID %#04x:\n", intelxl, seid );
216  DBGC2_HDA ( intelxl, 0, &buf->sw.cfg[0],
217  sizeof ( buf->sw.cfg[0] ) );
218 
219  /* Parse response */
220  type = ( seid & ICE_ADMIN_SWITCH_TYPE_MASK );
221  if ( type == ICE_ADMIN_SWITCH_TYPE_VSI ) {
222  intelxl->vsi = ( seid & ~ICE_ADMIN_SWITCH_TYPE_MASK );
223  DBGC ( intelxl, "ICE %p VSI %#04x uplink %#04x func "
224  "%#04x\n", intelxl, intelxl->vsi,
225  le16_to_cpu ( buf->sw.cfg[0].uplink ),
226  le16_to_cpu ( buf->sw.cfg[0].func ) );
227  }
228 
229  } while ( ( next = sw->next ) );
230 
231  /* Check that we found a VSI */
232  if ( ! intelxl->vsi ) {
233  DBGC ( intelxl, "ICE %p has no VSI\n", intelxl );
234  return -ENOENT;
235  }
236 
237  return 0;
238 }
Admin queue data buffer.
Definition: ice.h:459
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
unsigned short uint16_t
Definition: stdint.h:11
#define INTELXL_ADMIN_SWITCH
Admin queue Get Switch Configuration command.
Definition: intelxl.h:207
uint32_t type
Operating system type.
Definition: ena.h:12
uint16_t uplink
Uplink switching element ID.
Definition: ice.h:194
#define DBGC(...)
Definition: compiler.h:505
#define ENOENT
No such file or directory.
Definition: errno.h:515
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
uint16_t func
PF/VF number.
Definition: ice.h:196
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
uint16_t seid
Switching element ID and flags.
Definition: ice.h:192
Admin queue Get Switch Configuration command parameters.
Definition: ice.h:178
#define ICE_ADMIN_SWITCH_TYPE_MASK
Switching element ID type mask.
Definition: ice.h:200
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
struct ice_admin_switch_config cfg[1]
Switch configuration.
Definition: ice.h:208
#define le16_to_cpu(value)
Definition: byteswap.h:113
uint32_t next
Next descriptor address.
Definition: dwmac.h:22
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
#define DBGC2(...)
Definition: compiler.h:522
#define ICE_ADMIN_SWITCH_TYPE_VSI
Virtual Station Interface element type.
Definition: ice.h:203
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
struct ice_admin_switch_buffer sw
Get Switch Configuration data buffer.
Definition: ice.h:465

References ice_admin_switch_buffer::cfg, cmd, cpu_to_le16, DBGC, DBGC2, DBGC2_HDA, ENOENT, ice_admin_switch_config::func, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_ADMIN_SWITCH_TYPE_MASK, ICE_ADMIN_SWITCH_TYPE_VSI, intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_SWITCH, le16_to_cpu, next, rc, ice_admin_switch_config::seid, ice_admin_buffer::sw, type, ice_admin_switch_config::uplink, and intelxl_nic::vsi.

Referenced by ice_probe().

◆ ice_admin_rules()

static int ice_admin_rules ( struct intelxl_nic intelxl,
uint8_t mac 
)
static

Add switch rules.

Parameters
intelxlIntel device
macMAC address
Return values
rcReturn status code

Definition at line 247 of file ice.c.

247  {
248  struct ice_admin_descriptor *cmd;
249  struct ice_admin_rules_params *rules;
250  union ice_admin_buffer *buf;
251  int rc;
252 
253  /* Populate descriptor */
254  cmd = ice_admin_command_descriptor ( intelxl );
255  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_ADD_RULES );
257  cmd->len = cpu_to_le16 ( sizeof ( buf->rules ) );
258  rules = &cmd->params.rules;
259  rules->count = cpu_to_le16 ( 1 );
260  buf = ice_admin_command_buffer ( intelxl );
262  buf->rules.port = cpu_to_le16 ( intelxl->port );
263  buf->rules.action =
265  ICE_ADMIN_RULES_ACTION_VSI ( intelxl->vsi ) );
266  buf->rules.len = cpu_to_le16 ( sizeof ( buf->rules.hdr ) );
267  memcpy ( buf->rules.hdr.eth.h_dest, mac, ETH_ALEN );
270 
271  /* Issue command */
272  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
273  return rc;
274 
275  return 0;
276 }
Admin queue data buffer.
Definition: ice.h:459
uint16_t h_protocol
Protocol ID.
Definition: if_ether.h:38
uint16_t len
Header length.
Definition: ice.h:237
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define ICE_ADMIN_ADD_RULES
Admin queue Add Switch Rules command.
Definition: ice.h:212
#define ICE_ADMIN_RULES_RECIPE_PROMISC
Switch rule promiscuous recipe ID.
Definition: ice.h:248
#define ICE_ADMIN_RULES_ACTION_VALID
Switch rule action valid.
Definition: ice.h:251
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
uint16_t port
Source port.
Definition: ice.h:231
uint8_t mac[ETH_ALEN]
MAC address.
Definition: ena.h:24
Admin queue Add Switch Rules command parameters.
Definition: ice.h:215
uint8_t h_dest[ETH_ALEN]
Destination MAC address.
Definition: if_ether.h:34
void * memcpy(void *dest, const void *src, size_t len) __nonnull
union ice_admin_rules_buffer::@60 hdr
Header data.
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
#define ICE_ADMIN_RULES_ACTION_VSI(x)
Switch rule VSI number.
Definition: ice.h:254
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
unsigned int port
Port number.
Definition: intelxl.h:923
uint8_t h_source[ETH_ALEN]
Source MAC address.
Definition: if_ether.h:36
#define ETH_ALEN
Definition: if_ether.h:9
struct ethhdr eth
Ethernet header.
Definition: ice.h:241
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
uint32_t action
Action.
Definition: ice.h:233
struct ice_admin_rules_buffer rules
Add Switch Rules data buffer.
Definition: ice.h:467
static uint8_t ice_magic_mac[ETH_HLEN]
Magic MAC address.
Definition: ice.c:51
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:443
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define htons(value)
Definition: byteswap.h:136
#define ETH_P_8021Q
Definition: if_ether.h:22
uint16_t recipe
Receipt ID.
Definition: ice.h:229

References ice_admin_rules_buffer::action, cmd, cpu_to_le16, cpu_to_le32, ice_admin_rules_buffer::eth, ETH_ALEN, ETH_P_8021Q, ethhdr::h_dest, ethhdr::h_protocol, ethhdr::h_source, ice_admin_rules_buffer::hdr, htons, ICE_ADMIN_ADD_RULES, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_ADMIN_RULES_ACTION_VALID, ICE_ADMIN_RULES_ACTION_VSI, ICE_ADMIN_RULES_RECIPE_PROMISC, ice_magic_mac, intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, ice_admin_rules_buffer::len, mac, memcpy(), ice_admin_rules_buffer::port, intelxl_nic::port, rc, ice_admin_rules_buffer::recipe, ice_admin_buffer::rules, and intelxl_nic::vsi.

Referenced by ice_probe().

◆ ice_admin_schedule_is_parent()

static struct ice_admin_schedule_node* ice_admin_schedule_is_parent ( struct ice_admin_schedule_branch branch,
struct ice_admin_schedule_node node 
)
static

Check if scheduler node is a parent (i.e.

non-leaf) node

Parameters
branchScheduler topology branch
nodeScheduler topology node
Return values
childAny child node, or NULL if not found

Definition at line 286 of file ice.c.

287  {
288  unsigned int count = le16_to_cpu ( branch->count );
289  struct ice_admin_schedule_node *child;
290  unsigned int i;
291 
292  /* Find a child element, if any */
293  for ( i = 0 ; i < count ; i++ ) {
294  child = &branch->node[i];
295  if ( child->parent == node->teid )
296  return child;
297  }
298 
299  return NULL;
300 }
uint16_t count
Number of nodes.
Definition: ice.h:296
struct ice_admin_schedule_node node[0]
Nodes.
Definition: ice.h:300
Admin queue Query Default Scheduling Tree Topology node.
Definition: ice.h:282
static unsigned int count
Number of entries.
Definition: dwmac.h:225
#define le16_to_cpu(value)
Definition: byteswap.h:113
uint32_t node
NUMA node register offset.
Definition: ena.h:18
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
uint32_t parent
Parent TEID.
Definition: ice.h:284

References count, ice_admin_schedule_branch::count, le16_to_cpu, node, ice_admin_schedule_branch::node, NULL, and ice_admin_schedule_node::parent.

Referenced by ice_admin_schedule().

◆ ice_admin_schedule()

static int ice_admin_schedule ( struct intelxl_nic intelxl)
static

Query default scheduling tree topology.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 308 of file ice.c.

308  {
309  struct ice_admin_descriptor *cmd;
310  struct ice_admin_schedule_params *sched;
311  struct ice_admin_schedule_branch *branch;
313  union ice_admin_buffer *buf;
314  int i;
315  int rc;
316 
317  /* Populate descriptor */
318  cmd = ice_admin_command_descriptor ( intelxl );
319  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_SCHEDULE );
320  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
321  cmd->len = cpu_to_le16 ( sizeof ( buf->sched ) );
322  sched = &cmd->params.sched;
323  buf = ice_admin_command_buffer ( intelxl );
324 
325  /* Issue command */
326  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
327  return rc;
328 
329  /* Sanity checks */
330  if ( ! sched->branches ) {
331  DBGC ( intelxl, "ICE %p topology has no branches\n", intelxl );
332  return -EINVAL;
333  }
334  branch = buf->sched.branch;
335 
336  /* Identify leaf node */
337  for ( i = ( le16_to_cpu ( branch->count ) - 1 ) ; i >= 0 ; i-- ) {
338  node = &branch->node[i];
339  if ( ! ice_admin_schedule_is_parent ( branch, node ) ) {
340  intelxl->teid = le32_to_cpu ( node->teid );
341  DBGC2 ( intelxl, "ICE %p TEID %#08x type %d\n",
342  intelxl, intelxl->teid, node->config.type );
343  break;
344  }
345  }
346  if ( ! intelxl->teid ) {
347  DBGC ( intelxl, "ICE %p found no leaf TEID\n", intelxl );
348  return -EINVAL;
349  }
350 
351  return 0;
352 }
Admin queue data buffer.
Definition: ice.h:459
#define EINVAL
Invalid argument.
Definition: errno.h:429
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define le32_to_cpu(value)
Definition: byteswap.h:114
uint16_t count
Number of nodes.
Definition: ice.h:296
struct ice_admin_schedule_node node[0]
Nodes.
Definition: ice.h:300
union ice_admin_schedule_buffer sched
Query Default Scheduling Tree Topology data buffer.
Definition: ice.h:469
#define DBGC(...)
Definition: compiler.h:505
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
#define ICE_ADMIN_SCHEDULE
Admin queue Query Default Scheduling Tree Topology command.
Definition: ice.h:257
Admin queue Query Default Scheduling Tree Topology node.
Definition: ice.h:282
Admin queue Query Default Scheduling Tree Topology command parameters.
Definition: ice.h:260
static struct ice_admin_schedule_node * ice_admin_schedule_is_parent(struct ice_admin_schedule_branch *branch, struct ice_admin_schedule_node *node)
Check if scheduler node is a parent (i.e.
Definition: ice.c:286
Admin queue Query Default Scheduling Tree Topology branch.
Definition: ice.h:292
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
#define le16_to_cpu(value)
Definition: byteswap.h:113
uint32_t node
NUMA node register offset.
Definition: ena.h:18
Admin queue descriptor.
Definition: ice.h:479
uint32_t teid
Transmit element ID.
Definition: intelxl.h:931
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
#define DBGC2(...)
Definition: compiler.h:522
struct ice_admin_schedule_branch branch[0]
Branches.
Definition: ice.h:306
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References ice_admin_schedule_buffer::branch, cmd, ice_admin_schedule_branch::count, cpu_to_le16, DBGC, DBGC2, EINVAL, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_ADMIN_SCHEDULE, ice_admin_schedule_is_parent(), intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, le16_to_cpu, le32_to_cpu, node, ice_admin_schedule_branch::node, rc, ice_admin_buffer::sched, and intelxl_nic::teid.

Referenced by ice_probe().

◆ ice_admin_autoneg()

static int ice_admin_autoneg ( struct intelxl_nic intelxl)
static

Restart autonegotiation.

Parameters
intelxlIntel device
Return values
rcReturn status code

Definition at line 360 of file ice.c.

360  {
361  struct ice_admin_descriptor *cmd;
362  struct ice_admin_autoneg_params *autoneg;
363  int rc;
364 
365  /* Populate descriptor */
366  cmd = ice_admin_command_descriptor ( intelxl );
367  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
368  autoneg = &cmd->params.autoneg;
371 
372  /* Issue command */
373  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
374  return rc;
375 
376  return 0;
377 }
#define INTELXL_ADMIN_AUTONEG_FL_RESTART
Restart autonegotiation.
Definition: intelxl.h:338
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
uint8_t flags
Flags.
Definition: ice.h:316
#define INTELXL_ADMIN_AUTONEG
Admin queue Restart Autonegotiation command.
Definition: intelxl.h:327
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
Admin queue Restart Autonegotiation command parameters.
Definition: ice.h:312
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_AUTONEG_FL_ENABLE
Enable link.
Definition: intelxl.h:341
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, ice_admin_autoneg_params::flags, ice_admin_command_descriptor(), INTELXL_ADMIN_AUTONEG, INTELXL_ADMIN_AUTONEG_FL_ENABLE, INTELXL_ADMIN_AUTONEG_FL_RESTART, intelxl_admin_command(), and rc.

Referenced by ice_open().

◆ ice_admin_link()

static int ice_admin_link ( struct net_device netdev)
static

Get link status.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 385 of file ice.c.

385  {
386  struct intelxl_nic *intelxl = netdev->priv;
387  struct ice_admin_descriptor *cmd;
388  struct ice_admin_link_params *link;
389  union ice_admin_buffer *buf;
390  int rc;
391 
392  /* Populate descriptor */
393  cmd = ice_admin_command_descriptor ( intelxl );
394  cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
395  cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
396  cmd->len = cpu_to_le16 ( sizeof ( buf->link ) );
397  link = &cmd->params.link;
399  buf = ice_admin_command_buffer ( intelxl );
400 
401  /* Issue command */
402  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
403  return rc;
404  DBGC ( intelxl, "ICE %p speed %#02x status %#02x\n",
405  intelxl, le16_to_cpu ( buf->link.speed ), buf->link.status );
406 
407  /* Update network device */
408  if ( buf->link.status & INTELXL_ADMIN_LINK_UP ) {
410  } else {
412  }
413 
414  return 0;
415 }
Admin queue data buffer.
Definition: ice.h:459
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:344
#define DBGC(...)
Definition: compiler.h:505
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition: netdevice.c:231
void * priv
Driver private data.
Definition: netdevice.h:432
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition: netdevice.h:789
static struct net_device * netdev
Definition: gdbudp.c:52
u32 link
Link to next descriptor.
Definition: ar9003_mac.h:25
struct ice_admin_link_buffer link
Get Link Status data buffer.
Definition: ice.h:471
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define le16_to_cpu(value)
Definition: byteswap.h:113
Admin queue descriptor.
Definition: ice.h:479
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
#define INTELXL_ADMIN_LINK_UP
Link is up.
Definition: intelxl.h:366
#define INTELXL_ADMIN_LINK_NOTIFY
Notify driver of link status changes.
Definition: intelxl.h:363
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29

References cmd, cpu_to_le16, DBGC, ice_admin_command_buffer(), ice_admin_command_descriptor(), intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_LINK, INTELXL_ADMIN_LINK_NOTIFY, INTELXL_ADMIN_LINK_UP, le16_to_cpu, link, ice_admin_buffer::link, netdev, netdev_link_down(), netdev_link_up(), net_device::priv, rc, ice_admin_link_buffer::speed, and ice_admin_link_buffer::status.

Referenced by ice_admin_event(), ice_open(), and ice_probe().

◆ ice_admin_event()

static void ice_admin_event ( struct net_device netdev,
struct intelxl_admin_descriptor xlevt,
union intelxl_admin_buffer *xlbuf  __unused 
)
static

Handle admin event.

Parameters
netdevNetwork device
xlevtEvent descriptor
xlbufData buffer

Definition at line 424 of file ice.c.

426  {
427  struct intelxl_nic *intelxl = netdev->priv;
428  struct ice_admin_descriptor *evt =
429  container_of ( xlevt, struct ice_admin_descriptor, xl );
430 
431  /* Ignore unrecognised events */
432  if ( evt->opcode != cpu_to_le16 ( INTELXL_ADMIN_LINK ) ) {
433  DBGC ( intelxl, "INTELXL %p unrecognised event opcode "
434  "%#04x\n", intelxl, le16_to_cpu ( evt->opcode ) );
435  return;
436  }
437 
438  /* Update link status */
440 }
#define INTELXL_ADMIN_LINK
Admin queue Get Link Status command.
Definition: intelxl.h:344
static int ice_admin_link(struct net_device *netdev)
Get link status.
Definition: ice.c:385
#define DBGC(...)
Definition: compiler.h:505
uint16_t opcode
Opcode.
Definition: ice.h:489
#define container_of(ptr, type, field)
Get containing structure.
Definition: stddef.h:36
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define le16_to_cpu(value)
Definition: byteswap.h:113
Admin queue descriptor.
Definition: ice.h:479
#define cpu_to_le16(value)
Definition: byteswap.h:107
struct intelxl_admin_descriptor xl
Original 40 Gigabit Ethernet descriptor.
Definition: ice.h:483

References container_of, cpu_to_le16, DBGC, ice_admin_link(), INTELXL_ADMIN_LINK, le16_to_cpu, netdev, ice_admin_descriptor::opcode, net_device::priv, and ice_admin_descriptor::xl.

Referenced by ice_probe().

◆ ice_admin_add_txq()

static int ice_admin_add_txq ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Add transmit queue.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 449 of file ice.c.

450  {
451  struct ice_admin_descriptor *cmd;
452  struct ice_admin_add_txq_params *add_txq;
453  union ice_admin_buffer *buf;
454  struct ice_context_tx *ctx;
455  struct ice_schedule_tx *sched;
457  int rc;
458 
459  /* Populate descriptor */
460  cmd = ice_admin_command_descriptor ( intelxl );
461  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_ADD_TXQ );
463  cmd->len = cpu_to_le16 ( sizeof ( buf->add_txq ) );
464  add_txq = &cmd->params.add_txq;
465  add_txq->count = 1;
466  buf = ice_admin_command_buffer ( intelxl );
467  buf->add_txq.parent = cpu_to_le32 ( intelxl->teid );
468  buf->add_txq.count = 1;
469  ctx = &buf->add_txq.ctx;
470  address = dma ( &ring->map, ring->desc.raw );
471  ctx->base_port =
472  cpu_to_le64 ( ICE_TXQ_BASE_PORT ( address, intelxl->port ) );
473  ctx->pf_type = cpu_to_le16 ( ICE_TXQ_PF_TYPE ( intelxl->pf ) );
474  ctx->vsi = cpu_to_le16 ( intelxl->vsi );
477  sched = &buf->add_txq.sched;
482 
483  /* Issue command */
484  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
485  return rc;
486  DBGC ( intelxl, "ICE %p added TEID %#04x\n",
487  intelxl, le32_to_cpu ( buf->add_txq.teid ) );
488 
489  return 0;
490 }
Admin queue data buffer.
Definition: ice.h:459
#define ICE_SCHEDULE_EXCESS
Transmit scheduler configuration excess bandwidth section is valid.
Definition: ice.h:276
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct ice_schedule_tx sched
Scheduler configuration.
Definition: ice.h:377
#define ICE_TXQ_PF_TYPE(pf)
Transmit queue PF number.
Definition: ice.h:385
#define le32_to_cpu(value)
Definition: byteswap.h:114
uint8_t count
Number of queues.
Definition: ice.h:365
uint64_t address
Base address.
Definition: ena.h:24
Admin queue Add Transmit Queues command parameters.
Definition: ice.h:353
#define DBGC(...)
Definition: compiler.h:505
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
uint8_t sections
Valid sections.
Definition: ice.h:49
#define cpu_to_le64(value)
Definition: byteswap.h:109
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define ICE_TXQ_BASE_PORT(addr, port)
Transmit queue base address and port number.
Definition: ice.h:381
#define ICE_TXQ_FL_LEGACY
Transmit queue uses legacy mode.
Definition: ice.h:394
uint8_t count
Number of queue groups.
Definition: ice.h:355
#define ICE_SCHEDULE_GENERIC
Transmit scheduler configuration generic section is valid.
Definition: ice.h:270
unsigned int vsi
Virtual Station Interface switching element ID.
Definition: intelxl.h:927
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
#define ICE_SCHEDULE_WEIGHT
Transmit scheduler configuration default weight.
Definition: ice.h:279
void * raw
Raw data.
Definition: intelxl.h:764
uint16_t excess_weight
Excess bandwidth weight.
Definition: ice.h:61
union intelxl_ring::@79 desc
Descriptors.
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define ICE_SCHEDULE_COMMIT
Transmit scheduler configuration committed bandwidth section is valid.
Definition: ice.h:273
struct dma_mapping map
Descriptor ring DMA mapping.
Definition: intelxl.h:767
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
unsigned int port
Port number.
Definition: intelxl.h:923
struct ice_context_tx ctx
Transmit queue context.
Definition: ice.h:375
Transmit queue context.
Definition: ice.h:27
Admin queue descriptor.
Definition: ice.h:479
uint32_t teid
Transmit element ID.
Definition: intelxl.h:931
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
unsigned long physaddr_t
Definition: stdint.h:20
unsigned int pf
Physical function number.
Definition: intelxl.h:919
Transmit scheduler configuration.
Definition: ice.h:45
#define ICE_TXQ_FL_TSO
Transmit queue uses TSO.
Definition: ice.h:391
#define cpu_to_le16(value)
Definition: byteswap.h:107
uint32_t teid
Queue TEID.
Definition: ice.h:373
uint16_t commit_weight
Committeed bandwidth weight.
Definition: ice.h:57
struct ice_admin_add_txq_buffer add_txq
Add Transmit Queue data buffer.
Definition: ice.h:473
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:443
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
#define ICE_ADMIN_ADD_TXQ
Admin queue Add Transmit Queues command.
Definition: ice.h:350
physaddr_t dma(struct dma_mapping *map, void *addr)
Get DMA address from virtual address.
#define ICE_TXQ_LEN(count)
Transmit queue length.
Definition: ice.h:388
uint32_t parent
Parent TEID.
Definition: ice.h:363

References ice_admin_buffer::add_txq, address, cmd, ice_schedule_tx::commit_weight, ice_admin_add_txq_params::count, ice_admin_add_txq_buffer::count, cpu_to_le16, cpu_to_le32, cpu_to_le64, ice_admin_add_txq_buffer::ctx, ctx, DBGC, intelxl_ring::desc, dma(), ice_schedule_tx::excess_weight, ICE_ADMIN_ADD_TXQ, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_SCHEDULE_COMMIT, ICE_SCHEDULE_EXCESS, ICE_SCHEDULE_GENERIC, ICE_SCHEDULE_WEIGHT, ICE_TXQ_BASE_PORT, ICE_TXQ_FL_LEGACY, ICE_TXQ_FL_TSO, ICE_TXQ_LEN, ICE_TXQ_PF_TYPE, intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, INTELXL_TX_NUM_DESC, le32_to_cpu, intelxl_ring::map, ice_admin_add_txq_buffer::parent, intelxl_nic::pf, intelxl_nic::port, intelxl_ring::raw, rc, ice_admin_add_txq_buffer::sched, ice_schedule_tx::sections, ice_admin_add_txq_buffer::teid, intelxl_nic::teid, and intelxl_nic::vsi.

Referenced by ice_create_tx().

◆ ice_admin_disable_txq()

static int ice_admin_disable_txq ( struct intelxl_nic intelxl)
static

Disable transmit queue.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 499 of file ice.c.

499  {
500  struct ice_admin_descriptor *cmd;
501  struct ice_admin_disable_txq_params *disable_txq;
502  union ice_admin_buffer *buf;
503  int rc;
504 
505  /* Populate descriptor */
506  cmd = ice_admin_command_descriptor ( intelxl );
507  cmd->opcode = cpu_to_le16 ( ICE_ADMIN_DISABLE_TXQ );
509  cmd->len = cpu_to_le16 ( sizeof ( buf->disable_txq ) );
510  disable_txq = &cmd->params.disable_txq;
511  disable_txq->flags = ICE_TXQ_FL_FLUSH;
512  disable_txq->count = 1;
513  disable_txq->timeout = ICE_TXQ_TIMEOUT;
514  buf = ice_admin_command_buffer ( intelxl );
515  buf->disable_txq.parent = cpu_to_le32 ( intelxl->teid );
516  buf->disable_txq.count = 1;
517 
518  /* Issue command */
519  if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
520  return rc;
521 
522  return 0;
523 }
Admin queue data buffer.
Definition: ice.h:459
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
#define ICE_ADMIN_DISABLE_TXQ
Admin queue Disable Transmit Queues command.
Definition: ice.h:397
#define ICE_TXQ_FL_FLUSH
Disable queue and flush pipe.
Definition: ice.h:414
uint32_t parent
Parent TEID.
Definition: ice.h:422
struct ice_admin_descriptor * ice_admin_command_descriptor(struct intelxl_nic *intelxl)
Get next admin command queue descriptor.
Definition: ice.h:511
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define INTELXL_ADMIN_FL_BUF
Admin descriptor uses data buffer.
Definition: intelxl.h:446
struct ice_admin_disable_txq_buffer disable_txq
Disable Transmit Queue data buffer.
Definition: ice.h:475
Admin queue descriptor.
Definition: ice.h:479
uint32_t teid
Transmit element ID.
Definition: intelxl.h:931
int intelxl_admin_command(struct intelxl_nic *intelxl)
Issue admin queue command.
Definition: intelxl.c:278
static union ice_admin_buffer * ice_admin_command_buffer(struct intelxl_nic *intelxl)
Get next admin command queue data buffer.
Definition: ice.h:525
#define ICE_TXQ_TIMEOUT
Disable queue timeout.
Definition: ice.h:417
#define cpu_to_le16(value)
Definition: byteswap.h:107
#define INTELXL_ADMIN_FL_RD
Admin descriptor uses data buffer for command parameters.
Definition: intelxl.h:443
struct golan_eqe_cmd cmd
Definition: CIB_PRM.h:29
Admin queue Disable Transmit Queues command parameters.
Definition: ice.h:400
uint8_t count
Number of queues.
Definition: ice.h:424

References cmd, ice_admin_disable_txq_buffer::count, cpu_to_le16, cpu_to_le32, ice_admin_buffer::disable_txq, ice_admin_command_buffer(), ice_admin_command_descriptor(), ICE_ADMIN_DISABLE_TXQ, ICE_TXQ_FL_FLUSH, ICE_TXQ_TIMEOUT, intelxl_admin_command(), INTELXL_ADMIN_FL_BUF, INTELXL_ADMIN_FL_RD, ice_admin_disable_txq_buffer::parent, rc, and intelxl_nic::teid.

Referenced by ice_destroy_tx().

◆ ice_dump_tx()

static void ice_dump_tx ( struct intelxl_nic intelxl)
static

Dump transmit queue context (for debugging)

Parameters
intelxlIntel device

Definition at line 537 of file ice.c.

537  {
538  uint32_t ctx[ sizeof ( struct ice_context_tx ) / sizeof ( uint32_t ) ];
539  uint32_t stat;
540  unsigned int i;
541 
542  /* Do nothing unless debug output is enabled */
543  if ( ! DBG_EXTRA )
544  return;
545 
546  /* Trigger reading of transmit context */
549  intelxl->regs + ICE_GLCOMM_QTX_CNTX_CTL );
550 
551  /* Wait for operation to complete */
552  for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
553 
554  /* Check if operation is complete */
555  stat = readl ( intelxl->regs + ICE_GLCOMM_QTX_CNTX_STAT );
556  if ( ! ( stat & ICE_GLCOMM_QTX_CNTX_BUSY ) )
557  break;
558 
559  /* Delay */
560  mdelay ( 1 );
561  }
562 
563  /* Read context registers */
564  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx[0] ) ) ; i++ ) {
565  ctx[i] = cpu_to_le32 ( readl ( intelxl->regs +
566  ICE_GLCOMM_QTX_CNTX_DATA ( i )));
567  }
568 
569  /* Dump context */
570  DBGC2 ( intelxl, "ICE %p TX context:\n", intelxl );
571  DBGC2_HDA ( intelxl, 0, ctx, sizeof ( ctx ) );
572 }
void * regs
Registers.
Definition: intelxl.h:912
uint32_t stat
Completion status.
Definition: dwmac.h:12
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define ICE_GLCOMM_QTX_CNTX_STAT
Transmit Comm Scheduler Queue Context Status Register.
Definition: ice.h:91
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define DBGC2_HDA(...)
Definition: compiler.h:523
#define ICE_GLCOMM_QTX_CNTX_CTL
Transmit Comm Scheduler Queue Context Control Register.
Definition: ice.h:84
unsigned int uint32_t
Definition: stdint.h:12
Transmit queue context.
Definition: ice.h:27
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition: timer.c:79
#define DBGC2(...)
Definition: compiler.h:522
#define ICE_GLCOMM_QTX_CNTX_BUSY
In progress.
Definition: ice.h:92
#define ICE_GLCOMM_QTX_CNTX_CTL_EXEC
Execute.
Definition: ice.h:88
#define ICE_GLCOMM_QTX_CNTX_DATA(x)
Transmit Comm Scheduler Queue Context Data Registers.
Definition: ice.h:81
#define DBG_EXTRA
Definition: compiler.h:319
#define INTELXL_CTX_MAX_WAIT_MS
Maximum time to wait for a context operation to complete.
Definition: intelxl.h:604
#define ICE_GLCOMM_QTX_CNTX_CTL_CMD_READ
Read context.
Definition: ice.h:86

References cpu_to_le32, ctx, DBG_EXTRA, DBGC2, DBGC2_HDA, ICE_GLCOMM_QTX_CNTX_BUSY, ICE_GLCOMM_QTX_CNTX_CTL, ICE_GLCOMM_QTX_CNTX_CTL_CMD_READ, ICE_GLCOMM_QTX_CNTX_CTL_EXEC, ICE_GLCOMM_QTX_CNTX_DATA, ICE_GLCOMM_QTX_CNTX_STAT, INTELXL_CTX_MAX_WAIT_MS, mdelay(), readl(), intelxl_nic::regs, stat, and writel().

Referenced by ice_close().

◆ ice_dump_rx()

static void ice_dump_rx ( struct intelxl_nic intelxl)
static

Dump receive queue context (for debugging)

Parameters
intelxlIntel device

Definition at line 579 of file ice.c.

579  {
580  uint32_t ctx[ sizeof ( struct intelxl_context_rx ) /
581  sizeof ( uint32_t ) ];
582  unsigned int i;
583 
584  /* Do nothing unless debug output is enabled */
585  if ( ! DBG_EXTRA )
586  return;
587 
588  /* Read context registers */
589  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx[0] ) ) ; i++ ) {
590  ctx[i] = cpu_to_le32 ( readl ( intelxl->regs +
591  ICE_QRX_CONTEXT ( i ) ) );
592  }
593 
594  /* Dump context */
595  DBGC2 ( intelxl, "ICE %p RX context:\n", intelxl );
596  DBGC2_HDA ( intelxl, 0, ctx, sizeof ( ctx ) );
597 }
Receive queue context.
Definition: intelxl.h:568
void * regs
Registers.
Definition: intelxl.h:912
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
#define ICE_QRX_CONTEXT(x)
Receive Queue Context Registers.
Definition: ice.h:72
#define cpu_to_le32(value)
Definition: byteswap.h:108
#define DBGC2_HDA(...)
Definition: compiler.h:523
unsigned int uint32_t
Definition: stdint.h:12
#define DBGC2(...)
Definition: compiler.h:522
#define DBG_EXTRA
Definition: compiler.h:319

References cpu_to_le32, ctx, DBG_EXTRA, DBGC2, DBGC2_HDA, ICE_QRX_CONTEXT, readl(), and intelxl_nic::regs.

Referenced by ice_close().

◆ ice_create_tx()

static int ice_create_tx ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Create transmit queue.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 606 of file ice.c.

607  {
608  int rc;
609 
610  /* Allocate descriptor ring */
611  if ( ( rc = intelxl_alloc_ring ( intelxl, ring ) ) != 0 )
612  goto err_alloc;
613 
614  /* Add transmit queue */
615  if ( ( rc = ice_admin_add_txq ( intelxl, ring ) ) != 0 )
616  goto err_add_txq;
617 
618  return 0;
619 
620  err_add_txq:
621  intelxl_free_ring ( intelxl, ring );
622  err_alloc:
623  return rc;
624 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
static int ice_admin_add_txq(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Add transmit queue.
Definition: ice.c:449
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:996
int intelxl_alloc_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Allocate descriptor ring.
Definition: intelxl.c:957

References ice_admin_add_txq(), intelxl_alloc_ring(), intelxl_free_ring(), and rc.

Referenced by ice_open().

◆ ice_destroy_tx()

static void ice_destroy_tx ( struct intelxl_nic intelxl,
struct intelxl_ring ring 
)
static

Destroy transmit queue.

Parameters
intelxlIntel device
ringDescriptor ring
Return values
rcReturn status code

Definition at line 633 of file ice.c.

634  {
635  int rc;
636 
637  /* Disable transmit queue */
638  if ( ( rc = ice_admin_disable_txq ( intelxl ) ) != 0 ) {
639  /* Leak memory; there's nothing else we can do */
640  return;
641  }
642 
643  /* Free descriptor ring */
644  intelxl_free_ring ( intelxl, ring );
645 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void intelxl_free_ring(struct intelxl_nic *intelxl __unused, struct intelxl_ring *ring)
Free descriptor ring.
Definition: intelxl.c:996
static int ice_admin_disable_txq(struct intelxl_nic *intelxl)
Disable transmit queue.
Definition: ice.c:499

References ice_admin_disable_txq(), intelxl_free_ring(), and rc.

Referenced by ice_close(), and ice_open().

◆ ice_context_rx()

static int ice_context_rx ( struct intelxl_nic intelxl,
physaddr_t  address 
)
static

Program receive queue context.

Parameters
intelxlIntel device
addressDescriptor ring base address
Return values
rcReturn status code

Definition at line 654 of file ice.c.

655  {
656  union {
657  struct intelxl_context_rx rx;
658  uint32_t raw[ sizeof ( struct intelxl_context_rx ) /
659  sizeof ( uint32_t ) ];
660  } ctx;
662  unsigned int i;
663 
664  /* Initialise context */
665  memset ( &ctx, 0, sizeof ( ctx ) );
667  ctx.rx.base_count = cpu_to_le64 ( base_count );
668  ctx.rx.len = cpu_to_le16 ( INTELXL_CTX_RX_LEN ( intelxl->mfs ) );
670  ctx.rx.mfs = cpu_to_le16 ( INTELXL_CTX_RX_MFS ( intelxl->mfs ) );
671 
672  /* Write context registers */
673  for ( i = 0 ; i < ( sizeof ( ctx ) / sizeof ( ctx.raw[0] ) ) ; i++ ) {
674  writel ( le32_to_cpu ( ctx.raw[i] ),
675  ( intelxl->regs + ICE_QRX_CONTEXT ( i ) ) );
676  }
677 
678  return 0;
679 }
Receive queue context.
Definition: intelxl.h:568
void * regs
Registers.
Definition: intelxl.h:912
#define INTELXL_CTX_RX_LEN(len)
Receive queue data buffer length.
Definition: intelxl.h:592
#define le32_to_cpu(value)
Definition: byteswap.h:114
uint64_t address
Base address.
Definition: ena.h:24
unsigned long long uint64_t
Definition: stdint.h:13
#define cpu_to_le64(value)
Definition: byteswap.h:109
#define INTELXL_CTX_RX_MFS(mfs)
Receive queue maximum frame size.
Definition: intelxl.h:601
struct golan_eq_context ctx
Definition: CIB_PRM.h:28
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
#define INTELXL_CTX_RX_FL_DSIZE
Use 32-byte receive descriptors.
Definition: intelxl.h:595
#define ICE_QRX_CONTEXT(x)
Receive Queue Context Registers.
Definition: ice.h:72
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
uint64_t base_count
Base address and queue count.
Definition: intelxl.h:574
unsigned int uint32_t
Definition: stdint.h:12
#define INTELXL_CTX_RX_FL_CRCSTRIP
Strip CRC from received packets.
Definition: intelxl.h:598
u8 rx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets from the AP.
Definition: wpa.h:234
#define cpu_to_le16(value)
Definition: byteswap.h:107
__be32 raw[7]
Definition: CIB_PRM.h:28
#define INTELXL_CTX_RX_BASE_COUNT(base, count)
Receive queue base address and queue count.
Definition: intelxl.h:588
void * memset(void *dest, int character, size_t len) __nonnull

References address, intelxl_context_rx::base_count, cpu_to_le16, cpu_to_le64, ctx, ICE_QRX_CONTEXT, INTELXL_CTX_RX_BASE_COUNT, INTELXL_CTX_RX_FL_CRCSTRIP, INTELXL_CTX_RX_FL_DSIZE, INTELXL_CTX_RX_LEN, INTELXL_CTX_RX_MFS, INTELXL_RX_NUM_DESC, le32_to_cpu, memset(), intelxl_nic::mfs, raw, intelxl_nic::regs, rx, and writel().

Referenced by ice_probe().

◆ ice_open()

static int ice_open ( struct net_device netdev)
static

Open network device.

Parameters
netdevNetwork device
Return values
rcReturn status code

Definition at line 687 of file ice.c.

687  {
688  struct intelxl_nic *intelxl = netdev->priv;
689  int rc;
690 
691  /* Calculate maximum frame size */
692  intelxl->mfs = ( ( ETH_HLEN + netdev->mtu + 4 /* CRC */ +
693  INTELXL_ALIGN - 1 ) & ~( INTELXL_ALIGN - 1 ) );
694 
695  /* Set MAC address */
696  if ( ( rc = ice_admin_mac_write ( netdev ) ) != 0 )
697  goto err_mac_write;
698 
699  /* Set maximum frame size */
700  if ( ( rc = intelxl_admin_mac_config ( intelxl ) ) != 0 )
701  goto err_mac_config;
702 
703  /* Create receive descriptor ring */
704  if ( ( rc = intelxl_create_ring ( intelxl, &intelxl->rx ) ) != 0 )
705  goto err_create_rx;
706 
707  /* Create transmit descriptor ring */
708  if ( ( rc = ice_create_tx ( intelxl, &intelxl->tx ) ) != 0 )
709  goto err_create_tx;
710 
711  /* Restart autonegotiation */
712  ice_admin_autoneg ( intelxl );
713 
714  /* Update link state */
716 
717  return 0;
718 
719  ice_destroy_tx ( intelxl, &intelxl->tx );
720  err_create_tx:
721  intelxl_destroy_ring ( intelxl, &intelxl->rx );
722  err_create_rx:
723  err_mac_config:
724  err_mac_write:
725  return rc;
726 }
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1300
static int ice_admin_link(struct net_device *netdev)
Get link status.
Definition: ice.c:385
size_t mtu
Maximum transmission unit length.
Definition: netdevice.h:416
#define INTELXL_ALIGN
Alignment.
Definition: intelxl.h:27
size_t mfs
Maximum frame size.
Definition: intelxl.h:916
static int ice_create_tx(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create transmit queue.
Definition: ice.c:606
static void ice_destroy_tx(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy transmit queue.
Definition: ice.c:633
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
#define ETH_HLEN
Definition: if_ether.h:10
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
int intelxl_create_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Create descriptor ring.
Definition: intelxl.c:1266
static int ice_admin_autoneg(struct intelxl_nic *intelxl)
Restart autonegotiation.
Definition: ice.c:360
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
static int ice_admin_mac_write(struct net_device *netdev)
Set MAC address.
Definition: ice.c:164
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
int intelxl_admin_mac_config(struct intelxl_nic *intelxl)
Set MAC configuration.
Definition: intelxl.c:712

References ETH_HLEN, ice_admin_autoneg(), ice_admin_link(), ice_admin_mac_write(), ice_create_tx(), ice_destroy_tx(), intelxl_admin_mac_config(), INTELXL_ALIGN, intelxl_create_ring(), intelxl_destroy_ring(), intelxl_nic::mfs, net_device::mtu, netdev, net_device::priv, rc, intelxl_nic::rx, and intelxl_nic::tx.

◆ ice_close()

static void ice_close ( struct net_device netdev)
static

Close network device.

Parameters
netdevNetwork device

Definition at line 733 of file ice.c.

733  {
734  struct intelxl_nic *intelxl = netdev->priv;
735 
736  /* Dump contexts (for debugging) */
737  ice_dump_tx ( intelxl );
738  ice_dump_rx ( intelxl );
739 
740  /* Destroy transmit descriptor ring */
741  ice_destroy_tx ( intelxl, &intelxl->tx );
742 
743  /* Destroy receive descriptor ring */
744  intelxl_destroy_ring ( intelxl, &intelxl->rx );
745 
746  /* Discard any unused receive buffers */
747  intelxl_empty_rx ( intelxl );
748 }
void intelxl_destroy_ring(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy descriptor ring.
Definition: intelxl.c:1300
static void ice_destroy_tx(struct intelxl_nic *intelxl, struct intelxl_ring *ring)
Destroy transmit queue.
Definition: ice.c:633
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
static void ice_dump_rx(struct intelxl_nic *intelxl)
Dump receive queue context (for debugging)
Definition: ice.c:579
static void ice_dump_tx(struct intelxl_nic *intelxl)
Dump transmit queue context (for debugging)
Definition: ice.c:537
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
void intelxl_empty_rx(struct intelxl_nic *intelxl)
Discard unused receive I/O buffers.
Definition: intelxl.c:1367

References ice_destroy_tx(), ice_dump_rx(), ice_dump_tx(), intelxl_destroy_ring(), intelxl_empty_rx(), netdev, net_device::priv, intelxl_nic::rx, and intelxl_nic::tx.

◆ ice_probe()

static int ice_probe ( struct pci_device pci)
static

Probe PCI device.

Parameters
pciPCI device
Return values
rcReturn status code

Definition at line 771 of file ice.c.

771  {
772  struct net_device *netdev;
773  struct intelxl_nic *intelxl;
774  uint32_t pffunc_rid;
775  uint32_t pfgen_portnum;
776  int rc;
777 
778  /* Allocate and initialise net device */
779  netdev = alloc_etherdev ( sizeof ( *intelxl ) );
780  if ( ! netdev ) {
781  rc = -ENOMEM;
782  goto err_alloc;
783  }
786  intelxl = netdev->priv;
787  pci_set_drvdata ( pci, netdev );
788  netdev->dev = &pci->dev;
789  memset ( intelxl, 0, sizeof ( *intelxl ) );
790  intelxl->intr = ICE_GLINT_DYN_CTL;
791  intelxl->handle = ice_admin_event;
797  sizeof ( intelxl->tx.desc.tx[0] ), NULL );
799  sizeof ( intelxl->rx.desc.rx[0] ),
800  ice_context_rx );
801 
802  /* Fix up PCI device */
803  adjust_pci_device ( pci );
804 
805  /* Map registers */
806  intelxl->regs = pci_ioremap ( pci, pci->membase, ICE_BAR_SIZE );
807  if ( ! intelxl->regs ) {
808  rc = -ENODEV;
809  goto err_ioremap;
810  }
811 
812  /* Configure DMA */
813  intelxl->dma = &pci->dma;
814  dma_set_mask_64bit ( intelxl->dma );
815  netdev->dma = intelxl->dma;
816 
817  /* Locate PCI Express capability */
818  intelxl->exp = pci_find_capability ( pci, PCI_CAP_ID_EXP );
819  if ( ! intelxl->exp ) {
820  DBGC ( intelxl, "ICE %p missing PCIe capability\n",
821  intelxl );
822  rc = -ENXIO;
823  goto err_exp;
824  }
825 
826  /* Reset the function via PCIe FLR */
827  pci_reset ( pci, intelxl->exp );
828 
829  /* Get function and port number */
830  pffunc_rid = readl ( intelxl->regs + ICE_PFFUNC_RID );
831  intelxl->pf = ICE_PFFUNC_RID_FUNC_NUM ( pffunc_rid );
832  pfgen_portnum = readl ( intelxl->regs + ICE_PFGEN_PORTNUM );
833  intelxl->port = ICE_PFGEN_PORTNUM_PORT_NUM ( pfgen_portnum );
834  DBGC ( intelxl, "ICE %p PF %d using port %d\n",
835  intelxl, intelxl->pf, intelxl->port );
836 
837  /* Enable MSI-X dummy interrupt */
838  if ( ( rc = intelxl_msix_enable ( intelxl, pci,
839  INTELXL_MSIX_VECTOR ) ) != 0 )
840  goto err_msix;
841 
842  /* Open admin queues */
843  if ( ( rc = intelxl_open_admin ( intelxl ) ) != 0 )
844  goto err_open_admin;
845 
846  /* Get firmware version */
847  if ( ( rc = ice_admin_version ( intelxl ) ) != 0 )
848  goto err_admin_version;
849 
850  /* Clear PXE mode */
851  if ( ( rc = intelxl_admin_clear_pxe ( intelxl ) ) != 0 )
852  goto err_admin_clear_pxe;
853 
854  /* Get switch configuration */
855  if ( ( rc = ice_admin_switch ( intelxl ) ) != 0 )
856  goto err_admin_switch;
857 
858  /* Add broadcast address */
859  if ( ( rc = ice_admin_rules ( intelxl, eth_broadcast ) ) != 0 )
860  goto err_admin_rules_broadcast;
861 
862  /* Add promiscuous unicast address */
863  if ( ( rc = ice_admin_rules ( intelxl, ice_magic_mac ) ) != 0 )
864  goto err_admin_rules_magic;
865 
866  /* Query scheduler topology */
867  if ( ( rc = ice_admin_schedule ( intelxl ) ) != 0 )
868  goto err_admin_schedule;
869 
870  /* Get MAC address */
871  if ( ( rc = ice_admin_mac_read ( netdev ) ) != 0 )
872  goto err_admin_mac_read;
873 
874  /* Configure queue register addresses */
875  intelxl->tx.tail = ICE_QTX_COMM_DBELL;
876  intelxl->rx.reg = ICE_QRX_CTRL;
877  intelxl->rx.tail = ICE_QRX_TAIL;
878 
879  /* Configure interrupt causes */
881  intelxl->regs + ICE_QINT_TQCTL );
883  intelxl->regs + ICE_QINT_RQCTL );
884 
885  /* Set a default value for the queue context flex extension,
886  * since this register erroneously retains its value across at
887  * least a PCIe FLR.
888  */
891  intelxl->regs + ICE_QRX_FLXP_CNTXT );
892 
893  /* Register network device */
894  if ( ( rc = register_netdev ( netdev ) ) != 0 )
895  goto err_register_netdev;
896 
897  /* Set initial link state */
899 
900  return 0;
901 
903  err_register_netdev:
904  err_admin_mac_read:
905  err_admin_schedule:
906  err_admin_rules_magic:
907  err_admin_rules_broadcast:
908  err_admin_switch:
909  err_admin_clear_pxe:
910  err_admin_version:
911  intelxl_close_admin ( intelxl );
912  err_open_admin:
913  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
914  err_msix:
915  pci_reset ( pci, intelxl->exp );
916  err_exp:
917  iounmap ( intelxl->regs );
918  err_ioremap:
920  netdev_put ( netdev );
921  err_alloc:
922  return rc;
923 }
void * regs
Registers.
Definition: intelxl.h:912
unsigned long membase
Memory base.
Definition: pci.h:220
struct dma_device * dma
DMA device.
Definition: intelxl.h:914
struct arbelprm_rc_send_wqe rc
Definition: arbel.h:14
struct dma_device dma
DMA device.
Definition: pci.h:215
#define ICE_QINT_TQCTL_CAUSE_ENA
Enable.
Definition: ice.h:556
#define INTELXL_ADMIN_EVT
PF Admin Event Queue register block.
Definition: intelxl.h:40
int pci_find_capability(struct pci_device *pci, int cap)
Look for a PCI capability.
Definition: pciextra.c:39
static int ice_admin_link(struct net_device *netdev)
Get link status.
Definition: ice.c:385
void(* handle)(struct net_device *netdev, struct intelxl_admin_descriptor *evt, union intelxl_admin_buffer *buf)
Handle admin event.
Definition: intelxl.h:963
#define INTELXL_ADMIN_CMD
PF Admin Command Queue register block.
Definition: intelxl.h:37
Admin queue register offsets.
Definition: intelxl.h:64
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
uint8_t eth_broadcast[ETH_ALEN]
Ethernet broadcast MAC address.
Definition: ethernet.c:48
#define DBGC(...)
Definition: compiler.h:505
static int ice_admin_rules(struct intelxl_nic *intelxl, uint8_t *mac)
Add switch rules.
Definition: ice.c:247
int intelxl_admin_clear_pxe(struct intelxl_nic *intelxl)
Clear PXE mode.
Definition: intelxl.c:561
struct intelxl_admin command
Admin command queue.
Definition: intelxl.h:942
static __always_inline void dma_set_mask_64bit(struct dma_device *dma)
Set 64-bit addressable space mask.
Definition: dma.h:467
struct dma_device * dma
DMA device.
Definition: netdevice.h:367
#define ICE_QRX_FLXP_CNTXT_RXDID_PRIO_MAX
Maximum priority.
Definition: ice.h:100
static int ice_admin_mac_read(struct net_device *netdev)
Get MAC address.
Definition: ice.c:102
#define ICE_QRX_FLXP_CNTXT
Queue Context Flex Extension Register.
Definition: ice.h:95
int intelxl_open_admin(struct intelxl_nic *intelxl)
Open admin queues.
Definition: intelxl.c:877
static struct net_device_operations ice_operations
Network device operations.
Definition: ice.c:751
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:89
union intelxl_tx_descriptor * tx
Transmit descriptors.
Definition: intelxl.h:760
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition: pci.c:241
struct device dev
Generic device.
Definition: pci.h:213
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:937
#define ICE_QRX_FLXP_CNTXT_RXDID_IDX_LEGACY_32
32-byte legacy
Definition: ice.h:97
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition: netdevice.h:519
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition: pci.h:366
#define ENOMEM
Not enough space.
Definition: errno.h:535
struct intelxl_ring rx
Receive descriptor ring.
Definition: intelxl.h:952
static void intelxl_init_admin(struct intelxl_admin *admin, unsigned int base, const struct intelxl_admin_offsets *regs)
Initialise admin queue.
Definition: intelxl.h:476
#define ICE_QTX_COMM_DBELL
Transmit Comm Scheduler Queue Doorbell Register.
Definition: ice.h:78
static int ice_admin_switch(struct intelxl_nic *intelxl)
Get switch configuration.
Definition: ice.c:189
#define ICE_QINT_TQCTL
Transmit Queue Interrupt Cause Control Register.
Definition: ice.h:552
#define INTELXL_MAX_PKT_LEN
Maximum packet length (excluding CRC)
Definition: intelxl.h:827
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:576
Admin queue version number.
Definition: ice.h:111
#define INTELXL_TX_NUM_DESC
Number of transmit descriptors.
Definition: intelxl.h:809
void * priv
Driver private data.
Definition: netdevice.h:432
static void ice_admin_event(struct net_device *netdev, struct intelxl_admin_descriptor *xlevt, union intelxl_admin_buffer *xlbuf __unused)
Handle admin event.
Definition: ice.c:424
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct net_device * netdev
Definition: gdbudp.c:52
#define INTELXL_RX_NUM_DESC
Number of receive descriptors.
Definition: intelxl.h:818
union intelxl_ring::@79 desc
Descriptors.
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:942
unsigned int reg
Register block.
Definition: intelxl.h:774
#define ICE_QRX_CTRL
Global Receive Queue Control Register.
Definition: ice.h:69
union intelxl_rx_descriptor * rx
Receive descriptors.
Definition: intelxl.h:762
#define ICE_GLINT_DYN_CTL
Global Interrupt Dynamic Control Register.
Definition: ice.h:566
#define ICE_QINT_RQCTL_CAUSE_ENA
Enable.
Definition: ice.h:563
int register_netdev(struct net_device *netdev)
Register network device.
Definition: netdevice.c:760
unsigned int intr
Interrupt control register.
Definition: intelxl.h:935
A network device.
Definition: netdevice.h:353
#define ENODEV
No such device.
Definition: errno.h:510
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:532
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:91
unsigned int port
Port number.
Definition: intelxl.h:923
static int ice_admin_schedule(struct intelxl_nic *intelxl)
Query default scheduling tree topology.
Definition: ice.c:308
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
unsigned int uint32_t
Definition: stdint.h:12
static void intelxl_init_ring(struct intelxl_ring *ring, unsigned int count, size_t len, int(*context)(struct intelxl_nic *intelxl, physaddr_t address))
Initialise descriptor ring.
Definition: intelxl.h:796
struct intelxl_ring tx
Transmit descriptor ring.
Definition: intelxl.h:950
#define PCI_CAP_ID_EXP
PCI Express.
Definition: pci.h:98
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:907
struct device * dev
Underlying hardware device.
Definition: netdevice.h:365
unsigned int pf
Physical function number.
Definition: intelxl.h:919
#define ENXIO
No such device or address.
Definition: errno.h:600
#define ICE_QINT_RQCTL_ITR_INDX_NONE
No throttling.
Definition: ice.h:561
#define ICE_QINT_RQCTL
Receive Queue Interrupt Cause Control Register.
Definition: ice.h:559
#define ICE_PFFUNC_RID
Function Requester ID Information Register.
Definition: ice.h:540
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition: ethernet.c:265
static uint8_t ice_magic_mac[ETH_HLEN]
Magic MAC address.
Definition: ice.c:51
void iounmap(volatile const void *io_addr)
Unmap I/O address.
#define ICE_BAR_SIZE
BAR size.
Definition: ice.h:17
unsigned int tail
Tail register.
Definition: intelxl.h:776
#define ICE_QRX_TAIL
Receive Queue Tail Register.
Definition: ice.h:75
#define ICE_PFFUNC_RID_FUNC_NUM(x)
Function number.
Definition: ice.h:541
static int ice_context_rx(struct intelxl_nic *intelxl, physaddr_t address)
Program receive queue context.
Definition: ice.c:654
size_t max_pkt_len
Maximum packet length.
Definition: netdevice.h:410
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:929
#define ICE_PFGEN_PORTNUM_PORT_NUM(x)
Port number.
Definition: ice.h:547
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
#define NULL
NULL pointer (VOID *)
Definition: Base.h:322
#define ICE_PFGEN_PORTNUM
PF LAN Port Number Register.
Definition: ice.h:546
struct intelxl_admin event
Admin event queue.
Definition: intelxl.h:944
#define ICE_QINT_TQCTL_ITR_INDX_NONE
No throttling.
Definition: ice.h:554
void * memset(void *dest, int character, size_t len) __nonnull
int intelxl_msix_enable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Enable MSI-X dummy interrupt.
Definition: intelxl.c:63

References adjust_pci_device(), alloc_etherdev(), intelxl_nic::command, DBGC, intelxl_ring::desc, pci_device::dev, net_device::dev, pci_device::dma, net_device::dma, intelxl_nic::dma, dma_set_mask_64bit(), ENODEV, ENOMEM, ENXIO, eth_broadcast, intelxl_nic::event, intelxl_nic::exp, intelxl_nic::handle, ice_admin_event(), ice_admin_link(), ice_admin_mac_read(), ice_admin_rules(), ice_admin_schedule(), ice_admin_switch(), ICE_BAR_SIZE, ice_context_rx(), ICE_GLINT_DYN_CTL, ice_magic_mac, ice_operations, ICE_PFFUNC_RID, ICE_PFFUNC_RID_FUNC_NUM, ICE_PFGEN_PORTNUM, ICE_PFGEN_PORTNUM_PORT_NUM, ICE_QINT_RQCTL, ICE_QINT_RQCTL_CAUSE_ENA, ICE_QINT_RQCTL_ITR_INDX_NONE, ICE_QINT_TQCTL, ICE_QINT_TQCTL_CAUSE_ENA, ICE_QINT_TQCTL_ITR_INDX_NONE, ICE_QRX_CTRL, ICE_QRX_FLXP_CNTXT, ICE_QRX_FLXP_CNTXT_RXDID_IDX_LEGACY_32, ICE_QRX_FLXP_CNTXT_RXDID_PRIO_MAX, ICE_QRX_TAIL, ICE_QTX_COMM_DBELL, intelxl_admin_clear_pxe(), INTELXL_ADMIN_CMD, INTELXL_ADMIN_EVT, intelxl_close_admin(), intelxl_init_admin(), intelxl_init_ring(), INTELXL_MAX_PKT_LEN, intelxl_msix_disable(), intelxl_msix_enable(), INTELXL_MSIX_VECTOR, intelxl_open_admin(), INTELXL_RX_NUM_DESC, INTELXL_TX_NUM_DESC, intelxl_nic::intr, iounmap(), net_device::max_pkt_len, pci_device::membase, memset(), netdev, netdev_init(), netdev_nullify(), netdev_put(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), pci_ioremap(), pci_reset(), pci_set_drvdata(), intelxl_nic::pf, intelxl_nic::port, net_device::priv, rc, readl(), intelxl_ring::reg, register_netdev(), intelxl_nic::regs, intelxl_ring::rx, intelxl_nic::rx, intelxl_ring::tail, intelxl_ring::tx, intelxl_nic::tx, unregister_netdev(), and writel().

◆ ice_remove()

static void ice_remove ( struct pci_device pci)
static

Remove PCI device.

Parameters
pciPCI device

Definition at line 930 of file ice.c.

930  {
931  struct net_device *netdev = pci_get_drvdata ( pci );
932  struct intelxl_nic *intelxl = netdev->priv;
933 
934  /* Unregister network device */
936 
937  /* Close admin queues */
938  intelxl_close_admin ( intelxl );
939 
940  /* Disable MSI-X dummy interrupt */
941  intelxl_msix_disable ( intelxl, pci, INTELXL_MSIX_VECTOR );
942 
943  /* Reset the NIC */
944  pci_reset ( pci, intelxl->exp );
945 
946  /* Free network device */
947  iounmap ( intelxl->regs );
949  netdev_put ( netdev );
950 }
void * regs
Registers.
Definition: intelxl.h:912
void pci_reset(struct pci_device *pci, unsigned int exp)
Perform PCI Express function-level reset (FLR)
Definition: pciextra.c:89
unsigned int exp
PCI Express capability offset.
Definition: intelxl.h:937
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition: netdevice.h:576
void * priv
Driver private data.
Definition: netdevice.h:432
static struct net_device * netdev
Definition: gdbudp.c:52
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition: netdevice.c:942
A network device.
Definition: netdevice.h:353
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition: netdevice.h:532
void intelxl_msix_disable(struct intelxl_nic *intelxl, struct pci_device *pci, unsigned int vector)
Disable MSI-X dummy interrupt.
Definition: intelxl.c:91
An Intel 40 Gigabit network card.
Definition: intelxl.h:910
#define INTELXL_MSIX_VECTOR
MSI-X interrupt vector.
Definition: intelxl.h:907
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition: pci.h:376
void iounmap(volatile const void *io_addr)
Unmap I/O address.
void intelxl_close_admin(struct intelxl_nic *intelxl)
Close admin queues.
Definition: intelxl.c:929

References intelxl_nic::exp, intelxl_close_admin(), intelxl_msix_disable(), INTELXL_MSIX_VECTOR, iounmap(), netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), pci_reset(), net_device::priv, intelxl_nic::regs, and unregister_netdev().

Variable Documentation

◆ ice_magic_mac

uint8_t ice_magic_mac[ETH_HLEN] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 }
static

Magic MAC address.

Used as the source address and promiscuous unicast destination address in the "add switch rules" command.

Definition at line 51 of file ice.c.

Referenced by ice_admin_rules(), and ice_probe().

◆ ice_operations

struct net_device_operations ice_operations
static
Initial value:
= {
.open = ice_open,
.close = ice_close,
.transmit = intelxl_transmit,
.poll = intelxl_poll,
}
int intelxl_transmit(struct net_device *netdev, struct io_buffer *iobuf)
Transmit packet.
Definition: intelxl.c:1493
static void ice_close(struct net_device *netdev)
Close network device.
Definition: ice.c:733
static int ice_open(struct net_device *netdev)
Open network device.
Definition: ice.c:687
void intelxl_poll(struct net_device *netdev)
Poll for completed and received packets.
Definition: intelxl.c:1613

Network device operations.

Definition at line 751 of file ice.c.

Referenced by ice_probe().

◆ ice_nics

struct pci_device_id ice_nics[]
static
Initial value:
= {
PCI_ROM ( 0x8086, 0x124c, "e823l-bp", "E823-L backplane", 0 ),
PCI_ROM ( 0x8086, 0x124d, "e823l-sfp", "E823-L SFP", 0 ),
PCI_ROM ( 0x8086, 0x124e, "e823l-10gt", "E823-L 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x124f, "e823l-1g", "E823-L 1GbE", 0 ),
PCI_ROM ( 0x8086, 0x151d, "e823l-qsfp", "E823-L QSFP", 0 ),
PCI_ROM ( 0x8086, 0x1591, "e810c-bp", "E810-C backplane", 0 ),
PCI_ROM ( 0x8086, 0x1592, "e810c-qsfp", "E810-C QSFP", 0 ),
PCI_ROM ( 0x8086, 0x1593, "e810c-sfp", "E810-C SFP", 0 ),
PCI_ROM ( 0x8086, 0x1599, "e810-xxv-bp", "E810-XXV backplane", 0 ),
PCI_ROM ( 0x8086, 0x159a, "e810-xxv-qsfp", "E810-XXV QSFP", 0 ),
PCI_ROM ( 0x8086, 0x159b, "e810-xxv-sfp", "E810-XXV SFP", 0 ),
PCI_ROM ( 0x8086, 0x188a, "e823c-bp", "E823-C backplane", 0 ),
PCI_ROM ( 0x8086, 0x188b, "e823c-qsfp", "E823-C QSFP", 0 ),
PCI_ROM ( 0x8086, 0x188c, "e823c-sfp", "E823-C SFP", 0 ),
PCI_ROM ( 0x8086, 0x188d, "e823c-10gt", "E823-C 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x188e, "e823c-1g", "E823-C 1GbE", 0 ),
PCI_ROM ( 0x8086, 0x1890, "e822c-bp", "E822-C backplane", 0 ),
PCI_ROM ( 0x8086, 0x1891, "e822c-qsfp", "E822-C QSFP", 0 ),
PCI_ROM ( 0x8086, 0x1892, "e822c-sfp", "E822-C SFP", 0 ),
PCI_ROM ( 0x8086, 0x1893, "e822c-10gt", "E822-C 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x1894, "e822c-1g", "E822-C 1GbE", 0 ),
PCI_ROM ( 0x8086, 0x1897, "e822l-bp", "E822-L backplane", 0 ),
PCI_ROM ( 0x8086, 0x1898, "e822l-sfp", "E822-L SFP", 0 ),
PCI_ROM ( 0x8086, 0x1899, "e822l-10gt", "E822-L 10GBASE-T", 0 ),
PCI_ROM ( 0x8086, 0x189a, "e822l-1g", "E822-L 1GbE", 0 ),
}
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition: pci.h:308

PCI device IDs.

Definition at line 953 of file ice.c.

◆ __pci_driver

struct pci_driver ice_driver __pci_driver
Initial value:
= {
.ids = ice_nics,
.id_count = ( sizeof ( ice_nics ) / sizeof ( ice_nics[0] ) ),
.probe = ice_probe,
}
static struct xen_remove_from_physmap * remove
Definition: xenmem.h:39
static int ice_probe(struct pci_device *pci)
Probe PCI device.
Definition: ice.c:771
static struct pci_device_id ice_nics[]
PCI device IDs.
Definition: ice.c:953
static void ice_remove(struct pci_device *pci)
Remove PCI device.
Definition: ice.c:930

PCI driver.

Definition at line 982 of file ice.c.