iPXE
Functions
ath9k_ar9002_phy.c File Reference
#include <ipxe/io.h>
#include "hw.h"
#include "ar9002_phy.h"

Go to the source code of this file.

Functions

static int ar9002_hw_set_channel (struct ath_hw *ah, struct ath9k_channel *chan)
 DOC: Programming Atheros 802.11n analog front end radios. More...
 
static void ar9002_hw_spur_mitigate (struct ath_hw *ah, struct ath9k_channel *chan)
 ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan: More...
 
static void ar9002_olc_init (struct ath_hw *ah)
 
static u32 ar9002_hw_compute_pll_control (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ar9002_hw_do_getnf (struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
 
static void ar9002_hw_set_nf_limits (struct ath_hw *ah)
 
static void ar9002_hw_antdiv_comb_conf_get (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
 
static void ar9002_hw_antdiv_comb_conf_set (struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
 
void ar9002_hw_attach_phy_ops (struct ath_hw *ah)
 

Function Documentation

◆ ar9002_hw_set_channel()

static int ar9002_hw_set_channel ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

DOC: Programming Atheros 802.11n analog front end radios.

AR5416 MAC based PCI devices and AR518 MAC based PCI-Express devices have either an external AR2133 analog front end radio for single band 2.4 GHz communication or an AR5133 analog front end radio for dual band 2.4 GHz / 5 GHz communication.

All devices after the AR5416 and AR5418 family starting with the AR9280 have their analog front radios, MAC/BB and host PCIe/USB interface embedded into a single-chip and require less programming.

The following single-chips exist with a respective embedded radio:

AR9280 - 11n dual-band 2x2 MIMO for PCIe AR9281 - 11n single-band 1x2 MIMO for PCIe AR9285 - 11n single-band 1x1 for PCIe AR9287 - 11n single-band 2x2 MIMO for PCIe

AR9220 - 11n dual-band 2x2 MIMO for PCI AR9223 - 11n single-band 2x2 MIMO for PCI

AR9287 - 11n single-band 1x1 MIMO for USBar9002_hw_set_channel - set channel on single-chip device @ah: atheros hardware structure @chan:

This is the function to change channel on single-chip devices, that is all devices after ar9280.

This function takes the channel value in MHz and sets hardware channel value. Assumes writes have been enabled to analog bus.

Actual Expression,

For 2GHz channel, Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) (freq_ref = 40MHz)

For 5GHz channel, Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) (freq_ref = 40MHz/(24>>amodeRefSel))

Definition at line 71 of file ath9k_ar9002_phy.c.

72 {
73  u16 bMode, fracMode, aModeRefSel = 0;
74  u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
75  struct chan_centers centers;
76  u32 refDivA = 24;
77 
78  ath9k_hw_get_channel_centers(ah, chan, &centers);
79  freq = centers.synth_center;
80 
82  reg32 &= 0xc0000000;
83 
84  if (freq < 4800) { /* 2 GHz, fractional mode */
85  u32 txctl;
86  unsigned int regWrites = 0;
87 
88  bMode = 1;
89  fracMode = 1;
90  aModeRefSel = 0;
91  channelSel = CHANSEL_2G(freq);
92 
94  if (freq == 2484) {
95  /* Enable channel spreading for channel 14 */
96  REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
97  1, regWrites);
98  } else {
99  REG_WRITE_ARRAY(&ah->iniCckfirNormal,
100  1, regWrites);
101  }
102  } else {
103  txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
104  if (freq == 2484) {
105  /* Enable channel spreading for channel 14 */
107  txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
108  } else {
110  txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
111  }
112  }
113  } else {
114  bMode = 0;
115  fracMode = 0;
116 
117  switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
118  case 0:
119  if ((freq % 20) == 0)
120  aModeRefSel = 3;
121  else if ((freq % 10) == 0)
122  aModeRefSel = 2;
123  if (aModeRefSel)
124  break;
125  /* Fall through */
126  case 1:
127  default:
128  aModeRefSel = 0;
129  /*
130  * Enable 2G (fractional) mode for channels
131  * which are 5MHz spaced.
132  */
133  fracMode = 1;
134  refDivA = 1;
135  channelSel = CHANSEL_5G(freq);
136 
137  /* RefDivA setting */
139  AR_AN_SYNTH9_REFDIVA, refDivA);
140 
141  }
142 
143  if (!fracMode) {
144  ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
145  channelSel = ndiv & 0x1ff;
146  channelFrac = (ndiv & 0xfffffe00) * 2;
147  channelSel = (channelSel << 17) | channelFrac;
148  }
149  }
150 
151  reg32 = reg32 |
152  (bMode << 29) |
153  (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
154 
156 
157  ah->curchan = chan;
158  ah->curchan_rad_index = -1;
159 
160  return 0;
161 }
uint16_t u16
Definition: stdint.h:21
#define AR_SREV_9287_11_OR_LATER(_ah)
Definition: reg.h:836
#define AR_PHY_CCK_TX_CTRL_JAPAN
Definition: ar9002_phy.h:409
#define CHANSEL_5G(_freq)
Definition: phy.h:24
#define CHANSEL_2G(_freq)
Definition: phy.h:23
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_PHY_CCK_TX_CTRL
Definition: ar9002_phy.h:408
#define AR_AN_SYNTH9
Definition: reg.h:1277
#define AR_AN_SYNTH9_REFDIVA
Definition: reg.h:1278
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE_ARRAY(iniarray, column, regWr)
Definition: hw.h:119
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23
#define AR_PHY_SYNTH_CONTROL
Definition: ar9002_phy.h:158

References ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_JAPAN, AR_PHY_SYNTH_CONTROL, AR_SREV_9287_11_OR_LATER, ath9k_hw_get_channel_centers(), CHANSEL_2G, CHANSEL_5G, EEP_FRAC_N_5G, REG_READ, REG_RMW_FIELD, REG_WRITE, REG_WRITE_ARRAY, and chan_centers::synth_center.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_spur_mitigate()

static void ar9002_hw_spur_mitigate ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan:

For single-chip solutions. Converts to baseband spur frequency given the input channel frequency and compute register settings below.

Definition at line 171 of file ath9k_ar9002_phy.c.

173 {
174  int bb_spur = AR_NO_SPUR;
175  int freq;
176  int bin, cur_bin;
177  int bb_spur_off, spur_subchannel_sd;
178  int spur_freq_sd;
179  int spur_delta_phase;
180  int denominator;
181  int upper, lower, cur_vit_mask;
182  int tmp, newVal;
183  int i;
184  static const int pilot_mask_reg[4] = {
187  };
188  static const int chan_mask_reg[4] = {
191  };
192  static const int inc[4] = { 0, 100, 0, 0 };
193  struct chan_centers centers;
194 
195  int8_t mask_m[123];
196  int8_t mask_p[123];
197  int8_t mask_amt;
198  int tmp_mask;
199  int cur_bb_spur;
200  int is2GHz = IS_CHAN_2GHZ(chan);
201 
202  memset(&mask_m, 0, sizeof(int8_t) * 123);
203  memset(&mask_p, 0, sizeof(int8_t) * 123);
204 
205  ath9k_hw_get_channel_centers(ah, chan, &centers);
206  freq = centers.synth_center;
207 
208  ah->config.spurmode = SPUR_ENABLE_EEPROM;
209  for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
210  cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
211 
212  if (AR_NO_SPUR == cur_bb_spur)
213  break;
214 
215  if (is2GHz)
216  cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
217  else
218  cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
219 
220  cur_bb_spur = cur_bb_spur - freq;
221 
222  if (IS_CHAN_HT40(chan)) {
223  if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
224  (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
225  bb_spur = cur_bb_spur;
226  break;
227  }
228  } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
229  (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
230  bb_spur = cur_bb_spur;
231  break;
232  }
233  }
234 
235  if (AR_NO_SPUR == bb_spur) {
238  return;
239  } else {
242  }
243 
244  bin = bb_spur * 320;
245 
247 
249 
254  REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
255 
261  REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
262 
263  if (IS_CHAN_HT40(chan)) {
264  if (bb_spur < 0) {
265  spur_subchannel_sd = 1;
266  bb_spur_off = bb_spur + 10;
267  } else {
268  spur_subchannel_sd = 0;
269  bb_spur_off = bb_spur - 10;
270  }
271  } else {
272  spur_subchannel_sd = 0;
273  bb_spur_off = bb_spur;
274  }
275 
276  if (IS_CHAN_HT40(chan))
277  spur_delta_phase =
278  ((bb_spur * 262144) /
280  else
281  spur_delta_phase =
282  ((bb_spur * 524288) /
284 
285  denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
286  spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
287 
289  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
290  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
291  REG_WRITE(ah, AR_PHY_TIMING11, newVal);
292 
293  newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
294  REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
295 
296  cur_bin = -6000;
297  upper = bin + 100;
298  lower = bin - 100;
299 
300  for (i = 0; i < 4; i++) {
301  int pilot_mask = 0;
302  int chan_mask = 0;
303  int bp = 0;
304  for (bp = 0; bp < 30; bp++) {
305  if ((cur_bin > lower) && (cur_bin < upper)) {
306  pilot_mask = pilot_mask | 0x1 << bp;
307  chan_mask = chan_mask | 0x1 << bp;
308  }
309  cur_bin += 100;
310  }
311  cur_bin += inc[i];
312  REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
313  REG_WRITE(ah, chan_mask_reg[i], chan_mask);
314  }
315 
316  cur_vit_mask = 6100;
317  upper = bin + 120;
318  lower = bin - 120;
319 
320  for (i = 0; i < 123; i++) {
321  if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
322 
323  /* workaround for gcc bug #37014 */
324  volatile int tmp_v = abs(cur_vit_mask - bin);
325 
326  if (tmp_v < 75)
327  mask_amt = 1;
328  else
329  mask_amt = 0;
330  if (cur_vit_mask < 0)
331  mask_m[abs(cur_vit_mask / 100)] = mask_amt;
332  else
333  mask_p[cur_vit_mask / 100] = mask_amt;
334  }
335  cur_vit_mask -= 100;
336  }
337 
338  tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
339  | (mask_m[48] << 26) | (mask_m[49] << 24)
340  | (mask_m[50] << 22) | (mask_m[51] << 20)
341  | (mask_m[52] << 18) | (mask_m[53] << 16)
342  | (mask_m[54] << 14) | (mask_m[55] << 12)
343  | (mask_m[56] << 10) | (mask_m[57] << 8)
344  | (mask_m[58] << 6) | (mask_m[59] << 4)
345  | (mask_m[60] << 2) | (mask_m[61] << 0);
346  REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
348 
349  tmp_mask = (mask_m[31] << 28)
350  | (mask_m[32] << 26) | (mask_m[33] << 24)
351  | (mask_m[34] << 22) | (mask_m[35] << 20)
352  | (mask_m[36] << 18) | (mask_m[37] << 16)
353  | (mask_m[48] << 14) | (mask_m[39] << 12)
354  | (mask_m[40] << 10) | (mask_m[41] << 8)
355  | (mask_m[42] << 6) | (mask_m[43] << 4)
356  | (mask_m[44] << 2) | (mask_m[45] << 0);
357  REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
358  REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
359 
360  tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
361  | (mask_m[18] << 26) | (mask_m[18] << 24)
362  | (mask_m[20] << 22) | (mask_m[20] << 20)
363  | (mask_m[22] << 18) | (mask_m[22] << 16)
364  | (mask_m[24] << 14) | (mask_m[24] << 12)
365  | (mask_m[25] << 10) | (mask_m[26] << 8)
366  | (mask_m[27] << 6) | (mask_m[28] << 4)
367  | (mask_m[29] << 2) | (mask_m[30] << 0);
368  REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
369  REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
370 
371  tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
372  | (mask_m[2] << 26) | (mask_m[3] << 24)
373  | (mask_m[4] << 22) | (mask_m[5] << 20)
374  | (mask_m[6] << 18) | (mask_m[7] << 16)
375  | (mask_m[8] << 14) | (mask_m[9] << 12)
376  | (mask_m[10] << 10) | (mask_m[11] << 8)
377  | (mask_m[12] << 6) | (mask_m[13] << 4)
378  | (mask_m[14] << 2) | (mask_m[15] << 0);
379  REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
380  REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
381 
382  tmp_mask = (mask_p[15] << 28)
383  | (mask_p[14] << 26) | (mask_p[13] << 24)
384  | (mask_p[12] << 22) | (mask_p[11] << 20)
385  | (mask_p[10] << 18) | (mask_p[9] << 16)
386  | (mask_p[8] << 14) | (mask_p[7] << 12)
387  | (mask_p[6] << 10) | (mask_p[5] << 8)
388  | (mask_p[4] << 6) | (mask_p[3] << 4)
389  | (mask_p[2] << 2) | (mask_p[1] << 0);
390  REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
391  REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
392 
393  tmp_mask = (mask_p[30] << 28)
394  | (mask_p[29] << 26) | (mask_p[28] << 24)
395  | (mask_p[27] << 22) | (mask_p[26] << 20)
396  | (mask_p[25] << 18) | (mask_p[24] << 16)
397  | (mask_p[23] << 14) | (mask_p[22] << 12)
398  | (mask_p[21] << 10) | (mask_p[20] << 8)
399  | (mask_p[19] << 6) | (mask_p[18] << 4)
400  | (mask_p[17] << 2) | (mask_p[16] << 0);
401  REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
402  REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
403 
404  tmp_mask = (mask_p[45] << 28)
405  | (mask_p[44] << 26) | (mask_p[43] << 24)
406  | (mask_p[42] << 22) | (mask_p[41] << 20)
407  | (mask_p[40] << 18) | (mask_p[39] << 16)
408  | (mask_p[38] << 14) | (mask_p[37] << 12)
409  | (mask_p[36] << 10) | (mask_p[35] << 8)
410  | (mask_p[34] << 6) | (mask_p[33] << 4)
411  | (mask_p[32] << 2) | (mask_p[31] << 0);
412  REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
413  REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
414 
415  tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
416  | (mask_p[59] << 26) | (mask_p[58] << 24)
417  | (mask_p[57] << 22) | (mask_p[56] << 20)
418  | (mask_p[55] << 18) | (mask_p[54] << 16)
419  | (mask_p[53] << 14) | (mask_p[52] << 12)
420  | (mask_p[51] << 10) | (mask_p[50] << 8)
421  | (mask_p[49] << 6) | (mask_p[48] << 4)
422  | (mask_p[47] << 2) | (mask_p[46] << 0);
423  REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
424  REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
425 
427 }
#define AR_PHY_TIMING8
Definition: ar9002_phy.h:272
#define AR_SPUR_FEEQ_BOUND_HT40
Definition: hw.h:243
#define AR_PHY_TIMING7
Definition: ar9002_phy.h:271
#define AR_PHY_MASK2_M_16_30
Definition: ar9002_phy.h:511
#define AR_PHY_TIMING9
Definition: ar9002_phy.h:290
#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
Definition: ar9002_phy.h:449
#define AR_PHY_MASK2_M_31_45
Definition: ar9002_phy.h:510
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
Definition: ar9002_phy.h:197
#define AR_EEPROM_MODAL_SPURS
Definition: eeprom.h:25
#define REG_CLR_BIT(_a, _r, _f)
Definition: hw.h:109
#define AR_PHY_BIN_MASK_1
Definition: ar9002_phy.h:281
#define REGWRITE_BUFFER_FLUSH(_ah)
Definition: hw.h:95
#define AR_PHY_FORCE_CLKEN_CCK
Definition: ar9002_phy.h:448
uint16_t bp
Definition: registers.h:23
#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
Definition: ar9002_phy.h:525
#define AR_PHY_TIMING11_SPUR_FREQ_SD
Definition: ar9003_phy.h:36
#define AR_PHY_CHANNEL_MASK_01_30
Definition: ar9002_phy.h:532
#define AR_SPUR_FEEQ_BOUND_HT20
Definition: hw.h:244
#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM
Definition: ar9002_phy.h:522
#define AR_PHY_CHANNEL_MASK_31_60
Definition: ar9002_phy.h:533
#define AR_PHY_BIN_MASK2_3
Definition: ar9002_phy.h:278
#define AR_PHY_MASK2_P_61_45
Definition: ar9002_phy.h:516
#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
Definition: ar9002_phy.h:198
#define abs(x)
Definition: ath.h:44
#define AR_BASE_FREQ_5GHZ
Definition: hw.h:242
#define AR_PHY_MASK2_P_45_31
Definition: ar9002_phy.h:515
#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
Definition: ar9002_phy.h:353
#define SM(_v, _f)
Definition: hw.h:101
#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
Definition: ar9002_phy.h:199
#define AR_PHY_TIMING10
Definition: ar9002_phy.h:291
#define AR_PHY_TIMING_CTRL4(_i)
Definition: ar9002_phy.h:187
#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
Definition: ar9002_phy.h:200
#define SPUR_ENABLE_EEPROM
Definition: hw.h:237
signed char int8_t
Definition: stdint.h:15
#define AR_PHY_MASK2_P_30_16
Definition: ar9002_phy.h:514
#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
Definition: ar9002_phy.h:526
#define AR_PHY_SPUR_REG_MASK_RATE_CNTL
Definition: ar9002_phy.h:519
#define AR_PHY_TIMING11
Definition: ar9002_phy.h:295
uint8_t * tmp
Definition: entropy.h:156
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE
Definition: ar9002_phy.h:296
#define AR_PHY_SPUR_REG
Definition: ar9002_phy.h:517
#define AR_PHY_BIN_MASK2_4
Definition: ar9002_phy.h:279
#define AR_PHY_MASK2_M_00_15
Definition: ar9002_phy.h:512
#define AR_PHY_MASK_CTL
Definition: ar9002_phy.h:285
#define AR_NO_SPUR
Definition: hw.h:240
#define AR_PHY_SPUR_REG_MASK_RATE_SELECT
Definition: ar9002_phy.h:523
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define AR_PHY_MASK2_P_15_01
Definition: ar9002_phy.h:513
#define AR_PHY_BIN_MASK_2
Definition: ar9002_phy.h:282
#define AR_PHY_PILOT_MASK_31_60
Definition: ar9002_phy.h:530
#define AR_PHY_SFCORR_EXT
Definition: ar9002_phy.h:344
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_PILOT_MASK_01_30
Definition: ar9002_phy.h:529
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
uint8_t ah
Definition: registers.h:85
#define SPUR_RSSI_THRESH
Definition: hw.h:150
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
#define AR_PHY_BIN_MASK2_1
Definition: ar9002_phy.h:276
#define AR_PHY_BIN_MASK2_2
Definition: ar9002_phy.h:277
#define AR_PHY_BIN_MASK_3
Definition: ar9002_phy.h:283
#define AR_PHY_TIMING11_USE_SPUR_IN_AGC
Definition: ar9002_phy.h:298
#define ENABLE_REGWRITE_BUFFER(_ah)
Definition: hw.h:89
void * memset(void *dest, int character, size_t len) __nonnull
#define AR_BASE_FREQ_2GHZ
Definition: hw.h:241
#define AR_PHY_VIT_MASK2_M_46_61
Definition: ar9002_phy.h:509

References abs, ah, AR_BASE_FREQ_2GHZ, AR_BASE_FREQ_5GHZ, AR_EEPROM_MODAL_SPURS, AR_NO_SPUR, AR_PHY_BIN_MASK2_1, AR_PHY_BIN_MASK2_2, AR_PHY_BIN_MASK2_3, AR_PHY_BIN_MASK2_4, AR_PHY_BIN_MASK_1, AR_PHY_BIN_MASK_2, AR_PHY_BIN_MASK_3, AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX, AR_PHY_MASK2_M_00_15, AR_PHY_MASK2_M_16_30, AR_PHY_MASK2_M_31_45, AR_PHY_MASK2_P_15_01, AR_PHY_MASK2_P_30_16, AR_PHY_MASK2_P_45_31, AR_PHY_MASK2_P_61_45, AR_PHY_MASK_CTL, AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI, AR_PHY_SPUR_REG_MASK_RATE_CNTL, AR_PHY_SPUR_REG_MASK_RATE_SELECT, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_PHY_TIMING10, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, AR_PHY_TIMING11_SPUR_FREQ_SD, AR_PHY_TIMING11_USE_SPUR_IN_AGC, AR_PHY_TIMING7, AR_PHY_TIMING8, AR_PHY_TIMING9, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK, AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK, AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER, AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI, AR_PHY_VIT_MASK2_M_46_61, AR_SPUR_FEEQ_BOUND_HT20, AR_SPUR_FEEQ_BOUND_HT40, ath9k_hw_get_channel_centers(), bp, ENABLE_REGWRITE_BUFFER, IS_CHAN_2GHZ, IS_CHAN_HT40, memset(), REG_CLR_BIT, REG_READ, REG_WRITE, REGWRITE_BUFFER_FLUSH, SM, SPUR_ENABLE_EEPROM, SPUR_RSSI_THRESH, chan_centers::synth_center, and tmp.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_olc_init()

static void ar9002_olc_init ( struct ath_hw ah)
static

Definition at line 429 of file ath9k_ar9002_phy.c.

430 {
431  u32 i;
432 
434  return;
435 
443  udelay(100);
444  } else {
445  for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
446  ah->originalGain[i] =
447  MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
449  ah->PDADCdelta = 0;
450  }
451 }
#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE
Definition: reg.h:1419
#define AR_PHY_TX_PWRCTRL9
Definition: ar9002_phy.h:490
#define AR9280_TX_GAIN_TABLE_SIZE
Definition: eeprom.h:182
#define AR_PHY_TX_GAIN_TBL1
Definition: ar9002_phy.h:498
#define MS(_v, _f)
Definition: hw.h:102
#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL
Definition: ar9002_phy.h:495
#define OLC_FOR_AR9287_10_LATER
Definition: eeprom.h:108
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR9287_AN_TXPC0_TXPCMODE_S
Definition: reg.h:1416
#define AR9287_AN_TXPC0
Definition: reg.h:1414
#define AR9287_AN_TXPC0_TXPCMODE
Definition: reg.h:1415
#define OLC_FOR_AR9280_20_LATER
Definition: eeprom.h:106
void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val)
Definition: ath9k_eeprom.c:40
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_SET_BIT(_a, _r, _f)
Definition: hw.h:107
uint8_t ah
Definition: registers.h:85
#define AR_PHY_TX_GAIN
Definition: ar9002_phy.h:499
uint32_t u32
Definition: stdint.h:23

References ah, AR9280_TX_GAIN_TABLE_SIZE, AR9287_AN_TXPC0, AR9287_AN_TXPC0_TXPCMODE, AR9287_AN_TXPC0_TXPCMODE_S, AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE, AR_PHY_TX_GAIN, AR_PHY_TX_GAIN_TBL1, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL, ath9k_hw_analog_shift_rmw(), MS, OLC_FOR_AR9280_20_LATER, OLC_FOR_AR9287_10_LATER, REG_READ, REG_SET_BIT, and udelay().

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_compute_pll_control()

static u32 ar9002_hw_compute_pll_control ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 453 of file ath9k_ar9002_phy.c.

455 {
456  u32 pll;
457 
458  pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
459 
460  if (chan && IS_CHAN_HALF_RATE(chan))
461  pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
462  else if (chan && IS_CHAN_QUARTER_RATE(chan))
463  pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
464 
465  if (chan && IS_CHAN_5GHZ(chan)) {
466  if (IS_CHAN_A_FAST_CLOCK(ah, chan))
467  pll = 0x142c;
468  else if (AR_SREV_9280_20(ah))
469  pll = 0x2850;
470  else
471  pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
472  } else {
473  pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
474  }
475 
476  return pll;
477 }
#define AR_RTC_9160_PLL_REFDIV
Definition: reg.h:1152
#define IS_CHAN_HALF_RATE(_c)
Definition: hw.h:362
#define AR_SREV_9280_20(_ah)
Definition: reg.h:826
#define IS_CHAN_QUARTER_RATE(_c)
Definition: hw.h:363
#define SM(_v, _f)
Definition: hw.h:101
#define AR_RTC_9160_PLL_DIV
Definition: reg.h:1150
#define AR_RTC_9160_PLL_CLKSEL
Definition: reg.h:1154
#define IS_CHAN_5GHZ(_c)
Definition: hw.h:360
uint8_t ah
Definition: registers.h:85
#define IS_CHAN_A_FAST_CLOCK(_ah, _c)
Definition: hw.h:364
uint32_t u32
Definition: stdint.h:23

References ah, AR_RTC_9160_PLL_CLKSEL, AR_RTC_9160_PLL_DIV, AR_RTC_9160_PLL_REFDIV, AR_SREV_9280_20, IS_CHAN_5GHZ, IS_CHAN_A_FAST_CLOCK, IS_CHAN_HALF_RATE, IS_CHAN_QUARTER_RATE, and SM.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_do_getnf()

static void ar9002_hw_do_getnf ( struct ath_hw ah,
int16_t  nfarray[NUM_NF_READINGS] 
)
static

Definition at line 479 of file ath9k_ar9002_phy.c.

481 {
482  int16_t nf;
483 
485  nfarray[0] = sign_extend32(nf, 8);
486 
488  if (IS_CHAN_HT40(ah->curchan))
489  nfarray[3] = sign_extend32(nf, 8);
490 
491  if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
492  return;
493 
495  nfarray[1] = sign_extend32(nf, 8);
496 
498  if (IS_CHAN_HT40(ah->curchan))
499  nfarray[4] = sign_extend32(nf, 8);
500 }
#define AR9280_PHY_MINCCA_PWR
Definition: ar9002_phy.h:134
#define AR_PHY_CH1_CCA
Definition: ar9002_phy.h:569
#define MS(_v, _f)
Definition: hw.h:102
#define AR9280_PHY_EXT_MINCCA_PWR
Definition: ar9002_phy.h:341
static int32_t sign_extend32(uint32_t value, int index)
Definition: ath.h:69
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define AR_PHY_EXT_CCA
Definition: ar9002_phy.h:331
#define AR9280_PHY_CH1_EXT_MINCCA_PWR
Definition: ar9002_phy.h:582
#define AR_PHY_CH1_EXT_CCA
Definition: ar9002_phy.h:579
#define AR9280_PHY_CH1_MINCCA_PWR
Definition: ar9002_phy.h:572
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define AR_PHY_CCA
Definition: ar9002_phy.h:129
#define AR_SREV_9271(_ah)
Definition: reg.h:853
uint8_t ah
Definition: registers.h:85
signed short int16_t
Definition: stdint.h:16
#define IS_CHAN_HT40(_c)
Definition: hw.h:372

References ah, AR9280_PHY_CH1_EXT_MINCCA_PWR, AR9280_PHY_CH1_MINCCA_PWR, AR9280_PHY_EXT_MINCCA_PWR, AR9280_PHY_MINCCA_PWR, AR_PHY_CCA, AR_PHY_CH1_CCA, AR_PHY_CH1_EXT_CCA, AR_PHY_EXT_CCA, AR_SREV_9271, AR_SREV_9285, IS_CHAN_HT40, MS, REG_READ, and sign_extend32().

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_set_nf_limits()

static void ar9002_hw_set_nf_limits ( struct ath_hw ah)
static

Definition at line 502 of file ath9k_ar9002_phy.c.

503 {
504  if (AR_SREV_9285(ah)) {
507  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
508  } else if (AR_SREV_9287(ah)) {
511  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
512  } else if (AR_SREV_9271(ah)) {
515  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
516  } else {
519  ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
522  ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
523  }
524 }
#define AR_PHY_CCA_NOM_VAL_9285_2GHZ
Definition: ar9002_phy.h:603
#define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ
Definition: ar9002_phy.h:613
#define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ
Definition: ar9002_phy.h:609
#define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ
Definition: ar9002_phy.h:608
#define AR_SREV_9285(_ah)
Definition: reg.h:829
#define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ
Definition: ar9002_phy.h:600
#define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ
Definition: ar9002_phy.h:604
#define AR_SREV_9287(_ah)
Definition: reg.h:834
#define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ
Definition: ar9002_phy.h:605
#define AR_PHY_CCA_NOM_VAL_9287_2GHZ
Definition: ar9002_phy.h:611
#define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ
Definition: ar9002_phy.h:599
#define AR_PHY_CCA_NOM_VAL_9280_2GHZ
Definition: ar9002_phy.h:596
#define AR_PHY_CCA_NOM_VAL_9280_5GHZ
Definition: ar9002_phy.h:597
#define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ
Definition: ar9002_phy.h:601
#define AR_SREV_9271(_ah)
Definition: reg.h:853
#define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ
Definition: ar9002_phy.h:612
uint8_t ah
Definition: registers.h:85
#define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ
Definition: ar9002_phy.h:598
#define AR_PHY_CCA_NOM_VAL_9271_2GHZ
Definition: ar9002_phy.h:607

References ah, AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ, AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ, AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ, AR_PHY_CCA_NOM_VAL_9271_2GHZ, AR_PHY_CCA_NOM_VAL_9280_2GHZ, AR_PHY_CCA_NOM_VAL_9280_5GHZ, AR_PHY_CCA_NOM_VAL_9285_2GHZ, AR_PHY_CCA_NOM_VAL_9287_2GHZ, AR_SREV_9271, AR_SREV_9285, and AR_SREV_9287.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_antdiv_comb_conf_get()

static void ar9002_hw_antdiv_comb_conf_get ( struct ath_hw ah,
struct ath_hw_antcomb_conf antconf 
)
static

Definition at line 526 of file ath9k_ar9002_phy.c.

528 {
529  u32 regval;
530 
532  antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
534  antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
536  antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
538  antconf->lna1_lna2_delta = -3;
539  antconf->div_group = 0;
540 }
u8 fast_div_bias
Definition: hw.h:484
#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF
Definition: ar9002_phy.h:314
#define AR_PHY_9285_FAST_DIV_BIAS_S
Definition: ar9002_phy.h:308
#define AR_PHY_MULTICHAIN_GAIN_CTL
Definition: ar9002_phy.h:306
#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S
Definition: ar9002_phy.h:313
#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S
Definition: ar9002_phy.h:315
#define REG_READ(_ah, _reg)
Definition: hw.h:80
int lna1_lna2_delta
Definition: hw.h:487
#define AR_PHY_9285_FAST_DIV_BIAS
Definition: ar9002_phy.h:307
u8 main_lna_conf
Definition: hw.h:482
uint8_t ah
Definition: registers.h:85
#define AR_PHY_9285_ANT_DIV_ALT_LNACONF
Definition: ar9002_phy.h:312
uint32_t u32
Definition: stdint.h:23

References ah, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9285_ANT_DIV_ALT_LNACONF, AR_PHY_9285_ANT_DIV_ALT_LNACONF_S, AR_PHY_9285_ANT_DIV_MAIN_LNACONF, AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9285_FAST_DIV_BIAS, AR_PHY_9285_FAST_DIV_BIAS_S, AR_PHY_MULTICHAIN_GAIN_CTL, ath_hw_antcomb_conf::div_group, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::lna1_lna2_delta, ath_hw_antcomb_conf::main_lna_conf, and REG_READ.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_antdiv_comb_conf_set()

static void ar9002_hw_antdiv_comb_conf_set ( struct ath_hw ah,
struct ath_hw_antcomb_conf antconf 
)
static

Definition at line 542 of file ath9k_ar9002_phy.c.

544 {
545  u32 regval;
546 
551  regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
553  regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
555  regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
557 
559 }
u8 fast_div_bias
Definition: hw.h:484
#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF
Definition: ar9002_phy.h:314
#define AR_PHY_9285_FAST_DIV_BIAS_S
Definition: ar9002_phy.h:308
#define AR_PHY_MULTICHAIN_GAIN_CTL
Definition: ar9002_phy.h:306
#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S
Definition: ar9002_phy.h:313
#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S
Definition: ar9002_phy.h:315
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_9285_FAST_DIV_BIAS
Definition: ar9002_phy.h:307
u8 main_lna_conf
Definition: hw.h:482
uint8_t ah
Definition: registers.h:85
#define AR_PHY_9285_ANT_DIV_ALT_LNACONF
Definition: ar9002_phy.h:312
uint32_t u32
Definition: stdint.h:23

References ah, ath_hw_antcomb_conf::alt_lna_conf, AR_PHY_9285_ANT_DIV_ALT_LNACONF, AR_PHY_9285_ANT_DIV_ALT_LNACONF_S, AR_PHY_9285_ANT_DIV_MAIN_LNACONF, AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S, AR_PHY_9285_FAST_DIV_BIAS, AR_PHY_9285_FAST_DIV_BIAS_S, AR_PHY_MULTICHAIN_GAIN_CTL, ath_hw_antcomb_conf::fast_div_bias, ath_hw_antcomb_conf::main_lna_conf, REG_READ, and REG_WRITE.

Referenced by ar9002_hw_attach_phy_ops().

◆ ar9002_hw_attach_phy_ops()

void ar9002_hw_attach_phy_ops ( struct ath_hw ah)

Definition at line 561 of file ath9k_ar9002_phy.c.

562 {
563  struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
564  struct ath_hw_ops *ops = ath9k_hw_ops(ah);
565 
566  priv_ops->set_rf_regs = NULL;
567  priv_ops->rf_alloc_ext_banks = NULL;
568  priv_ops->rf_free_ext_banks = NULL;
571  priv_ops->olc_init = ar9002_olc_init;
573  priv_ops->do_getnf = ar9002_hw_do_getnf;
574 
577 
579 }
void(* rf_free_ext_banks)(struct ath_hw *ah)
Definition: hw.h:566
void(* spur_mitigate_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:563
int(* rf_alloc_ext_banks)(struct ath_hw *ah)
Definition: hw.h:565
static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, struct ath9k_channel *chan)
void(* olc_init)(struct ath_hw *ah)
Definition: hw.h:574
struct ath_hw_private_ops - callbacks used internally by hardware code
Definition: hw.h:550
void(* antdiv_comb_conf_set)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:641
static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
DOC: Programming Atheros 802.11n analog front end radios.
static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
static void ar9002_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
int(* set_rf_regs)(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex)
Definition: hw.h:567
static void ar9002_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
ar9002_hw_spur_mitigate - convert baseband spur frequency @ah: atheros hardware structure @chan:
struct ath_hw_ops - callbacks used by hardware code and driver code
Definition: hw.h:603
static void ar9002_olc_init(struct ath_hw *ah)
static struct ath_hw_ops * ath9k_hw_ops(struct ath_hw *ah)
Definition: hw.h:884
static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
void(* antdiv_comb_conf_get)(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
Definition: hw.h:639
int(* rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:561
static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, struct ath_hw_antcomb_conf *antconf)
uint8_t ah
Definition: registers.h:85
u32(* compute_pll_control)(struct ath_hw *ah, struct ath9k_channel *chan)
Definition: hw.h:582
static struct ath_hw_private_ops * ath9k_hw_private_ops(struct ath_hw *ah)
Definition: hw.h:879
void(* do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS])
Definition: hw.h:586
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath_hw_ops::antdiv_comb_conf_get, ath_hw_ops::antdiv_comb_conf_set, ar9002_hw_antdiv_comb_conf_get(), ar9002_hw_antdiv_comb_conf_set(), ar9002_hw_compute_pll_control(), ar9002_hw_do_getnf(), ar9002_hw_set_channel(), ar9002_hw_set_nf_limits(), ar9002_hw_spur_mitigate(), ar9002_olc_init(), ath9k_hw_ops(), ath9k_hw_private_ops(), ath_hw_private_ops::compute_pll_control, ath_hw_private_ops::do_getnf, NULL, ath_hw_private_ops::olc_init, ath_hw_private_ops::rf_alloc_ext_banks, ath_hw_private_ops::rf_free_ext_banks, ath_hw_private_ops::rf_set_freq, ath_hw_private_ops::set_rf_regs, and ath_hw_private_ops::spur_mitigate_freq.

Referenced by ar9002_hw_attach_ops().