iPXE
bnxt.c File Reference
#include <mii.h>
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <unistd.h>
#include <byteswap.h>
#include <ipxe/pci.h>
#include <ipxe/iobuf.h>
#include <ipxe/dma.h>
#include <ipxe/timer.h>
#include <ipxe/malloc.h>
#include <ipxe/if_ether.h>
#include <ipxe/ethernet.h>
#include <ipxe/netdevice.h>
#include "bnxt.h"
#include "bnxt_dbg.h"

Go to the source code of this file.

Macros

#define bnxt_down_chip(bp)
#define bnxt_up_chip(bp)
#define bnxt_down_nic(bp)
#define bnxt_up_nic(bp)
#define bnxt_up_init(bp)
#define BNXT_FW_HEALTH_WIN_OFF   0x3000
#define BNXT_REG_WINDOW_BASE   0x400
#define BNXT_GRC_BASE_MASK   0xfff
#define BNXT_GRC_OFFSET_MASK   0xffc

Typedefs

typedef int(* hwrm_func_t) (struct bnxt *bp)

Functions

 FILE_LICENCE (GPL2_ONLY)
static void bnxt_service_cq (struct net_device *dev)
static void bnxt_tx_complete (struct net_device *dev, u16 hw_idx)
static void bnxt_adv_cq_index (struct bnxt *bp, u16 cnt)
static void bnxt_adv_nq_index (struct bnxt *bp, u16 cnt)
static int bnxt_rx_complete (struct net_device *dev, struct rx_pkt_cmpl *rx)
void bnxt_link_evt (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
u8 bnxt_is_pci_vf (struct pci_device *pdev)
 Check if Virtual Function.
static void bnxt_down_pci (struct bnxt *bp)
static void * bnxt_pci_base (struct pci_device *pdev, unsigned int reg)
static int bnxt_get_pci_info (struct bnxt *bp)
static int bnxt_get_device_address (struct bnxt *bp)
static void bnxt_set_link (struct bnxt *bp)
static void dev_p5_db (struct bnxt *bp, u32 idx, u32 xid, u32 flag)
static void dev_p7_db (struct bnxt *bp, u32 idx, u32 xid, u32 flag, u32 epoch, u32 toggle)
static void bnxt_db_nq (struct bnxt *bp)
static void bnxt_db_cq (struct bnxt *bp)
static void bnxt_db_rx (struct bnxt *bp, u32 idx)
static void bnxt_db_tx (struct bnxt *bp, u32 idx)
void bnxt_add_vlan (struct io_buffer *iob, u16 vlan)
static u16 bnxt_get_pkt_vlan (char *src)
static u32 bnxt_tx_avail (struct bnxt *bp)
void bnxt_set_txq (struct bnxt *bp, int entry, physaddr_t mapping, int len)
int bnxt_free_rx_iob (struct bnxt *bp)
static void bnxt_set_rx_desc (u8 *buf, struct io_buffer *iob, u16 cid, u32 idx)
static int bnxt_alloc_rx_iob (struct bnxt *bp, u16 cons_id, u16 iob_idx)
int bnxt_post_rx_buffers (struct bnxt *bp)
u8 bnxt_rx_drop (struct bnxt *bp, struct io_buffer *iob, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi, u16 rx_len)
void bnxt_rx_process (struct net_device *dev, struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi)
void bnxt_mm_init_hwrm (struct bnxt *bp, const char *func)
void bnxt_mm_init_rings (struct bnxt *bp, const char *func)
void bnxt_mm_nic (struct bnxt *bp)
void bnxt_free_rings_mem (struct bnxt *bp)
void bnxt_free_hwrm_mem (struct bnxt *bp)
int bnxt_alloc_hwrm_mem (struct bnxt *bp)
int bnxt_alloc_rings_mem (struct bnxt *bp)
static void hwrm_init (struct bnxt *bp, struct input *req, u16 cmd, u16 len)
static void hwrm_write_req (struct bnxt *bp, void *req, u32 cnt)
static void short_hwrm_cmd_req (struct bnxt *bp, u16 len, u16 req_type)
static int wait_resp (struct bnxt *bp, u32 tmo, u16 len, const char *func)
static int bnxt_hwrm_ver_get (struct bnxt *bp)
static int bnxt_hwrm_func_resource_qcaps (struct bnxt *bp)
static u32 bnxt_set_ring_info (struct bnxt *bp)
static void bnxt_hwrm_assign_resources (struct bnxt *bp)
static int bnxt_hwrm_func_qcaps_req (struct bnxt *bp)
static int bnxt_hwrm_func_qcfg_req (struct bnxt *bp)
static int bnxt_hwrm_port_phy_qcaps_req (struct bnxt *bp)
static int bnxt_hwrm_func_reset_req (struct bnxt *bp)
static int bnxt_hwrm_func_cfg_req (struct bnxt *bp)
static int bnxt_hwrm_error_recovery_req (struct bnxt *bp)
static int bnxt_hwrm_func_drv_rgtr (struct bnxt *bp)
static int bnxt_hwrm_func_drv_unrgtr (struct bnxt *bp)
static int bnxt_hwrm_set_async_event (struct bnxt *bp)
static int bnxt_hwrm_cfa_l2_filter_alloc (struct bnxt *bp)
static int bnxt_hwrm_cfa_l2_filter_free (struct bnxt *bp)
u32 set_rx_mask (u32 rx_mask)
static int bnxt_hwrm_set_rx_mask (struct bnxt *bp, u32 rx_mask)
static int bnxt_hwrm_port_phy_qcfg (struct bnxt *bp, u16 idx)
static int bnxt_hwrm_nvm_get_variable_req (struct bnxt *bp, u16 data_len, u16 option_num, u16 dimensions, u16 index_0)
static int bnxt_get_link_speed (struct bnxt *bp)
static int bnxt_hwrm_backing_store_qcfg (struct bnxt *bp)
static int bnxt_hwrm_backing_store_cfg (struct bnxt *bp)
static int bnxt_hwrm_queue_qportcfg (struct bnxt *bp)
static int bnxt_hwrm_port_mac_cfg (struct bnxt *bp)
static int bnxt_hwrm_port_phy_cfg (struct bnxt *bp)
static int bnxt_query_phy_link (struct bnxt *bp)
static int bnxt_get_phy_link (struct bnxt *bp)
static int bnxt_hwrm_stat_ctx_alloc (struct bnxt *bp)
static int bnxt_hwrm_stat_ctx_free (struct bnxt *bp)
static int bnxt_hwrm_ring_free_grp (struct bnxt *bp)
static int bnxt_hwrm_ring_alloc_grp (struct bnxt *bp)
int bnxt_hwrm_ring_free (struct bnxt *bp, u16 ring_id, u8 ring_type)
static int bnxt_hwrm_ring_alloc (struct bnxt *bp, u8 type)
static int bnxt_hwrm_ring_alloc_cq (struct bnxt *bp)
static int bnxt_hwrm_ring_alloc_tx (struct bnxt *bp)
static int bnxt_hwrm_ring_alloc_rx (struct bnxt *bp)
static int bnxt_hwrm_ring_free_cq (struct bnxt *bp)
static int bnxt_hwrm_ring_free_tx (struct bnxt *bp)
static int bnxt_hwrm_ring_free_rx (struct bnxt *bp)
static int bnxt_hwrm_ring_alloc_nq (struct bnxt *bp)
static int bnxt_hwrm_ring_free_nq (struct bnxt *bp)
static int bnxt_hwrm_vnic_alloc (struct bnxt *bp)
static int bnxt_hwrm_vnic_free (struct bnxt *bp)
static int bnxt_hwrm_vnic_cfg (struct bnxt *bp)
static int bnxt_set_rx_mask (struct bnxt *bp)
static int bnxt_reset_rx_mask (struct bnxt *bp)
static int bnxt_get_link_state (struct bnxt *bp)
int bnxt_hwrm_run (hwrm_func_t cmds[], struct bnxt *bp, int flag)
static int bnxt_open (struct net_device *dev)
static void bnxt_tx_adjust_pkt (struct bnxt *bp, struct io_buffer *iob)
static int bnxt_tx (struct net_device *dev, struct io_buffer *iob)
u32 bnxt_er_reg_write (struct bnxt *bp, u32 reg_addr, u32 reg_val)
u32 bnxt_er_reg_read (struct bnxt *bp, u32 reg_addr)
u32 bnxt_er_get_reg_val (struct bnxt *bp, u32 reg_addr, u32 reg_type, u32 mask)
void bnxt_rst_reg_val (struct bnxt *bp, u32 reg_addr, u32 reg_val)
void bnxt_rst_er_registers (struct bnxt *bp)
void bnxt_er_task (struct bnxt *bp, u8 hb_task)
void bnxt_process_er_event (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
void bnxt_process_reset_notify_event (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
void bnxt_link_speed_evt (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
void bnxt_link_speed_chg_evt (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
void bnxt_port_phy_chg_evt (struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
static void bnxt_service_nq (struct net_device *dev)
static void bnxt_er_task_timer (struct retry_timer *timer, int over __unused)
static void bnxt_er_wait_timer (struct retry_timer *timer, int over __unused)
static void bnxt_poll (struct net_device *dev)
static void bnxt_close (struct net_device *dev)
static int bnxt_init_one (struct pci_device *pci)
static void bnxt_remove_one (struct pci_device *pci)

Variables

static struct pci_device_id bnxt_nics []
hwrm_func_t bring_up_init []
hwrm_func_t bring_down_chip []
hwrm_func_t bring_down_nic []
hwrm_func_t bring_up_chip []
hwrm_func_t bring_up_nic []
static struct net_device_operations bnxt_netdev_ops
struct pci_driver bnxt_pci_driver __pci_driver

Macro Definition Documentation

◆ bnxt_down_chip

#define bnxt_down_chip ( bp)
Value:
hwrm_func_t bring_down_chip[]
Definition bnxt.c:2095
int bnxt_hwrm_run(hwrm_func_t cmds[], struct bnxt *bp, int flag)
Definition bnxt.c:2151
uint16_t bp
Definition registers.h:9

Definition at line 2175 of file bnxt.c.

◆ bnxt_up_chip

#define bnxt_up_chip ( bp)
Value:
hwrm_func_t bring_up_chip[]
Definition bnxt.c:2115

Definition at line 2176 of file bnxt.c.

Referenced by bnxt_er_task(), and bnxt_open().

◆ bnxt_down_nic

#define bnxt_down_nic ( bp)
Value:
hwrm_func_t bring_down_nic[]
Definition bnxt.c:2100

Definition at line 2177 of file bnxt.c.

Referenced by bnxt_close(), and bnxt_open().

◆ bnxt_up_nic

#define bnxt_up_nic ( bp)
Value:
hwrm_func_t bring_up_nic[]
Definition bnxt.c:2133

Definition at line 2178 of file bnxt.c.

Referenced by bnxt_er_task(), and bnxt_open().

◆ bnxt_up_init

#define bnxt_up_init ( bp)
Value:
hwrm_func_t bring_up_init[]
Definition bnxt.c:2086

Definition at line 2179 of file bnxt.c.

Referenced by bnxt_init_one().

◆ BNXT_FW_HEALTH_WIN_OFF

#define BNXT_FW_HEALTH_WIN_OFF   0x3000

Definition at line 2290 of file bnxt.c.

Referenced by bnxt_er_reg_read(), and bnxt_er_reg_write().

◆ BNXT_REG_WINDOW_BASE

#define BNXT_REG_WINDOW_BASE   0x400

Definition at line 2291 of file bnxt.c.

Referenced by bnxt_er_reg_read(), and bnxt_er_reg_write().

◆ BNXT_GRC_BASE_MASK

#define BNXT_GRC_BASE_MASK   0xfff

Definition at line 2292 of file bnxt.c.

Referenced by bnxt_er_reg_read(), and bnxt_er_reg_write().

◆ BNXT_GRC_OFFSET_MASK

#define BNXT_GRC_OFFSET_MASK   0xffc

Definition at line 2293 of file bnxt.c.

Referenced by bnxt_er_reg_read(), and bnxt_er_reg_write().

Typedef Documentation

◆ hwrm_func_t

typedef int(* hwrm_func_t) (struct bnxt *bp)

Definition at line 2084 of file bnxt.c.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( GPL2_ONLY )

References bp, rx, and u16.

◆ bnxt_service_cq()

void bnxt_service_cq ( struct net_device * dev)
static

Definition at line 2587 of file bnxt.c.

2588{
2589 struct bnxt *bp = dev->priv;
2590 struct cmpl_base *cmp;
2591 struct tx_cmpl *tx;
2592 u16 old_cid = bp->cq.cons_id;
2594 u32 cq_type;
2595 struct hwrm_async_event_cmpl *evt;
2596
2597 while ( done == SERVICE_NEXT_CQ_BD ) {
2598 cmp = ( struct cmpl_base * ) BD_NOW ( CQ_DMA_ADDR ( bp ),
2599 bp->cq.cons_id,
2600 sizeof ( struct cmpl_base ) );
2601
2602 if ( ( cmp->info3_v & CMPL_BASE_V ) ^ bp->cq.completion_bit )
2603 break;
2604
2605 cq_type = cmp->type & CMPL_BASE_TYPE_MASK;
2606 dump_evt ( ( u8 * ) cmp, cq_type, bp->cq.cons_id, 0 );
2607 dump_cq ( cmp, bp->cq.cons_id, bp->nq.toggle );
2608
2609 switch ( cq_type ) {
2611 tx = ( struct tx_cmpl * ) cmp;
2612 bnxt_tx_complete ( dev, ( u16 ) tx->opaque );
2613 bnxt_adv_cq_index ( bp, 1 );
2614 break;
2616 bnxt_adv_cq_index ( bp, 1 );
2617 break;
2620 done = bnxt_rx_complete ( dev,
2621 ( struct rx_pkt_cmpl * ) cmp );
2622 break;
2624 evt = ( struct hwrm_async_event_cmpl * ) cmp;
2625 switch ( evt->event_id ) {
2627 bnxt_link_evt ( bp,
2628 ( struct hwrm_async_event_cmpl * ) cmp );
2629 break;
2632 ( struct hwrm_async_event_cmpl * ) cmp );
2633 break;
2636 ( struct hwrm_async_event_cmpl * ) cmp );
2637 break;
2640 ( struct hwrm_async_event_cmpl * ) cmp );
2641 break;
2644 ( struct hwrm_async_event_cmpl * ) cmp );
2645 break;
2648 ( struct hwrm_async_event_cmpl * ) cmp );
2649 break;
2650 default:
2651 break;
2652 }
2653 bnxt_adv_cq_index ( bp, 1 );
2654 break;
2655 default:
2657 break;
2658 }
2659 }
2660
2661 if ( bp->cq.cons_id != old_cid )
2662 bnxt_db_cq ( bp );
2663}
static void bnxt_db_cq(struct bnxt *bp)
Definition bnxt.c:229
void bnxt_link_speed_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2542
void bnxt_link_speed_chg_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2558
void bnxt_process_er_event(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2480
void bnxt_port_phy_chg_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2572
static void bnxt_tx_complete(struct net_device *dev, u16 hw_idx)
Definition bnxt.c:318
void bnxt_link_evt(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2279
static int bnxt_rx_complete(struct net_device *dev, struct rx_pkt_cmpl *rx)
Definition bnxt.c:491
static void bnxt_adv_cq_index(struct bnxt *bp, u16 cnt)
Definition bnxt.c:452
void bnxt_process_reset_notify_event(struct bnxt *bp, struct hwrm_async_event_cmpl *evt)
Definition bnxt.c:2520
#define CMPL_BASE_TYPE_TX_L2
Definition bnxt.h:522
#define CMPL_BASE_TYPE_RX_L2_V3
Definition bnxt.h:527
#define BD_NOW(bd, entry, len)
Definition bnxt.h:162
#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
Definition bnxt.h:532
#define CMPL_BASE_TYPE_MASK
Definition bnxt.h:520
#define CQ_DMA_ADDR(bp)
Definition bnxt.h:179
#define CMPL_BASE_TYPE_RX_L2
Definition bnxt.h:523
#define NO_MORE_CQ_BD_TO_SERVICE
Definition bnxt.h:187
#define SERVICE_NEXT_CQ_BD
Definition bnxt.h:188
#define CMPL_BASE_V
Definition bnxt.h:542
#define CMPL_BASE_TYPE_STAT_EJECT
Definition bnxt.h:528
#define dump_evt(cq, ty, id, ring)
Definition bnxt_dbg.h:660
#define dump_cq(cq, id, toggle)
Definition bnxt_dbg.h:508
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE
Definition bnxt_hsi.h:560
#define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY
Definition bnxt_hsi.h:563
#define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE
Definition bnxt_hsi.h:561
#define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
Definition bnxt_hsi.h:562
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
Definition bnxt_hsi.h:554
#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE
Definition bnxt_hsi.h:556
struct bofm_section_header done
Definition bofm_test.c:46
#define u8
Definition igbvf_osdep.h:40
Definition bnxt.h:949
struct net_device * dev
Definition bnxt.h:967
u16 type
Definition bnxt.h:519
u32 info3_v
Definition bnxt.h:541
void * priv
Driver private data.
Definition netdevice.h:432
#define u16
Definition vga.h:20
#define u32
Definition vga.h:21
u8 tx[WPA_TKIP_MIC_KEY_LEN]
MIC key for packets to the AP.
Definition wpa.h:4

References ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, BD_NOW, bnxt_adv_cq_index(), bnxt_db_cq(), bnxt_link_evt(), bnxt_link_speed_chg_evt(), bnxt_link_speed_evt(), bnxt_port_phy_chg_evt(), bnxt_process_er_event(), bnxt_process_reset_notify_event(), bnxt_rx_complete(), bnxt_tx_complete(), bp, CMPL_BASE_TYPE_HWRM_ASYNC_EVENT, CMPL_BASE_TYPE_MASK, CMPL_BASE_TYPE_RX_L2, CMPL_BASE_TYPE_RX_L2_V3, CMPL_BASE_TYPE_STAT_EJECT, CMPL_BASE_TYPE_TX_L2, CMPL_BASE_V, CQ_DMA_ADDR, bnxt::dev, done, dump_cq, dump_evt, hwrm_async_event_cmpl::event_id, cmpl_base::info3_v, NO_MORE_CQ_BD_TO_SERVICE, net_device::priv, SERVICE_NEXT_CQ_BD, tx, cmpl_base::type, u16, u32, and u8.

Referenced by bnxt_poll().

◆ bnxt_tx_complete()

void bnxt_tx_complete ( struct net_device * dev,
u16 hw_idx )
static

Definition at line 318 of file bnxt.c.

319{
320 struct bnxt *bp = dev->priv;
321 struct io_buffer *iob;
322
323 iob = bp->tx.iob[hw_idx];
324 dbg_tx_done ( iob->data, iob_len ( iob ), hw_idx );
325 netdev_tx_complete ( dev, iob );
326 bp->tx.cons_id = NEXT_IDX ( hw_idx, bp->tx.ring_cnt );
327 bp->tx.cnt++;
328 dump_tx_stat ( bp );
329}
#define NEXT_IDX(N, S)
Definition bnxt.h:161
#define dbg_tx_done(pkt, len, idx)
Definition bnxt_dbg.h:569
#define dump_tx_stat(bp)
Definition bnxt_dbg.h:566
static size_t iob_len(struct io_buffer *iobuf)
Calculate length of data in an I/O buffer.
Definition iobuf.h:220
static void netdev_tx_complete(struct net_device *netdev, struct io_buffer *iobuf)
Complete network transmission.
Definition netdevice.h:770
A persistent I/O buffer.
Definition iobuf.h:98
void * data
Start of data.
Definition iobuf.h:113

References bp, io_buffer::data, dbg_tx_done, bnxt::dev, dump_tx_stat, iob_len(), netdev_tx_complete(), NEXT_IDX, net_device::priv, and u16.

Referenced by bnxt_service_cq().

◆ bnxt_adv_cq_index()

void bnxt_adv_cq_index ( struct bnxt * bp,
u16 cnt )
static

Definition at line 452 of file bnxt.c.

453{
454 u16 cons_id;
455
456 cons_id = bp->cq.cons_id + cnt;
457 if ( cons_id >= bp->cq.ring_cnt ) {
458 /* Toggle completion bit when the ring wraps. */
459 bp->cq.completion_bit ^= 1;
460 bp->cq.epoch ^= 1;
461 cons_id = cons_id - bp->cq.ring_cnt;
462 }
463 bp->cq.cons_id = cons_id;
464}

References bp, and u16.

Referenced by bnxt_rx_process(), and bnxt_service_cq().

◆ bnxt_adv_nq_index()

void bnxt_adv_nq_index ( struct bnxt * bp,
u16 cnt )
static

Definition at line 2265 of file bnxt.c.

2266{
2267 u16 cons_id;
2268
2269 cons_id = bp->nq.cons_id + cnt;
2270 if ( cons_id >= bp->nq.ring_cnt ) {
2271 /* Toggle completion bit when the ring wraps. */
2272 bp->nq.completion_bit ^= 1;
2273 bp->nq.epoch ^= 1;
2274 cons_id = cons_id - bp->nq.ring_cnt;
2275 }
2276 bp->nq.cons_id = cons_id;
2277}

References bp, and u16.

Referenced by bnxt_service_nq().

◆ bnxt_rx_complete()

int bnxt_rx_complete ( struct net_device * dev,
struct rx_pkt_cmpl * rx )
static

Definition at line 491 of file bnxt.c.

493{
494 struct bnxt *bp = dev->priv;
495 struct rx_pkt_cmpl_hi *rx_cmp_hi;
496 u8 cmpl_bit = bp->cq.completion_bit;
497
498 if ( bp->cq.cons_id == ( bp->cq.ring_cnt - 1 ) ) {
499 rx_cmp_hi = ( struct rx_pkt_cmpl_hi * ) CQ_DMA_ADDR ( bp );
500 cmpl_bit ^= 0x1; /* Ring has wrapped. */
501 } else
502 rx_cmp_hi = ( struct rx_pkt_cmpl_hi * ) ( rx_cmp + 1 );
503
504 if ( ! ( ( rx_cmp_hi->errors_v2 & RX_PKT_CMPL_V2 ) ^ cmpl_bit ) ) {
505 bnxt_rx_process ( dev, bp, rx_cmp, rx_cmp_hi );
506 return SERVICE_NEXT_CQ_BD;
507 } else
509}
void bnxt_rx_process(struct net_device *dev, struct bnxt *bp, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi)
Definition bnxt.c:466
#define RX_PKT_CMPL_V2
Definition bnxt.h:670
u16 errors_v2
Definition bnxt.h:669

References bnxt_rx_process(), bp, CQ_DMA_ADDR, bnxt::dev, rx_pkt_cmpl_hi::errors_v2, NO_MORE_CQ_BD_TO_SERVICE, net_device::priv, RX_PKT_CMPL_V2, SERVICE_NEXT_CQ_BD, and u8.

Referenced by bnxt_service_cq().

◆ bnxt_link_evt()

void bnxt_link_evt ( struct bnxt * bp,
struct hwrm_async_event_cmpl * evt )

Definition at line 2279 of file bnxt.c.

2280{
2281 if ( evt->event_data1 & 0x01 )
2282 bp->link_status = STATUS_LINK_ACTIVE;
2283 else
2284 bp->link_status = STATUS_LINK_DOWN;
2285
2286 bnxt_set_link ( bp );
2287 dbg_link_status ( bp );
2288}
static void bnxt_set_link(struct bnxt *bp)
Definition bnxt.c:179
#define STATUS_LINK_DOWN
Definition bnxt.h:60
#define STATUS_LINK_ACTIVE
Definition bnxt.h:59
#define dbg_link_status(bp)
Definition bnxt_dbg.h:661

References bnxt_set_link(), bp, dbg_link_status, hwrm_async_event_cmpl::event_data1, STATUS_LINK_ACTIVE, and STATUS_LINK_DOWN.

Referenced by bnxt_service_cq(), and bnxt_service_nq().

◆ bnxt_is_pci_vf()

u8 bnxt_is_pci_vf ( struct pci_device * pdev)

Check if Virtual Function.

Definition at line 97 of file bnxt.c.

98{
99 if ( FLAG_TEST ( pdev->id->driver_data, BNXT_FLAG_PCI_VF ) ) {
100 return 1;
101 }
102 return 0;
103}
#define FLAG_TEST(f, b)
Definition bnxt.h:39
#define BNXT_FLAG_PCI_VF
Definition bnxt.h:47
unsigned long driver_data
Arbitrary driver data.
Definition pci.h:186
struct pci_device_id * id
Driver device ID.
Definition pci.h:251

References BNXT_FLAG_PCI_VF, pci_device_id::driver_data, FLAG_TEST, pci_device::id, and u8.

Referenced by bnxt_get_pci_info().

◆ bnxt_down_pci()

void bnxt_down_pci ( struct bnxt * bp)
static

Definition at line 105 of file bnxt.c.

106{
107 DBGP ( "%s\n", __func__ );
108 if ( bp->bar2 ) {
109 iounmap ( bp->bar2 );
110 bp->bar2 = NULL;
111 }
112 if ( bp->bar1 ) {
113 iounmap ( bp->bar1 );
114 bp->bar1 = NULL;
115 }
116 if ( bp->bar0 ) {
117 iounmap ( bp->bar0 );
118 bp->bar0 = NULL;
119 }
120}
#define NULL
NULL pointer (VOID *).
Definition Base.h:321
#define DBGP(...)
Definition compiler.h:557
void iounmap(volatile const void *io_addr)
Unmap I/O address.

References bp, DBGP, iounmap(), and NULL.

Referenced by bnxt_init_one(), and bnxt_remove_one().

◆ bnxt_pci_base()

void * bnxt_pci_base ( struct pci_device * pdev,
unsigned int reg )
static

Definition at line 122 of file bnxt.c.

123{
124 unsigned long reg_base, reg_size;
125
126 reg_base = pci_bar_start ( pdev, reg );
127 reg_size = pci_bar_size ( pdev, reg );
128 return pci_ioremap ( pdev, reg_base, reg_size );
129}
void * pci_ioremap(struct pci_device *pci, unsigned long bus_addr, size_t len)
Map PCI bus address as an I/O address.
static unsigned int unsigned int reg
Definition myson.h:162
unsigned long pci_bar_size(struct pci_device *pci, unsigned int reg)
Get the size of a PCI BAR.
Definition pci.c:178
unsigned long pci_bar_start(struct pci_device *pci, unsigned int reg)
Find the start of a PCI BAR.
Definition pci.c:111

References pci_bar_size(), pci_bar_start(), pci_ioremap(), and reg.

Referenced by bnxt_get_pci_info().

◆ bnxt_get_pci_info()

int bnxt_get_pci_info ( struct bnxt * bp)
static

Definition at line 131 of file bnxt.c.

132{
133 u16 cmd_reg = 0;
134
135 DBGP ( "%s\n", __func__ );
136 /* Disable Interrupt */
137 pci_read_config_word ( bp->pdev, PCI_COMMAND, &bp->cmd_reg );
138 cmd_reg = bp->cmd_reg | PCI_COMMAND_INTX_DISABLE;
139 pci_write_config_word ( bp->pdev, PCI_COMMAND, cmd_reg );
140 pci_read_config_word ( bp->pdev, PCI_COMMAND, &cmd_reg );
141
142 /* SSVID */
144 &bp->subsystem_vendor );
145
146 /* SSDID */
148 &bp->subsystem_device );
149
150 /* Function Number */
151 pci_read_config_byte ( bp->pdev, PCICFG_ME_REGISTER, &bp->pf_num);
152
153 /* Get Bar Address */
154 bp->bar0 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_0 );
155 bp->bar1 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_2 );
156 bp->bar2 = bnxt_pci_base ( bp->pdev, PCI_BASE_ADDRESS_4 );
157
158 /* Virtual function */
159 bp->vf = bnxt_is_pci_vf ( bp->pdev );
160
161 dbg_pci ( bp, __func__, cmd_reg );
162 return STATUS_SUCCESS;
163}
u8 bnxt_is_pci_vf(struct pci_device *pdev)
Check if Virtual Function.
Definition bnxt.c:97
static void * bnxt_pci_base(struct pci_device *pdev, unsigned int reg)
Definition bnxt.c:122
#define PCICFG_ME_REGISTER
Definition bnxt.h:125
#define STATUS_SUCCESS
Definition bnxt.h:55
#define dbg_pci(bp, func, creg)
Definition bnxt_dbg.h:140
int pci_read_config_word(struct pci_device *pci, unsigned int where, uint16_t *value)
Read 16-bit word from PCI configuration space.
int pci_write_config_word(struct pci_device *pci, unsigned int where, uint16_t value)
Write 16-bit word to PCI configuration space.
int pci_read_config_byte(struct pci_device *pci, unsigned int where, uint8_t *value)
Read byte from PCI configuration space.
#define PCI_SUBSYSTEM_ID
PCI subsystem ID.
Definition pci.h:79
#define PCI_BASE_ADDRESS_2
Definition pci.h:65
#define PCI_COMMAND_INTX_DISABLE
Interrupt disable.
Definition pci.h:33
#define PCI_BASE_ADDRESS_0
Definition pci.h:63
#define PCI_COMMAND
PCI command.
Definition pci.h:26
#define PCI_BASE_ADDRESS_4
Definition pci.h:67
#define PCI_SUBSYSTEM_VENDOR_ID
PCI subsystem vendor ID.
Definition pci.h:76

References bnxt_is_pci_vf(), bnxt_pci_base(), bp, dbg_pci, DBGP, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_2, PCI_BASE_ADDRESS_4, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, pci_read_config_byte(), pci_read_config_word(), PCI_SUBSYSTEM_ID, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config_word(), PCICFG_ME_REGISTER, STATUS_SUCCESS, and u16.

Referenced by bnxt_init_one().

◆ bnxt_get_device_address()

int bnxt_get_device_address ( struct bnxt * bp)
static

Definition at line 165 of file bnxt.c.

166{
167 struct net_device *dev = bp->dev;
168
169 DBGP ( "%s\n", __func__ );
170 memcpy ( &dev->hw_addr[0], ( char * ) &bp->mac_addr[0], ETH_ALEN );
171 if ( !is_valid_ether_addr ( &dev->hw_addr[0] ) ) {
172 DBGP ( "- %s ( ): Failed\n", __func__ );
173 return -EINVAL;
174 }
175
176 return STATUS_SUCCESS;
177}
static int is_valid_ether_addr(const void *addr)
Check if Ethernet address is valid.
Definition ethernet.h:78
#define EINVAL
Invalid argument.
Definition errno.h:472
#define ETH_ALEN
Definition if_ether.h:9
void * memcpy(void *dest, const void *src, size_t len) __nonnull
A network device.
Definition netdevice.h:353
struct device * dev
Underlying hardware device.
Definition netdevice.h:365

References bp, DBGP, net_device::dev, EINVAL, ETH_ALEN, is_valid_ether_addr(), memcpy(), and STATUS_SUCCESS.

◆ bnxt_set_link()

void bnxt_set_link ( struct bnxt * bp)
static

Definition at line 179 of file bnxt.c.

180{
181 if ( bp->link_status == STATUS_LINK_ACTIVE )
182 netdev_link_up ( bp->dev );
183 else
184 netdev_link_down ( bp->dev );
185}
void netdev_link_down(struct net_device *netdev)
Mark network device as having link down.
Definition netdevice.c:231
static void netdev_link_up(struct net_device *netdev)
Mark network device as having link up.
Definition netdevice.h:792

References bp, netdev_link_down(), netdev_link_up(), and STATUS_LINK_ACTIVE.

Referenced by bnxt_get_phy_link(), bnxt_init_one(), bnxt_link_evt(), bnxt_link_speed_chg_evt(), bnxt_link_speed_evt(), and bnxt_port_phy_chg_evt().

◆ dev_p5_db()

void dev_p5_db ( struct bnxt * bp,
u32 idx,
u32 xid,
u32 flag )
static

Definition at line 187 of file bnxt.c.

188{
189 void *off;
190 u64 val;
191
192 if ( bp->vf )
193 off = ( void * ) ( bp->bar1 + DB_OFFSET_VF );
194 else
195 off = ( void * ) ( bp->bar1 + DB_OFFSET_PF );
196
197 val = ( ( u64 )DBC_MSG_XID ( xid, flag ) << 32 ) |
198 ( u64 )DBC_MSG_IDX ( idx );
199 writeq ( val, off );
200}
uint32_t flag
Flag number.
Definition aqc1xx.h:2
#define DB_OFFSET_VF
Definition bnxt.h:196
#define DB_OFFSET_PF
Definition bnxt.h:195
#define DBC_MSG_XID(xid, flg)
Definition bnxt.h:199
#define DBC_MSG_IDX(idx)
Definition bnxt.h:197
#define writeq(data, io_addr)
Definition io.h:273
void __asmcall int val
Definition setjmp.h:12
uint64_t u64
Definition stdint.h:26

References bp, DB_OFFSET_PF, DB_OFFSET_VF, DBC_MSG_IDX, DBC_MSG_XID, flag, u32, val, and writeq.

Referenced by bnxt_db_cq(), bnxt_db_nq(), bnxt_db_rx(), and bnxt_db_tx().

◆ dev_p7_db()

void dev_p7_db ( struct bnxt * bp,
u32 idx,
u32 xid,
u32 flag,
u32 epoch,
u32 toggle )
static

Definition at line 202 of file bnxt.c.

203{
204 void *off;
205 u64 val;
206
207 off = ( void * ) ( bp->bar1 );
208
209 val = ( ( u64 ) DBC_MSG_XID ( xid, flag ) << 32 ) |
210 ( u64 ) DBC_MSG_IDX ( idx ) |
211 ( u64 ) DBC_MSG_EPCH ( epoch ) |
212 ( u64 ) DBC_MSG_TOGGLE ( toggle );
213 writeq ( val, off );
214}
#define DBC_MSG_EPCH(idx)
Definition bnxt.h:202
#define DBC_MSG_TOGGLE(idx)
Definition bnxt.h:204

References bp, DBC_MSG_EPCH, DBC_MSG_IDX, DBC_MSG_TOGGLE, DBC_MSG_XID, flag, u32, val, and writeq.

Referenced by bnxt_db_cq(), bnxt_db_nq(), bnxt_db_rx(), and bnxt_db_tx().

◆ bnxt_db_nq()

void bnxt_db_nq ( struct bnxt * bp)
static

Definition at line 216 of file bnxt.c.

217{
218 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
219 dev_p7_db ( bp, ( u32 ) bp->nq.cons_id,
220 ( u32 ) bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM,
221 ( u32 ) bp->nq.epoch, 0 );
222 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
223 dev_p5_db ( bp, ( u32 ) bp->nq.cons_id,
224 ( u32 ) bp->nq_ring_id, DBC_DBC_TYPE_NQ_ARM );
225 else
226 writel ( CMPL_DOORBELL_KEY_CMPL, ( bp->bar1 + 0 ) );
227}
static void dev_p7_db(struct bnxt *bp, u32 idx, u32 xid, u32 flag, u32 epoch, u32 toggle)
Definition bnxt.c:202
static void dev_p5_db(struct bnxt *bp, u32 idx, u32 xid, u32 flag)
Definition bnxt.c:187
#define BNXT_FLAG_IS_CHIP_P5
Definition bnxt.h:49
#define DBC_DBC_TYPE_NQ_ARM
Definition bnxt.h:443
#define BNXT_FLAG_IS_CHIP_P7
Definition bnxt.h:51
#define CMPL_DOORBELL_KEY_CMPL
Definition bnxt.h:406
#define writel
Definition w89c840.c:160

References BNXT_FLAG_IS_CHIP_P5, BNXT_FLAG_IS_CHIP_P7, bp, CMPL_DOORBELL_KEY_CMPL, DBC_DBC_TYPE_NQ_ARM, dev_p5_db(), dev_p7_db(), FLAG_TEST, u32, and writel.

Referenced by bnxt_service_nq().

◆ bnxt_db_cq()

void bnxt_db_cq ( struct bnxt * bp)
static

Definition at line 229 of file bnxt.c.

230{
231 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
232 dev_p7_db ( bp, ( u32 ) bp->cq.cons_id,
233 ( u32 ) bp->cq_ring_id, DBC_DBC_TYPE_CQ,
234 ( u32 ) bp->cq.epoch, ( u32 )bp->nq.toggle );
235 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
236 dev_p5_db ( bp, ( u32 ) bp->cq.cons_id,
237 ( u32 ) bp->cq_ring_id, DBC_DBC_TYPE_CQ);
238 else
239 writel ( CQ_DOORBELL_KEY_IDX ( bp->cq.cons_id ),
240 ( bp->bar1 + 0 ) );
241}
#define CQ_DOORBELL_KEY_IDX(a)
Definition bnxt.h:1069
#define DBC_DBC_TYPE_CQ
Definition bnxt.h:436

References BNXT_FLAG_IS_CHIP_P5, BNXT_FLAG_IS_CHIP_P7, bp, CQ_DOORBELL_KEY_IDX, DBC_DBC_TYPE_CQ, dev_p5_db(), dev_p7_db(), FLAG_TEST, u32, and writel.

Referenced by bnxt_service_cq().

◆ bnxt_db_rx()

void bnxt_db_rx ( struct bnxt * bp,
u32 idx )
static

Definition at line 243 of file bnxt.c.

244{
245 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
246 dev_p7_db ( bp, idx, ( u32 ) bp->rx_ring_id, DBC_DBC_TYPE_SRQ,
247 ( u32 ) bp->rx.epoch, 0 );
248 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
249 dev_p5_db ( bp, idx, ( u32 ) bp->rx_ring_id, DBC_DBC_TYPE_SRQ );
250 else
251 writel ( RX_DOORBELL_KEY_RX | idx, ( bp->bar1 + 0 ) );
252}
#define DBC_DBC_TYPE_SRQ
Definition bnxt.h:434
#define RX_DOORBELL_KEY_RX
Definition bnxt.h:394

References BNXT_FLAG_IS_CHIP_P5, BNXT_FLAG_IS_CHIP_P7, bp, DBC_DBC_TYPE_SRQ, dev_p5_db(), dev_p7_db(), FLAG_TEST, RX_DOORBELL_KEY_RX, u32, and writel.

Referenced by bnxt_post_rx_buffers().

◆ bnxt_db_tx()

void bnxt_db_tx ( struct bnxt * bp,
u32 idx )
static

Definition at line 254 of file bnxt.c.

255{
256 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7 ) )
257 dev_p7_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ,
258 ( u32 )bp->tx.epoch, 0 );
259 else if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5 ) )
260 dev_p5_db ( bp, idx, ( u32 )bp->tx_ring_id, DBC_DBC_TYPE_SQ );
261 else
262 writel ( TX_DOORBELL_KEY_TX | idx, ( bp->bar1 + 0 ) );
263}
#define DBC_DBC_TYPE_SQ
Definition bnxt.h:432
#define TX_DOORBELL_KEY_TX
Definition bnxt.h:384

References BNXT_FLAG_IS_CHIP_P5, BNXT_FLAG_IS_CHIP_P7, bp, DBC_DBC_TYPE_SQ, dev_p5_db(), dev_p7_db(), FLAG_TEST, TX_DOORBELL_KEY_TX, u32, and writel.

Referenced by bnxt_tx().

◆ bnxt_add_vlan()

void bnxt_add_vlan ( struct io_buffer * iob,
u16 vlan )

Definition at line 265 of file bnxt.c.

266{
267 char *src = ( char * )iob->data;
268 u16 len = iob_len ( iob );
269
270 memmove ( ( char * ) &src[MAC_HDR_SIZE + VLAN_HDR_SIZE],
271 ( char * ) &src[MAC_HDR_SIZE],
272 ( len - MAC_HDR_SIZE ) );
273
274 * ( u16 * ) ( &src[MAC_HDR_SIZE] ) = BYTE_SWAP_S ( ETHERTYPE_VLAN );
275 * ( u16 * ) ( &src[MAC_HDR_SIZE + 2] ) = BYTE_SWAP_S ( vlan );
276 iob_put ( iob, VLAN_HDR_SIZE );
277}
static const void * src
Definition string.h:48
#define ETHERTYPE_VLAN
Definition bnxt.h:191
#define VLAN_HDR_SIZE
Definition bnxt.h:190
#define BYTE_SWAP_S(w)
Definition bnxt.h:192
#define MAC_HDR_SIZE
Definition bnxt.h:189
ring len
Length.
Definition dwmac.h:226
void * memmove(void *dest, const void *src, size_t len) __nonnull
#define iob_put(iobuf, len)
Definition iobuf.h:185

References BYTE_SWAP_S, io_buffer::data, ETHERTYPE_VLAN, iob_len(), iob_put, len, MAC_HDR_SIZE, memmove(), src, u16, and VLAN_HDR_SIZE.

Referenced by bnxt_tx_adjust_pkt().

◆ bnxt_get_pkt_vlan()

u16 bnxt_get_pkt_vlan ( char * src)
static

Definition at line 279 of file bnxt.c.

280{
281 if ( * ( ( u16 * ) &src[MAC_HDR_SIZE] ) == BYTE_SWAP_S ( ETHERTYPE_VLAN ) )
282 return BYTE_SWAP_S ( * ( ( u16 * ) &src[MAC_HDR_SIZE + 2] ) );
283 return 0;
284}

References BYTE_SWAP_S, ETHERTYPE_VLAN, MAC_HDR_SIZE, src, and u16.

Referenced by bnxt_tx_adjust_pkt().

◆ bnxt_tx_avail()

u32 bnxt_tx_avail ( struct bnxt * bp)
inlinestatic

Definition at line 286 of file bnxt.c.

287{
288 u32 avail;
289 u32 use;
290
291 barrier ( );
292 avail = TX_AVAIL ( bp->tx.ring_cnt );
293 use = TX_IN_USE ( bp->tx.prod_id, bp->tx.cons_id, bp->tx.ring_cnt );
294 dbg_tx_avail ( bp, avail, use );
295 return ( avail-use );
296}
#define TX_IN_USE(a, b, c)
Definition bnxt.h:177
#define TX_AVAIL(r)
Definition bnxt.h:176
#define dbg_tx_avail(bp, a, u)
Definition bnxt_dbg.h:563
#define barrier()
Optimisation barrier.
Definition compiler.h:658

References barrier, bp, dbg_tx_avail, TX_AVAIL, TX_IN_USE, and u32.

Referenced by bnxt_tx().

◆ bnxt_set_txq()

void bnxt_set_txq ( struct bnxt * bp,
int entry,
physaddr_t mapping,
int len )

Definition at line 298 of file bnxt.c.

299{
300 struct tx_bd_short *prod_bd;
301
302 prod_bd = ( struct tx_bd_short * ) BD_NOW ( bp->tx.bd_virt,
303 entry, sizeof ( struct tx_bd_short ) );
304 if ( len < 512 )
306 else if ( len < 1024 )
308 else if ( len < 2048 )
310 else
312 prod_bd->flags_type |= TX_BD_FLAGS;
313 prod_bd->dma = mapping;
314 prod_bd->len = len;
315 prod_bd->opaque = ( u32 )entry;
316}
#define TX_BD_FLAGS
Definition bnxt.h:1073
#define TX_BD_SHORT_FLAGS_LHINT_GTE2K
Definition bnxt.h:468
#define TX_BD_SHORT_FLAGS_LHINT_LT512
Definition bnxt.h:465
#define TX_BD_SHORT_FLAGS_LHINT_LT2K
Definition bnxt.h:467
#define TX_BD_SHORT_FLAGS_LHINT_LT1K
Definition bnxt.h:466
physaddr_t dma
Definition bnxt.h:473
u32 opaque
Definition bnxt.h:472
u16 len
Definition bnxt.h:471
u16 flags_type
Definition bnxt.h:452

References BD_NOW, bp, tx_bd_short::dma, tx_bd_short::flags_type, len, tx_bd_short::len, tx_bd_short::opaque, TX_BD_FLAGS, TX_BD_SHORT_FLAGS_LHINT_GTE2K, TX_BD_SHORT_FLAGS_LHINT_LT1K, TX_BD_SHORT_FLAGS_LHINT_LT2K, TX_BD_SHORT_FLAGS_LHINT_LT512, and u32.

Referenced by bnxt_tx().

◆ bnxt_free_rx_iob()

int bnxt_free_rx_iob ( struct bnxt * bp)

Definition at line 331 of file bnxt.c.

332{
333 unsigned int i;
334
335 DBGP ( "%s\n", __func__ );
336 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RX_IOB ) ) )
337 return STATUS_SUCCESS;
338
339 for ( i = 0; i < bp->rx.buf_cnt; i++ ) {
340 if ( bp->rx.iob[i] ) {
341 free_rx_iob ( bp->rx.iob[i] );
342 bp->rx.iob[i] = NULL;
343 }
344 }
345 bp->rx.iob_cnt = 0;
346
347 FLAG_RESET ( bp->flag_hwrm, VALID_RX_IOB );
348 return STATUS_SUCCESS;
349}
#define FLAG_RESET(f, b)
Definition bnxt.h:40
#define VALID_RX_IOB
Definition bnxt.h:906
void free_rx_iob(struct io_buffer *iobuf)
Unmap and free I/O buffer for receive DMA.
Definition iobuf.c:215

References bp, DBGP, FLAG_RESET, FLAG_TEST, free_rx_iob(), NULL, STATUS_SUCCESS, and VALID_RX_IOB.

Referenced by bnxt_er_task().

◆ bnxt_set_rx_desc()

void bnxt_set_rx_desc ( u8 * buf,
struct io_buffer * iob,
u16 cid,
u32 idx )
static

Definition at line 351 of file bnxt.c.

353{
354 struct rx_prod_pkt_bd *desc;
355 u16 off = cid * sizeof ( struct rx_prod_pkt_bd );
356
357 desc = ( struct rx_prod_pkt_bd * ) &buf[off];
360 desc->opaque = idx;
361 desc->dma = iob_dma ( iob );
362}
#define MAX_ETHERNET_PACKET_BUFFER_SIZE
Definition bnxt.h:140
#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
Definition bnxt.h:870
struct ena_llq_option desc
Descriptor counts.
Definition ena.h:9
static __always_inline physaddr_t iob_dma(struct io_buffer *iobuf)
Get I/O buffer DMA address.
Definition iobuf.h:328

References desc, iob_dma(), MAX_ETHERNET_PACKET_BUFFER_SIZE, RX_PROD_PKT_BD_TYPE_RX_PROD_PKT, u16, u32, and u8.

Referenced by bnxt_alloc_rx_iob().

◆ bnxt_alloc_rx_iob()

int bnxt_alloc_rx_iob ( struct bnxt * bp,
u16 cons_id,
u16 iob_idx )
static

Definition at line 364 of file bnxt.c.

365{
366 struct io_buffer *iob;
367
368 iob = alloc_rx_iob ( BNXT_RX_STD_DMA_SZ, bp->dma );
369 if ( !iob ) {
370 DBGP ( "- %s ( ): alloc_iob Failed\n", __func__ );
371 return -ENOMEM;
372 }
373
374 dbg_alloc_rx_iob ( iob, iob_idx, cons_id );
375 bnxt_set_rx_desc ( ( u8 * )bp->rx.bd_virt, iob, cons_id,
376 ( u32 ) iob_idx );
377 bp->rx.iob[iob_idx] = iob;
378 return 0;
379}
static void bnxt_set_rx_desc(u8 *buf, struct io_buffer *iob, u16 cid, u32 idx)
Definition bnxt.c:351
#define BNXT_RX_STD_DMA_SZ
Definition bnxt.h:160
#define dbg_alloc_rx_iob(iob, id, cid)
Definition bnxt_dbg.h:462
#define ENOMEM
Not enough space.
Definition errno.h:578
struct io_buffer * alloc_rx_iob(size_t len, struct dma_device *dma)
Allocate and map I/O buffer for receive DMA.
Definition iobuf.c:188

References alloc_rx_iob(), BNXT_RX_STD_DMA_SZ, bnxt_set_rx_desc(), bp, dbg_alloc_rx_iob, DBGP, ENOMEM, u16, u32, and u8.

Referenced by bnxt_post_rx_buffers().

◆ bnxt_post_rx_buffers()

int bnxt_post_rx_buffers ( struct bnxt * bp)

Definition at line 381 of file bnxt.c.

382{
383 u16 cons_id = ( bp->rx.cons_id % bp->rx.ring_cnt );
384 u16 iob_idx;
385
386 while ( bp->rx.iob_cnt < bp->rx.buf_cnt ) {
387 iob_idx = ( cons_id % bp->rx.buf_cnt );
388 if ( !bp->rx.iob[iob_idx] ) {
389 if ( bnxt_alloc_rx_iob ( bp, cons_id, iob_idx ) < 0 ) {
390 dbg_alloc_rx_iob_fail ( iob_idx, cons_id );
391 break;
392 }
393 }
394 cons_id = NEXT_IDX ( cons_id, bp->rx.ring_cnt );
395 /* If the ring has wrapped, flip the epoch bit */
396 if ( iob_idx > cons_id )
397 bp->rx.epoch ^= 1;
398 bp->rx.iob_cnt++;
399 }
400
401 if ( cons_id != bp->rx.cons_id ) {
402 dbg_rx_cid ( bp->rx.cons_id, cons_id );
403 bp->rx.cons_id = cons_id;
404 bnxt_db_rx ( bp, ( u32 )cons_id );
405 }
406
407 FLAG_SET ( bp->flag_hwrm, VALID_RX_IOB );
408 return STATUS_SUCCESS;
409}
static int bnxt_alloc_rx_iob(struct bnxt *bp, u16 cons_id, u16 iob_idx)
Definition bnxt.c:364
static void bnxt_db_rx(struct bnxt *bp, u32 idx)
Definition bnxt.c:243
#define FLAG_SET(f, b)
Definition bnxt.h:38
#define dbg_rx_cid(idx, cid)
Definition bnxt_dbg.h:463
#define dbg_alloc_rx_iob_fail(iob_idx, cons_id)
Definition bnxt_dbg.h:464

References bnxt_alloc_rx_iob(), bnxt_db_rx(), bp, dbg_alloc_rx_iob_fail, dbg_rx_cid, FLAG_SET, NEXT_IDX, STATUS_SUCCESS, u16, u32, and VALID_RX_IOB.

Referenced by bnxt_rx_process().

◆ bnxt_rx_drop()

u8 bnxt_rx_drop ( struct bnxt * bp,
struct io_buffer * iob,
struct rx_pkt_cmpl * rx_cmp,
struct rx_pkt_cmpl_hi * rx_cmp_hi,
u16 rx_len )

Definition at line 411 of file bnxt.c.

414{
415 struct rx_pkt_v3_cmpl *rx_cmp_v3 = ( struct rx_pkt_v3_cmpl * ) rx_cmp;
416 struct rx_pkt_v3_cmpl_hi *rx_cmp_hi_v3 = ( struct rx_pkt_v3_cmpl_hi * ) rx_cmp_hi;
417 u8 *rx_buf = ( u8 * ) iob->data;
418 u16 err_flags;
419 u8 ignore_chksum_err = 0;
420 int i;
421
422 if ( ( rx_cmp_v3->flags_type & RX_PKT_V3_CMPL_TYPE_MASK ) ==
424 err_flags = rx_cmp_hi_v3->errors_v2 >> RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT;
425 } else
426 err_flags = rx_cmp_hi->errors_v2 >> RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT;
427 if ( rx_cmp_hi->errors_v2 == 0x20 || rx_cmp_hi->errors_v2 == 0x21 )
428 ignore_chksum_err = 1;
429
430 if ( err_flags && !ignore_chksum_err ) {
431 bp->rx.drop_err++;
432 return 1;
433 }
434
435 for ( i = 0; i < 6; i++ ) {
436 if ( rx_buf[6 + i] != bp->mac_addr[i] )
437 break;
438 }
439
440 /* Drop the loopback packets */
441 if ( i == 6 ) {
442 bp->rx.drop_lb++;
443 return 2;
444 }
445
446 iob_put ( iob, rx_len );
447
448 bp->rx.good++;
449 return 0;
450}
#define RX_PKT_V3_CMPL_TYPE_RX_L2_V3
Definition bnxt.h:726
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT
Definition bnxt.h:674
#define RX_PKT_V3_CMPL_TYPE_MASK
Definition bnxt.h:718
#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT
Definition bnxt.h:822

References bp, io_buffer::data, rx_pkt_cmpl_hi::errors_v2, rx_pkt_v3_cmpl_hi::errors_v2, rx_pkt_v3_cmpl::flags_type, iob_put, RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT, RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_SFT, RX_PKT_V3_CMPL_TYPE_MASK, RX_PKT_V3_CMPL_TYPE_RX_L2_V3, u16, and u8.

Referenced by bnxt_rx_process().

◆ bnxt_rx_process()

void bnxt_rx_process ( struct net_device * dev,
struct bnxt * bp,
struct rx_pkt_cmpl * rx_cmp,
struct rx_pkt_cmpl_hi * rx_cmp_hi )

Definition at line 466 of file bnxt.c.

469{
470 u32 desc_idx = rx_cmp->opaque & ( NUM_RX_BUFFERS - 1 );
471 struct io_buffer *iob = bp->rx.iob[desc_idx];
472 u8 drop;
473
474 dump_rx_bd ( rx_cmp, rx_cmp_hi, desc_idx );
475 assert ( iob );
476 drop = bnxt_rx_drop ( bp, iob, rx_cmp, rx_cmp_hi, rx_cmp->len );
477 dbg_rxp ( iob->data, rx_cmp->len, drop );
478 if ( drop )
479 netdev_rx_err ( dev, iob, -EINVAL );
480 else
481 netdev_rx ( dev, iob );
482
483 bp->rx.cnt++;
484 bp->rx.iob[desc_idx] = NULL;
485 bp->rx.iob_cnt--;
487 bnxt_adv_cq_index ( bp, 2 ); /* Rx completion is 2 entries. */
488 dbg_rx_stat ( bp );
489}
#define assert(condition)
Assert a condition at run-time.
Definition assert.h:61
int bnxt_post_rx_buffers(struct bnxt *bp)
Definition bnxt.c:381
u8 bnxt_rx_drop(struct bnxt *bp, struct io_buffer *iob, struct rx_pkt_cmpl *rx_cmp, struct rx_pkt_cmpl_hi *rx_cmp_hi, u16 rx_len)
Definition bnxt.c:411
#define NUM_RX_BUFFERS
Definition bnxt.h:146
#define dbg_rx_stat(bp)
Definition bnxt_dbg.h:466
#define dbg_rxp(iob, rx_len, drop)
Definition bnxt_dbg.h:465
#define dump_rx_bd(rx_cmp, rx_cmp_hi, desc_idx)
Definition bnxt_dbg.h:461
void netdev_rx(struct net_device *netdev, struct io_buffer *iobuf)
Add packet to receive queue.
Definition netdevice.c:549
void netdev_rx_err(struct net_device *netdev, struct io_buffer *iobuf, int rc)
Discard received packet.
Definition netdevice.c:587
u32 opaque
Definition bnxt.h:635
u16 len
Definition bnxt.h:634

References assert, bnxt_adv_cq_index(), bnxt_post_rx_buffers(), bnxt_rx_drop(), bp, io_buffer::data, dbg_rx_stat, dbg_rxp, dump_rx_bd, EINVAL, rx_pkt_cmpl::len, netdev_rx(), netdev_rx_err(), NULL, NUM_RX_BUFFERS, rx_pkt_cmpl::opaque, u32, and u8.

Referenced by bnxt_rx_complete().

◆ bnxt_mm_init_hwrm()

void bnxt_mm_init_hwrm ( struct bnxt * bp,
const char * func )

Definition at line 511 of file bnxt.c.

512{
513 DBGP ( "%s\n", __func__ );
514 memset ( bp->hwrm_addr_req, 0, REQ_BUFFER_SIZE );
515 memset ( bp->hwrm_addr_resp, 0, RESP_BUFFER_SIZE );
516 memset ( bp->hwrm_addr_dma, 0, DMA_BUFFER_SIZE );
517 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
518 bp->hwrm_cmd_timeout = HWRM_CMD_DEFAULT_TIMEOUT;
519 dbg_mem ( bp, func );
520}
#define HWRM_CMD_DEFAULT_TIMEOUT
Definition bnxt.h:134
#define RESP_BUFFER_SIZE
Definition bnxt.h:157
#define REQ_BUFFER_SIZE
Definition bnxt.h:156
#define DMA_BUFFER_SIZE
Definition bnxt.h:158
#define dbg_mem(bp, func)
Definition bnxt_dbg.h:175
#define HWRM_MAX_REQ_LEN
Definition bnxt_hsi.h:364
void * memset(void *dest, int character, size_t len) __nonnull

References bp, dbg_mem, DBGP, DMA_BUFFER_SIZE, HWRM_CMD_DEFAULT_TIMEOUT, HWRM_MAX_REQ_LEN, memset(), REQ_BUFFER_SIZE, and RESP_BUFFER_SIZE.

Referenced by bnxt_alloc_hwrm_mem().

◆ bnxt_mm_init_rings()

void bnxt_mm_init_rings ( struct bnxt * bp,
const char * func )

Definition at line 522 of file bnxt.c.

523{
524 DBGP ( "%s\n", __func__ );
525 memset ( bp->tx.bd_virt, 0, TX_RING_BUFFER_SIZE );
526 memset ( bp->rx.bd_virt, 0, RX_RING_BUFFER_SIZE );
527 memset ( bp->cq.bd_virt, 0, CQ_RING_BUFFER_SIZE );
528 memset ( bp->nq.bd_virt, 0, NQ_RING_BUFFER_SIZE );
529
530 bp->link_status = STATUS_LINK_DOWN;
531 bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
533 bp->nq.ring_cnt = MAX_NQ_DESC_CNT;
534 bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
535 bp->tx.ring_cnt = MAX_TX_DESC_CNT;
536 bp->rx.ring_cnt = MAX_RX_DESC_CNT;
537 bp->rx.buf_cnt = NUM_RX_BUFFERS;
538 dbg_mem ( bp, func );
539}
#define MAX_TX_DESC_CNT
Definition bnx2.h:3881
#define MAX_RX_DESC_CNT
Definition bnx2.h:3885
#define MAX_CQ_DESC_CNT
Definition bnxt.h:149
#define TX_RING_BUFFER_SIZE
Definition bnxt.h:150
#define RX_RING_BUFFER_SIZE
Definition bnxt.h:151
#define NQ_RING_BUFFER_SIZE
Definition bnxt.h:173
#define MAX_NQ_DESC_CNT
Definition bnxt.h:172
#define LINK_DEFAULT_TIMEOUT
Definition bnxt.h:166
#define CQ_RING_BUFFER_SIZE
Definition bnxt.h:153

References bp, CQ_RING_BUFFER_SIZE, dbg_mem, DBGP, LINK_DEFAULT_TIMEOUT, MAX_CQ_DESC_CNT, MAX_ETHERNET_PACKET_BUFFER_SIZE, MAX_NQ_DESC_CNT, MAX_RX_DESC_CNT, MAX_TX_DESC_CNT, memset(), NQ_RING_BUFFER_SIZE, NUM_RX_BUFFERS, RX_RING_BUFFER_SIZE, STATUS_LINK_DOWN, and TX_RING_BUFFER_SIZE.

Referenced by bnxt_alloc_rings_mem().

◆ bnxt_mm_nic()

void bnxt_mm_nic ( struct bnxt * bp)

Definition at line 541 of file bnxt.c.

542{
543 DBGP ( "%s\n", __func__ );
544 memset ( bp->cq.bd_virt, 0, CQ_RING_BUFFER_SIZE );
545 memset ( bp->tx.bd_virt, 0, TX_RING_BUFFER_SIZE );
546 memset ( bp->rx.bd_virt, 0, RX_RING_BUFFER_SIZE );
547 memset ( bp->nq.bd_virt, 0, NQ_RING_BUFFER_SIZE );
548 bp->nq.cons_id = 0;
549 bp->nq.completion_bit = 0x1;
550 bp->nq.epoch = 0;
551 bp->nq.toggle = 0;
552 bp->cq.cons_id = 0;
553 bp->cq.completion_bit = 0x1;
554 bp->cq.epoch = 0;
555 bp->tx.prod_id = 0;
556 bp->tx.cons_id = 0;
557 bp->tx.epoch = 0;
558 bp->rx.cons_id = 0;
559 bp->rx.iob_cnt = 0;
560 bp->rx.epoch = 0;
561
563 bp->nq.ring_cnt = MAX_NQ_DESC_CNT;
564 bp->cq.ring_cnt = MAX_CQ_DESC_CNT;
565 bp->tx.ring_cnt = MAX_TX_DESC_CNT;
566 bp->rx.ring_cnt = MAX_RX_DESC_CNT;
567 bp->rx.buf_cnt = NUM_RX_BUFFERS;
568}

References bp, CQ_RING_BUFFER_SIZE, DBGP, MAX_CQ_DESC_CNT, MAX_ETHERNET_PACKET_BUFFER_SIZE, MAX_NQ_DESC_CNT, MAX_RX_DESC_CNT, MAX_TX_DESC_CNT, memset(), NQ_RING_BUFFER_SIZE, NUM_RX_BUFFERS, RX_RING_BUFFER_SIZE, and TX_RING_BUFFER_SIZE.

Referenced by bnxt_er_task(), and bnxt_open().

◆ bnxt_free_rings_mem()

void bnxt_free_rings_mem ( struct bnxt * bp)

Definition at line 570 of file bnxt.c.

571{
572 DBGP ( "%s\n", __func__ );
573 if ( bp->nq.bd_virt ) {
574 dma_free ( &bp->nq_mapping, bp->nq.bd_virt, NQ_RING_BUFFER_SIZE );
575 bp->nq.bd_virt = NULL;
576 }
577
578 if ( bp->cq.bd_virt ) {
579 dma_free ( &bp->cq_mapping, bp->cq.bd_virt, CQ_RING_BUFFER_SIZE );
580 bp->cq.bd_virt = NULL;
581 }
582
583 if ( bp->rx.bd_virt ) {
584 dma_free ( &bp->rx_mapping, bp->rx.bd_virt, RX_RING_BUFFER_SIZE );
585 bp->rx.bd_virt = NULL;
586 }
587
588 if ( bp->tx.bd_virt ) {
589 dma_free ( &bp->tx_mapping, bp->tx.bd_virt, TX_RING_BUFFER_SIZE );
590 bp->tx.bd_virt = NULL;
591 }
592
593 DBGP ( "- %s ( ): - Done\n", __func__ );
594}
void dma_free(struct dma_mapping *map, void *addr, size_t len)
Unmap and free DMA-coherent buffer.

References bp, CQ_RING_BUFFER_SIZE, DBGP, dma_free(), NQ_RING_BUFFER_SIZE, NULL, RX_RING_BUFFER_SIZE, and TX_RING_BUFFER_SIZE.

Referenced by bnxt_alloc_rings_mem(), bnxt_close(), and bnxt_open().

◆ bnxt_free_hwrm_mem()

void bnxt_free_hwrm_mem ( struct bnxt * bp)

Definition at line 596 of file bnxt.c.

597{
598 DBGP ( "%s\n", __func__ );
599 if ( bp->hwrm_addr_dma ) {
600 dma_free ( &bp->dma_mapped, bp->hwrm_addr_dma, DMA_BUFFER_SIZE );
601 bp->hwrm_addr_dma = NULL;
602 }
603
604 if ( bp->hwrm_addr_resp ) {
605 dma_free ( &bp->resp_mapping, bp->hwrm_addr_resp, RESP_BUFFER_SIZE );
606 bp->hwrm_addr_resp = NULL;
607 }
608
609 if ( bp->hwrm_addr_req ) {
610 dma_free ( &bp->req_mapping, bp->hwrm_addr_req, REQ_BUFFER_SIZE );
611 bp->hwrm_addr_req = NULL;
612 }
613 DBGP ( "- %s ( ): - Done\n", __func__ );
614}

References bp, DBGP, DMA_BUFFER_SIZE, dma_free(), NULL, REQ_BUFFER_SIZE, and RESP_BUFFER_SIZE.

Referenced by bnxt_alloc_hwrm_mem(), bnxt_init_one(), and bnxt_remove_one().

◆ bnxt_alloc_hwrm_mem()

int bnxt_alloc_hwrm_mem ( struct bnxt * bp)

Definition at line 616 of file bnxt.c.

617{
618 DBGP ( "%s\n", __func__ );
619 bp->hwrm_addr_req = dma_alloc ( bp->dma, &bp->req_mapping,
621 bp->hwrm_addr_resp = dma_alloc ( bp->dma, &bp->resp_mapping,
623 bp->hwrm_addr_dma = dma_alloc ( bp->dma, &bp->dma_mapped,
625
626 if ( bp->hwrm_addr_req && bp->hwrm_addr_resp && bp->hwrm_addr_dma) {
627 bnxt_mm_init_hwrm ( bp, __func__ );
628 return STATUS_SUCCESS;
629 }
630
631 DBGP ( "- %s ( ): Failed\n", __func__ );
633 return -ENOMEM;
634}
void bnxt_mm_init_hwrm(struct bnxt *bp, const char *func)
Definition bnxt.c:511
void bnxt_free_hwrm_mem(struct bnxt *bp)
Definition bnxt.c:596
void * dma_alloc(struct dma_device *dma, struct dma_mapping *map, size_t len, size_t align)
Allocate and map DMA-coherent buffer.

References bnxt_free_hwrm_mem(), bnxt_mm_init_hwrm(), bp, DBGP, dma_alloc(), DMA_BUFFER_SIZE, ENOMEM, REQ_BUFFER_SIZE, RESP_BUFFER_SIZE, and STATUS_SUCCESS.

Referenced by bnxt_init_one().

◆ bnxt_alloc_rings_mem()

int bnxt_alloc_rings_mem ( struct bnxt * bp)

Definition at line 636 of file bnxt.c.

637{
638 DBGP ( "%s\n", __func__ );
639 bp->tx.bd_virt = dma_alloc ( bp->dma, &bp->tx_mapping,
641 bp->rx.bd_virt = dma_alloc ( bp->dma, &bp->rx_mapping,
643 bp->cq.bd_virt = dma_alloc ( bp->dma, &bp->cq_mapping,
645 bp->nq.bd_virt = dma_alloc ( bp->dma, &bp->nq_mapping,
647 if ( bp->tx.bd_virt && bp->rx.bd_virt &&
648 bp->nq.bd_virt && bp->cq.bd_virt) {
649 bnxt_mm_init_rings ( bp, __func__ );
650 return STATUS_SUCCESS;
651 }
652
653 DBGP ( "- %s ( ): Failed\n", __func__ );
655 return -ENOMEM;
656}
void bnxt_free_rings_mem(struct bnxt *bp)
Definition bnxt.c:570
void bnxt_mm_init_rings(struct bnxt *bp, const char *func)
Definition bnxt.c:522
#define DMA_ALIGN_4K
Definition bnxt.h:155
#define BNXT_DMA_ALIGNMENT
Definition bnxt.h:154

References BNXT_DMA_ALIGNMENT, bnxt_free_rings_mem(), bnxt_mm_init_rings(), bp, CQ_RING_BUFFER_SIZE, DBGP, DMA_ALIGN_4K, dma_alloc(), ENOMEM, NQ_RING_BUFFER_SIZE, RX_RING_BUFFER_SIZE, STATUS_SUCCESS, and TX_RING_BUFFER_SIZE.

Referenced by bnxt_open().

◆ hwrm_init()

void hwrm_init ( struct bnxt * bp,
struct input * req,
u16 cmd,
u16 len )
static

Definition at line 658 of file bnxt.c.

659{
660 memset ( req, 0, len );
661 req->req_type = cmd;
664 req->resp_addr = RESP_DMA_ADDR ( bp );
665 req->seq_id = bp->seq_id++;
666}
struct golan_eqe_cmd cmd
Definition CIB_PRM.h:1
#define RESP_DMA_ADDR(bp)
Definition bnxt.h:183
#define HWRM_NA_SIGNATURE
Definition bnxt_hsi.h:363
__le16 seq_id
Definition bnxt_hsi.h:71
__le16 req_type
Definition bnxt_hsi.h:69
__le16 target_id
Definition bnxt_hsi.h:72
__le64 resp_addr
Definition bnxt_hsi.h:73
__le16 cmpl_ring
Definition bnxt_hsi.h:70

References bp, cmd, input::cmpl_ring, HWRM_NA_SIGNATURE, len, memset(), input::req_type, input::resp_addr, RESP_DMA_ADDR, input::seq_id, input::target_id, and u16.

Referenced by bnxt_hwrm_backing_store_cfg(), bnxt_hwrm_backing_store_qcfg(), bnxt_hwrm_cfa_l2_filter_alloc(), bnxt_hwrm_cfa_l2_filter_free(), bnxt_hwrm_error_recovery_req(), bnxt_hwrm_func_cfg_req(), bnxt_hwrm_func_drv_rgtr(), bnxt_hwrm_func_drv_unrgtr(), bnxt_hwrm_func_qcaps_req(), bnxt_hwrm_func_qcfg_req(), bnxt_hwrm_func_reset_req(), bnxt_hwrm_func_resource_qcaps(), bnxt_hwrm_nvm_get_variable_req(), bnxt_hwrm_port_mac_cfg(), bnxt_hwrm_port_phy_cfg(), bnxt_hwrm_port_phy_qcaps_req(), bnxt_hwrm_port_phy_qcfg(), bnxt_hwrm_queue_qportcfg(), bnxt_hwrm_ring_alloc(), bnxt_hwrm_ring_alloc_grp(), bnxt_hwrm_ring_free(), bnxt_hwrm_ring_free_grp(), bnxt_hwrm_set_async_event(), bnxt_hwrm_set_rx_mask(), bnxt_hwrm_stat_ctx_alloc(), bnxt_hwrm_stat_ctx_free(), bnxt_hwrm_ver_get(), bnxt_hwrm_vnic_alloc(), bnxt_hwrm_vnic_cfg(), and bnxt_hwrm_vnic_free().

◆ hwrm_write_req()

void hwrm_write_req ( struct bnxt * bp,
void * req,
u32 cnt )
static

Definition at line 668 of file bnxt.c.

669{
670 u32 i = 0;
671
672 for ( i = 0; i < cnt; i++ ) {
673 writel ( ( ( u32 * ) req )[i],
674 ( bp->bar0 + GRC_COM_CHAN_BASE + ( i * 4 ) ) );
675 }
676 writel ( 0x1, ( bp->bar0 + GRC_COM_CHAN_BASE + GRC_COM_CHAN_TRIG ) );
677}
#define GRC_COM_CHAN_BASE
Definition bnxt.h:126
#define GRC_COM_CHAN_TRIG
Definition bnxt.h:127

References bp, GRC_COM_CHAN_BASE, GRC_COM_CHAN_TRIG, u32, and writel.

Referenced by short_hwrm_cmd_req(), and wait_resp().

◆ short_hwrm_cmd_req()

void short_hwrm_cmd_req ( struct bnxt * bp,
u16 len,
u16 req_type )
static

Definition at line 679 of file bnxt.c.

680{
681 struct hwrm_short_input sreq;
682
683 memset ( &sreq, 0, sizeof ( struct hwrm_short_input ) );
684 sreq.req_type = req_type;
685 sreq.signature = SHORT_REQ_SIGNATURE_SHORT_CMD;
686 sreq.size = len;
687 sreq.req_addr = REQ_DMA_ADDR ( bp );
688
689 dbg_short_cmd ( ( u8 * ) &sreq, __func__,
690 sizeof ( struct hwrm_short_input ) );
691 /* Ensure request buffer is flushed before writing short command */
692 wmb();
693 hwrm_write_req ( bp, &sreq, sizeof ( struct hwrm_short_input ) / 4 );
694}
static void hwrm_write_req(struct bnxt *bp, void *req, u32 cnt)
Definition bnxt.c:668
#define REQ_DMA_ADDR(bp)
Definition bnxt.h:182
#define dbg_short_cmd(sreq, func, len)
Definition bnxt_dbg.h:398
#define SHORT_REQ_SIGNATURE_SHORT_CMD
Definition bnxt_hsi.h:88
#define wmb()
Definition io.h:546
__le16 req_type
Definition bnxt_hsi.h:86

References bp, dbg_short_cmd, hwrm_write_req(), len, memset(), hwrm_short_input::req_addr, REQ_DMA_ADDR, hwrm_short_input::req_type, SHORT_REQ_SIGNATURE_SHORT_CMD, hwrm_short_input::signature, hwrm_short_input::size, u16, u8, and wmb.

Referenced by wait_resp().

◆ wait_resp()

int wait_resp ( struct bnxt * bp,
u32 tmo,
u16 len,
const char * func )
static

Definition at line 696 of file bnxt.c.

697{
698 struct input *req = ( struct input * ) REQ_DMA_ADDR ( bp );
699 struct output *resp = ( struct output * ) RESP_DMA_ADDR ( bp );
700 u8 *ptr = ( u8 * )resp;
701 u32 idx;
702 u32 wait_cnt = HWRM_CMD_DEFAULT_MULTIPLAYER ( ( u32 )tmo );
703 u16 resp_len = 0;
704 u16 ret = STATUS_TIMEOUT;
705
706 if ( ( len > bp->hwrm_max_req_len ) ||
709 else
710 hwrm_write_req ( bp, req, ( u32 ) ( len / 4 ) );
711
712 for ( idx = 0; idx < wait_cnt; idx++ ) {
713 resp_len = resp->resp_len;
714
715 if ( resp_len != 0 && resp_len <= ( u16 ) RESP_BUFFER_SIZE ) {
716 if ( resp->seq_id == req->seq_id &&
717 resp->req_type == req->req_type &&
718 ptr[resp_len - 1] == 1 ) {
719 bp->last_resp_code = resp->error_code;
720 ret = resp->error_code;
721 break;
722 }
723 }
725 }
726 dbg_hw_cmd ( bp, func, len, resp_len, tmo, ret );
727 return ( int )ret;
728}
static void short_hwrm_cmd_req(struct bnxt *bp, u16 len, u16 req_type)
Definition bnxt.c:679
#define STATUS_TIMEOUT
Definition bnxt.h:79
#define HWRM_CMD_POLL_WAIT_TIME
Definition bnxt.h:135
#define HWRM_CMD_DEFAULT_MULTIPLAYER(a)
Definition bnxt.h:136
#define BNXT_FLAG_HWRM_SHORT_CMD_REQ
Definition bnxt.h:42
#define dbg_hw_cmd(bp, func, cmd_len, resp_len, cmd_tmo, err)
Definition bnxt_dbg.h:378
__le16 error_code
Definition bnxt_hsi.h:78
__le16 req_type
Definition bnxt_hsi.h:79
__le16 resp_len
Definition bnxt_hsi.h:81
__le16 seq_id
Definition bnxt_hsi.h:80
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition timer.c:61

References BNXT_FLAG_HWRM_SHORT_CMD_REQ, bp, dbg_hw_cmd, output::error_code, FLAG_TEST, HWRM_CMD_DEFAULT_MULTIPLAYER, HWRM_CMD_POLL_WAIT_TIME, hwrm_write_req(), len, REQ_DMA_ADDR, input::req_type, output::req_type, RESP_BUFFER_SIZE, RESP_DMA_ADDR, output::resp_len, input::seq_id, output::seq_id, short_hwrm_cmd_req(), STATUS_TIMEOUT, u16, u32, u8, and udelay().

Referenced by bnxt_hwrm_backing_store_cfg(), bnxt_hwrm_backing_store_qcfg(), bnxt_hwrm_cfa_l2_filter_alloc(), bnxt_hwrm_cfa_l2_filter_free(), bnxt_hwrm_error_recovery_req(), bnxt_hwrm_func_cfg_req(), bnxt_hwrm_func_drv_rgtr(), bnxt_hwrm_func_drv_unrgtr(), bnxt_hwrm_func_qcaps_req(), bnxt_hwrm_func_qcfg_req(), bnxt_hwrm_func_reset_req(), bnxt_hwrm_func_resource_qcaps(), bnxt_hwrm_nvm_get_variable_req(), bnxt_hwrm_port_mac_cfg(), bnxt_hwrm_port_phy_cfg(), bnxt_hwrm_port_phy_qcaps_req(), bnxt_hwrm_port_phy_qcfg(), bnxt_hwrm_queue_qportcfg(), bnxt_hwrm_ring_alloc(), bnxt_hwrm_ring_alloc_grp(), bnxt_hwrm_ring_free(), bnxt_hwrm_ring_free_grp(), bnxt_hwrm_set_async_event(), bnxt_hwrm_set_rx_mask(), bnxt_hwrm_stat_ctx_alloc(), bnxt_hwrm_stat_ctx_free(), bnxt_hwrm_ver_get(), bnxt_hwrm_vnic_alloc(), bnxt_hwrm_vnic_cfg(), and bnxt_hwrm_vnic_free().

◆ bnxt_hwrm_ver_get()

int bnxt_hwrm_ver_get ( struct bnxt * bp)
static

Definition at line 730 of file bnxt.c.

731{
732 u16 cmd_len = ( u16 )sizeof ( struct hwrm_ver_get_input );
733 struct hwrm_ver_get_input *req;
734 struct hwrm_ver_get_output *resp;
735 int rc;
736
737 DBGP ( "%s\n", __func__ );
738 req = ( struct hwrm_ver_get_input * ) REQ_DMA_ADDR ( bp );
739 resp = ( struct hwrm_ver_get_output * ) RESP_DMA_ADDR ( bp );
740 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VER_GET, cmd_len );
741 req->hwrm_intf_maj = HWRM_VERSION_MAJOR;
742 req->hwrm_intf_min = HWRM_VERSION_MINOR;
743 req->hwrm_intf_upd = HWRM_VERSION_UPDATE;
744 rc = wait_resp ( bp, HWRM_CMD_DEFAULT_TIMEOUT, cmd_len, __func__ );
745 if ( rc )
746 return STATUS_FAILURE;
747
748 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
749 resp->hwrm_intf_min_8b << 8 |
750 resp->hwrm_intf_upd_8b;
751 bp->hwrm_cmd_timeout = ( u32 ) resp->def_req_timeout;
752 if ( !bp->hwrm_cmd_timeout )
753 bp->hwrm_cmd_timeout = ( u32 ) HWRM_CMD_DEFAULT_TIMEOUT;
754 if ( resp->hwrm_intf_maj_8b >= 1 )
755 bp->hwrm_max_req_len = resp->max_req_win_len;
756 bp->chip_id = resp->chip_rev << 24 | resp->chip_metal << 16 |
757 resp->chip_bond_id << 8 | resp->chip_platform_type;
758 bp->chip_num = resp->chip_num;
759 if ( resp->dev_caps_cfg & SHORT_CMD_SUPPORTED )
761 if ( resp->dev_caps_cfg & SHORT_CMD_REQUIRED )
763 bp->hwrm_max_ext_req_len = resp->max_ext_req_len;
764 if ( ( bp->chip_num == CHIP_NUM_57508 ) ||
765 ( bp->chip_num == CHIP_NUM_57504 ) ||
766 ( bp->chip_num == CHIP_NUM_57502 ) ) {
767 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P5 );
769 }
770 if ( bp->chip_num == CHIP_NUM_57608 ) {
771 FLAG_SET ( bp->flags, BNXT_FLAG_IS_CHIP_P7 );
773 }
774 dbg_fw_ver ( resp, bp->hwrm_cmd_timeout );
775 return STATUS_SUCCESS;
776}
struct arbelprm_rc_send_wqe rc
Definition arbel.h:3
static int wait_resp(struct bnxt *bp, u32 tmo, u16 len, const char *func)
Definition bnxt.c:696
static void hwrm_init(struct bnxt *bp, struct input *req, u16 cmd, u16 len)
Definition bnxt.c:658
#define STATUS_FAILURE
Definition bnxt.h:56
#define CHIP_NUM_57608
Definition bnxt.h:1106
#define SHORT_CMD_SUPPORTED
Definition bnxt.h:1062
#define CHIP_NUM_57502
Definition bnxt.h:1104
#define BNXT_FLAG_IS_CHIP_P5_PLUS
Definition bnxt.h:50
#define CHIP_NUM_57504
Definition bnxt.h:1103
#define SHORT_CMD_REQUIRED
Definition bnxt.h:1063
#define BNXT_FLAG_HWRM_SHORT_CMD_SUPP
Definition bnxt.h:41
#define CHIP_NUM_57508
Definition bnxt.h:1102
#define dbg_fw_ver(resp, tmo)
Definition bnxt_dbg.h:319
#define HWRM_VERSION_MINOR
Definition bnxt_hsi.h:370
#define HWRM_VER_GET
Definition bnxt_hsi.h:98
#define HWRM_VERSION_MAJOR
Definition bnxt_hsi.h:369
#define HWRM_VERSION_UPDATE
Definition bnxt_hsi.h:371

References BNXT_FLAG_HWRM_SHORT_CMD_REQ, BNXT_FLAG_HWRM_SHORT_CMD_SUPP, BNXT_FLAG_IS_CHIP_P5, BNXT_FLAG_IS_CHIP_P5_PLUS, BNXT_FLAG_IS_CHIP_P7, bp, hwrm_ver_get_output::chip_bond_id, hwrm_ver_get_output::chip_metal, hwrm_ver_get_output::chip_num, CHIP_NUM_57502, CHIP_NUM_57504, CHIP_NUM_57508, CHIP_NUM_57608, hwrm_ver_get_output::chip_platform_type, hwrm_ver_get_output::chip_rev, dbg_fw_ver, DBGP, hwrm_ver_get_output::def_req_timeout, hwrm_ver_get_output::dev_caps_cfg, FLAG_SET, HWRM_CMD_DEFAULT_TIMEOUT, hwrm_init(), hwrm_ver_get_input::hwrm_intf_maj, hwrm_ver_get_output::hwrm_intf_maj_8b, hwrm_ver_get_input::hwrm_intf_min, hwrm_ver_get_output::hwrm_intf_min_8b, hwrm_ver_get_input::hwrm_intf_upd, hwrm_ver_get_output::hwrm_intf_upd_8b, HWRM_VER_GET, HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE, hwrm_ver_get_output::max_ext_req_len, hwrm_ver_get_output::max_req_win_len, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, SHORT_CMD_REQUIRED, SHORT_CMD_SUPPORTED, STATUS_FAILURE, STATUS_SUCCESS, u16, u32, and wait_resp().

◆ bnxt_hwrm_func_resource_qcaps()

int bnxt_hwrm_func_resource_qcaps ( struct bnxt * bp)
static

Definition at line 778 of file bnxt.c.

779{
780 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_resource_qcaps_input );
783 int rc;
784
785 DBGP ( "%s\n", __func__ );
786 req = ( struct hwrm_func_resource_qcaps_input * ) REQ_DMA_ADDR ( bp );
787 resp = ( struct hwrm_func_resource_qcaps_output * ) RESP_DMA_ADDR ( bp );
788 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_RESOURCE_QCAPS, cmd_len );
789 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
790 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
791 if ( rc != STATUS_SUCCESS )
792 return STATUS_SUCCESS;
793
795
796 // VFs
797 if ( !bp->vf ) {
798 bp->max_vfs = resp->max_vfs;
799 bp->vf_res_strategy = resp->vf_reservation_strategy;
800 }
801
802 // vNICs
803 bp->min_vnics = resp->min_vnics;
804 bp->max_vnics = resp->max_vnics;
805
806 // MSI-X
807 bp->max_msix = resp->max_msix;
808
809 // Ring Groups
810 bp->min_hw_ring_grps = resp->min_hw_ring_grps;
811 bp->max_hw_ring_grps = resp->max_hw_ring_grps;
812
813 // TX Rings
814 bp->min_tx_rings = resp->min_tx_rings;
815 bp->max_tx_rings = resp->max_tx_rings;
816
817 // RX Rings
818 bp->min_rx_rings = resp->min_rx_rings;
819 bp->max_rx_rings = resp->max_rx_rings;
820
821 // Completion Rings
822 bp->min_cp_rings = resp->min_cmpl_rings;
823 bp->max_cp_rings = resp->max_cmpl_rings;
824
825 // RSS Contexts
826 bp->min_rsscos_ctxs = resp->min_rsscos_ctx;
827 bp->max_rsscos_ctxs = resp->max_rsscos_ctx;
828
829 // L2 Contexts
830 bp->min_l2_ctxs = resp->min_l2_ctxs;
831 bp->max_l2_ctxs = resp->max_l2_ctxs;
832
833 // Statistic Contexts
834 bp->min_stat_ctxs = resp->min_stat_ctx;
835 bp->max_stat_ctxs = resp->max_stat_ctx;
837 return STATUS_SUCCESS;
838}
#define BNXT_FLAG_RESOURCE_QCAPS_SUPPORT
Definition bnxt.h:43
#define dbg_func_resource_qcaps(bp)
Definition bnxt_dbg.h:320
#define HWRM_FUNC_RESOURCE_QCAPS
Definition bnxt_hsi.h:281

References BNXT_FLAG_RESOURCE_QCAPS_SUPPORT, bp, dbg_func_resource_qcaps, DBGP, hwrm_func_resource_qcaps_input::fid, FLAG_SET, HWRM_FUNC_RESOURCE_QCAPS, hwrm_init(), HWRM_NA_SIGNATURE, hwrm_func_resource_qcaps_output::max_cmpl_rings, hwrm_func_resource_qcaps_output::max_hw_ring_grps, hwrm_func_resource_qcaps_output::max_l2_ctxs, hwrm_func_resource_qcaps_output::max_msix, hwrm_func_resource_qcaps_output::max_rsscos_ctx, hwrm_func_resource_qcaps_output::max_rx_rings, hwrm_func_resource_qcaps_output::max_stat_ctx, hwrm_func_resource_qcaps_output::max_tx_rings, hwrm_func_resource_qcaps_output::max_vfs, hwrm_func_resource_qcaps_output::max_vnics, hwrm_func_resource_qcaps_output::min_cmpl_rings, hwrm_func_resource_qcaps_output::min_hw_ring_grps, hwrm_func_resource_qcaps_output::min_l2_ctxs, hwrm_func_resource_qcaps_output::min_rsscos_ctx, hwrm_func_resource_qcaps_output::min_rx_rings, hwrm_func_resource_qcaps_output::min_stat_ctx, hwrm_func_resource_qcaps_output::min_tx_rings, hwrm_func_resource_qcaps_output::min_vnics, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_SUCCESS, u16, hwrm_func_resource_qcaps_output::vf_reservation_strategy, and wait_resp().

◆ bnxt_set_ring_info()

u32 bnxt_set_ring_info ( struct bnxt * bp)
static

Definition at line 840 of file bnxt.c.

841{
842 u32 enables = 0;
843
844 DBGP ( "%s\n", __func__ );
845 bp->num_cmpl_rings = DEFAULT_NUMBER_OF_CMPL_RINGS;
846 bp->num_tx_rings = DEFAULT_NUMBER_OF_TX_RINGS;
847 bp->num_rx_rings = DEFAULT_NUMBER_OF_RX_RINGS;
848 bp->num_hw_ring_grps = DEFAULT_NUMBER_OF_RING_GRPS;
849 bp->num_stat_ctxs = DEFAULT_NUMBER_OF_STAT_CTXS;
850
851 if ( bp->min_cp_rings <= DEFAULT_NUMBER_OF_CMPL_RINGS )
852 bp->num_cmpl_rings = bp->min_cp_rings;
853
854 if ( bp->min_tx_rings <= DEFAULT_NUMBER_OF_TX_RINGS )
855 bp->num_tx_rings = bp->min_tx_rings;
856
857 if ( bp->min_rx_rings <= DEFAULT_NUMBER_OF_RX_RINGS )
858 bp->num_rx_rings = bp->min_rx_rings;
859
860 if ( bp->min_hw_ring_grps <= DEFAULT_NUMBER_OF_RING_GRPS )
861 bp->num_hw_ring_grps = bp->min_hw_ring_grps;
862
863 if ( bp->min_stat_ctxs <= DEFAULT_NUMBER_OF_STAT_CTXS )
864 bp->num_stat_ctxs = bp->min_stat_ctxs;
865
866 dbg_num_rings ( bp );
872 return enables;
873}
#define DEFAULT_NUMBER_OF_STAT_CTXS
Definition bnxt.h:145
#define DEFAULT_NUMBER_OF_RING_GRPS
Definition bnxt.h:144
#define DEFAULT_NUMBER_OF_TX_RINGS
Definition bnxt.h:142
#define DEFAULT_NUMBER_OF_RX_RINGS
Definition bnxt.h:143
#define DEFAULT_NUMBER_OF_CMPL_RINGS
Definition bnxt.h:141
#define dbg_num_rings(bp)
Definition bnxt_dbg.h:325
#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS
Definition bnxt_hsi.h:1556
#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS
Definition bnxt_hsi.h:1542
#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS
Definition bnxt_hsi.h:1545
#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS
Definition bnxt_hsi.h:1541
#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS
Definition bnxt_hsi.h:1540

References bp, dbg_num_rings, DBGP, DEFAULT_NUMBER_OF_CMPL_RINGS, DEFAULT_NUMBER_OF_RING_GRPS, DEFAULT_NUMBER_OF_RX_RINGS, DEFAULT_NUMBER_OF_STAT_CTXS, DEFAULT_NUMBER_OF_TX_RINGS, FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS, FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS, FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS, FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS, FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS, and u32.

Referenced by bnxt_hwrm_assign_resources().

◆ bnxt_hwrm_assign_resources()

void bnxt_hwrm_assign_resources ( struct bnxt * bp)
static

Definition at line 875 of file bnxt.c.

876{
877 struct hwrm_func_cfg_input *req;
878 u32 enables = 0;
879
880 DBGP ( "%s\n", __func__ );
883
884 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
885 req->num_cmpl_rings = bp->num_cmpl_rings;
886 req->num_tx_rings = bp->num_tx_rings;
887 req->num_rx_rings = bp->num_rx_rings;
888 req->num_stat_ctxs = bp->num_stat_ctxs;
889 req->num_hw_ring_grps = bp->num_hw_ring_grps;
890 req->enables = enables;
891}
static u32 bnxt_set_ring_info(struct bnxt *bp)
Definition bnxt.c:840

References BNXT_FLAG_RESOURCE_QCAPS_SUPPORT, bnxt_set_ring_info(), bp, DBGP, hwrm_func_cfg_input::enables, FLAG_TEST, hwrm_func_cfg_input::num_cmpl_rings, hwrm_func_cfg_input::num_hw_ring_grps, hwrm_func_cfg_input::num_rx_rings, hwrm_func_cfg_input::num_stat_ctxs, hwrm_func_cfg_input::num_tx_rings, REQ_DMA_ADDR, and u32.

Referenced by bnxt_hwrm_func_cfg_req().

◆ bnxt_hwrm_func_qcaps_req()

int bnxt_hwrm_func_qcaps_req ( struct bnxt * bp)
static

Definition at line 893 of file bnxt.c.

894{
895 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_qcaps_input );
896 struct hwrm_func_qcaps_input *req;
897 struct hwrm_func_qcaps_output *resp;
898 int rc;
899
900 DBGP ( "%s\n", __func__ );
901 if ( bp->vf )
902 return STATUS_SUCCESS;
903
904 req = ( struct hwrm_func_qcaps_input * ) REQ_DMA_ADDR ( bp );
905 resp = ( struct hwrm_func_qcaps_output * ) RESP_DMA_ADDR ( bp );
906 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_QCAPS, cmd_len );
907 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
908 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
909 if ( rc ) {
910 DBGP ( "- %s ( ): Failed\n", __func__ );
911 return STATUS_FAILURE;
912 }
913
914 bp->fid = resp->fid;
915 bp->port_idx = ( u8 ) resp->port_id;
916
918 bp->err_rcvry_supported = 1;
919 }
920
921 /* Get MAC address for this PF */
922 memcpy ( &bp->mac_addr[0], &resp->mac_address[0], ETH_ALEN );
923 dbg_func_qcaps ( bp );
924
925 return STATUS_SUCCESS;
926}
#define dbg_func_qcaps(bp)
Definition bnxt_dbg.h:321
#define HWRM_FUNC_QCAPS
Definition bnxt_hsi.h:108
#define FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE
Definition bnxt_hsi.h:1366

References bp, dbg_func_qcaps, DBGP, ETH_ALEN, hwrm_func_qcaps_input::fid, hwrm_func_qcaps_output::fid, hwrm_func_qcaps_output::flags, FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE, HWRM_FUNC_QCAPS, hwrm_init(), HWRM_NA_SIGNATURE, hwrm_func_qcaps_output::mac_address, memcpy(), hwrm_func_qcaps_output::port_id, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, u8, and wait_resp().

◆ bnxt_hwrm_func_qcfg_req()

int bnxt_hwrm_func_qcfg_req ( struct bnxt * bp)
static

Definition at line 928 of file bnxt.c.

929{
930 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_qcfg_input );
931 struct hwrm_func_qcfg_input *req;
932 struct hwrm_func_qcfg_output *resp;
933 int rc;
934
935 DBGP ( "%s\n", __func__ );
936 req = ( struct hwrm_func_qcfg_input * ) REQ_DMA_ADDR ( bp );
937 resp = ( struct hwrm_func_qcfg_output * ) RESP_DMA_ADDR ( bp );
938 hwrm_init ( bp, ( void * )req, ( u16 ) HWRM_FUNC_QCFG, cmd_len );
939 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
940 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
941 if ( rc ) {
942 DBGP ( "- %s ( ): Failed\n", __func__ );
943 return STATUS_FAILURE;
944 }
945
947 FLAG_SET ( bp->flags, BNXT_FLAG_MULTI_HOST );
948
949 if ( resp->port_partition_type &
951 FLAG_SET ( bp->flags, BNXT_FLAG_NPAR_MODE );
952
953 bp->ordinal_value = ( u8 ) resp->pci_id & 0x0F;
954 bp->stat_ctx_id = resp->stat_ctx_id;
955
956 /* If VF is set to TRUE, then use some data from func_qcfg ( ). */
957 if ( bp->vf ) {
958 bp->fid = resp->fid;
959 bp->port_idx = ( u8 ) resp->port_id;
960 bp->vlan_id = resp->vlan;
961
962 /* Get MAC address for this VF */
963 memcpy ( bp->mac_addr, resp->mac_address, ETH_ALEN );
964 }
965 dbg_func_qcfg ( bp );
966 return STATUS_SUCCESS;
967}
#define BNXT_FLAG_NPAR_MODE
Definition bnxt.h:45
#define BNXT_FLAG_MULTI_HOST
Definition bnxt.h:44
#define dbg_func_qcfg(bp)
Definition bnxt_dbg.h:322
#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST
Definition bnxt_hsi.h:1417
#define HWRM_FUNC_QCFG
Definition bnxt_hsi.h:109
#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0
Definition bnxt_hsi.h:1433

References BNXT_FLAG_MULTI_HOST, BNXT_FLAG_NPAR_MODE, bp, dbg_func_qcfg, DBGP, ETH_ALEN, hwrm_func_qcfg_input::fid, hwrm_func_qcfg_output::fid, FLAG_SET, hwrm_func_qcfg_output::flags, FUNC_QCFG_RESP_FLAGS_MULTI_HOST, FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0, HWRM_FUNC_QCFG, hwrm_init(), HWRM_NA_SIGNATURE, hwrm_func_qcfg_output::mac_address, memcpy(), hwrm_func_qcfg_output::pci_id, hwrm_func_qcfg_output::port_id, hwrm_func_qcfg_output::port_partition_type, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, hwrm_func_qcfg_output::stat_ctx_id, STATUS_FAILURE, STATUS_SUCCESS, u16, u8, hwrm_func_qcfg_output::vlan, and wait_resp().

◆ bnxt_hwrm_port_phy_qcaps_req()

int bnxt_hwrm_port_phy_qcaps_req ( struct bnxt * bp)
static

Definition at line 969 of file bnxt.c.

970{
971 u16 cmd_len = ( u16 )sizeof ( struct hwrm_port_phy_qcaps_input );
972 struct hwrm_port_phy_qcaps_input *req;
973 struct hwrm_port_phy_qcaps_output *resp;
974 int rc;
975
976 DBGP ( "%s\n", __func__ );
977
978 req = ( struct hwrm_port_phy_qcaps_input * ) REQ_DMA_ADDR ( bp );
979 resp = ( struct hwrm_port_phy_qcaps_output * ) RESP_DMA_ADDR ( bp );
980 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_QCAPS, cmd_len );
981 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
982 if ( rc ) {
983 DBGP ( "-s %s ( ): Failed\n", __func__ );
984 return STATUS_FAILURE;
985 }
986
989
990 return STATUS_SUCCESS;
991}
#define BNXT_FLAG_LINK_SPEEDS2
Definition bnxt.h:48
#define HWRM_PORT_PHY_QCAPS
Definition bnxt_hsi.h:129
#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED
Definition bnxt_hsi.h:4237

References BNXT_FLAG_LINK_SPEEDS2, bp, DBGP, FLAG_SET, hwrm_port_phy_qcaps_output::flags2, hwrm_init(), HWRM_PORT_PHY_QCAPS, PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_func_reset_req()

int bnxt_hwrm_func_reset_req ( struct bnxt * bp)
static

Definition at line 993 of file bnxt.c.

994{
995 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_reset_input );
996 struct hwrm_func_reset_input *req;
997
998 DBGP ( "%s\n", __func__ );
999 req = ( struct hwrm_func_reset_input * ) REQ_DMA_ADDR ( bp );
1000 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_RESET, cmd_len );
1001 if ( !bp->vf )
1002 req->func_reset_level = FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME;
1003
1004 return wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
1005}
#define HWRM_CMD_WAIT(b)
Definition bnxt.h:139
#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME
Definition bnxt_hsi.h:1181
#define HWRM_FUNC_RESET
Definition bnxt_hsi.h:104

References bp, DBGP, hwrm_func_reset_input::func_reset_level, FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME, HWRM_CMD_WAIT, HWRM_FUNC_RESET, hwrm_init(), REQ_DMA_ADDR, u16, and wait_resp().

◆ bnxt_hwrm_func_cfg_req()

int bnxt_hwrm_func_cfg_req ( struct bnxt * bp)
static

Definition at line 1007 of file bnxt.c.

1008{
1009 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_cfg_input );
1010 struct hwrm_func_cfg_input *req;
1011
1012 DBGP ( "%s\n", __func__ );
1013 if ( bp->vf )
1014 return STATUS_SUCCESS;
1015
1016 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
1017 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_CFG, cmd_len );
1018 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
1020 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
1021 req->enables |= ( FUNC_CFG_REQ_ENABLES_NUM_MSIX |
1024 req->num_msix = 1;
1025 req->num_vnics = 1;
1026 req->evb_mode = FUNC_CFG_REQ_EVB_MODE_NO_EVB;
1027 }
1028 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1029}
static void bnxt_hwrm_assign_resources(struct bnxt *bp)
Definition bnxt.c:875
#define FUNC_CFG_REQ_ENABLES_NUM_MSIX
Definition bnxt_hsi.h:1558
#define FUNC_CFG_REQ_EVB_MODE_NO_EVB
Definition bnxt_hsi.h:1614
#define FUNC_CFG_REQ_ENABLES_EVB_MODE
Definition bnxt_hsi.h:1554
#define FUNC_CFG_REQ_ENABLES_NUM_VNICS
Definition bnxt_hsi.h:1544
#define HWRM_FUNC_CFG
Definition bnxt_hsi.h:110

References BNXT_FLAG_IS_CHIP_P5_PLUS, bnxt_hwrm_assign_resources(), bp, DBGP, hwrm_func_cfg_input::enables, hwrm_func_cfg_input::evb_mode, hwrm_func_cfg_input::fid, FLAG_TEST, FUNC_CFG_REQ_ENABLES_EVB_MODE, FUNC_CFG_REQ_ENABLES_NUM_MSIX, FUNC_CFG_REQ_ENABLES_NUM_VNICS, FUNC_CFG_REQ_EVB_MODE_NO_EVB, HWRM_FUNC_CFG, hwrm_init(), HWRM_NA_SIGNATURE, hwrm_func_cfg_input::num_msix, hwrm_func_cfg_input::num_vnics, REQ_DMA_ADDR, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_error_recovery_req()

int bnxt_hwrm_error_recovery_req ( struct bnxt * bp)
static

Definition at line 1031 of file bnxt.c.

1032{
1035 int rc = 0;
1036 u8 i = 0;
1037 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_error_recovery_qcfg_input );
1038
1039 DBGP ( "%s\n", __func__ );
1040 /* Set default error recovery heartbeat polling value (in 100ms)*/
1041 bp->er.drv_poll_freq = 100;
1042 if ( ! ( bp->err_rcvry_supported ) ) {
1043 return STATUS_SUCCESS;
1044 }
1045
1046 req = ( struct hwrm_error_recovery_qcfg_input * ) REQ_DMA_ADDR ( bp );
1047 resp = ( struct hwrm_error_recovery_qcfg_output * ) RESP_DMA_ADDR ( bp );
1048
1049 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_ER_QCFG, cmd_len );
1050
1051 rc = wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
1052 if ( rc ) {
1053 DBGP ( "- %s ( ): Failed\n", __func__ );
1054 return STATUS_FAILURE;
1055 }
1056
1057 bp->er.flags = resp->flags;
1058 bp->er.drv_poll_freq = resp->driver_polling_freq;
1059 bp->er.master_wait_period = resp->master_wait_period;
1060 bp->er.normal_wait_period = resp->normal_wait_period;
1061 bp->er.master_wait_post_rst = resp->master_wait_post_reset;
1062 bp->er.max_bailout_post_rst = resp->max_bailout_time;
1063
1064 bp->er.fw_status_reg = resp->fw_health_status_reg;
1065 bp->er.fw_hb_reg = resp->fw_heartbeat_reg;
1066 bp->er.fw_rst_cnt_reg = resp->fw_reset_cnt_reg;
1067 bp->er.recvry_cnt_reg = resp->err_recovery_cnt_reg;
1068 bp->er.rst_inprg_reg = resp->reset_inprogress_reg;
1069
1070 bp->er.rst_inprg_reg_mask = resp->reset_inprogress_reg_mask;
1071 bp->er.reg_array_cnt = resp->reg_array_cnt;
1072
1073 DBGP ( "flags = 0x%x\n", resp->flags );
1074 DBGP ( "driver_polling_freq = 0x%x\n", resp->driver_polling_freq );
1075 DBGP ( "master_wait_period = 0x%x\n", resp->master_wait_period );
1076 DBGP ( "normal_wait_period = 0x%x\n", resp->normal_wait_period );
1077 DBGP ( "wait_post_reset = 0x%x\n", resp->master_wait_post_reset );
1078 DBGP ( "bailout_post_reset = 0x%x\n", resp->max_bailout_time );
1079 DBGP ( "reg_array_cnt = %x\n", resp->reg_array_cnt );
1080
1081 for ( i = 0; i < resp->reg_array_cnt; i++ ) {
1082 bp->er.rst_reg[i] = resp->reset_reg[i];
1083 bp->er.rst_reg_val[i] = resp->reset_reg_val[i];
1084 bp->er.delay_after_rst[i] = resp->delay_after_reset[i];
1085
1086 DBGP ( "rst_reg = %x ", bp->er.rst_reg[i] );
1087 DBGP ( "rst_reg_val = %x ", bp->er.rst_reg_val[i] );
1088 DBGP ( "rst_after_reset = %x\n", bp->er.delay_after_rst[i] );
1089 }
1090
1091 return STATUS_SUCCESS;
1092}
#define HWRM_ER_QCFG
Definition bnxt_hsi.h:99

References bp, DBGP, hwrm_error_recovery_qcfg_output::delay_after_reset, hwrm_error_recovery_qcfg_output::driver_polling_freq, hwrm_error_recovery_qcfg_output::err_recovery_cnt_reg, hwrm_error_recovery_qcfg_output::flags, hwrm_error_recovery_qcfg_output::fw_health_status_reg, hwrm_error_recovery_qcfg_output::fw_heartbeat_reg, hwrm_error_recovery_qcfg_output::fw_reset_cnt_reg, HWRM_CMD_WAIT, HWRM_ER_QCFG, hwrm_init(), hwrm_error_recovery_qcfg_output::master_wait_period, hwrm_error_recovery_qcfg_output::master_wait_post_reset, hwrm_error_recovery_qcfg_output::max_bailout_time, hwrm_error_recovery_qcfg_output::normal_wait_period, rc, hwrm_error_recovery_qcfg_output::reg_array_cnt, REQ_DMA_ADDR, hwrm_error_recovery_qcfg_output::reset_inprogress_reg, hwrm_error_recovery_qcfg_output::reset_inprogress_reg_mask, hwrm_error_recovery_qcfg_output::reset_reg, hwrm_error_recovery_qcfg_output::reset_reg_val, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, u8, and wait_resp().

◆ bnxt_hwrm_func_drv_rgtr()

int bnxt_hwrm_func_drv_rgtr ( struct bnxt * bp)
static

Definition at line 1094 of file bnxt.c.

1095{
1096 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_drv_rgtr_input );
1097 struct hwrm_func_drv_rgtr_input *req;
1098 int rc;
1099
1100 DBGP ( "%s\n", __func__ );
1101 req = ( struct hwrm_func_drv_rgtr_input * ) REQ_DMA_ADDR ( bp );
1102 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_DRV_RGTR, cmd_len );
1103
1104 /* Register with HWRM */
1105 req->enables = FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
1109
1110 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE;
1111 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE;
1112 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE;
1113 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE;
1114
1115 if ( bp->err_rcvry_supported ) {
1118 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY;
1119 req->async_event_fwd[0] |= 1 << ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY;
1120 }
1121
1122 req->os_type = FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER;
1123 req->ver_maj = IPXE_VERSION_MAJOR;
1124 req->ver_min = IPXE_VERSION_MINOR;
1125 req->ver_upd = IPXE_VERSION_UPDATE;
1126 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1127 if ( rc ) {
1128 DBGP ( "- %s ( ): Failed\n", __func__ );
1129 return STATUS_FAILURE;
1130 }
1131
1132 FLAG_SET ( bp->flag_hwrm, VALID_DRIVER_REG );
1133 return STATUS_SUCCESS;
1134}
#define IPXE_VERSION_UPDATE
Definition bnxt.h:33
#define IPXE_VERSION_MINOR
Definition bnxt.h:32
#define VALID_DRIVER_REG
Definition bnxt.h:899
#define IPXE_VERSION_MAJOR
Definition bnxt.h:31
#define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT
Definition bnxt_hsi.h:1835
#define FUNC_DRV_RGTR_REQ_ENABLES_VER
Definition bnxt_hsi.h:1838
#define HWRM_FUNC_DRV_RGTR
Definition bnxt_hsi.h:116
#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
Definition bnxt_hsi.h:1841
#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER
Definition bnxt_hsi.h:1844
#define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT
Definition bnxt_hsi.h:1834
#define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE
Definition bnxt_hsi.h:1831
#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
Definition bnxt_hsi.h:1837

References ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, hwrm_func_drv_rgtr_input::async_event_fwd, bp, DBGP, hwrm_func_drv_rgtr_input::enables, FLAG_SET, hwrm_func_drv_rgtr_input::flags, FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD, FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE, FUNC_DRV_RGTR_REQ_ENABLES_VER, FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE, FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT, FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT, FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER, HWRM_FUNC_DRV_RGTR, hwrm_init(), IPXE_VERSION_MAJOR, IPXE_VERSION_MINOR, IPXE_VERSION_UPDATE, hwrm_func_drv_rgtr_input::os_type, rc, REQ_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_DRIVER_REG, hwrm_func_drv_rgtr_input::ver_maj, hwrm_func_drv_rgtr_input::ver_min, hwrm_func_drv_rgtr_input::ver_upd, and wait_resp().

◆ bnxt_hwrm_func_drv_unrgtr()

int bnxt_hwrm_func_drv_unrgtr ( struct bnxt * bp)
static

Definition at line 1136 of file bnxt.c.

1137{
1138 u16 cmd_len = ( u16 )sizeof ( struct hwrm_func_drv_unrgtr_input );
1139 struct hwrm_func_drv_unrgtr_input *req;
1140 int rc;
1141
1142 DBGP ( "%s\n", __func__ );
1143 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_DRIVER_REG ) ) )
1144 return STATUS_SUCCESS;
1145
1146 req = ( struct hwrm_func_drv_unrgtr_input * ) REQ_DMA_ADDR ( bp );
1147 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_DRV_UNRGTR, cmd_len );
1149 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1150 if ( rc )
1151 return STATUS_FAILURE;
1152
1153 FLAG_RESET ( bp->flag_hwrm, VALID_DRIVER_REG );
1154 return STATUS_SUCCESS;
1155}
#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN
Definition bnxt_hsi.h:1889
#define HWRM_FUNC_DRV_UNRGTR
Definition bnxt_hsi.h:113

References bp, DBGP, FLAG_RESET, FLAG_TEST, hwrm_func_drv_unrgtr_input::flags, FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN, HWRM_FUNC_DRV_UNRGTR, hwrm_init(), rc, REQ_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_DRIVER_REG, and wait_resp().

◆ bnxt_hwrm_set_async_event()

int bnxt_hwrm_set_async_event ( struct bnxt * bp)
static

Definition at line 1157 of file bnxt.c.

1158{
1159 int rc;
1160 u16 idx;
1161
1162 DBGP ( "%s\n", __func__ );
1163 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
1164 idx = bp->nq_ring_id;
1165 else
1166 idx = bp->cq_ring_id;
1167 if ( bp->vf ) {
1168 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_vf_cfg_input );
1169 struct hwrm_func_vf_cfg_input *req;
1170
1171 req = ( struct hwrm_func_vf_cfg_input * ) REQ_DMA_ADDR ( bp );
1172 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_VF_CFG,
1173 cmd_len );
1174 req->enables = VF_CFG_ENABLE_FLAGS;
1175 req->async_event_cr = idx;
1176 req->mtu = bp->mtu;
1177 req->guest_vlan = bp->vlan_id;
1178 memcpy ( ( char * ) &req->dflt_mac_addr[0], bp->mac_addr,
1179 ETH_ALEN );
1180 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1181 } else {
1182 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_cfg_input );
1183 struct hwrm_func_cfg_input *req;
1184
1185 req = ( struct hwrm_func_cfg_input * ) REQ_DMA_ADDR ( bp );
1186 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_CFG, cmd_len );
1187 req->fid = ( u16 ) HWRM_NA_SIGNATURE;
1189 req->async_event_cr = idx;
1190 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1191 }
1192 return rc;
1193}
#define VF_CFG_ENABLE_FLAGS
Definition bnxt.h:1096
#define HWRM_FUNC_VF_CFG
Definition bnxt_hsi.h:102
#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR
Definition bnxt_hsi.h:1551

References hwrm_func_cfg_input::async_event_cr, hwrm_func_vf_cfg_input::async_event_cr, BNXT_FLAG_IS_CHIP_P5_PLUS, bp, DBGP, hwrm_func_vf_cfg_input::dflt_mac_addr, hwrm_func_cfg_input::enables, hwrm_func_vf_cfg_input::enables, ETH_ALEN, hwrm_func_cfg_input::fid, FLAG_TEST, FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR, hwrm_func_vf_cfg_input::guest_vlan, HWRM_FUNC_CFG, HWRM_FUNC_VF_CFG, hwrm_init(), HWRM_NA_SIGNATURE, memcpy(), hwrm_func_vf_cfg_input::mtu, rc, REQ_DMA_ADDR, u16, VF_CFG_ENABLE_FLAGS, and wait_resp().

◆ bnxt_hwrm_cfa_l2_filter_alloc()

int bnxt_hwrm_cfa_l2_filter_alloc ( struct bnxt * bp)
static

Definition at line 1195 of file bnxt.c.

1196{
1197 u16 cmd_len = ( u16 )sizeof ( struct hwrm_cfa_l2_filter_alloc_input );
1200 int rc;
1202 u32 enables;
1203
1204 DBGP ( "%s\n", __func__ );
1205 req = ( struct hwrm_cfa_l2_filter_alloc_input * ) REQ_DMA_ADDR ( bp );
1206 resp = ( struct hwrm_cfa_l2_filter_alloc_output * ) RESP_DMA_ADDR ( bp );
1207 if ( bp->vf )
1212
1213 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_FILTER_ALLOC,
1214 cmd_len );
1215 req->flags = flags;
1216 req->enables = enables;
1217 memcpy ( ( char * ) &req->l2_addr[0], ( char * ) &bp->mac_addr[0],
1218 ETH_ALEN );
1219 memset ( ( char * ) &req->l2_addr_mask[0], 0xff, ETH_ALEN );
1220 if ( !bp->vf ) {
1221 memcpy ( ( char * ) &req->t_l2_addr[0], bp->mac_addr, ETH_ALEN );
1222 memset ( ( char * ) &req->t_l2_addr_mask[0], 0xff, ETH_ALEN );
1223 }
1225 req->src_id = ( u32 ) bp->port_idx;
1226 req->dst_id = bp->vnic_id;
1227 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1228 if ( rc )
1229 return STATUS_FAILURE;
1230
1231 FLAG_SET ( bp->flag_hwrm, VALID_L2_FILTER );
1232 bp->l2_filter_id = resp->l2_filter_id;
1233 return STATUS_SUCCESS;
1234}
#define VALID_L2_FILTER
Definition bnxt.h:907
#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT
Definition bnxt_hsi.h:6562
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
Definition bnxt_hsi.h:6530
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
Definition bnxt_hsi.h:6521
#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
Definition bnxt_hsi.h:6517
#define HWRM_CFA_L2_FILTER_ALLOC
Definition bnxt_hsi.h:172
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
Definition bnxt_hsi.h:6529
#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
Definition bnxt_hsi.h:6544
uint8_t flags
Flags.
Definition ena.h:7

References bp, CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID, CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR, CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK, CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST, CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX, CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT, DBGP, hwrm_cfa_l2_filter_alloc_input::dst_id, hwrm_cfa_l2_filter_alloc_input::enables, ETH_ALEN, FLAG_SET, flags, hwrm_cfa_l2_filter_alloc_input::flags, HWRM_CFA_L2_FILTER_ALLOC, hwrm_init(), hwrm_cfa_l2_filter_alloc_input::l2_addr, hwrm_cfa_l2_filter_alloc_input::l2_addr_mask, hwrm_cfa_l2_filter_alloc_output::l2_filter_id, memcpy(), memset(), rc, REQ_DMA_ADDR, RESP_DMA_ADDR, hwrm_cfa_l2_filter_alloc_input::src_id, hwrm_cfa_l2_filter_alloc_input::src_type, STATUS_FAILURE, STATUS_SUCCESS, hwrm_cfa_l2_filter_alloc_input::t_l2_addr, hwrm_cfa_l2_filter_alloc_input::t_l2_addr_mask, u16, u32, VALID_L2_FILTER, and wait_resp().

◆ bnxt_hwrm_cfa_l2_filter_free()

int bnxt_hwrm_cfa_l2_filter_free ( struct bnxt * bp)
static

Definition at line 1236 of file bnxt.c.

1237{
1238 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_cfa_l2_filter_free_input );
1240 int rc;
1241
1242 DBGP ( "%s\n", __func__ );
1243 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_L2_FILTER ) ) )
1244 return STATUS_SUCCESS;
1245
1246 req = ( struct hwrm_cfa_l2_filter_free_input * ) REQ_DMA_ADDR ( bp );
1247 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_FILTER_FREE,
1248 cmd_len );
1249 req->l2_filter_id = bp->l2_filter_id;
1250 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1251 if ( rc ) {
1252 DBGP ( "- %s ( ): Failed\n", __func__ );
1253 return STATUS_FAILURE;
1254 }
1255
1256 FLAG_RESET ( bp->flag_hwrm, VALID_L2_FILTER );
1257 return STATUS_SUCCESS;
1258}
#define HWRM_CFA_L2_FILTER_FREE
Definition bnxt_hsi.h:173

References bp, DBGP, FLAG_RESET, FLAG_TEST, HWRM_CFA_L2_FILTER_FREE, hwrm_init(), hwrm_cfa_l2_filter_free_input::l2_filter_id, rc, REQ_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_L2_FILTER, and wait_resp().

◆ set_rx_mask()

u32 set_rx_mask ( u32 rx_mask)

Definition at line 1260 of file bnxt.c.

1261{
1262 u32 mask = 0;
1263
1264 if ( !rx_mask )
1265 return mask;
1266
1268 if ( rx_mask != RX_MASK_ACCEPT_NONE ) {
1269 if ( rx_mask & RX_MASK_ACCEPT_MULTICAST )
1271 if ( rx_mask & RX_MASK_ACCEPT_ALL_MULTICAST )
1273 if ( rx_mask & RX_MASK_PROMISCUOUS_MODE )
1275 }
1276 return mask;
1277}
#define RX_MASK_ACCEPT_ALL_MULTICAST
Definition bnxt.h:86
#define RX_MASK_ACCEPT_MULTICAST
Definition bnxt.h:85
#define RX_MASK_PROMISCUOUS_MODE
Definition bnxt.h:89
#define RX_MASK_ACCEPT_NONE
Definition bnxt.h:83
#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
Definition bnxt_hsi.h:6683
#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
Definition bnxt_hsi.h:6681
#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
Definition bnxt_hsi.h:6684
#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
Definition bnxt_hsi.h:6682

References CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST, CFA_L2_SET_RX_MASK_REQ_MASK_BCAST, CFA_L2_SET_RX_MASK_REQ_MASK_MCAST, CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS, RX_MASK_ACCEPT_ALL_MULTICAST, RX_MASK_ACCEPT_MULTICAST, RX_MASK_ACCEPT_NONE, RX_MASK_PROMISCUOUS_MODE, and u32.

Referenced by bnxt_hwrm_set_rx_mask().

◆ bnxt_hwrm_set_rx_mask()

int bnxt_hwrm_set_rx_mask ( struct bnxt * bp,
u32 rx_mask )
static

Definition at line 1279 of file bnxt.c.

1280{
1281 u16 cmd_len = ( u16 )sizeof ( struct hwrm_cfa_l2_set_rx_mask_input );
1283 u32 mask = set_rx_mask ( rx_mask );
1284
1285 req = ( struct hwrm_cfa_l2_set_rx_mask_input * ) REQ_DMA_ADDR ( bp );
1286 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_CFA_L2_SET_RX_MASK,
1287 cmd_len );
1288 req->vnic_id = bp->vnic_id;
1289 req->mask = mask;
1290
1291 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1292}
u32 set_rx_mask(u32 rx_mask)
Definition bnxt.c:1260
#define HWRM_CFA_L2_SET_RX_MASK
Definition bnxt_hsi.h:175

References bp, HWRM_CFA_L2_SET_RX_MASK, hwrm_init(), hwrm_cfa_l2_set_rx_mask_input::mask, REQ_DMA_ADDR, set_rx_mask(), u16, u32, hwrm_cfa_l2_set_rx_mask_input::vnic_id, and wait_resp().

Referenced by bnxt_reset_rx_mask(), and bnxt_set_rx_mask().

◆ bnxt_hwrm_port_phy_qcfg()

int bnxt_hwrm_port_phy_qcfg ( struct bnxt * bp,
u16 idx )
static

Definition at line 1294 of file bnxt.c.

1295{
1296 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_phy_qcfg_input );
1297 struct hwrm_port_phy_qcfg_input *req;
1298 struct hwrm_port_phy_qcfg_output *resp;
1299 int rc;
1300
1301 DBGP ( "%s\n", __func__ );
1302 req = ( struct hwrm_port_phy_qcfg_input * ) REQ_DMA_ADDR ( bp );
1303 resp = ( struct hwrm_port_phy_qcfg_output * ) RESP_DMA_ADDR ( bp );
1304 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_QCFG, cmd_len );
1305 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1306 if ( rc ) {
1307 DBGP ( "- %s ( ): Failed\n", __func__ );
1308 return STATUS_FAILURE;
1309 }
1310
1311 if ( idx & SUPPORT_SPEEDS )
1312 bp->support_speeds = resp->support_speeds;
1313
1314 if ( idx & SUPPORT_SPEEDS2 )
1315 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
1316 bp->auto_link_speeds2_mask = resp->auto_link_speeds2;
1317
1318 if ( idx & DETECT_MEDIA )
1319 bp->media_detect = resp->module_status;
1320
1321 if ( idx & PHY_SPEED )
1322 bp->current_link_speed = resp->link_speed;
1323
1324 if ( idx & PHY_STATUS ) {
1325 if ( resp->link == PORT_PHY_QCFG_RESP_LINK_LINK )
1326 bp->link_status = STATUS_LINK_ACTIVE;
1327 else
1328 bp->link_status = STATUS_LINK_DOWN;
1329 }
1330 return STATUS_SUCCESS;
1331}
#define PHY_STATUS
Definition bnxt.h:206
#define DETECT_MEDIA
Definition bnxt.h:208
#define SUPPORT_SPEEDS
Definition bnxt.h:209
#define SUPPORT_SPEEDS2
Definition bnxt.h:210
#define PHY_SPEED
Definition bnxt.h:207
#define PORT_PHY_QCFG_RESP_LINK_LINK
Definition bnxt_hsi.h:3251
#define HWRM_PORT_PHY_QCFG
Definition bnxt_hsi.h:126

References hwrm_port_phy_qcfg_output::auto_link_speeds2, BNXT_FLAG_LINK_SPEEDS2, bp, DBGP, DETECT_MEDIA, FLAG_TEST, hwrm_init(), HWRM_PORT_PHY_QCFG, hwrm_port_phy_qcfg_output::link, hwrm_port_phy_qcfg_output::link_speed, hwrm_port_phy_qcfg_output::module_status, PHY_SPEED, PHY_STATUS, PORT_PHY_QCFG_RESP_LINK_LINK, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_LINK_ACTIVE, STATUS_LINK_DOWN, STATUS_SUCCESS, SUPPORT_SPEEDS, hwrm_port_phy_qcfg_output::support_speeds, SUPPORT_SPEEDS2, u16, and wait_resp().

Referenced by bnxt_get_link_state(), bnxt_get_phy_link(), bnxt_link_speed_chg_evt(), bnxt_link_speed_evt(), bnxt_port_phy_chg_evt(), and bnxt_query_phy_link().

◆ bnxt_hwrm_nvm_get_variable_req()

int bnxt_hwrm_nvm_get_variable_req ( struct bnxt * bp,
u16 data_len,
u16 option_num,
u16 dimensions,
u16 index_0 )
static

Definition at line 1333 of file bnxt.c.

1335{
1336 u16 cmd_len = ( u16 )sizeof ( struct hwrm_nvm_get_variable_input );
1337 struct hwrm_nvm_get_variable_input *req;
1338
1339 DBGP ( "%s\n", __func__ );
1340 req = ( struct hwrm_nvm_get_variable_input * ) REQ_DMA_ADDR ( bp );
1341 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_NVM_GET_VARIABLE, cmd_len );
1342 req->dest_data_addr = DMA_DMA_ADDR ( bp );
1343 req->data_len = data_len;
1344 req->option_num = option_num;
1345 req->dimensions = dimensions;
1346 req->index_0 = index_0;
1347 return wait_resp ( bp,
1348 HWRM_CMD_FLASH_MULTIPLAYER ( bp->hwrm_cmd_timeout ),
1349 cmd_len, __func__ );
1350}
#define DMA_DMA_ADDR(bp)
Definition bnxt.h:184
#define HWRM_CMD_FLASH_MULTIPLAYER(a)
Definition bnxt.h:137
#define HWRM_NVM_GET_VARIABLE
Definition bnxt_hsi.h:309
uint32_t data_len
Microcode data size (or 0 to indicate 2000 bytes).
Definition ucode.h:15

References bp, data_len, hwrm_nvm_get_variable_input::data_len, DBGP, hwrm_nvm_get_variable_input::dest_data_addr, hwrm_nvm_get_variable_input::dimensions, DMA_DMA_ADDR, HWRM_CMD_FLASH_MULTIPLAYER, hwrm_init(), HWRM_NVM_GET_VARIABLE, hwrm_nvm_get_variable_input::index_0, hwrm_nvm_get_variable_input::option_num, REQ_DMA_ADDR, u16, and wait_resp().

Referenced by bnxt_get_link_speed().

◆ bnxt_get_link_speed()

int bnxt_get_link_speed ( struct bnxt * bp)
static

Definition at line 1352 of file bnxt.c.

1353{
1354 u32 *ptr32 = ( u32 * ) DMA_DMA_ADDR ( bp );
1355
1356 DBGP ( "%s\n", __func__ );
1357 if ( ! ( FLAG_TEST (bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) ) {
1360 1, ( u16 ) bp->port_idx ) != STATUS_SUCCESS )
1361 return STATUS_FAILURE;
1362 bp->link_set = SET_LINK ( *ptr32, SPEED_DRV_MASK, SPEED_DRV_SHIFT );
1365 ( u16 ) bp->port_idx ) != STATUS_SUCCESS )
1366 return STATUS_FAILURE;
1367 bp->link_set |= SET_LINK ( *ptr32, D3_SPEED_FW_MASK,
1369 }
1371 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
1372 return STATUS_FAILURE;
1373 bp->link_set |= SET_LINK ( *ptr32, SPEED_FW_MASK, SPEED_FW_SHIFT );
1376 1, ( u16 )bp->port_idx ) != STATUS_SUCCESS )
1377 return STATUS_FAILURE;
1378 bp->link_set |= SET_LINK ( *ptr32, MEDIA_AUTO_DETECT_MASK,
1380
1381 /* Use LINK_SPEED_FW_xxx which is valid for CHIP_P7 and earlier devices */
1382 switch ( bp->link_set & LINK_SPEED_FW_MASK ) {
1383 case LINK_SPEED_FW_1G:
1385 break;
1386 case LINK_SPEED_FW_2_5G:
1388 break;
1389 case LINK_SPEED_FW_10G:
1391 break;
1392 case LINK_SPEED_FW_25G:
1394 break;
1395 case LINK_SPEED_FW_40G:
1397 break;
1398 case LINK_SPEED_FW_50G:
1400 break;
1403 break;
1404 case LINK_SPEED_FW_100G:
1406 break;
1409 break;
1412 break;
1413 case LINK_SPEED_FW_200G:
1415 break;
1418 break;
1421 break;
1424 break;
1427 break;
1428 default:
1430 break;
1431 }
1432 prn_set_speed ( bp->link_set );
1433 return STATUS_SUCCESS;
1434}
static int bnxt_hwrm_nvm_get_variable_req(struct bnxt *bp, u16 data_len, u16 option_num, u16 dimensions, u16 index_0)
Definition bnxt.c:1333
#define LINK_SPEED_FW_40G
Definition bnxt.h:309
#define LINK_SPEED_FW_1G
Definition bnxt.h:303
#define SET_MEDIUM_SPEED(bp, s)
Definition bnxt.h:117
#define PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM
Definition bnxt.h:358
#define LINK_SPEED_FW_100G_PAM4
Definition bnxt.h:319
#define MEDIUM_SPEED_25GBPS
Definition bnxt.h:101
#define MEDIA_AUTO_DETECT_MASK
Definition bnxt.h:1090
#define D3_SPEED_FW_SHIFT
Definition bnxt.h:1089
#define SET_MEDIUM_DUPLEX(bp, d)
Definition bnxt.h:122
#define MEDIUM_SPEED_400PAM4_112GBPS
Definition bnxt.h:111
#define MEDIUM_SPEED_50PAM4GBPS
Definition bnxt.h:106
#define LINK_SPEED_DRV_NUM
Definition bnxt.h:220
#define LINK_SPEED_FW_AUTONEG
Definition bnxt.h:301
#define MEDIUM_SPEED_200PAM4_112GBPS
Definition bnxt.h:109
#define SET_LINK(p, m, s)
Definition bnxt.h:1082
#define LINK_SPEED_FW_10G
Definition bnxt.h:305
#define MEDIUM_SPEED_100PAM4_112GBPS
Definition bnxt.h:108
#define MEDIUM_SPEED_400PAM4GBPS
Definition bnxt.h:110
#define LINK_SPEED_FW_50G
Definition bnxt.h:311
#define SPEED_DRV_SHIFT
Definition bnxt.h:1085
#define LINK_SPEED_FW_MASK
Definition bnxt.h:299
#define LINK_SPEED_FW_2_5G
Definition bnxt.h:329
#define LINK_SPEED_FW_50G_PAM4
Definition bnxt.h:317
#define D3_LINK_SPEED_FW_NUM
Definition bnxt.h:334
#define LINK_SPEED_FW_NUM
Definition bnxt.h:298
#define MEDIUM_SPEED_100GBPS
Definition bnxt.h:104
#define MEDIUM_FULL_DUPLEX
Definition bnxt.h:119
#define MEDIUM_SPEED_40GBPS
Definition bnxt.h:102
#define SPEED_FW_SHIFT
Definition bnxt.h:1087
#define MEDIUM_SPEED_200GBPS
Definition bnxt.h:105
#define MEDIUM_SPEED_100PAM4GBPS
Definition bnxt.h:107
#define LINK_SPEED_FW_400G_PAM4
Definition bnxt.h:325
#define MEDIUM_SPEED_50GBPS
Definition bnxt.h:103
#define D3_SPEED_FW_MASK
Definition bnxt.h:1088
#define LINK_SPEED_FW_100G
Definition bnxt.h:313
#define LINK_SPEED_FW_200G
Definition bnxt.h:315
#define SPEED_DRV_MASK
Definition bnxt.h:1084
#define LINK_SPEED_FW_200G_PAM4_112
Definition bnxt.h:323
#define LINK_SPEED_FW_100G_PAM4_112
Definition bnxt.h:321
#define MEDIUM_SPEED_1000MBPS
Definition bnxt.h:97
#define MEDIUM_SPEED_10GBPS
Definition bnxt.h:99
#define MEDIUM_SPEED_2500MBPS
Definition bnxt.h:98
#define MEDIUM_SPEED_AUTONEG
Definition bnxt.h:93
#define LINK_SPEED_FW_400G_PAM4_112
Definition bnxt.h:327
#define LINK_SPEED_FW_25G
Definition bnxt.h:307
#define SPEED_FW_MASK
Definition bnxt.h:1086
#define MEDIA_AUTO_DETECT_SHIFT
Definition bnxt.h:1091
#define prn_set_speed(speed)
Definition bnxt_dbg.h:323

References BNXT_FLAG_IS_CHIP_P5_PLUS, bnxt_hwrm_nvm_get_variable_req(), bp, D3_LINK_SPEED_FW_NUM, D3_SPEED_FW_MASK, D3_SPEED_FW_SHIFT, DBGP, DMA_DMA_ADDR, FLAG_TEST, LINK_SPEED_DRV_NUM, LINK_SPEED_FW_100G, LINK_SPEED_FW_100G_PAM4, LINK_SPEED_FW_100G_PAM4_112, LINK_SPEED_FW_10G, LINK_SPEED_FW_1G, LINK_SPEED_FW_200G, LINK_SPEED_FW_200G_PAM4_112, LINK_SPEED_FW_25G, LINK_SPEED_FW_2_5G, LINK_SPEED_FW_400G_PAM4, LINK_SPEED_FW_400G_PAM4_112, LINK_SPEED_FW_40G, LINK_SPEED_FW_50G, LINK_SPEED_FW_50G_PAM4, LINK_SPEED_FW_AUTONEG, LINK_SPEED_FW_MASK, LINK_SPEED_FW_NUM, MEDIA_AUTO_DETECT_MASK, MEDIA_AUTO_DETECT_SHIFT, MEDIUM_FULL_DUPLEX, MEDIUM_SPEED_1000MBPS, MEDIUM_SPEED_100GBPS, MEDIUM_SPEED_100PAM4_112GBPS, MEDIUM_SPEED_100PAM4GBPS, MEDIUM_SPEED_10GBPS, MEDIUM_SPEED_200GBPS, MEDIUM_SPEED_200PAM4_112GBPS, MEDIUM_SPEED_2500MBPS, MEDIUM_SPEED_25GBPS, MEDIUM_SPEED_400PAM4_112GBPS, MEDIUM_SPEED_400PAM4GBPS, MEDIUM_SPEED_40GBPS, MEDIUM_SPEED_50GBPS, MEDIUM_SPEED_50PAM4GBPS, MEDIUM_SPEED_AUTONEG, PORT_CFG_LINK_SETTINGS_MEDIA_AUTO_DETECT_NUM, prn_set_speed, SET_LINK, SET_MEDIUM_DUPLEX, SET_MEDIUM_SPEED, SPEED_DRV_MASK, SPEED_DRV_SHIFT, SPEED_FW_MASK, SPEED_FW_SHIFT, STATUS_FAILURE, STATUS_SUCCESS, u16, and u32.

Referenced by bnxt_query_phy_link().

◆ bnxt_hwrm_backing_store_qcfg()

int bnxt_hwrm_backing_store_qcfg ( struct bnxt * bp)
static

Definition at line 1436 of file bnxt.c.

1437{
1438 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_backing_store_qcfg_input );
1440
1441 DBGP ( "%s\n", __func__ );
1442 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) || bp->vf )
1443 return STATUS_SUCCESS;
1444
1445 req = ( struct hwrm_func_backing_store_qcfg_input * ) REQ_DMA_ADDR ( bp );
1446 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_FUNC_BACKING_STORE_QCFG,
1447 cmd_len );
1448 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1449}
#define HWRM_FUNC_BACKING_STORE_QCFG
Definition bnxt_hsi.h:285

References BNXT_FLAG_IS_CHIP_P5_PLUS, bp, DBGP, FLAG_TEST, HWRM_FUNC_BACKING_STORE_QCFG, hwrm_init(), REQ_DMA_ADDR, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_backing_store_cfg()

int bnxt_hwrm_backing_store_cfg ( struct bnxt * bp)
static

Definition at line 1451 of file bnxt.c.

1452{
1453 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_func_backing_store_cfg_input );
1455
1456 DBGP ( "%s\n", __func__ );
1457 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) || bp->vf )
1458 return STATUS_SUCCESS;
1459
1460 req = ( struct hwrm_func_backing_store_cfg_input * ) REQ_DMA_ADDR ( bp );
1461 hwrm_init ( bp, ( void * )req, ( u16 )HWRM_FUNC_BACKING_STORE_CFG,
1462 cmd_len );
1464 req->enables = 0;
1465 return wait_resp ( bp, HWRM_CMD_WAIT ( 6 ), cmd_len, __func__ );
1466}
#define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE
Definition bnxt_hsi.h:2162
#define HWRM_FUNC_BACKING_STORE_CFG
Definition bnxt_hsi.h:284

References BNXT_FLAG_IS_CHIP_P5_PLUS, bp, DBGP, hwrm_func_backing_store_cfg_input::enables, FLAG_TEST, hwrm_func_backing_store_cfg_input::flags, FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE, HWRM_CMD_WAIT, HWRM_FUNC_BACKING_STORE_CFG, hwrm_init(), REQ_DMA_ADDR, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_queue_qportcfg()

int bnxt_hwrm_queue_qportcfg ( struct bnxt * bp)
static

Definition at line 1468 of file bnxt.c.

1469{
1470 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_queue_qportcfg_input );
1471 struct hwrm_queue_qportcfg_input *req;
1472 struct hwrm_queue_qportcfg_output *resp;
1473 int rc;
1474
1475 DBGP ( "%s\n", __func__ );
1476
1477 req = ( struct hwrm_queue_qportcfg_input * ) REQ_DMA_ADDR ( bp );
1478 resp = ( struct hwrm_queue_qportcfg_output * ) RESP_DMA_ADDR ( bp );
1479 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_QUEUE_QPORTCFG, cmd_len );
1480 req->flags = 0;
1481 req->port_id = bp->port_idx;
1482 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1483 if ( rc ) {
1484 DBGP ( "- %s ( ): Failed\n", __func__ );
1485 return STATUS_FAILURE;
1486 }
1487
1488 bp->queue_id = resp->queue_id0;
1489 return STATUS_SUCCESS;
1490}
#define HWRM_QUEUE_QPORTCFG
Definition bnxt_hsi.h:135

References bp, DBGP, hwrm_queue_qportcfg_input::flags, hwrm_init(), HWRM_QUEUE_QPORTCFG, hwrm_queue_qportcfg_input::port_id, hwrm_queue_qportcfg_output::queue_id0, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_port_mac_cfg()

int bnxt_hwrm_port_mac_cfg ( struct bnxt * bp)
static

Definition at line 1492 of file bnxt.c.

1493{
1494 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_mac_cfg_input );
1495 struct hwrm_port_mac_cfg_input *req;
1496
1497 DBGP ( "%s\n", __func__ );
1498 if ( bp->vf )
1499 return STATUS_SUCCESS;
1500
1501 req = ( struct hwrm_port_mac_cfg_input * ) REQ_DMA_ADDR ( bp );
1502 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_MAC_CFG, cmd_len );
1503 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
1504 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1505}
#define PORT_MAC_CFG_REQ_LPBK_NONE
Definition bnxt_hsi.h:3646
#define HWRM_PORT_MAC_CFG
Definition bnxt_hsi.h:120

References bp, DBGP, hwrm_init(), HWRM_PORT_MAC_CFG, hwrm_port_mac_cfg_input::lpbk, PORT_MAC_CFG_REQ_LPBK_NONE, REQ_DMA_ADDR, STATUS_SUCCESS, u16, and wait_resp().

◆ bnxt_hwrm_port_phy_cfg()

int bnxt_hwrm_port_phy_cfg ( struct bnxt * bp)
static

Definition at line 1507 of file bnxt.c.

1508{
1509 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_port_phy_cfg_input );
1510 struct hwrm_port_phy_cfg_input *req;
1511 u32 flags;
1512 u32 enables = 0;
1518 u8 auto_mode = 0;
1519 u8 auto_pause = 0;
1520 u8 auto_duplex = 0;
1521
1522 DBGP ( "%s\n", __func__ );
1523 req = ( struct hwrm_port_phy_cfg_input * ) REQ_DMA_ADDR ( bp );
1526
1527 switch ( GET_MEDIUM_SPEED ( bp->medium ) ) {
1530 break;
1532 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1535 } else {
1537 }
1538 break;
1540 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1543 } else {
1545 }
1546 break;
1548 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1551 } else {
1553 }
1554 break;
1556 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1559 } else {
1561 }
1562 break;
1564 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1567 } else {
1570 }
1571 break;
1573 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1576 } else {
1578 }
1579 break;
1581 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1584 } else {
1587 }
1588 break;
1590 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1593 }
1594 break;
1596 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1599 } else {
1602 }
1603 break;
1605 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1608 }
1609 break;
1611 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1614 }
1615 break;
1617 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) ) {
1620 }
1621 break;
1622 default:
1628 if ( FLAG_TEST (bp->flags, BNXT_FLAG_LINK_SPEEDS2 ) )
1630 else
1635 auto_link_speed_mask = bp->support_speeds;
1636 auto_link_speeds2_mask = bp->auto_link_speeds2_mask;
1637 break;
1638 }
1639
1640 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_PORT_PHY_CFG, cmd_len );
1641 req->flags = flags;
1642 req->enables = enables;
1643 req->port_id = bp->port_idx;
1644 req->force_link_speed = force_link_speed;
1645 req->force_pam4_link_speed = force_pam4_link_speed;
1646 req->force_link_speeds2 = force_link_speeds2;
1647 req->auto_mode = auto_mode;
1648 req->auto_duplex = auto_duplex;
1649 req->auto_pause = auto_pause;
1650 req->auto_link_speed_mask = auto_link_speed_mask;
1651 req->auto_link_speeds2_mask = auto_link_speeds2_mask;
1652
1653 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1654}
#define GET_MEDIUM_SPEED(m)
Definition bnxt.h:116
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX
Definition bnxt_hsi.h:3110
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB
Definition bnxt_hsi.h:3168
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56
Definition bnxt_hsi.h:3186
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2
Definition bnxt_hsi.h:3080
#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
Definition bnxt_hsi.h:3042
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112
Definition bnxt_hsi.h:3190
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
Definition bnxt_hsi.h:3068
#define HWRM_PORT_PHY_CFG
Definition bnxt_hsi.h:119
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112
Definition bnxt_hsi.h:3191
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56
Definition bnxt_hsi.h:3188
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB
Definition bnxt_hsi.h:3184
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56
Definition bnxt_hsi.h:3187
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB
Definition bnxt_hsi.h:3090
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB
Definition bnxt_hsi.h:3085
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB
Definition bnxt_hsi.h:3091
#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
Definition bnxt_hsi.h:3111
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB
Definition bnxt_hsi.h:3183
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56
Definition bnxt_hsi.h:3189
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
Definition bnxt_hsi.h:3069
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
Definition bnxt_hsi.h:3071
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
Definition bnxt_hsi.h:3067
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112
Definition bnxt_hsi.h:3192
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB
Definition bnxt_hsi.h:3093
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
Definition bnxt_hsi.h:3170
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB
Definition bnxt_hsi.h:3181
#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
Definition bnxt_hsi.h:3107
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB
Definition bnxt_hsi.h:3092
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB
Definition bnxt_hsi.h:3182
#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK
Definition bnxt_hsi.h:3081
#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
Definition bnxt_hsi.h:3102
#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED
Definition bnxt_hsi.h:3078
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB
Definition bnxt_hsi.h:3185
#define PORT_PHY_CFG_REQ_FLAGS_FORCE
Definition bnxt_hsi.h:3044
#define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB
Definition bnxt_hsi.h:3169
#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB
Definition bnxt_hsi.h:3088

References hwrm_port_phy_cfg_input::auto_duplex, hwrm_port_phy_cfg_input::auto_link_speed_mask, hwrm_port_phy_cfg_input::auto_link_speeds2_mask, hwrm_port_phy_cfg_input::auto_mode, hwrm_port_phy_cfg_input::auto_pause, BNXT_FLAG_LINK_SPEEDS2, bp, DBGP, hwrm_port_phy_cfg_input::enables, FLAG_TEST, flags, hwrm_port_phy_cfg_input::flags, hwrm_port_phy_cfg_input::force_link_speed, hwrm_port_phy_cfg_input::force_link_speeds2, hwrm_port_phy_cfg_input::force_pam4_link_speed, GET_MEDIUM_SPEED, hwrm_init(), HWRM_PORT_PHY_CFG, MEDIUM_SPEED_1000MBPS, MEDIUM_SPEED_100GBPS, MEDIUM_SPEED_100PAM4_112GBPS, MEDIUM_SPEED_100PAM4GBPS, MEDIUM_SPEED_10GBPS, MEDIUM_SPEED_200GBPS, MEDIUM_SPEED_200PAM4_112GBPS, MEDIUM_SPEED_25GBPS, MEDIUM_SPEED_400PAM4_112GBPS, MEDIUM_SPEED_400PAM4GBPS, MEDIUM_SPEED_40GBPS, MEDIUM_SPEED_50GBPS, MEDIUM_SPEED_50PAM4GBPS, hwrm_port_phy_cfg_input::port_id, PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH, PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK, PORT_PHY_CFG_REQ_AUTO_PAUSE_RX, PORT_PHY_CFG_REQ_AUTO_PAUSE_TX, PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX, PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK, PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK, PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE, PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE, PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2, PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED, PORT_PHY_CFG_REQ_FLAGS_FORCE, PORT_PHY_CFG_REQ_FLAGS_RESET_PHY, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB, PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56, PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB, PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB, PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB, REQ_DMA_ADDR, u16, u32, u8, and wait_resp().

Referenced by bnxt_query_phy_link().

◆ bnxt_query_phy_link()

int bnxt_query_phy_link ( struct bnxt * bp)
static

Definition at line 1656 of file bnxt.c.

1657{
1659
1660 DBGP ( "%s\n", __func__ );
1661 /* Query Link Status */
1663 return STATUS_FAILURE;
1664
1665 if ( bp->link_status == STATUS_LINK_ACTIVE )
1666 return STATUS_SUCCESS;
1667
1668 /* If VF is set to TRUE, Do not issue the following commands */
1669 if ( bp->vf )
1670 return STATUS_SUCCESS;
1671
1672 /* If multi_host or NPAR, Do not issue bnxt_get_link_speed */
1673 if ( FLAG_TEST ( bp->flags, PORT_PHY_FLAGS ) ) {
1674 dbg_flags ( __func__, bp->flags );
1675 return STATUS_SUCCESS;
1676 }
1677
1678 /* HWRM_NVM_GET_VARIABLE - speed */
1680 return STATUS_FAILURE;
1681
1682 /* Configure link if it is not up */
1684
1685 /* refresh link speed values after bringing link up */
1686 return bnxt_hwrm_port_phy_qcfg ( bp, flag );
1687}
static int bnxt_get_link_speed(struct bnxt *bp)
Definition bnxt.c:1352
static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp)
Definition bnxt.c:1507
static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp, u16 idx)
Definition bnxt.c:1294
#define PORT_PHY_FLAGS
Definition bnxt.h:1078
#define QCFG_PHY_ALL
Definition bnxt.h:211
#define dbg_flags(func, flags)
Definition bnxt_dbg.h:326

References bnxt_get_link_speed(), bnxt_hwrm_port_phy_cfg(), bnxt_hwrm_port_phy_qcfg(), bp, dbg_flags, DBGP, DETECT_MEDIA, flag, FLAG_TEST, PHY_SPEED, PHY_STATUS, PORT_PHY_FLAGS, QCFG_PHY_ALL, STATUS_FAILURE, STATUS_LINK_ACTIVE, STATUS_SUCCESS, and u16.

◆ bnxt_get_phy_link()

int bnxt_get_phy_link ( struct bnxt * bp)
static

Definition at line 1689 of file bnxt.c.

1690{
1691 u16 i;
1693
1694 DBGP ( "%s\n", __func__ );
1695 dbg_chip_info ( bp );
1696 for ( i = 0; i < ( bp->wait_link_timeout / 100 ); i++ ) {
1698 break;
1699
1700 if ( bp->link_status == STATUS_LINK_ACTIVE )
1701 break;
1702
1703// if ( bp->media_detect )
1704// break;
1706 }
1707 dbg_link_state ( bp, ( u32 ) ( ( i + 1 ) * 100 ) );
1708 if ( !bp->er.er_rst_on )
1709 bnxt_set_link ( bp );
1710
1711 return STATUS_SUCCESS;
1712}
#define LINK_POLL_WAIT_TIME
Definition bnxt.h:167
#define dbg_link_state(bp, tmo)
Definition bnxt_dbg.h:663
#define dbg_chip_info(bp)
Definition bnxt_dbg.h:324
void mdelay(unsigned long msecs)
Delay for a fixed number of milliseconds.
Definition timer.c:79

References bnxt_hwrm_port_phy_qcfg(), bnxt_set_link(), bp, dbg_chip_info, dbg_link_state, DBGP, DETECT_MEDIA, flag, LINK_POLL_WAIT_TIME, mdelay(), PHY_SPEED, PHY_STATUS, STATUS_LINK_ACTIVE, STATUS_SUCCESS, u16, and u32.

◆ bnxt_hwrm_stat_ctx_alloc()

int bnxt_hwrm_stat_ctx_alloc ( struct bnxt * bp)
static

Definition at line 1714 of file bnxt.c.

1715{
1716 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_stat_ctx_alloc_input );
1717 struct hwrm_stat_ctx_alloc_input *req;
1718 struct hwrm_stat_ctx_alloc_output *resp;
1719 int rc;
1720
1721 DBGP ( "%s\n", __func__ );
1722 req = ( struct hwrm_stat_ctx_alloc_input * ) REQ_DMA_ADDR ( bp );
1723 resp = ( struct hwrm_stat_ctx_alloc_output * ) RESP_DMA_ADDR ( bp );
1724 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_STAT_CTX_ALLOC, cmd_len );
1725 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1726 if ( rc ) {
1727 DBGP ( "- %s ( ): Failed\n", __func__ );
1728 return STATUS_FAILURE;
1729 }
1730
1731 FLAG_SET ( bp->flag_hwrm, VALID_STAT_CTX );
1732 bp->stat_ctx_id = ( u16 )resp->stat_ctx_id;
1733 return STATUS_SUCCESS;
1734}
#define VALID_STAT_CTX
Definition bnxt.h:900
#define HWRM_STAT_CTX_ALLOC
Definition bnxt_hsi.h:191

References bp, DBGP, FLAG_SET, hwrm_init(), HWRM_STAT_CTX_ALLOC, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, hwrm_stat_ctx_alloc_output::stat_ctx_id, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_STAT_CTX, and wait_resp().

◆ bnxt_hwrm_stat_ctx_free()

int bnxt_hwrm_stat_ctx_free ( struct bnxt * bp)
static

Definition at line 1736 of file bnxt.c.

1737{
1738 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_stat_ctx_free_input );
1739 struct hwrm_stat_ctx_free_input *req;
1740 int rc;
1741
1742 DBGP ( "%s\n", __func__ );
1743 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_STAT_CTX ) ) )
1744 return STATUS_SUCCESS;
1745
1746 req = ( struct hwrm_stat_ctx_free_input * ) REQ_DMA_ADDR ( bp );
1747 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_STAT_CTX_FREE, cmd_len );
1748 req->stat_ctx_id = ( u32 ) bp->stat_ctx_id;
1749 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1750 if ( rc ) {
1751 DBGP ( "- %s ( ): Failed\n", __func__ );
1752 return STATUS_FAILURE;
1753 }
1754
1755 FLAG_RESET ( bp->flag_hwrm, VALID_STAT_CTX );
1756 return STATUS_SUCCESS;
1757}
#define HWRM_STAT_CTX_FREE
Definition bnxt_hsi.h:192

References bp, DBGP, FLAG_RESET, FLAG_TEST, hwrm_init(), HWRM_STAT_CTX_FREE, rc, REQ_DMA_ADDR, hwrm_stat_ctx_free_input::stat_ctx_id, STATUS_FAILURE, STATUS_SUCCESS, u16, u32, VALID_STAT_CTX, and wait_resp().

◆ bnxt_hwrm_ring_free_grp()

int bnxt_hwrm_ring_free_grp ( struct bnxt * bp)
static

Definition at line 1759 of file bnxt.c.

1760{
1761 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_grp_free_input );
1762 struct hwrm_ring_grp_free_input *req;
1763 int rc;
1764
1765 DBGP ( "%s\n", __func__ );
1766 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_GRP ) ) )
1767 return STATUS_SUCCESS;
1768
1769 req = ( struct hwrm_ring_grp_free_input * ) REQ_DMA_ADDR ( bp );
1770 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_GRP_FREE, cmd_len );
1771 req->ring_group_id = ( u32 ) bp->ring_grp_id;
1772 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1773 if ( rc ) {
1774 DBGP ( "- %s ( ): Failed\n", __func__ );
1775 return STATUS_FAILURE;
1776 }
1777
1778 FLAG_RESET ( bp->flag_hwrm, VALID_RING_GRP );
1779 return STATUS_SUCCESS;
1780}
#define VALID_RING_GRP
Definition bnxt.h:904
#define HWRM_RING_GRP_FREE
Definition bnxt_hsi.h:167

References bp, DBGP, FLAG_RESET, FLAG_TEST, hwrm_init(), HWRM_RING_GRP_FREE, rc, REQ_DMA_ADDR, hwrm_ring_grp_free_input::ring_group_id, STATUS_FAILURE, STATUS_SUCCESS, u16, u32, VALID_RING_GRP, and wait_resp().

◆ bnxt_hwrm_ring_alloc_grp()

int bnxt_hwrm_ring_alloc_grp ( struct bnxt * bp)
static

Definition at line 1782 of file bnxt.c.

1783{
1784 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_grp_alloc_input );
1785 struct hwrm_ring_grp_alloc_input *req;
1786 struct hwrm_ring_grp_alloc_output *resp;
1787 int rc;
1788
1789 DBGP ( "%s\n", __func__ );
1790 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) )
1791 return STATUS_SUCCESS;
1792
1793 req = ( struct hwrm_ring_grp_alloc_input * ) REQ_DMA_ADDR ( bp );
1794 resp = ( struct hwrm_ring_grp_alloc_output * ) RESP_DMA_ADDR ( bp );
1795 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_GRP_ALLOC, cmd_len );
1796 req->cr = bp->cq_ring_id;
1797 req->rr = bp->rx_ring_id;
1798 req->ar = ( u16 )HWRM_NA_SIGNATURE;
1799 if ( bp->vf )
1800 req->sc = bp->stat_ctx_id;
1801
1802 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1803 if ( rc ) {
1804 DBGP ( "- %s ( ): Failed\n", __func__ );
1805 return STATUS_FAILURE;
1806 }
1807
1808 FLAG_SET ( bp->flag_hwrm, VALID_RING_GRP );
1809 bp->ring_grp_id = ( u16 ) resp->ring_group_id;
1810 return STATUS_SUCCESS;
1811}
#define HWRM_RING_GRP_ALLOC
Definition bnxt_hsi.h:166

References hwrm_ring_grp_alloc_input::ar, BNXT_FLAG_IS_CHIP_P5_PLUS, bp, hwrm_ring_grp_alloc_input::cr, DBGP, FLAG_SET, FLAG_TEST, hwrm_init(), HWRM_NA_SIGNATURE, HWRM_RING_GRP_ALLOC, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, hwrm_ring_grp_alloc_output::ring_group_id, hwrm_ring_grp_alloc_input::rr, hwrm_ring_grp_alloc_input::sc, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_RING_GRP, and wait_resp().

◆ bnxt_hwrm_ring_free()

int bnxt_hwrm_ring_free ( struct bnxt * bp,
u16 ring_id,
u8 ring_type )

Definition at line 1813 of file bnxt.c.

1814{
1815 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_ring_free_input );
1816 struct hwrm_ring_free_input *req;
1817
1818 DBGP ( "%s\n", __func__ );
1819 req = ( struct hwrm_ring_free_input * ) REQ_DMA_ADDR ( bp );
1820 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_FREE, cmd_len );
1821 req->ring_type = ring_type;
1822 req->ring_id = ring_id;
1823 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1824}
#define HWRM_RING_FREE
Definition bnxt_hsi.h:161

References bp, DBGP, hwrm_init(), HWRM_RING_FREE, REQ_DMA_ADDR, hwrm_ring_free_input::ring_id, hwrm_ring_free_input::ring_type, u16, u8, and wait_resp().

◆ bnxt_hwrm_ring_alloc()

int bnxt_hwrm_ring_alloc ( struct bnxt * bp,
u8 type )
static

Definition at line 1826 of file bnxt.c.

1827{
1828 u16 cmd_len = ( u16 )sizeof ( struct hwrm_ring_alloc_input );
1829 struct hwrm_ring_alloc_input *req;
1830 struct hwrm_ring_alloc_output *resp;
1831 int rc;
1832
1833 DBGP ( "%s\n", __func__ );
1834 req = ( struct hwrm_ring_alloc_input * ) REQ_DMA_ADDR ( bp );
1835 resp = ( struct hwrm_ring_alloc_output * ) RESP_DMA_ADDR ( bp );
1836 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_RING_ALLOC, cmd_len );
1837 req->ring_type = type;
1838 switch ( type ) {
1840 req->page_size = LM_PAGE_BITS ( 12 );
1841 req->int_mode = BNXT_CQ_INTR_MODE ( ( (FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P7) ) || bp->vf ) );
1842 req->length = ( u32 ) bp->nq.ring_cnt;
1843 req->logical_id = 0xFFFF; // Required value for Thor FW?
1844 req->page_tbl_addr = NQ_DMA_ADDR ( bp );
1845 break;
1847 req->page_size = LM_PAGE_BITS ( 8 );
1848 req->int_mode = BNXT_CQ_INTR_MODE ( bp->vf );
1849 req->length = ( u32 ) bp->cq.ring_cnt;
1850 req->page_tbl_addr = CQ_DMA_ADDR ( bp );
1851 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1852 break;
1854 req->nq_ring_id = bp->nq_ring_id;
1855 req->cq_handle = ( u64 ) bp->nq_ring_id;
1856 break;
1858 req->page_size = LM_PAGE_BITS ( 8 );
1859 req->int_mode = RING_ALLOC_REQ_INT_MODE_POLL;
1860 req->length = ( u32 ) bp->tx.ring_cnt;
1861 req->queue_id = ( u16 ) bp->queue_id;
1862 req->stat_ctx_id = ( u32 ) bp->stat_ctx_id;
1863 req->cmpl_ring_id = bp->cq_ring_id;
1864 req->page_tbl_addr = TX_DMA_ADDR ( bp );
1865 break;
1867 req->page_size = LM_PAGE_BITS ( 8 );
1868 req->int_mode = RING_ALLOC_REQ_INT_MODE_POLL;
1869 req->length = ( u32 ) bp->rx.ring_cnt;
1870 req->stat_ctx_id = ( u32 ) STAT_CTX_ID;
1871 req->cmpl_ring_id = bp->cq_ring_id;
1872 req->page_tbl_addr = RX_DMA_ADDR ( bp );
1873 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1874 break;
1875 req->queue_id = ( u16 ) RX_RING_QID;
1876 req->rx_buf_size = MAX_ETHERNET_PACKET_BUFFER_SIZE;
1878 break;
1879 default:
1880 return STATUS_SUCCESS;
1881 }
1882 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
1883 if ( rc ) {
1884 DBGP ( "- %s ( ): Failed, type = %x\n", __func__, type );
1885 return STATUS_FAILURE;
1886 }
1887
1889 FLAG_SET ( bp->flag_hwrm, VALID_RING_CQ );
1890 bp->cq_ring_id = resp->ring_id;
1891 } else if ( type == RING_ALLOC_REQ_RING_TYPE_TX ) {
1892 FLAG_SET ( bp->flag_hwrm, VALID_RING_TX );
1893 bp->tx_ring_id = resp->ring_id;
1894 } else if ( type == RING_ALLOC_REQ_RING_TYPE_RX ) {
1895 FLAG_SET ( bp->flag_hwrm, VALID_RING_RX );
1896 bp->rx_ring_id = resp->ring_id;
1897 } else if ( type == RING_ALLOC_REQ_RING_TYPE_NQ ) {
1898 FLAG_SET ( bp->flag_hwrm, VALID_RING_NQ );
1899 bp->nq_ring_id = resp->ring_id;
1900 }
1901 DBGP ( "- %s ( ): , type = %x, ring_id = %x\n", __func__, type, resp->ring_id );
1902 return STATUS_SUCCESS;
1903}
#define NQ_DMA_ADDR(bp)
Definition bnxt.h:178
#define VALID_RING_NQ
Definition bnxt.h:908
#define STAT_CTX_ID
Definition bnxt.h:175
#define BNXT_CQ_INTR_MODE(vf)
Definition bnxt.h:163
#define RX_DMA_ADDR(bp)
Definition bnxt.h:181
#define VALID_RING_RX
Definition bnxt.h:903
#define TX_DMA_ADDR(bp)
Definition bnxt.h:180
#define VALID_RING_TX
Definition bnxt.h:902
#define VALID_RING_CQ
Definition bnxt.h:901
#define LM_PAGE_BITS(a)
Definition bnxt.h:159
#define RX_RING_QID
Definition bnxt.h:174
#define HWRM_RING_ALLOC
Definition bnxt_hsi.h:160
#define RING_ALLOC_REQ_INT_MODE_POLL
Definition bnxt_hsi.h:6270
#define RING_ALLOC_REQ_RING_TYPE_RX
Definition bnxt_hsi.h:6216
#define RING_ALLOC_REQ_RING_TYPE_NQ
Definition bnxt_hsi.h:6219
#define RING_ALLOC_REQ_RING_TYPE_TX
Definition bnxt_hsi.h:6215
#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL
Definition bnxt_hsi.h:6214
#define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID
Definition bnxt_hsi.h:6211
#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
Definition bnxt_hsi.h:6212
uint32_t type
Operating system type.
Definition ena.h:1

References BNXT_CQ_INTR_MODE, BNXT_FLAG_IS_CHIP_P5_PLUS, BNXT_FLAG_IS_CHIP_P7, bp, hwrm_ring_alloc_input::cmpl_ring_id, CQ_DMA_ADDR, hwrm_ring_alloc_input::cq_handle, DBGP, hwrm_ring_alloc_input::enables, FLAG_SET, FLAG_TEST, hwrm_init(), HWRM_RING_ALLOC, hwrm_ring_alloc_input::int_mode, hwrm_ring_alloc_input::length, LM_PAGE_BITS, hwrm_ring_alloc_input::logical_id, MAX_ETHERNET_PACKET_BUFFER_SIZE, NQ_DMA_ADDR, hwrm_ring_alloc_input::nq_ring_id, hwrm_ring_alloc_input::page_size, hwrm_ring_alloc_input::page_tbl_addr, hwrm_ring_alloc_input::queue_id, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID, RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID, RING_ALLOC_REQ_INT_MODE_POLL, RING_ALLOC_REQ_RING_TYPE_L2_CMPL, RING_ALLOC_REQ_RING_TYPE_NQ, RING_ALLOC_REQ_RING_TYPE_RX, RING_ALLOC_REQ_RING_TYPE_TX, hwrm_ring_alloc_output::ring_id, hwrm_ring_alloc_input::ring_type, hwrm_ring_alloc_input::rx_buf_size, RX_DMA_ADDR, RX_RING_QID, STAT_CTX_ID, hwrm_ring_alloc_input::stat_ctx_id, STATUS_FAILURE, STATUS_SUCCESS, TX_DMA_ADDR, type, u16, u32, u8, VALID_RING_CQ, VALID_RING_NQ, VALID_RING_RX, VALID_RING_TX, and wait_resp().

Referenced by bnxt_hwrm_ring_alloc_cq(), bnxt_hwrm_ring_alloc_nq(), bnxt_hwrm_ring_alloc_rx(), and bnxt_hwrm_ring_alloc_tx().

◆ bnxt_hwrm_ring_alloc_cq()

int bnxt_hwrm_ring_alloc_cq ( struct bnxt * bp)
static

Definition at line 1905 of file bnxt.c.

1906{
1907 DBGP ( "%s\n", __func__ );
1909}
static int bnxt_hwrm_ring_alloc(struct bnxt *bp, u8 type)
Definition bnxt.c:1826

References bnxt_hwrm_ring_alloc(), bp, DBGP, and RING_ALLOC_REQ_RING_TYPE_L2_CMPL.

◆ bnxt_hwrm_ring_alloc_tx()

int bnxt_hwrm_ring_alloc_tx ( struct bnxt * bp)
static

Definition at line 1911 of file bnxt.c.

1912{
1913 DBGP ( "%s\n", __func__ );
1915}

References bnxt_hwrm_ring_alloc(), bp, DBGP, and RING_ALLOC_REQ_RING_TYPE_TX.

◆ bnxt_hwrm_ring_alloc_rx()

int bnxt_hwrm_ring_alloc_rx ( struct bnxt * bp)
static

Definition at line 1917 of file bnxt.c.

1918{
1919 DBGP ( "%s\n", __func__ );
1921}

References bnxt_hwrm_ring_alloc(), bp, DBGP, and RING_ALLOC_REQ_RING_TYPE_RX.

◆ bnxt_hwrm_ring_free_cq()

int bnxt_hwrm_ring_free_cq ( struct bnxt * bp)
static

Definition at line 1923 of file bnxt.c.

1924{
1925 int ret = STATUS_SUCCESS;
1926
1927 DBGP ( "%s\n", __func__ );
1928 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_CQ ) ) )
1929 return ret;
1930
1931 ret = RING_FREE ( bp, bp->cq_ring_id, RING_FREE_REQ_RING_TYPE_L2_CMPL );
1932 if ( ret == STATUS_SUCCESS )
1933 FLAG_RESET ( bp->flag_hwrm, VALID_RING_CQ );
1934
1935 return ret;
1936}
#define RING_FREE(bp, rid, flag)
Definition bnxt.h:1081
#define RING_FREE_REQ_RING_TYPE_L2_CMPL
Definition bnxt_hsi.h:6296

References bp, DBGP, FLAG_RESET, FLAG_TEST, RING_FREE, RING_FREE_REQ_RING_TYPE_L2_CMPL, STATUS_SUCCESS, and VALID_RING_CQ.

◆ bnxt_hwrm_ring_free_tx()

int bnxt_hwrm_ring_free_tx ( struct bnxt * bp)
static

Definition at line 1938 of file bnxt.c.

1939{
1940 int ret = STATUS_SUCCESS;
1941
1942 DBGP ( "%s\n", __func__ );
1943 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_TX ) ) )
1944 return ret;
1945
1946 ret = RING_FREE ( bp, bp->tx_ring_id, RING_FREE_REQ_RING_TYPE_TX );
1947 if ( ret == STATUS_SUCCESS )
1948 FLAG_RESET ( bp->flag_hwrm, VALID_RING_TX );
1949
1950 return ret;
1951}
#define RING_FREE_REQ_RING_TYPE_TX
Definition bnxt_hsi.h:6297

References bp, DBGP, FLAG_RESET, FLAG_TEST, RING_FREE, RING_FREE_REQ_RING_TYPE_TX, STATUS_SUCCESS, and VALID_RING_TX.

◆ bnxt_hwrm_ring_free_rx()

int bnxt_hwrm_ring_free_rx ( struct bnxt * bp)
static

Definition at line 1953 of file bnxt.c.

1954{
1955 int ret = STATUS_SUCCESS;
1956
1957 DBGP ( "%s\n", __func__ );
1958 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_RX ) ) )
1959 return ret;
1960
1961 ret = RING_FREE ( bp, bp->rx_ring_id, RING_FREE_REQ_RING_TYPE_RX );
1962 if ( ret == STATUS_SUCCESS )
1963 FLAG_RESET ( bp->flag_hwrm, VALID_RING_RX );
1964
1965 return ret;
1966}
#define RING_FREE_REQ_RING_TYPE_RX
Definition bnxt_hsi.h:6298

References bp, DBGP, FLAG_RESET, FLAG_TEST, RING_FREE, RING_FREE_REQ_RING_TYPE_RX, STATUS_SUCCESS, and VALID_RING_RX.

◆ bnxt_hwrm_ring_alloc_nq()

int bnxt_hwrm_ring_alloc_nq ( struct bnxt * bp)
static

◆ bnxt_hwrm_ring_free_nq()

int bnxt_hwrm_ring_free_nq ( struct bnxt * bp)
static

Definition at line 1975 of file bnxt.c.

1976{
1977 int ret = STATUS_SUCCESS;
1978
1979 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
1980 return STATUS_SUCCESS;
1981
1982 DBGP ( "%s\n", __func__ );
1983 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_RING_NQ ) ) )
1984 return ret;
1985
1986 ret = RING_FREE ( bp, bp->nq_ring_id, RING_FREE_REQ_RING_TYPE_NQ );
1987 if ( ret == STATUS_SUCCESS )
1988 FLAG_RESET ( bp->flag_hwrm, VALID_RING_NQ );
1989
1990 return ret;
1991}
#define RING_FREE_REQ_RING_TYPE_NQ
Definition bnxt_hsi.h:6301

References BNXT_FLAG_IS_CHIP_P5_PLUS, bp, DBGP, FLAG_RESET, FLAG_TEST, RING_FREE, RING_FREE_REQ_RING_TYPE_NQ, STATUS_SUCCESS, and VALID_RING_NQ.

◆ bnxt_hwrm_vnic_alloc()

int bnxt_hwrm_vnic_alloc ( struct bnxt * bp)
static

Definition at line 1993 of file bnxt.c.

1994{
1995 u16 cmd_len = ( u16 )sizeof ( struct hwrm_vnic_alloc_input );
1996 struct hwrm_vnic_alloc_input *req;
1997 struct hwrm_vnic_alloc_output *resp;
1998 int rc;
1999
2000 DBGP ( "%s\n", __func__ );
2001 req = ( struct hwrm_vnic_alloc_input * ) REQ_DMA_ADDR ( bp );
2002 resp = ( struct hwrm_vnic_alloc_output * ) RESP_DMA_ADDR ( bp );
2003 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_ALLOC, cmd_len );
2004 req->flags = VNIC_ALLOC_REQ_FLAGS_DEFAULT;
2005 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
2006 if ( rc ) {
2007 DBGP ( "- %s ( ): Failed\n", __func__ );
2008 return STATUS_FAILURE;
2009 }
2010
2011 FLAG_SET ( bp->flag_hwrm, VALID_VNIC_ID );
2012 bp->vnic_id = resp->vnic_id;
2013 return STATUS_SUCCESS;
2014}
#define VALID_VNIC_ID
Definition bnxt.h:905
#define VNIC_ALLOC_REQ_FLAGS_DEFAULT
Definition bnxt_hsi.h:5769
#define HWRM_VNIC_ALLOC
Definition bnxt_hsi.h:149

References bp, DBGP, FLAG_SET, hwrm_vnic_alloc_input::flags, hwrm_init(), HWRM_VNIC_ALLOC, rc, REQ_DMA_ADDR, RESP_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_VNIC_ID, VNIC_ALLOC_REQ_FLAGS_DEFAULT, hwrm_vnic_alloc_output::vnic_id, and wait_resp().

◆ bnxt_hwrm_vnic_free()

int bnxt_hwrm_vnic_free ( struct bnxt * bp)
static

Definition at line 2016 of file bnxt.c.

2017{
2018 u16 cmd_len = ( u16 )sizeof ( struct hwrm_vnic_free_input );
2019 struct hwrm_vnic_free_input *req;
2020 int rc;
2021
2022 DBGP ( "%s\n", __func__ );
2023 if ( ! ( FLAG_TEST ( bp->flag_hwrm, VALID_VNIC_ID ) ) )
2024 return STATUS_SUCCESS;
2025
2026 req = ( struct hwrm_vnic_free_input * ) REQ_DMA_ADDR ( bp );
2027 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_FREE, cmd_len );
2028 req->vnic_id = bp->vnic_id;
2029 rc = wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
2030 if ( rc ) {
2031 DBGP ( "- %s ( ): Failed\n", __func__ );
2032 return STATUS_FAILURE;
2033 }
2034
2035 FLAG_RESET ( bp->flag_hwrm, VALID_VNIC_ID );
2036 return STATUS_SUCCESS;
2037}
#define HWRM_VNIC_FREE
Definition bnxt_hsi.h:150

References bp, DBGP, FLAG_RESET, FLAG_TEST, hwrm_init(), HWRM_VNIC_FREE, rc, REQ_DMA_ADDR, STATUS_FAILURE, STATUS_SUCCESS, u16, VALID_VNIC_ID, hwrm_vnic_free_input::vnic_id, and wait_resp().

◆ bnxt_hwrm_vnic_cfg()

int bnxt_hwrm_vnic_cfg ( struct bnxt * bp)
static

Definition at line 2039 of file bnxt.c.

2040{
2041 u16 cmd_len = ( u16 ) sizeof ( struct hwrm_vnic_cfg_input );
2042 struct hwrm_vnic_cfg_input *req;
2043
2044 DBGP ( "%s\n", __func__ );
2045 req = ( struct hwrm_vnic_cfg_input * ) REQ_DMA_ADDR ( bp );
2046 hwrm_init ( bp, ( void * ) req, ( u16 ) HWRM_VNIC_CFG, cmd_len );
2047 req->enables = VNIC_CFG_REQ_ENABLES_MRU;
2048 req->mru = bp->mtu;
2049
2050 if ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) {
2051 req->enables |= ( VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
2053 req->default_rx_ring_id = bp->rx_ring_id;
2054 req->default_cmpl_ring_id = bp->cq_ring_id;
2055 } else {
2056 req->enables |= VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP;
2057 req->dflt_ring_grp = bp->ring_grp_id;
2058 }
2059
2060 req->vnic_id = bp->vnic_id;
2061 return wait_resp ( bp, bp->hwrm_cmd_timeout, cmd_len, __func__ );
2062}
#define HWRM_VNIC_CFG
Definition bnxt_hsi.h:151
#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
Definition bnxt_hsi.h:5821
#define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID
Definition bnxt_hsi.h:5827
#define VNIC_CFG_REQ_ENABLES_MRU
Definition bnxt_hsi.h:5825
#define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID
Definition bnxt_hsi.h:5826

References BNXT_FLAG_IS_CHIP_P5_PLUS, bp, DBGP, hwrm_vnic_cfg_input::default_cmpl_ring_id, hwrm_vnic_cfg_input::default_rx_ring_id, hwrm_vnic_cfg_input::dflt_ring_grp, hwrm_vnic_cfg_input::enables, FLAG_TEST, hwrm_init(), HWRM_VNIC_CFG, hwrm_vnic_cfg_input::mru, REQ_DMA_ADDR, u16, VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID, VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID, VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP, VNIC_CFG_REQ_ENABLES_MRU, hwrm_vnic_cfg_input::vnic_id, and wait_resp().

◆ bnxt_set_rx_mask()

int bnxt_set_rx_mask ( struct bnxt * bp)
static

Definition at line 2064 of file bnxt.c.

2065{
2066 return bnxt_hwrm_set_rx_mask ( bp, RX_MASK );
2067}
static int bnxt_hwrm_set_rx_mask(struct bnxt *bp, u32 rx_mask)
Definition bnxt.c:1279
#define RX_MASK
Definition bnxt.h:168

References bnxt_hwrm_set_rx_mask(), bp, and RX_MASK.

◆ bnxt_reset_rx_mask()

int bnxt_reset_rx_mask ( struct bnxt * bp)
static

Definition at line 2069 of file bnxt.c.

2070{
2071 return bnxt_hwrm_set_rx_mask ( bp, 0 );
2072}

References bnxt_hwrm_set_rx_mask(), and bp.

◆ bnxt_get_link_state()

int bnxt_get_link_state ( struct bnxt * bp)
static

Definition at line 2074 of file bnxt.c.

2075{
2076 int rc = 0;
2077
2078 DBGP ( "%s \n", __func__ );
2080
2081 return rc;
2082}

References bnxt_hwrm_port_phy_qcfg(), bp, DBGP, PHY_STATUS, and rc.

◆ bnxt_hwrm_run()

int bnxt_hwrm_run ( hwrm_func_t cmds[],
struct bnxt * bp,
int flag )

Definition at line 2151 of file bnxt.c.

2152{
2153 hwrm_func_t *ptr;
2154 int ret;
2155 u8 Status = 0;
2156
2157 for ( ptr = cmds; *ptr; ++ptr ) {
2158 memset ( ( void * ) REQ_DMA_ADDR ( bp ), 0, REQ_BUFFER_SIZE );
2159 memset ( ( void * ) RESP_DMA_ADDR ( bp ), 0, RESP_BUFFER_SIZE );
2160 ret = ( *ptr ) ( bp );
2161 if ( ret ) {
2162 DBGP ( "- %s ( ): Failed\n", __func__ );
2164
2165 // Initialization path failure,
2166 // return failure immediately
2167 // else cleanup the resources
2168 if ( flag )
2169 return STATUS_FAILURE;
2170 }
2171 }
2172 return Status;
2173}
int(* hwrm_func_t)(struct bnxt *bp)
Definition bnxt.c:2084
PXENV_STATUS_t Status
PXE status code.
Definition pxe_api.h:0

References bp, DBGP, flag, memset(), REQ_BUFFER_SIZE, REQ_DMA_ADDR, RESP_BUFFER_SIZE, RESP_DMA_ADDR, Status, STATUS_FAILURE, and u8.

◆ bnxt_open()

int bnxt_open ( struct net_device * dev)
static

Definition at line 2181 of file bnxt.c.

2182{
2183 struct bnxt *bp = dev->priv;
2184
2185 DBGP ( "%s\n", __func__ );
2186
2187 /* Allocate and Initialise device specific parameters */
2188 if ( bnxt_alloc_rings_mem ( bp ) != 0 ) {
2189 DBGP ( "- %s ( ): bnxt_alloc_rings_mem Failed\n", __func__ );
2190 return -ENOMEM;
2191 }
2192
2193 bnxt_mm_nic ( bp );
2194
2195 if ( bnxt_up_chip ( bp ) != 0 ) {
2196 DBGP ( "- %s ( ): bnxt_up_chip Failed\n", __func__ );
2197 goto err_bnxt_open;
2198 }
2199
2200 if ( bnxt_up_nic ( bp ) != 0 ) {
2201 DBGP ( "- %s ( ): bnxt_up_nic\n", __func__);
2202 goto err_bnxt_open;
2203 }
2204
2205 return 0;
2206
2207err_bnxt_open:
2208 bnxt_down_nic ( bp );
2209
2211
2212 return -1;
2213}
int bnxt_alloc_rings_mem(struct bnxt *bp)
Definition bnxt.c:636
#define bnxt_up_chip(bp)
Definition bnxt.c:2176
#define bnxt_down_nic(bp)
Definition bnxt.c:2177
void bnxt_mm_nic(struct bnxt *bp)
Definition bnxt.c:541
#define bnxt_up_nic(bp)
Definition bnxt.c:2178

References bnxt_alloc_rings_mem(), bnxt_down_nic, bnxt_free_rings_mem(), bnxt_mm_nic(), bnxt_up_chip, bnxt_up_nic, bp, DBGP, bnxt::dev, ENOMEM, and net_device::priv.

◆ bnxt_tx_adjust_pkt()

void bnxt_tx_adjust_pkt ( struct bnxt * bp,
struct io_buffer * iob )
static

Definition at line 2215 of file bnxt.c.

2216{
2217 u16 prev_len = iob_len ( iob );
2218
2219 bp->vlan_tx = bnxt_get_pkt_vlan ( ( char * )iob->data );
2220 if ( !bp->vlan_tx && bp->vlan_id )
2221 bnxt_add_vlan ( iob, bp->vlan_id );
2222
2223 dbg_tx_vlan ( bp, ( char * )iob->data, prev_len, iob_len ( iob ) );
2224 if ( iob_len ( iob ) != prev_len )
2225 prev_len = iob_len ( iob );
2226
2227}
void bnxt_add_vlan(struct io_buffer *iob, u16 vlan)
Definition bnxt.c:265
static u16 bnxt_get_pkt_vlan(char *src)
Definition bnxt.c:279
#define dbg_tx_vlan(bp, src, plen, len)
Definition bnxt_dbg.h:564

References bnxt_add_vlan(), bnxt_get_pkt_vlan(), bp, io_buffer::data, dbg_tx_vlan, iob_len(), and u16.

Referenced by bnxt_tx().

◆ bnxt_tx()

int bnxt_tx ( struct net_device * dev,
struct io_buffer * iob )
static

Definition at line 2229 of file bnxt.c.

2230{
2231 struct bnxt *bp = dev->priv;
2232 u16 len, entry;
2233 physaddr_t mapping;
2234
2235 if ( bp->er.er_rst_on ) {
2236 /* Error recovery has been initiated */
2237 return -EBUSY;
2238 }
2239
2240 if ( bnxt_tx_avail ( bp ) < 1 ) {
2241 DBGP ( "- %s ( ): Failed no bd's available\n", __func__ );
2242 return -ENOBUFS;
2243 }
2244
2245 mapping = iob_dma ( iob );
2246 bnxt_tx_adjust_pkt ( bp, iob );
2247 entry = bp->tx.prod_id;
2248 len = iob_len ( iob );
2249 bp->tx.iob[entry] = iob;
2250 bnxt_set_txq ( bp, entry, mapping, len );
2251 entry = NEXT_IDX ( entry, bp->tx.ring_cnt );
2252 /* If the ring has wrapped, toggle the epoch bit */
2253 if ( bp->tx.prod_id > entry )
2254 bp->tx.epoch ^= 1;
2255 dump_tx_pkt ( ( u8 * ) iob->data, len, bp->tx.prod_id );
2256 /* Packets are ready, update Tx producer idx local and on card. */
2257 bnxt_db_tx ( bp, ( u32 ) entry );
2258 bp->tx.prod_id = entry;
2259 bp->tx.cnt_req++;
2260 /* memory barrier */
2261 mb ( );
2262 return 0;
2263}
unsigned long physaddr_t
Definition stdint.h:20
static u32 bnxt_tx_avail(struct bnxt *bp)
Definition bnxt.c:286
static void bnxt_tx_adjust_pkt(struct bnxt *bp, struct io_buffer *iob)
Definition bnxt.c:2215
void bnxt_set_txq(struct bnxt *bp, int entry, physaddr_t mapping, int len)
Definition bnxt.c:298
static void bnxt_db_tx(struct bnxt *bp, u32 idx)
Definition bnxt.c:254
#define dump_tx_pkt(pkt, len, idx)
Definition bnxt_dbg.h:567
#define EBUSY
Device or resource busy.
Definition errno.h:382
#define ENOBUFS
No buffer space available.
Definition errno.h:542
void mb(void)
Memory barrier.

References bnxt_db_tx(), bnxt_set_txq(), bnxt_tx_adjust_pkt(), bnxt_tx_avail(), bp, io_buffer::data, DBGP, bnxt::dev, dump_tx_pkt, EBUSY, ENOBUFS, iob_dma(), iob_len(), len, mb(), NEXT_IDX, net_device::priv, u16, u32, and u8.

◆ bnxt_er_reg_write()

u32 bnxt_er_reg_write ( struct bnxt * bp,
u32 reg_addr,
u32 reg_val )

Definition at line 2295 of file bnxt.c.

2296{
2297 u32 reg_base = 0;
2298
2299 reg_base = reg_addr & ~BNXT_GRC_BASE_MASK;
2300
2301 writel ( reg_base, bp->bar0 + BNXT_REG_WINDOW_BASE + 8 );
2302
2303 writel ( reg_val, bp->bar0 + ( BNXT_FW_HEALTH_WIN_OFF +
2304 ( reg_addr & BNXT_GRC_OFFSET_MASK ) ) );
2305
2306 DBGP ("bnxt_er_reg_write: reg_addr = %x, reg_val = %x\n", reg_addr, reg_val);
2307 return reg_val;
2308}
#define BNXT_FW_HEALTH_WIN_OFF
Definition bnxt.c:2290
#define BNXT_GRC_BASE_MASK
Definition bnxt.c:2292
#define BNXT_GRC_OFFSET_MASK
Definition bnxt.c:2293
#define BNXT_REG_WINDOW_BASE
Definition bnxt.c:2291

References BNXT_FW_HEALTH_WIN_OFF, BNXT_GRC_BASE_MASK, BNXT_GRC_OFFSET_MASK, BNXT_REG_WINDOW_BASE, bp, DBGP, u32, and writel.

Referenced by bnxt_rst_reg_val().

◆ bnxt_er_reg_read()

u32 bnxt_er_reg_read ( struct bnxt * bp,
u32 reg_addr )

Definition at line 2310 of file bnxt.c.

2311{
2312 u32 reg_val = 0;
2313 u32 reg_base = 0;
2314
2315 reg_base = reg_addr & ~BNXT_GRC_BASE_MASK;
2316
2317 writel ( reg_base, bp->bar0 + BNXT_REG_WINDOW_BASE + 8 );
2318
2319 reg_val = readl ( bp->bar0 + ( BNXT_FW_HEALTH_WIN_OFF +
2320 ( reg_addr & BNXT_GRC_OFFSET_MASK ) ) );
2321
2322 DBGP ("bnxt_er_reg_read: reg_addr = %x, reg_val = %x\n", reg_addr, reg_val);
2323 return reg_val;
2324}
#define readl
Definition w89c840.c:157

References BNXT_FW_HEALTH_WIN_OFF, BNXT_GRC_BASE_MASK, BNXT_GRC_OFFSET_MASK, BNXT_REG_WINDOW_BASE, bp, DBGP, readl, u32, and writel.

Referenced by bnxt_er_get_reg_val().

◆ bnxt_er_get_reg_val()

u32 bnxt_er_get_reg_val ( struct bnxt * bp,
u32 reg_addr,
u32 reg_type,
u32 mask )

Definition at line 2326 of file bnxt.c.

2327{
2328 u32 reg_val = 0;
2329
2330 switch ( reg_type ) {
2332 pci_read_config_dword ( bp->pdev, reg_addr & mask, &reg_val );
2333 break;
2335 reg_val = bnxt_er_reg_read ( bp, reg_addr );
2336 break;
2338 reg_val = readl ( bp->bar0 + ( reg_addr & mask ) );
2339 break;
2341 reg_val = readl ( bp->bar1 + ( reg_addr & mask ) );
2342 break;
2343 default:
2344 break;
2345 }
2346 DBGP ( "read_reg_val bp %p addr %x type %x : reg_val = %x\n", bp, reg_addr, reg_type, reg_val );
2347 return reg_val;
2348}
u32 bnxt_er_reg_read(struct bnxt *bp, u32 reg_addr)
Definition bnxt.c:2310
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1
Definition bnxt_hsi.h:1758
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG
Definition bnxt_hsi.h:1755
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC
Definition bnxt_hsi.h:1756
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0
Definition bnxt_hsi.h:1757
int pci_read_config_dword(struct pci_device *pci, unsigned int where, uint32_t *value)
Read 32-bit dword from PCI configuration space.

References bnxt_er_reg_read(), bp, DBGP, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG, pci_read_config_dword(), readl, and u32.

Referenced by bnxt_er_task(), and bnxt_process_er_event().

◆ bnxt_rst_reg_val()

void bnxt_rst_reg_val ( struct bnxt * bp,
u32 reg_addr,
u32 reg_val )

Definition at line 2350 of file bnxt.c.

2351{
2353 u32 reg_type = reg_addr & ER_QCFG_RESET_REG_ADDR_SPACE_MASK;
2354
2355 switch ( reg_type ) {
2357 pci_write_config_dword ( bp->pdev, reg_addr & mask, reg_val );
2358 break;
2360 bnxt_er_reg_write ( bp, reg_addr, reg_val );
2361 break;
2363 writel ( reg_val, bp->bar0 + ( reg_addr & mask ) );
2364 break;
2366 writel ( reg_val, bp->bar1 + ( reg_addr & mask ) );
2367 break;
2368 default:
2369 break;
2370 }
2371}
u32 bnxt_er_reg_write(struct bnxt *bp, u32 reg_addr, u32 reg_val)
Definition bnxt.c:2295
#define ER_QCFG_RESET_REG_ADDR_MASK
Definition bnxt_hsi.h:1803
#define ER_QCFG_RESET_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1796
int pci_write_config_dword(struct pci_device *pci, unsigned int where, uint32_t value)
Write 32-bit dword to PCI configuration space.

References bnxt_er_reg_write(), bp, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR0, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_BAR1, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_GRC, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_PCIE_CFG, ER_QCFG_RESET_REG_ADDR_MASK, ER_QCFG_RESET_REG_ADDR_SPACE_MASK, pci_write_config_dword(), u32, and writel.

Referenced by bnxt_rst_er_registers().

◆ bnxt_rst_er_registers()

void bnxt_rst_er_registers ( struct bnxt * bp)

Definition at line 2373 of file bnxt.c.

2374{
2375 u32 delay_time = 0;
2376 u8 i;
2377
2378 for ( i = 0; i < bp->er.reg_array_cnt; i++ ) {
2379 bnxt_rst_reg_val ( bp, bp->er.rst_reg[i], bp->er.rst_reg_val[i] );
2380
2381 delay_time = bp->er.delay_after_rst[i];
2382 if ( delay_time ) {
2383 udelay ( delay_time * 100000 );
2384 }
2385 }
2386
2387}
void bnxt_rst_reg_val(struct bnxt *bp, u32 reg_addr, u32 reg_val)
Definition bnxt.c:2350

References bnxt_rst_reg_val(), bp, u32, u8, and udelay().

Referenced by bnxt_er_task().

◆ bnxt_er_task()

void bnxt_er_task ( struct bnxt * bp,
u8 hb_task )

Definition at line 2389 of file bnxt.c.

2390{
2391 u32 present_hb_cnt;
2392 unsigned short pci_command, new_command;
2393 u8 i;
2394
2395 DBGP ( "%s(hb_task: %d)\n", __func__, hb_task );
2396 if ( bp->er.er_rst_on ) {
2397 if ( timer_running ( &bp->wait_timer) ) {
2398 /* Reset already in progress */
2399 return;
2400 }
2401 }
2402
2403 if ( hb_task ) {
2404 present_hb_cnt = bnxt_er_get_reg_val ( bp,
2405 bp->er.fw_hb_reg,
2406 bp->er.fw_hb_reg & ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK,
2408
2409 if ( present_hb_cnt != bp->er.last_fw_hb ) {
2410 bp->er.last_fw_hb = present_hb_cnt;
2411 return;
2412 }
2413 }
2414
2415 /* Heartbeat not incrementing, trigger error recovery */
2416 DBGP ( "%s(): Trigger Error Recovery\n", __func__ );
2417 bp->er.er_rst_on = 1;
2418 /* Set a recovery phase wait timer */
2419 start_timer_fixed ( &bp->wait_timer, BNXT_ER_WAIT_TIMER_INTERVAL ( bp ) );
2420
2421 /* Disable bus master */
2422 pci_read_config_word ( bp->pdev, PCI_COMMAND, &pci_command );
2423 new_command = pci_command & ~PCI_COMMAND_MASTER;
2424 pci_write_config_word ( bp->pdev, PCI_COMMAND, new_command );
2425
2426 /* Free up resources */
2427 bnxt_free_rx_iob ( bp );
2428
2429 /* wait for firmware to be operational */
2430 udelay ( bp->er.rst_min_dsecs * 100000 );
2431
2432 /* Reconfigure the PCI attributes */
2433 pci_write_config_word ( bp->pdev, PCI_COMMAND, pci_command );
2434
2435 if ( hb_task ) {
2436 if ( bp->er.master_pf ) {
2437 /* wait for master func wait period */
2438 udelay ( bp->er.master_wait_period * 100000 );
2439
2440 /* Reset register values */
2442
2443 /* wait for master wait post reset */
2444 udelay ( bp->er.master_wait_post_rst * 100000 );
2445 } else {
2446 /* wait for normal func wait period */
2447 udelay ( bp->er.normal_wait_period * 100000 );
2448 }
2449 }
2450
2451 for ( i = 0; i < bp->er.max_bailout_post_rst; i++ ) {
2452 bp->er.fw_health_status = bnxt_er_get_reg_val ( bp,
2453 bp->er.fw_status_reg,
2454 bp->er.fw_status_reg & ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK,
2456
2457 if ( bp->er.fw_health_status == FW_STATUS_REG_CODE_READY )
2458 break;
2459
2460 /* wait for 1 second */
2461 udelay ( 1000000 );
2462 }
2463
2464 if ( bp->er.fw_health_status == FW_STATUS_REG_CODE_READY ) {
2465 /* Initialize resources */
2466 bnxt_mm_nic ( bp );
2467
2468 /* Get device specific information */
2469 bnxt_up_chip ( bp );
2470
2471 /* Allocate queues */
2472 bnxt_up_nic ( bp );
2473 }
2474
2475 /* Clear Reset in progress flag */
2476 bp->er.er_rst_on = 0;
2477 stop_timer ( &bp->wait_timer );
2478}
void bnxt_rst_er_registers(struct bnxt *bp)
Definition bnxt.c:2373
int bnxt_free_rx_iob(struct bnxt *bp)
Definition bnxt.c:331
u32 bnxt_er_get_reg_val(struct bnxt *bp, u32 reg_addr, u32 reg_type, u32 mask)
Definition bnxt.c:2326
#define FW_STATUS_REG_CODE_READY
Definition bnxt.h:942
#define BNXT_ER_WAIT_TIMER_INTERVAL(x)
Definition bnxt.h:1108
#define ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1753
#define ER_QCFG_FW_HEALTH_REG_ADDR_MASK
Definition bnxt_hsi.h:1760
#define ER_QCFG_FW_HB_REG_ADDR_MASK
Definition bnxt_hsi.h:1770
#define ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1763
#define PCI_COMMAND_MASTER
Bus master.
Definition pci.h:29
void start_timer_fixed(struct retry_timer *timer, unsigned long timeout)
Start timer with a specified timeout.
Definition retry.c:65
void stop_timer(struct retry_timer *timer)
Stop timer.
Definition retry.c:118

References bnxt_er_get_reg_val(), BNXT_ER_WAIT_TIMER_INTERVAL, bnxt_free_rx_iob(), bnxt_mm_nic(), bnxt_rst_er_registers(), bnxt_up_chip, bnxt_up_nic, bp, DBGP, ER_QCFG_FW_HB_REG_ADDR_MASK, ER_QCFG_FW_HB_REG_ADDR_SPACE_MASK, ER_QCFG_FW_HEALTH_REG_ADDR_MASK, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK, FW_STATUS_REG_CODE_READY, PCI_COMMAND, PCI_COMMAND_MASTER, pci_read_config_word(), pci_write_config_word(), start_timer_fixed(), stop_timer(), u32, u8, and udelay().

Referenced by bnxt_er_task_timer(), and bnxt_poll().

◆ bnxt_process_er_event()

void bnxt_process_er_event ( struct bnxt * bp,
struct hwrm_async_event_cmpl * evt )

Definition at line 2480 of file bnxt.c.

2482{
2483 if ( evt->event_data1 &
2485 bp->er.driver_initiated_recovery = 1;
2486 start_timer_fixed ( &bp->task_timer, BNXT_ER_TIMER_INTERVAL ( bp ) );
2487
2488 } else {
2489 bp->er.driver_initiated_recovery = 0;
2490 stop_timer ( &bp->task_timer );
2491 }
2492
2493 if ( evt->event_data1 &
2495 bp->er.master_pf = 1;
2496 } else {
2497 bp->er.master_pf = 0;
2498 }
2499
2500 bp->er.fw_health_status = bnxt_er_get_reg_val ( bp,
2501 bp->er.fw_status_reg,
2502 bp->er.fw_status_reg & ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK,
2504 /* Intialize the last fw heart beat count */
2505 bp->er.last_fw_hb = 0;
2506 bp->er.last_fw_rst_cnt = bnxt_er_get_reg_val ( bp,
2507 bp->er.fw_rst_cnt_reg,
2508 bp->er.fw_rst_cnt_reg & ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK,
2510 bp->er.rst_in_progress = bnxt_er_get_reg_val ( bp,
2511 bp->er.rst_inprg_reg,
2512 bp->er.rst_inprg_reg & ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK,
2514 bp->er.err_recovery_cnt = bnxt_er_get_reg_val ( bp,
2515 bp->er.recvry_cnt_reg,
2516 bp->er.recvry_cnt_reg & ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK,
2518}
#define BNXT_ER_TIMER_INTERVAL(x)
Definition bnxt.h:1107
#define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC
Definition bnxt_hsi.h:588
#define ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED
Definition bnxt_hsi.h:589
#define ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1783
#define ER_QCFG_RESET_INPRG_REG_ADDR_MASK
Definition bnxt_hsi.h:1790
#define ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1808
#define ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK
Definition bnxt_hsi.h:1773
#define ER_QCFG_RCVRY_CNT_REG_ADDR_MASK
Definition bnxt_hsi.h:1815
#define ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK
Definition bnxt_hsi.h:1780

References ASYNC_EVENT_CMPL_ER_EVENT_DATA1_MASTER_FUNC, ASYNC_EVENT_CMPL_ER_EVENT_DATA1_RECOVERY_ENABLED, bnxt_er_get_reg_val(), BNXT_ER_TIMER_INTERVAL, bp, ER_QCFG_FW_HEALTH_REG_ADDR_MASK, ER_QCFG_FW_HEALTH_REG_ADDR_SPACE_MASK, ER_QCFG_FW_RESET_CNT_REG_ADDR_MASK, ER_QCFG_FW_RESET_CNT_REG_ADDR_SPACE_MASK, ER_QCFG_RCVRY_CNT_REG_ADDR_MASK, ER_QCFG_RCVRY_CNT_REG_ADDR_SPACE_MASK, ER_QCFG_RESET_INPRG_REG_ADDR_MASK, ER_QCFG_RESET_INPRG_REG_ADDR_SPACE_MASK, hwrm_async_event_cmpl::event_data1, start_timer_fixed(), and stop_timer().

Referenced by bnxt_service_cq(), and bnxt_service_nq().

◆ bnxt_process_reset_notify_event()

void bnxt_process_reset_notify_event ( struct bnxt * bp,
struct hwrm_async_event_cmpl * evt )

Definition at line 2520 of file bnxt.c.

2522{
2523 DBGP ( "Reset Notify Async event" );
2524 if ( ( ( evt->event_data1 ) &
2527 DBGP ( " error recovery initiated\n" );
2528 bp->er.rst_min_dsecs = evt->timestamp_lo;
2529 bp->er.rst_max_dsecs = evt->timestamp_hi;
2530
2531 if ( bp->er.rst_min_dsecs == 0 )
2532 bp->er.rst_min_dsecs = ER_DFLT_FW_RST_MIN_DSECS;
2533
2534 if ( bp->er.rst_max_dsecs == 0 )
2535 bp->er.rst_max_dsecs = ER_DFLT_FW_RST_MAX_DSECS;
2536
2537 // Trigger Error recovery
2538 bp->er.er_initiate = 1;
2539 }
2540}
#define ER_DFLT_FW_RST_MAX_DSECS
Definition bnxt.h:941
#define ER_DFLT_FW_RST_MIN_DSECS
Definition bnxt.h:940
#define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK
Definition bnxt_hsi.h:591
#define ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL
Definition bnxt_hsi.h:590

References ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_FATAL, ASYNC_EVENT_CMPL_EVENT_DATA1_REASON_CODE_MASK, bp, DBGP, ER_DFLT_FW_RST_MAX_DSECS, ER_DFLT_FW_RST_MIN_DSECS, hwrm_async_event_cmpl::event_data1, hwrm_async_event_cmpl::timestamp_hi, and hwrm_async_event_cmpl::timestamp_lo.

Referenced by bnxt_service_cq(), and bnxt_service_nq().

◆ bnxt_link_speed_evt()

void bnxt_link_speed_evt ( struct bnxt * bp,
struct hwrm_async_event_cmpl * evt )

Definition at line 2542 of file bnxt.c.

2543{
2545 DBGP ("bnxt_link_speed_evt: event data = %lx\n",
2547 }
2548
2550 return;
2551 }
2552
2553 bnxt_set_link ( bp );
2554 dbg_link_info ( bp );
2555 dbg_link_status ( bp );
2556}
#define dbg_link_info(bp)
Definition bnxt_dbg.h:662
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE
Definition bnxt_hsi.h:664
#define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK
Definition bnxt_hsi.h:665

References ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_FORCE, ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_MASK, bnxt_hwrm_port_phy_qcfg(), bnxt_set_link(), bp, dbg_link_info, dbg_link_status, DBGP, hwrm_async_event_cmpl::event_data1, QCFG_PHY_ALL, and STATUS_SUCCESS.

Referenced by bnxt_service_cq(), and bnxt_service_nq().

◆ bnxt_link_speed_chg_evt()

◆ bnxt_port_phy_chg_evt()

◆ bnxt_service_nq()

void bnxt_service_nq ( struct net_device * dev)
static

Definition at line 2665 of file bnxt.c.

2666{
2667 struct bnxt *bp = dev->priv;
2668 struct nq_base *nqp;
2669 u16 old_cid = bp->nq.cons_id;
2671 u32 nq_type;
2672 struct hwrm_async_event_cmpl *evt;
2673
2674 if ( ! ( FLAG_TEST ( bp->flags, BNXT_FLAG_IS_CHIP_P5_PLUS ) ) )
2675 return;
2676
2677 while ( done == SERVICE_NEXT_NQ_BD ) {
2678 nqp = ( struct nq_base * ) BD_NOW ( NQ_DMA_ADDR ( bp ),
2679 bp->nq.cons_id,
2680 sizeof ( struct nq_base ) );
2681 if ( ( nqp->v & NQ_CN_V ) ^ bp->nq.completion_bit )
2682 break;
2683 nq_type = ( nqp->type & NQ_CN_TYPE_MASK );
2684 bp->nq.toggle = ( ( nqp->type & NQ_CN_TOGGLE_MASK ) >> NQ_CN_TOGGLE_SFT );
2685 dump_evt ( ( u8 * )nqp, nq_type, bp->nq.cons_id, 1 );
2686 dump_nq ( nqp, bp->nq.cons_id );
2687
2688 switch ( nq_type ) {
2690 evt = ( struct hwrm_async_event_cmpl * ) nqp;
2691 switch ( evt->event_id ) {
2693 bnxt_link_evt ( bp,
2694 ( struct hwrm_async_event_cmpl * ) nqp );
2695 break;
2698 ( struct hwrm_async_event_cmpl * ) nqp );
2699 break;
2702 ( struct hwrm_async_event_cmpl * ) nqp );
2703 break;
2706 ( struct hwrm_async_event_cmpl * ) nqp );
2707 break;
2710 ( struct hwrm_async_event_cmpl * ) nqp );
2711 break;
2714 ( struct hwrm_async_event_cmpl * ) nqp );
2715 break;
2716 default:
2717 break;
2718 }
2719 bnxt_adv_nq_index ( bp, 1 );
2720 break;
2722 bnxt_adv_nq_index ( bp, 1 );
2723 break;
2724 default:
2726 break;
2727 }
2728 }
2729
2730 if ( bp->nq.cons_id != old_cid )
2731 bnxt_db_nq ( bp );
2732}
static void bnxt_db_nq(struct bnxt *bp)
Definition bnxt.c:216
static void bnxt_adv_nq_index(struct bnxt *bp, u16 cnt)
Definition bnxt.c:2265
#define NQ_CN_TYPE_MASK
Definition bnxt.h:568
#define NQ_CN_TOGGLE_MASK
Definition bnxt.h:570
#define SERVICE_NEXT_NQ_BD
Definition bnxt.h:186
#define NQ_CN_TYPE_CQ_NOTIFICATION
Definition bnxt.h:573
#define NO_MORE_NQ_BD_TO_SERVICE
Definition bnxt.h:185
#define NQ_CN_TOGGLE_SFT
Definition bnxt.h:571
#define NQ_CN_V
Definition bnxt.h:587
#define dump_nq(nq, id)
Definition bnxt_dbg.h:509
u16 type
Definition bnxt.h:560
u32 v
Definition bnxt.h:581

References ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, BD_NOW, bnxt_adv_nq_index(), bnxt_db_nq(), BNXT_FLAG_IS_CHIP_P5_PLUS, bnxt_link_evt(), bnxt_link_speed_chg_evt(), bnxt_link_speed_evt(), bnxt_port_phy_chg_evt(), bnxt_process_er_event(), bnxt_process_reset_notify_event(), bp, CMPL_BASE_TYPE_HWRM_ASYNC_EVENT, bnxt::dev, done, dump_evt, dump_nq, hwrm_async_event_cmpl::event_id, FLAG_TEST, NO_MORE_NQ_BD_TO_SERVICE, NQ_CN_TOGGLE_MASK, NQ_CN_TOGGLE_SFT, NQ_CN_TYPE_CQ_NOTIFICATION, NQ_CN_TYPE_MASK, NQ_CN_V, NQ_DMA_ADDR, net_device::priv, SERVICE_NEXT_NQ_BD, nq_base::type, u16, u32, u8, and nq_base::v.

Referenced by bnxt_poll().

◆ bnxt_er_task_timer()

void bnxt_er_task_timer ( struct retry_timer * timer,
int over __unused )
static

Definition at line 2734 of file bnxt.c.

2735{
2736 struct bnxt *bp = container_of ( timer, struct bnxt, task_timer );
2737
2738 /* Restart timer */
2740 if ( bp->er.driver_initiated_recovery ) {
2741 bnxt_er_task ( bp, 1 );
2742 }
2743}
void bnxt_er_task(struct bnxt *bp, u8 hb_task)
Definition bnxt.c:2389
#define container_of(ptr, type, field)
Get containing structure.
Definition stddef.h:36
struct retry_timer task_timer
Definition bnxt.h:986
A timer.
Definition timer.h:29

References __unused, bnxt_er_task(), BNXT_ER_TIMER_INTERVAL, bp, container_of, start_timer_fixed(), and bnxt::task_timer.

Referenced by bnxt_init_one().

◆ bnxt_er_wait_timer()

void bnxt_er_wait_timer ( struct retry_timer * timer,
int over __unused )
static

Definition at line 2745 of file bnxt.c.

2746{
2747 struct bnxt *bp = container_of (timer, struct bnxt, wait_timer );
2748 /* The sole function of this timer is to wait for the specified
2749 * amount of time to complete error recovery phase
2750 */
2751 stop_timer ( &bp->wait_timer );
2752 return;
2753}
struct retry_timer wait_timer
Definition bnxt.h:987

References __unused, bp, container_of, stop_timer(), and bnxt::wait_timer.

Referenced by bnxt_init_one().

◆ bnxt_poll()

void bnxt_poll ( struct net_device * dev)
static

Definition at line 2755 of file bnxt.c.

2756{
2757 struct bnxt *bp = dev->priv;
2758
2759 mb ( );
2760 bnxt_service_nq ( dev );
2761 bnxt_service_cq ( dev );
2762
2763 if ( bp->er.er_initiate ) {
2764 bnxt_er_task ( bp, 0 );
2765 bp->er.er_initiate = 0;
2766 }
2767
2768}
static void bnxt_service_cq(struct net_device *dev)
Definition bnxt.c:2587
static void bnxt_service_nq(struct net_device *dev)
Definition bnxt.c:2665

References bnxt_er_task(), bnxt_service_cq(), bnxt_service_nq(), bp, bnxt::dev, mb(), and net_device::priv.

◆ bnxt_close()

void bnxt_close ( struct net_device * dev)
static

Definition at line 2770 of file bnxt.c.

2771{
2772 struct bnxt *bp = dev->priv;
2773
2774 DBGP ( "%s\n", __func__ );
2775 stop_timer ( &bp->task_timer );
2776 stop_timer ( &bp->wait_timer );
2777
2778 bnxt_down_nic ( bp );
2779
2781
2782}

References bnxt_down_nic, bnxt_free_rings_mem(), bp, DBGP, bnxt::dev, net_device::priv, and stop_timer().

◆ bnxt_init_one()

int bnxt_init_one ( struct pci_device * pci)
static

Definition at line 2791 of file bnxt.c.

2792{
2793 struct net_device *netdev;
2794 struct bnxt *bp;
2795 int err = 0;
2796
2797 DBGP ( "%s\n", __func__ );
2798 /* Allocate network device */
2799 netdev = alloc_etherdev ( sizeof ( *bp ) );
2800 if ( !netdev ) {
2801 DBGP ( "- %s ( ): alloc_etherdev Failed\n", __func__ );
2802 err = -ENOMEM;
2803 goto disable_pdev;
2804 }
2805
2806 /* Initialise network device */
2808
2809 /* Driver private area for this device */
2810 bp = netdev->priv;
2811
2812 /* Set PCI driver private data */
2813 pci_set_drvdata ( pci, netdev );
2814
2815 /* Clear Private area data */
2816 memset ( bp, 0, sizeof ( *bp ) );
2817 bp->pdev = pci;
2818 bp->dev = netdev;
2819 netdev->dev = &pci->dev;
2820
2821 timer_init ( &bp->task_timer, bnxt_er_task_timer, &netdev->refcnt );
2822 timer_init ( &bp->wait_timer, bnxt_er_wait_timer, &netdev->refcnt );
2823
2824 /* Configure DMA */
2825 bp->dma = &pci->dma;
2826 netdev->dma = bp->dma;
2827
2828 /* Enable PCI device */
2829 adjust_pci_device ( pci );
2830
2831 /* Get PCI Information */
2833
2834 /* Allocate HWRM memory */
2835 if ( ( err = bnxt_alloc_hwrm_mem ( bp ) ) != 0 )
2836 goto err_alloc_hwrm;
2837
2838 bp->link_status = STATUS_LINK_DOWN;
2839 bp->wait_link_timeout = LINK_DEFAULT_TIMEOUT;
2840 if ( ( err = bnxt_up_init ( bp ) ) != 0 )
2841 goto err_up_init;
2842
2843 /* Register Network device */
2844 if ( ( err = register_netdev ( netdev ) ) != 0 ) {
2845 DBGP ( "- %s ( ): register_netdev Failed\n", __func__ );
2846 goto err_register_netdev;
2847 }
2848
2849 /* Set Initial Link State */
2850 bnxt_set_link ( bp );
2851
2852 return 0;
2853
2855err_register_netdev:
2856err_up_init:
2858err_alloc_hwrm:
2859 bnxt_down_pci ( bp );
2861 netdev_put ( netdev );
2862disable_pdev:
2863 pci_set_drvdata ( pci, NULL );
2864 return err;
2865}
static int bnxt_get_pci_info(struct bnxt *bp)
Definition bnxt.c:131
static void bnxt_down_pci(struct bnxt *bp)
Definition bnxt.c:105
static void bnxt_er_task_timer(struct retry_timer *timer, int over __unused)
Definition bnxt.c:2734
int bnxt_alloc_hwrm_mem(struct bnxt *bp)
Definition bnxt.c:616
#define bnxt_up_init(bp)
Definition bnxt.c:2179
static struct net_device_operations bnxt_netdev_ops
Definition bnxt.c:2784
static void bnxt_er_wait_timer(struct retry_timer *timer, int over __unused)
Definition bnxt.c:2745
struct net_device * alloc_etherdev(size_t priv_size)
Allocate Ethernet device.
Definition ethernet.c:266
static struct net_device * netdev
Definition gdbudp.c:53
void unregister_netdev(struct net_device *netdev)
Unregister network device.
Definition netdevice.c:946
int register_netdev(struct net_device *netdev)
Register network device.
Definition netdevice.c:760
static void netdev_init(struct net_device *netdev, struct net_device_operations *op)
Initialise a network device.
Definition netdevice.h:522
static void netdev_nullify(struct net_device *netdev)
Stop using a network device.
Definition netdevice.h:535
static void netdev_put(struct net_device *netdev)
Drop reference to network device.
Definition netdevice.h:579
void adjust_pci_device(struct pci_device *pci)
Enable PCI device.
Definition pci.c:255
static void pci_set_drvdata(struct pci_device *pci, void *priv)
Set PCI driver-private data.
Definition pci.h:370
struct device dev
Generic device.
Definition pci.h:216
struct dma_device dma
DMA device.
Definition pci.h:218

References adjust_pci_device(), alloc_etherdev(), bnxt_alloc_hwrm_mem(), bnxt_down_pci(), bnxt_er_task_timer(), bnxt_er_wait_timer(), bnxt_free_hwrm_mem(), bnxt_get_pci_info(), bnxt_netdev_ops, bnxt_set_link(), bnxt_up_init, bp, DBGP, pci_device::dev, pci_device::dma, ENOMEM, LINK_DEFAULT_TIMEOUT, memset(), netdev, netdev_init(), netdev_nullify(), netdev_put(), NULL, pci_set_drvdata(), register_netdev(), STATUS_LINK_DOWN, and unregister_netdev().

◆ bnxt_remove_one()

void bnxt_remove_one ( struct pci_device * pci)
static

Definition at line 2867 of file bnxt.c.

2868{
2869 struct net_device *netdev = pci_get_drvdata ( pci );
2870 struct bnxt *bp = netdev->priv;
2871
2872 DBGP ( "%s\n", __func__ );
2873 /* Unregister network device */
2875
2876 /* Free HWRM buffers */
2878
2879 /* iounmap PCI BAR ( s ) */
2880 bnxt_down_pci ( bp );
2881
2882 /* Stop network device */
2884
2885 /* Drop refernce to network device */
2886 netdev_put ( netdev );
2887 DBGP ( "%s - Done\n", __func__ );
2888}
static void * pci_get_drvdata(struct pci_device *pci)
Get PCI driver-private data.
Definition pci.h:380

References bnxt_down_pci(), bnxt_free_hwrm_mem(), bp, DBGP, netdev, netdev_nullify(), netdev_put(), pci_get_drvdata(), and unregister_netdev().

Variable Documentation

◆ bnxt_nics

struct pci_device_id bnxt_nics[]
static

Definition at line 28 of file bnxt.c.

28 {
29 PCI_ROM( 0x14e4, 0x1604, "14e4-1604", "Broadcom BCM957454", 0 ),
30 PCI_ROM( 0x14e4, 0x1605, "14e4-1605", "Broadcom BCM957454 RDMA", 0 ),
31 PCI_ROM( 0x14e4, 0x1606, "14e4-1606", "Broadcom BCM957454 RDMA VF", BNXT_FLAG_PCI_VF ),
32 PCI_ROM( 0x14e4, 0x1607, "bcm957454-1607", "Broadcom BCM957454 HV VF", BNXT_FLAG_PCI_VF ),
33 PCI_ROM( 0x14e4, 0x1608, "bcm957454-1608", "Broadcom BCM957454 RDMA HV VF", BNXT_FLAG_PCI_VF ),
34 PCI_ROM( 0x14e4, 0x1609, "14e4-1609", "Broadcom BCM957454 VF", BNXT_FLAG_PCI_VF ),
35 PCI_ROM( 0x14e4, 0x1614, "14e4-1614", "Broadcom BCM957454", 0 ),
36 PCI_ROM( 0x14e4, 0x16bd, "bcm95741x-16bd", "Broadcom BCM95741x RDMA HV VF", BNXT_FLAG_PCI_VF ),
37 PCI_ROM( 0x14e4, 0x16c0, "14e4-16c0", "Broadcom BCM957417", 0 ),
38 PCI_ROM( 0x14e4, 0x16c1, "14e4-16c1", "Broadcom BCM95741x VF", BNXT_FLAG_PCI_VF ),
39 PCI_ROM( 0x14e4, 0x16c5, "bcm95741x-16c5", "Broadcom BCM95741x HV VF", BNXT_FLAG_PCI_VF ),
40 PCI_ROM( 0x14e4, 0x16c8, "14e4-16c8", "Broadcom BCM957301", 0 ),
41 PCI_ROM( 0x14e4, 0x16c9, "14e4-16c9", "Broadcom BCM957302", 0 ),
42 PCI_ROM( 0x14e4, 0x16ca, "14e4-16ca", "Broadcom BCM957304", 0 ),
43 PCI_ROM( 0x14e4, 0x16cc, "14e4-16cc", "Broadcom BCM957417 MF", 0 ),
44 PCI_ROM( 0x14e4, 0x16cd, "14e4-16cd", "Broadcom BCM958700", 0 ),
45 PCI_ROM( 0x14e4, 0x16ce, "14e4-16ce", "Broadcom BCM957311", 0 ),
46 PCI_ROM( 0x14e4, 0x16cf, "14e4-16cf", "Broadcom BCM957312", 0 ),
47 PCI_ROM( 0x14e4, 0x16d0, "14e4-16d0", "Broadcom BCM957402", 0 ),
48 PCI_ROM( 0x14e4, 0x16d1, "14e4-16d1", "Broadcom BCM957404", 0 ),
49 PCI_ROM( 0x14e4, 0x16d2, "14e4-16d2", "Broadcom BCM957406", 0 ),
50 PCI_ROM( 0x14e4, 0x16d4, "14e4-16d4", "Broadcom BCM957402 MF", 0 ),
51 PCI_ROM( 0x14e4, 0x16d5, "14e4-16d5", "Broadcom BCM957407", 0 ),
52 PCI_ROM( 0x14e4, 0x16d6, "14e4-16d6", "Broadcom BCM957412", 0 ),
53 PCI_ROM( 0x14e4, 0x16d7, "14e4-16d7", "Broadcom BCM957414", 0 ),
54 PCI_ROM( 0x14e4, 0x16d8, "14e4-16d8", "Broadcom BCM957416", 0 ),
55 PCI_ROM( 0x14e4, 0x16d9, "14e4-16d9", "Broadcom BCM957417", 0 ),
56 PCI_ROM( 0x14e4, 0x16da, "14e4-16da", "Broadcom BCM957402", 0 ),
57 PCI_ROM( 0x14e4, 0x16db, "14e4-16db", "Broadcom BCM957404", 0 ),
58 PCI_ROM( 0x14e4, 0x16dc, "14e4-16dc", "Broadcom BCM95741x VF", BNXT_FLAG_PCI_VF ),
59 PCI_ROM( 0x14e4, 0x16de, "14e4-16de", "Broadcom BCM957412 MF", 0 ),
60 PCI_ROM( 0x14e4, 0x16df, "14e4-16df", "Broadcom BCM957314", 0 ),
61 PCI_ROM( 0x14e4, 0x16e0, "14e4-16e0", "Broadcom BCM957317", 0 ),
62 PCI_ROM( 0x14e4, 0x16e2, "14e4-16e2", "Broadcom BCM957417", 0 ),
63 PCI_ROM( 0x14e4, 0x16e3, "14e4-16e3", "Broadcom BCM957416", 0 ),
64 PCI_ROM( 0x14e4, 0x16e4, "14e4-16e4", "Broadcom BCM957317", 0 ),
65 PCI_ROM( 0x14e4, 0x16e7, "14e4-16e7", "Broadcom BCM957404 MF", 0 ),
66 PCI_ROM( 0x14e4, 0x16e8, "14e4-16e8", "Broadcom BCM957406 MF", 0 ),
67 PCI_ROM( 0x14e4, 0x16e9, "14e4-16e9", "Broadcom BCM957407", 0 ),
68 PCI_ROM( 0x14e4, 0x16ea, "14e4-16ea", "Broadcom BCM957407 MF", 0 ),
69 PCI_ROM( 0x14e4, 0x16eb, "14e4-16eb", "Broadcom BCM957412 RDMA MF", 0 ),
70 PCI_ROM( 0x14e4, 0x16ec, "14e4-16ec", "Broadcom BCM957414 MF", 0 ),
71 PCI_ROM( 0x14e4, 0x16ed, "14e4-16ed", "Broadcom BCM957414 RDMA MF", 0 ),
72 PCI_ROM( 0x14e4, 0x16ee, "14e4-16ee", "Broadcom BCM957416 MF", 0 ),
73 PCI_ROM( 0x14e4, 0x16ef, "14e4-16ef", "Broadcom BCM957416 RDMA MF", 0 ),
74 PCI_ROM( 0x14e4, 0x16f0, "14e4-16f0", "Broadcom BCM957320", 0 ),
75 PCI_ROM( 0x14e4, 0x16f1, "14e4-16f1", "Broadcom BCM957320", 0 ),
76 PCI_ROM( 0x14e4, 0x1750, "14e4-1750", "Broadcom BCM957508", 0 ),
77 PCI_ROM( 0x14e4, 0x1751, "14e4-1751", "Broadcom BCM957504", 0 ),
78 PCI_ROM( 0x14e4, 0x1752, "14e4-1752", "Broadcom BCM957502", 0 ),
79 PCI_ROM( 0x14e4, 0x1760, "14e4-1760", "Broadcom BCM957608", 0 ),
80 PCI_ROM( 0x14e4, 0x1800, "14e4-1800", "Broadcom BCM957502 MF", 0 ),
81 PCI_ROM( 0x14e4, 0x1801, "14e4-1801", "Broadcom BCM957504 MF", 0 ),
82 PCI_ROM( 0x14e4, 0x1802, "14e4-1802", "Broadcom BCM957508 MF", 0 ),
83 PCI_ROM( 0x14e4, 0x1803, "14e4-1803", "Broadcom BCM957502 RDMA MF", 0 ),
84 PCI_ROM( 0x14e4, 0x1804, "14e4-1804", "Broadcom BCM957504 RDMA MF", 0 ),
85 PCI_ROM( 0x14e4, 0x1805, "14e4-1805", "Broadcom BCM957508 RDMA MF", 0 ),
86 PCI_ROM( 0x14e4, 0x1806, "14e4-1806", "Broadcom BCM9575xx VF", BNXT_FLAG_PCI_VF ),
87 PCI_ROM( 0x14e4, 0x1807, "14e4-1807", "Broadcom BCM9575xx RDMA VF", BNXT_FLAG_PCI_VF ),
88 PCI_ROM( 0x14e4, 0x1808, "14e4-1808", "Broadcom BCM9575xx HV VF", BNXT_FLAG_PCI_VF ),
89 PCI_ROM( 0x14e4, 0x1809, "14e4-1809", "Broadcom BCM9575xx RDMA HV VF", BNXT_FLAG_PCI_VF ),
90 PCI_ROM( 0x14e4, 0x1819, "bcm95760x-1819", "Broadcom BCM95760x VF", BNXT_FLAG_PCI_VF ),
91 PCI_ROM( 0x14e4, 0x181b, "bcm95760x-181b", "Broadcom BCM95760x HV VF", BNXT_FLAG_PCI_VF ),
92};
#define PCI_ROM(_vendor, _device, _name, _description, _data)
Definition pci.h:311

◆ bring_up_init

hwrm_func_t bring_up_init[]
Initial value:
= {
}
static int bnxt_get_link_state(struct bnxt *bp)
Definition bnxt.c:2074
static int bnxt_hwrm_func_qcfg_req(struct bnxt *bp)
Definition bnxt.c:928
static int bnxt_hwrm_ver_get(struct bnxt *bp)
Definition bnxt.c:730
static int bnxt_get_device_address(struct bnxt *bp)
Definition bnxt.c:165
static int bnxt_hwrm_func_qcaps_req(struct bnxt *bp)
Definition bnxt.c:893

Definition at line 2086 of file bnxt.c.

2086 {
2087 bnxt_hwrm_ver_get, /* HWRM_VER_GET */
2088 bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
2089 bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
2090 bnxt_get_device_address, /* HW MAC address */
2092 NULL
2093};

◆ bring_down_chip

hwrm_func_t bring_down_chip[]
Initial value:
= {
}
static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
Definition bnxt.c:1136

Definition at line 2095 of file bnxt.c.

2095 {
2096 bnxt_hwrm_func_drv_unrgtr, /* HWRM_FUNC_DRV_UNRGTR */
2097 NULL,
2098};

◆ bring_down_nic

hwrm_func_t bring_down_nic[]
Initial value:
= {
}
static int bnxt_hwrm_ring_free_grp(struct bnxt *bp)
Definition bnxt.c:1759
static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
Definition bnxt.c:1736
static int bnxt_hwrm_ring_free_cq(struct bnxt *bp)
Definition bnxt.c:1923
static int bnxt_reset_rx_mask(struct bnxt *bp)
Definition bnxt.c:2069
static int bnxt_hwrm_cfa_l2_filter_free(struct bnxt *bp)
Definition bnxt.c:1236
static int bnxt_hwrm_ring_free_nq(struct bnxt *bp)
Definition bnxt.c:1975
static int bnxt_hwrm_vnic_free(struct bnxt *bp)
Definition bnxt.c:2016
static int bnxt_hwrm_ring_free_tx(struct bnxt *bp)
Definition bnxt.c:1938
static int bnxt_hwrm_vnic_cfg(struct bnxt *bp)
Definition bnxt.c:2039
static int bnxt_hwrm_ring_free_rx(struct bnxt *bp)
Definition bnxt.c:1953

Definition at line 2100 of file bnxt.c.

2100 {
2101 bnxt_hwrm_cfa_l2_filter_free, /* HWRM_CFA_L2_FILTER_FREE */
2103 bnxt_hwrm_vnic_cfg, /* HWRM_VNIC_CFG */
2104 bnxt_free_rx_iob, /* HWRM_FREE_IOB */
2105 bnxt_hwrm_vnic_free, /* HWRM_VNIC_FREE */
2106 bnxt_hwrm_ring_free_grp, /* HWRM_RING_GRP_FREE */
2107 bnxt_hwrm_ring_free_rx, /* HWRM_RING_FREE - RX Ring */
2108 bnxt_hwrm_ring_free_tx, /* HWRM_RING_FREE - TX Ring */
2109 bnxt_hwrm_stat_ctx_free, /* HWRM_STAT_CTX_FREE */
2110 bnxt_hwrm_ring_free_cq, /* HWRM_RING_FREE - CQ Ring */
2111 bnxt_hwrm_ring_free_nq, /* HWRM_RING_FREE - NQ Ring */
2112 bnxt_hwrm_func_drv_unrgtr, /* HWRM_FUNC_DRV_UNRGTR */
2113 NULL,
2114};

◆ bring_up_chip

hwrm_func_t bring_up_chip[]
Initial value:
= {
}
static int bnxt_hwrm_error_recovery_req(struct bnxt *bp)
Definition bnxt.c:1031
static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
Definition bnxt.c:1094
static int bnxt_hwrm_backing_store_qcfg(struct bnxt *bp)
Definition bnxt.c:1436
static int bnxt_hwrm_backing_store_cfg(struct bnxt *bp)
Definition bnxt.c:1451
static int bnxt_hwrm_func_resource_qcaps(struct bnxt *bp)
Definition bnxt.c:778
static int bnxt_hwrm_port_mac_cfg(struct bnxt *bp)
Definition bnxt.c:1492
static int bnxt_hwrm_func_cfg_req(struct bnxt *bp)
Definition bnxt.c:1007
static int bnxt_hwrm_port_phy_qcaps_req(struct bnxt *bp)
Definition bnxt.c:969
static int bnxt_hwrm_func_reset_req(struct bnxt *bp)
Definition bnxt.c:993
static int bnxt_query_phy_link(struct bnxt *bp)
Definition bnxt.c:1656

Definition at line 2115 of file bnxt.c.

2115 {
2116 bnxt_hwrm_ver_get, /* HWRM_VER_GET */
2117 bnxt_hwrm_func_reset_req, /* HWRM_FUNC_RESET */
2118 bnxt_hwrm_func_qcaps_req, /* HWRM_FUNC_QCAPS */
2119 bnxt_hwrm_func_drv_rgtr, /* HWRM_FUNC_DRV_RGTR */
2120 bnxt_hwrm_error_recovery_req, /* HWRM_ERROR_RECOVERY_REQ */
2121 bnxt_hwrm_backing_store_cfg, /* HWRM_FUNC_BACKING_STORE_CFG */
2122 bnxt_hwrm_backing_store_qcfg, /* HWRM_FUNC_BACKING_STORE_QCFG */
2123 bnxt_hwrm_func_resource_qcaps, /* HWRM_FUNC_RESOURCE_QCAPS */
2124 bnxt_hwrm_port_phy_qcaps_req, /* HWRM_PORT_PHY_QCAPS */
2125 bnxt_hwrm_func_qcfg_req, /* HWRM_FUNC_QCFG */
2126 bnxt_hwrm_port_mac_cfg, /* HWRM_PORT_MAC_CFG */
2127 bnxt_hwrm_func_cfg_req, /* HWRM_FUNC_CFG */
2128 bnxt_query_phy_link, /* HWRM_PORT_PHY_QCFG */
2129 bnxt_get_device_address, /* HW MAC address */
2130 NULL,
2131};

◆ bring_up_nic

hwrm_func_t bring_up_nic[]
Initial value:
= {
}
static int bnxt_hwrm_ring_alloc_nq(struct bnxt *bp)
Definition bnxt.c:1968
static int bnxt_hwrm_vnic_alloc(struct bnxt *bp)
Definition bnxt.c:1993
static int bnxt_hwrm_ring_alloc_grp(struct bnxt *bp)
Definition bnxt.c:1782
static int bnxt_hwrm_ring_alloc_rx(struct bnxt *bp)
Definition bnxt.c:1917
static int bnxt_hwrm_cfa_l2_filter_alloc(struct bnxt *bp)
Definition bnxt.c:1195
static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
Definition bnxt.c:1468
static int bnxt_hwrm_ring_alloc_tx(struct bnxt *bp)
Definition bnxt.c:1911
static int bnxt_set_rx_mask(struct bnxt *bp)
Definition bnxt.c:2064
static int bnxt_hwrm_ring_alloc_cq(struct bnxt *bp)
Definition bnxt.c:1905
static int bnxt_hwrm_set_async_event(struct bnxt *bp)
Definition bnxt.c:1157
static int bnxt_get_phy_link(struct bnxt *bp)
Definition bnxt.c:1689
static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
Definition bnxt.c:1714

Definition at line 2133 of file bnxt.c.

2133 {
2134 bnxt_hwrm_stat_ctx_alloc, /* HWRM_STAT_CTX_ALLOC */
2135 bnxt_hwrm_queue_qportcfg, /* HWRM_QUEUE_QPORTCFG */
2136 bnxt_hwrm_ring_alloc_nq, /* HWRM_RING_ALLOC - NQ Ring */
2137 bnxt_hwrm_ring_alloc_cq, /* HWRM_RING_ALLOC - CQ Ring */
2138 bnxt_hwrm_ring_alloc_tx, /* HWRM_RING_ALLOC - TX Ring */
2139 bnxt_hwrm_ring_alloc_rx, /* HWRM_RING_ALLOC - RX Ring */
2140 bnxt_hwrm_ring_alloc_grp, /* HWRM_RING_GRP_ALLOC - Group */
2141 bnxt_hwrm_vnic_alloc, /* HWRM_VNIC_ALLOC */
2142 bnxt_post_rx_buffers, /* Post RX buffers */
2143 bnxt_hwrm_set_async_event, /* ENABLES_ASYNC_EVENT_CR */
2144 bnxt_hwrm_vnic_cfg, /* HWRM_VNIC_CFG */
2145 bnxt_hwrm_cfa_l2_filter_alloc, /* HWRM_CFA_L2_FILTER_ALLOC */
2146 bnxt_get_phy_link, /* HWRM_PORT_PHY_QCFG - PhyLink */
2147 bnxt_set_rx_mask, /* HWRM_CFA_L2_SET_RX_MASK */
2148 NULL,
2149};

◆ bnxt_netdev_ops

struct net_device_operations bnxt_netdev_ops
static
Initial value:
= {
.open = bnxt_open,
.close = bnxt_close,
.poll = bnxt_poll,
.transmit = bnxt_tx,
}
static void bnxt_poll(struct net_device *dev)
Definition bnxt.c:2755
static void bnxt_close(struct net_device *dev)
Definition bnxt.c:2770
static int bnxt_open(struct net_device *dev)
Definition bnxt.c:2181
static int bnxt_tx(struct net_device *dev, struct io_buffer *iob)
Definition bnxt.c:2229

Definition at line 2784 of file bnxt.c.

2784 {
2785 .open = bnxt_open,
2786 .close = bnxt_close,
2787 .poll = bnxt_poll,
2788 .transmit = bnxt_tx,
2789};

Referenced by bnxt_init_one().

◆ __pci_driver

struct pci_driver bnxt_pci_driver __pci_driver
Initial value:
= {
.ids = bnxt_nics,
.id_count = ARRAY_SIZE ( bnxt_nics ),
.probe = bnxt_init_one,
.remove = bnxt_remove_one,
}
static struct pci_device_id bnxt_nics[]
Definition bnxt.c:28
static int bnxt_init_one(struct pci_device *pci)
Definition bnxt.c:2791
static void bnxt_remove_one(struct pci_device *pci)
Definition bnxt.c:2867
#define ARRAY_SIZE(x)
Definition efx_common.h:43

Definition at line 2891 of file bnxt.c.

2891 {
2892 .ids = bnxt_nics,
2893 .id_count = ARRAY_SIZE ( bnxt_nics ),
2894 .probe = bnxt_init_one,
2895 .remove = bnxt_remove_one,
2896};