iPXE
Data Structures | Defines | Enumerations | Functions | Variables
ath9k.h File Reference
#include "common.h"

Go to the source code of this file.

Data Structures

struct  ath_config
struct  ath_descdma
struct  ath_txq
struct  ath_atx_ac
struct  ath_frame_info
struct  ath_buf_state
struct  ath_buf
struct  ath_atx_tid
struct  ath_node
struct  ath_tx_control
struct  ath_tx
 : Index is mac80211 queue number. More...
struct  ath_rx_edma
struct  ath_rx
struct  ath9k_legacy_rate
struct  survey_info
struct  ath9k_vif_iter_data
struct  ath_softc

Defines

#define ito64(x)
#define INCR(_l, _sz)
#define DECR(_l,_sz)
#define A_MAX(a, b)   ((a) > (b) ? (a) : (b))
#define TSF_TO_TU(_h, _l)   ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
#define ATH_TXQ_SETUP(sc, i)   ((sc)->tx.txqsetup & (1<<i))
#define ATH_TXBUF_RESET(_bf)
#define ATH_RXBUF_RESET(_bf)
#define bf_isampdu(bf)   (bf->bf_state.bf_type & BUF_AMPDU)
#define bf_isaggr(bf)   (bf->bf_state.bf_type & BUF_AGGR)
#define bf_isxretried(bf)   (bf->bf_state.bf_type & BUF_XRETRY)
#define ATH_TXSTATUS_RING_SIZE   64
#define ATH_RXBUF   16
#define ATH_TXBUF   16
#define ATH_TXBUF_RESERVE   5
#define ATH_MAX_QDEPTH   (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
#define ATH_TXMAXTRY   13
#define TID_TO_WME_AC(_tid)
#define ATH_AGGR_DELIM_SZ   4
#define ATH_AGGR_MINPLEN   256 /* in bytes, minimum packet length */
#define ATH_AGGR_ENCRYPTDELIM   10
#define ATH_AGGR_MIN_QDEPTH   2
#define ATH_AMPDU_SUBFRAME_DEFAULT   32
#define FCS_LEN   4
#define IEEE80211_SEQ_SEQ_SHIFT   4
#define IEEE80211_SEQ_MAX   4096
#define IEEE80211_WEP_IVLEN   3
#define IEEE80211_WEP_KIDLEN   1
#define IEEE80211_WEP_CRCLEN   4
#define IEEE80211_MAX_MPDU_LEN
#define ATH_BA_ISSET(_bm, _n)
#define ATH_BA_INDEX(_st, _seq)   (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
#define ATH_AGGR_GET_NDELIM(_len)
#define BAW_WITHIN(_start, _bawsz, _seqno)   ((((_seqno) - (_start)) & 4095) < (_bawsz))
#define ATH_AN_2_TID(_an, _tidno)   (&(_an)->tid[(_tidno)])
#define ATH_TX_COMPLETE_POLL_INT   1000
#define ATH_TXFIFO_DEPTH   8
#define AGGR_CLEANUP   BIT(1)
#define AGGR_ADDBA_COMPLETE   BIT(2)
#define AGGR_ADDBA_PROGRESS   BIT(3)
#define ATH_TX_ERROR   0x01
#define ATH_TX_XRETRY   0x02
#define ATH_TX_BAR   0x04
#define ATH_STA_SHORT_CALINTERVAL   1000 /* 1 second */
#define ATH_AP_SHORT_CALINTERVAL   100 /* 100 ms */
#define ATH_ANI_POLLINTERVAL_OLD   100 /* 100 ms */
#define ATH_ANI_POLLINTERVAL_NEW   1000 /* 1000 ms */
#define ATH_LONG_CALINTERVAL_INT   1000 /* 1000 ms */
#define ATH_LONG_CALINTERVAL   30000 /* 30 seconds */
#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
#define DEFAULT_CACHELINE   32
#define ATH_REGCLASSIDS_MAX   10
#define ATH_CABQ_READY_TIME   80 /* % of beacon interval */
#define ATH_MAX_SW_RETRIES   10
#define ATH_CHAN_MAX   255
#define ATH_TXPOWER_MAX   100 /* .5 dBm units */
#define ATH_RATE_DUMMY_MARKER   0
#define SC_OP_INVALID   BIT(0)
#define SC_OP_BEACONS   BIT(1)
#define SC_OP_RXAGGR   BIT(2)
#define SC_OP_TXAGGR   BIT(3)
#define SC_OP_OFFCHANNEL   BIT(4)
#define SC_OP_PREAMBLE_SHORT   BIT(5)
#define SC_OP_PROTECT_ENABLE   BIT(6)
#define SC_OP_RXFLUSH   BIT(7)
#define SC_OP_LED_ASSOCIATED   BIT(8)
#define SC_OP_LED_ON   BIT(9)
#define SC_OP_TSF_RESET   BIT(11)
#define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
#define SC_OP_BT_SCAN   BIT(13)
#define SC_OP_ANI_RUN   BIT(14)
#define SC_OP_ENABLE_APM   BIT(15)
#define SC_OP_PRIM_STA_VIF   BIT(16)
#define PS_WAIT_FOR_BEACON   BIT(0)
#define PS_WAIT_FOR_CAB   BIT(1)
#define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
#define PS_WAIT_FOR_TX_ACK   BIT(3)
#define PS_BEACON_SYNC   BIT(4)
#define PS_TSFOOR_SYNC   BIT(5)

Enumerations

enum  buffer_type { BUF_AMPDU = BIT(0), BUF_AGGR = BIT(1), BUF_XRETRY = BIT(2) }
 enum buffer_type - Buffer type flags More...
enum  ATH_AGGR_STATUS { ATH_AGGR_DONE, ATH_AGGR_BAW_CLOSED, ATH_AGGR_LIMITED }
enum  ath9k_rate_control_flags {
  IEEE80211_TX_RC_USE_RTS_CTS = BIT(0), IEEE80211_TX_RC_USE_CTS_PROTECT = BIT(1), IEEE80211_TX_RC_USE_SHORT_PREAMBLE = BIT(2), IEEE80211_TX_RC_MCS = BIT(3),
  IEEE80211_TX_RC_GREEN_FIELD = BIT(4), IEEE80211_TX_RC_40_MHZ_WIDTH = BIT(5), IEEE80211_TX_RC_DUP_DATA = BIT(6), IEEE80211_TX_RC_SHORT_GI = BIT(7)
}
enum  survey_info_flags {
  SURVEY_INFO_NOISE_DBM = 1<<0, SURVEY_INFO_IN_USE = 1<<1, SURVEY_INFO_CHANNEL_TIME = 1<<2, SURVEY_INFO_CHANNEL_TIME_BUSY = 1<<3,
  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY = 1<<4, SURVEY_INFO_CHANNEL_TIME_RX = 1<<5, SURVEY_INFO_CHANNEL_TIME_TX = 1<<6
}

Functions

 FILE_LICENCE (BSD2)
int ath_descdma_setup (struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head, const char *name, int nbuf, int ndesc, int is_tx)
void ath_descdma_cleanup (struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head)
int ath_startrecv (struct ath_softc *sc)
int ath_stoprecv (struct ath_softc *sc)
void ath_flushrecv (struct ath_softc *sc)
u32 ath_calcrxfilter (struct ath_softc *sc)
int ath_rx_init (struct ath_softc *sc, int nbufs)
void ath_rx_cleanup (struct ath_softc *sc)
int ath_rx_tasklet (struct ath_softc *sc, int flush, int hp)
struct ath_txqath_txq_setup (struct ath_softc *sc, int qtype, int subtype)
void ath_tx_cleanupq (struct ath_softc *sc, struct ath_txq *txq)
int ath_drain_all_txq (struct ath_softc *sc, int retry_tx)
void ath_draintxq (struct ath_softc *sc, struct ath_txq *txq, int retry_tx)
void ath_txq_schedule (struct ath_softc *sc, struct ath_txq *txq)
int ath_tx_init (struct ath_softc *sc, int nbufs)
void ath_tx_cleanup (struct ath_softc *sc)
int ath_txq_update (struct ath_softc *sc, int qnum, struct ath9k_tx_queue_info *q)
int ath_tx_start (struct net80211_device *dev, struct io_buffer *iob, struct ath_tx_control *txctl)
void ath_tx_tasklet (struct ath_softc *sc)
void ath_hw_pll_work (struct ath_softc *sc)
void ath_ani_calibrate (struct ath_softc *sc)
void ath9k_tasklet (struct ath_softc *sc)
int ath_reset (struct ath_softc *sc, int retry_tx)
static void ath_read_cachesize (struct ath_common *common, int *csz)
void ath_isr (struct net80211_device *dev)
void ath9k_init_crypto (struct ath_softc *sc)
int ath9k_init_device (u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
void ath9k_deinit_device (struct ath_softc *sc)
void ath9k_set_hw_capab (struct ath_softc *sc, struct net80211_device *dev)
int ath_set_channel (struct ath_softc *sc, struct net80211_device *dev, struct ath9k_channel *hchan)
void ath_radio_enable (struct ath_softc *sc, struct net80211_device *dev)
void ath_radio_disable (struct ath_softc *sc, struct net80211_device *dev)
int ath9k_setpower (struct ath_softc *sc, enum ath9k_power_mode mode)
int ath9k_uses_beacons (int type)
u8 ath_txchainmask_reduction (struct ath_softc *sc, u8 chainmask, u32 rate)
void ath_start_rfkill_poll (struct ath_softc *sc)
void ath9k_rfkill_poll_state (struct net80211_device *dev)

Variables

struct ath_config __attribute__
struct net80211_device_operations ath9k_ops
int ath9k_modparam_nohwcrypt
int is_ath9k_unloaded

Define Documentation

#define ito64 (   x)
Value:
(sizeof(x) == 1) ?                      \
        (((unsigned long long int)(x)) & (0xff)) :      \
        (sizeof(x) == 2) ?                              \
        (((unsigned long long int)(x)) & 0xffff) :      \
        ((sizeof(x) == 4) ?                             \
         (((unsigned long long int)(x)) & 0xffffffff) : \
         (unsigned long long int)(x))

Definition at line 37 of file ath9k.h.

Referenced by ath_descdma_setup(), and ath_tx_txqaddbuf().

#define INCR (   _l,
  _sz 
)
Value:
do {                    \
                (_l)++;                         \
                (_l) &= ((_sz) - 1);            \
        } while (0)

Definition at line 46 of file ath9k.h.

Referenced by ath_tx_send_normal().

#define DECR (   _l,
  _sz 
)
Value:
do {                    \
                (_l)--;                         \
                (_l) &= ((_sz) - 1);            \
        } while (0)

Definition at line 52 of file ath9k.h.

#define A_MAX (   a,
 
)    ((a) > (b) ? (a) : (b))

Definition at line 57 of file ath9k.h.

#define TSF_TO_TU (   _h,
  _l 
)    ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))

Definition at line 59 of file ath9k.h.

#define ATH_TXQ_SETUP (   sc,
 
)    ((sc)->tx.txqsetup & (1<<i))
#define ATH_TXBUF_RESET (   _bf)
Value:
do {                            \
                (_bf)->bf_stale = 0;                    \
                (_bf)->bf_lastbf = NULL;                        \
                (_bf)->bf_next = NULL;                          \
                memset(&((_bf)->bf_state), 0,                   \
                       sizeof(struct ath_buf_state));           \
        } while (0)

Definition at line 73 of file ath9k.h.

Referenced by ath_tx_setup_buffer().

#define ATH_RXBUF_RESET (   _bf)
Value:
do {            \
                (_bf)->bf_stale = 0;    \
        } while (0)

Definition at line 81 of file ath9k.h.

Referenced by ath_rx_buf_link().

#define bf_isampdu (   bf)    (bf->bf_state.bf_type & BUF_AMPDU)

Definition at line 99 of file ath9k.h.

#define bf_isaggr (   bf)    (bf->bf_state.bf_type & BUF_AGGR)

Definition at line 100 of file ath9k.h.

Referenced by ath_buf_set_rate().

#define bf_isxretried (   bf)    (bf->bf_state.bf_type & BUF_XRETRY)

Definition at line 101 of file ath9k.h.

Referenced by ath_tx_complete_buf().

#define ATH_TXSTATUS_RING_SIZE   64

Definition at line 103 of file ath9k.h.

#define ATH_RXBUF   16

Definition at line 122 of file ath9k.h.

#define ATH_TXBUF   16

Definition at line 123 of file ath9k.h.

#define ATH_TXBUF_RESERVE   5

Definition at line 124 of file ath9k.h.

Definition at line 125 of file ath9k.h.

Referenced by ath_tx_complete(), and ath_tx_start().

#define ATH_TXMAXTRY   13

Definition at line 126 of file ath9k.h.

Referenced by ath_buf_set_rate().

#define TID_TO_WME_AC (   _tid)
Value:
((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
         (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
         (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
         WME_AC_VO)

Definition at line 128 of file ath9k.h.

#define ATH_AGGR_DELIM_SZ   4

Definition at line 134 of file ath9k.h.

#define ATH_AGGR_MINPLEN   256 /* in bytes, minimum packet length */

Definition at line 135 of file ath9k.h.

#define ATH_AGGR_ENCRYPTDELIM   10

Definition at line 137 of file ath9k.h.

#define ATH_AGGR_MIN_QDEPTH   2

Definition at line 139 of file ath9k.h.

Referenced by ath_txq_schedule().

#define ATH_AMPDU_SUBFRAME_DEFAULT   32

Definition at line 140 of file ath9k.h.

#define FCS_LEN   4

Definition at line 142 of file ath9k.h.

#define IEEE80211_SEQ_SEQ_SHIFT   4

Definition at line 143 of file ath9k.h.

#define IEEE80211_SEQ_MAX   4096

Definition at line 144 of file ath9k.h.

Referenced by ath_tx_send_normal().

#define IEEE80211_WEP_IVLEN   3

Definition at line 145 of file ath9k.h.

#define IEEE80211_WEP_KIDLEN   1

Definition at line 146 of file ath9k.h.

#define IEEE80211_WEP_CRCLEN   4

Definition at line 147 of file ath9k.h.

Value:
(3840 + FCS_LEN +               \
                                    (IEEE80211_WEP_IVLEN +      \
                                     IEEE80211_WEP_KIDLEN +     \
                                     IEEE80211_WEP_CRCLEN))

Definition at line 148 of file ath9k.h.

Referenced by ath_rx_init().

#define ATH_BA_ISSET (   _bm,
  _n 
)
Value:
(((_n) < (WME_BA_BMP_SIZE)) &&          \
                                ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))

Definition at line 155 of file ath9k.h.

#define ATH_BA_INDEX (   _st,
  _seq 
)    (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))

Definition at line 159 of file ath9k.h.

#define ATH_AGGR_GET_NDELIM (   _len)
Value:
(((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
        DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))

Definition at line 162 of file ath9k.h.

#define BAW_WITHIN (   _start,
  _bawsz,
  _seqno 
)    ((((_seqno) - (_start)) & 4095) < (_bawsz))

Definition at line 166 of file ath9k.h.

#define ATH_AN_2_TID (   _an,
  _tidno 
)    (&(_an)->tid[(_tidno)])

Definition at line 169 of file ath9k.h.

#define ATH_TX_COMPLETE_POLL_INT   1000

Definition at line 171 of file ath9k.h.

Referenced by ath_tx_complete_poll_work().

#define ATH_TXFIFO_DEPTH   8

Definition at line 179 of file ath9k.h.

Referenced by ath_txq_setup().

#define AGGR_CLEANUP   BIT(1)

Definition at line 261 of file ath9k.h.

#define AGGR_ADDBA_COMPLETE   BIT(2)

Definition at line 262 of file ath9k.h.

#define AGGR_ADDBA_PROGRESS   BIT(3)

Definition at line 263 of file ath9k.h.

#define ATH_TX_ERROR   0x01

Definition at line 272 of file ath9k.h.

Referenced by ath_tx_complete_buf().

#define ATH_TX_XRETRY   0x02

Definition at line 273 of file ath9k.h.

Referenced by ath_tx_complete_buf().

#define ATH_TX_BAR   0x04

Definition at line 274 of file ath9k.h.

Referenced by ath_tx_complete_buf().

#define ATH_STA_SHORT_CALINTERVAL   1000 /* 1 second */

Definition at line 334 of file ath9k.h.

Referenced by ath_ani_calibrate().

#define ATH_AP_SHORT_CALINTERVAL   100 /* 100 ms */

Definition at line 335 of file ath9k.h.

#define ATH_ANI_POLLINTERVAL_OLD   100 /* 100 ms */

Definition at line 336 of file ath9k.h.

#define ATH_ANI_POLLINTERVAL_NEW   1000 /* 1000 ms */

Definition at line 337 of file ath9k.h.

#define ATH_LONG_CALINTERVAL_INT   1000 /* 1000 ms */

Definition at line 338 of file ath9k.h.

Referenced by ath_ani_calibrate().

#define ATH_LONG_CALINTERVAL   30000 /* 30 seconds */

Definition at line 339 of file ath9k.h.

Referenced by ath_ani_calibrate().

#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */

Definition at line 340 of file ath9k.h.

Referenced by ath_ani_calibrate().

#define DEFAULT_CACHELINE   32

Definition at line 353 of file ath9k.h.

Referenced by ath_pci_read_cachesize().

#define ATH_REGCLASSIDS_MAX   10

Definition at line 354 of file ath9k.h.

#define ATH_CABQ_READY_TIME   80 /* % of beacon interval */

Definition at line 355 of file ath9k.h.

#define ATH_MAX_SW_RETRIES   10

Definition at line 356 of file ath9k.h.

#define ATH_CHAN_MAX   255

Definition at line 357 of file ath9k.h.

#define ATH_TXPOWER_MAX   100 /* .5 dBm units */

Definition at line 359 of file ath9k.h.

Referenced by ath9k_init_misc().

#define ATH_RATE_DUMMY_MARKER   0

Definition at line 360 of file ath9k.h.

#define SC_OP_INVALID   BIT(0)
#define SC_OP_BEACONS   BIT(1)

Definition at line 363 of file ath9k.h.

Referenced by ath9k_config_bss().

#define SC_OP_RXAGGR   BIT(2)

Definition at line 364 of file ath9k.h.

#define SC_OP_TXAGGR   BIT(3)

Definition at line 365 of file ath9k.h.

Referenced by ath_tx_processq().

#define SC_OP_OFFCHANNEL   BIT(4)

Definition at line 366 of file ath9k.h.

Referenced by ath9k_config(), ath_set_channel(), ath_start_ani(), and ath_startrecv().

#define SC_OP_PREAMBLE_SHORT   BIT(5)

Definition at line 367 of file ath9k.h.

Referenced by ath9k_bss_info_changed(), ath9k_config(), and ath_buf_set_rate().

#define SC_OP_PROTECT_ENABLE   BIT(6)

Definition at line 368 of file ath9k.h.

Referenced by ath9k_bss_info_changed(), and ath_buf_set_rate().

#define SC_OP_RXFLUSH   BIT(7)

Definition at line 369 of file ath9k.h.

Referenced by ath_flushrecv(), ath_rx_init(), and ath_rx_tasklet().

#define SC_OP_LED_ASSOCIATED   BIT(8)

Definition at line 370 of file ath9k.h.

#define SC_OP_LED_ON   BIT(9)

Definition at line 371 of file ath9k.h.

#define SC_OP_TSF_RESET   BIT(11)

Definition at line 372 of file ath9k.h.

#define SC_OP_BT_PRIORITY_DETECTED   BIT(12)

Definition at line 373 of file ath9k.h.

#define SC_OP_BT_SCAN   BIT(13)

Definition at line 374 of file ath9k.h.

#define SC_OP_ANI_RUN   BIT(14)

Definition at line 375 of file ath9k.h.

Referenced by ath9k_bss_iter(), ath9k_config_bss(), and ath_start_ani().

#define SC_OP_ENABLE_APM   BIT(15)

Definition at line 376 of file ath9k.h.

Referenced by ath_txchainmask_reduction().

#define SC_OP_PRIM_STA_VIF   BIT(16)

Definition at line 377 of file ath9k.h.

Referenced by ath9k_bss_iter(), and ath9k_config_bss().

#define PS_WAIT_FOR_BEACON   BIT(0)

Definition at line 380 of file ath9k.h.

Referenced by ath9k_bss_iter(), and ath_isr().

#define PS_WAIT_FOR_CAB   BIT(1)

Definition at line 381 of file ath9k.h.

#define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)

Definition at line 382 of file ath9k.h.

#define PS_WAIT_FOR_TX_ACK   BIT(3)

Definition at line 383 of file ath9k.h.

#define PS_BEACON_SYNC   BIT(4)

Definition at line 384 of file ath9k.h.

Referenced by ath9k_bss_iter().

#define PS_TSFOOR_SYNC   BIT(5)

Definition at line 385 of file ath9k.h.


Enumeration Type Documentation

enum buffer_type - Buffer type flags

: This buffer is an ampdu, as part of an aggregate (during TX) : Indicates whether the buffer can be aggregated (used in aggregation scheduling) : To denote excessive retries of the buffer

Enumerator:
BUF_AMPDU 
BUF_AGGR 
BUF_XRETRY 

Definition at line 93 of file ath9k.h.

                 {
        BUF_AMPDU               = BIT(0),
        BUF_AGGR                = BIT(1),
        BUF_XRETRY              = BIT(2),
};
Enumerator:
ATH_AGGR_DONE 
ATH_AGGR_BAW_CLOSED 
ATH_AGGR_LIMITED 

Definition at line 173 of file ath9k.h.

Enumerator:
IEEE80211_TX_RC_USE_RTS_CTS 
IEEE80211_TX_RC_USE_CTS_PROTECT 
IEEE80211_TX_RC_USE_SHORT_PREAMBLE 
IEEE80211_TX_RC_MCS 
IEEE80211_TX_RC_GREEN_FIELD 
IEEE80211_TX_RC_40_MHZ_WIDTH 
IEEE80211_TX_RC_DUP_DATA 
IEEE80211_TX_RC_SHORT_GI 

Definition at line 396 of file ath9k.h.

Enumerator:
SURVEY_INFO_NOISE_DBM 
SURVEY_INFO_IN_USE 
SURVEY_INFO_CHANNEL_TIME 
SURVEY_INFO_CHANNEL_TIME_BUSY 
SURVEY_INFO_CHANNEL_TIME_EXT_BUSY 
SURVEY_INFO_CHANNEL_TIME_RX 
SURVEY_INFO_CHANNEL_TIME_TX 

Definition at line 420 of file ath9k.h.


Function Documentation

FILE_LICENCE ( BSD2  )
int ath_descdma_setup ( struct ath_softc sc,
struct ath_descdma dd,
struct list_head head,
const char *  name,
int  nbuf,
int  ndesc,
int  is_tx 
)

Definition at line 180 of file ath9k_init.c.

References ATH9K_HW_CAP_4KB_SPLITTRANS, ATH_DESC_4KB_BOUND_CHECK, ath_buf::bf_desc, ath_hw::caps, DBG, DBG2, ath_descdma::dd_bufptr, ath_descdma::dd_desc, ath_descdma::dd_desc_len, ath_descdma::dd_desc_paddr, ds, DS2PHYS, ENOMEM, error, free_dma(), ath9k_hw_capabilities::hw_caps, INIT_LIST_HEAD, ito64, list_add_tail, malloc_dma(), memset(), NULL, ath_softc::sc_ah, ath9k_hw_capabilities::tx_desc_len, virt_to_bus(), and zalloc().

Referenced by ath_rx_init(), and ath_tx_init().

{
#define DS2PHYS(_dd, _ds)                                               \
        ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))
#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)
        u8 *ds;
        struct ath_buf *bf;
        int i, bsize, error, desc_len;

        DBG2("ath9k: %s DMA: %d buffers %d desc/buf\n",
                name, nbuf, ndesc);

        INIT_LIST_HEAD(head);

        if (is_tx)
                desc_len = sc->sc_ah->caps.tx_desc_len;
        else
                desc_len = sizeof(struct ath_desc);

        /* ath_desc must be a multiple of DWORDs */
        if ((desc_len % 4) != 0) {
                DBG("ath9k: ath_desc not DWORD aligned\n");
                error = -ENOMEM;
                goto fail;
        }

        dd->dd_desc_len = desc_len * nbuf * ndesc;

        /*
         * Need additional DMA memory because we can't use
         * descriptors that cross the 4K page boundary.
         * However, iPXE only utilizes 16 buffers, which
         * will never make up more than half of one page,
         * so we will only ever skip 1 descriptor, if that.
         */
        if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
                u32 ndesc_skipped = 1;
                u32 dma_len;

                dma_len = ndesc_skipped * desc_len;
                dd->dd_desc_len += dma_len;
        }

        /* allocate descriptors */
        dd->dd_desc = malloc_dma(dd->dd_desc_len, 16);
        if (dd->dd_desc == NULL) {
                error = -ENOMEM;
                goto fail;
        }
        dd->dd_desc_paddr = virt_to_bus(dd->dd_desc);
        ds = (u8 *) dd->dd_desc;
        DBG2("ath9k: %s DMA map: %p (%d) -> %llx (%d)\n",
                name, ds, (u32) dd->dd_desc_len,
                ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);

        /* allocate buffers */
        bsize = sizeof(struct ath_buf) * nbuf;
        bf = zalloc(bsize);
        if (bf == NULL) {
                error = -ENOMEM;
                goto fail2;
        }
        dd->dd_bufptr = bf;

        for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
                bf->bf_desc = ds;
                bf->bf_daddr = DS2PHYS(dd, ds);

                if (!(sc->sc_ah->caps.hw_caps &
                      ATH9K_HW_CAP_4KB_SPLITTRANS)) {
                        /*
                         * Skip descriptor addresses which can cause 4KB
                         * boundary crossing (addr + length) with a 32 dword
                         * descriptor fetch.
                         */
                        while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
                                ds += (desc_len * ndesc);
                                bf->bf_desc = ds;
                                bf->bf_daddr = DS2PHYS(dd, ds);
                        }
                }
                list_add_tail(&bf->list, head);
        }
        return 0;
fail2:
        free_dma(dd->dd_desc, dd->dd_desc_len);
fail:
        memset(dd, 0, sizeof(*dd));
        return error;
#undef ATH_DESC_4KB_BOUND_CHECK
#undef DS2PHYS
}
void ath_descdma_cleanup ( struct ath_softc sc,
struct ath_descdma dd,
struct list_head head 
)

Referenced by ath_rx_cleanup(), and ath_tx_cleanup().

int ath_startrecv ( struct ath_softc sc)

Definition at line 194 of file ath9k_recv.c.

References ah, ath9k_hw_putrxbuf(), ath9k_hw_rxena(), ath9k_hw_startpcureceive(), ath_opmode_init(), ath_rx_buf_link(), ath_buf::bf_daddr, ath_buf::list, list_empty, list_first_entry, list_for_each_entry_safe, NULL, ath_softc::rx, ath_rx::rxbuf, ath_rx::rxlink, ath_softc::sc_ah, ath_softc::sc_flags, and SC_OP_OFFCHANNEL.

Referenced by ath9k_start(), ath_reset(), and ath_set_channel().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath_buf *bf, *tbf;

        if (list_empty(&sc->rx.rxbuf))
                goto start_recv;

        sc->rx.rxlink = NULL;
        list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
                ath_rx_buf_link(sc, bf);
        }

        /* We could have deleted elements so the list may be empty now */
        if (list_empty(&sc->rx.rxbuf))
                goto start_recv;

        bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
        ath9k_hw_putrxbuf(ah, bf->bf_daddr);
        ath9k_hw_rxena(ah);

start_recv:
        ath_opmode_init(sc);
        ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));

        return 0;
}
int ath_stoprecv ( struct ath_softc sc)

Definition at line 222 of file ath9k_recv.c.

References ah, ath_hw::ah_flags, AH_UNPLUGGED, ath9k_hw_abortpcurecv(), ath9k_hw_setrxfilter(), ath9k_hw_stopdmarecv(), DBG, NULL, ath_softc::rx, ath_rx::rxlink, and ath_softc::sc_ah.

Referenced by ath9k_stop(), ath_radio_disable(), ath_reset(), and ath_set_channel().

{
        struct ath_hw *ah = sc->sc_ah;
        int stopped, reset = 0;

        ath9k_hw_abortpcurecv(ah);
        ath9k_hw_setrxfilter(ah, 0);
        stopped = ath9k_hw_stopdmarecv(ah, &reset);

        sc->rx.rxlink = NULL;

        if (!(ah->ah_flags & AH_UNPLUGGED) &&
            !stopped) {
                DBG("ath9k: "
                        "Could not stop RX, we could be "
                        "confusing the DMA engine when we start RX up\n");
        }
        return stopped && !reset;
}
void ath_flushrecv ( struct ath_softc sc)

Definition at line 242 of file ath9k_recv.c.

References ath_rx_tasklet(), ath_softc::sc_flags, and SC_OP_RXFLUSH.

Referenced by ath_radio_disable(), and ath_reset().

u32 ath_calcrxfilter ( struct ath_softc sc)

Definition at line 179 of file ath9k_recv.c.

References ath9k_hw_getrxfilter(), ATH9K_RX_FILTER_BCAST, ATH9K_RX_FILTER_BEACON, ATH9K_RX_FILTER_MCAST, ATH9K_RX_FILTER_UCAST, RX_FILTER_PRESERVE, and ath_softc::sc_ah.

Referenced by ath_opmode_init().

{
#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)

        u32 rfilt;

        rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
                | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
                | ATH9K_RX_FILTER_MCAST | ATH9K_RX_FILTER_BEACON;

        return rfilt;

#undef RX_FILTER_PRESERVE
}
int ath_rx_init ( struct ath_softc sc,
int  nbufs 
)

Definition at line 97 of file ath9k_recv.c.

References alloc_iob_raw(), ath9k_hw_common(), ath_descdma_setup(), ath_rx_cleanup(), ath_buf::bf_buf_addr, ath_buf::bf_mpdu, ath_common::cachelsz, ath_hw::caps, common, io_buffer::data, DBG, DBG2, ENOMEM, error, IEEE80211_MAX_MPDU_LEN, ath_buf::list, list_for_each_entry, NULL, ath_softc::rx, ath_common::rx_bufsize, ath9k_hw_capabilities::rx_status_len, ath_rx::rxbuf, ath_rx::rxdma, ath_rx::rxlink, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_RXFLUSH, and virt_to_bus().

Referenced by ath9k_init_device().

{
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
        struct io_buffer *iob;
        struct ath_buf *bf;
        int error = 0;

        sc->sc_flags &= ~SC_OP_RXFLUSH;

        common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
                             sc->sc_ah->caps.rx_status_len;

        DBG2("ath9k: cachelsz %d rxbufsize %d\n",
                common->cachelsz, common->rx_bufsize);

        /* Initialize rx descriptors */

        error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
                        "rx", nbufs, 1, 0);
        if (error != 0) {
                DBG("ath9k: "
                        "failed to allocate rx descriptors: %d\n",
                        error);
                goto err;
        }

        list_for_each_entry(bf, &sc->rx.rxbuf, list) {
                iob = alloc_iob_raw ( common->rx_bufsize, common->cachelsz, 0 );
                if (iob == NULL) {
                        error = -ENOMEM;
                        goto err;
                }

                bf->bf_mpdu = iob;
                bf->bf_buf_addr = virt_to_bus ( iob->data );
        }
        sc->rx.rxlink = NULL;

err:
        if (error)
                ath_rx_cleanup(sc);

        return error;
}
void ath_rx_cleanup ( struct ath_softc sc)
int ath_rx_tasklet ( struct ath_softc sc,
int  flush,
int  hp 
)

Definition at line 430 of file ath9k_recv.c.

References ah, alloc_iob_raw(), ath9k_hw_common(), ath9k_hw_rxena(), ath9k_rx_iob_preprocess(), ath_get_next_rx_buf(), ath_rx_buf_link(), ath_setdefantenna(), ath_buf::bf_buf_addr, ath_buf::bf_mpdu, ath9k_legacy_rate::bitrate, ath_common::cachelsz, ath_hw::caps, common, DBGIO, ath_rx::defant, ath_softc::dev, iob_pull, iob_put, ath_buf::list, list_add_tail, list_del, memset(), net80211_rx(), NULL, ath_softc::rates, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_softc::rx, ath_common::rx_bufsize, ath9k_hw_capabilities::rx_status_len, ath_rx::rxbuf, ath_rx::rxotherant, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_RXFLUSH, and virt_to_bus().

Referenced by ath9k_tasklet(), and ath_flushrecv().

{
        struct ath_buf *bf;
        struct io_buffer *iob = NULL, *requeue_iob;
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        /*
         * The hw can technically differ from common->hw when using ath9k
         * virtual wiphy so to account for that we iterate over the active
         * wiphys and find the appropriate wiphy and therefore hw.
         */
        struct net80211_device *dev = sc->dev;
        int retval;
        int decrypt_error = 0;
        struct ath_rx_status rs;
        int rix = 0;

        do {
                /* If handling rx interrupt and flush is in progress => exit */
                if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
                        break;

                memset(&rs, 0, sizeof(rs));
                bf = ath_get_next_rx_buf(sc, &rs);

                if (!bf)
                        break;

                iob = bf->bf_mpdu;
                if (!iob)
                        continue;

                /*
                 * If we're asked to flush receive queue, directly
                 * chain it back at the queue without processing it.
                 */
                if (flush)
                        goto requeue_drop_frag;

                retval = ath9k_rx_iob_preprocess(common, dev, &rs,
                                                 &rix, &decrypt_error);
                if (retval)
                        goto requeue_drop_frag;

                /* Ensure we always have an iob to requeue once we are done
                 * processing the current buffer's iob */
                requeue_iob = alloc_iob_raw ( common->rx_bufsize,
                                              common->cachelsz, 0 );

                /* If there is no memory we ignore the current RX'd frame,
                 * tell hardware it can give us a new frame using the old
                 * iob and put it at the tail of the sc->rx.rxbuf list for
                 * processing. */
                if (!requeue_iob)
                        goto requeue_drop_frag;

                iob_put(iob, rs.rs_datalen + ah->caps.rx_status_len);
                if (ah->caps.rx_status_len)
                        iob_pull(iob, ah->caps.rx_status_len);

                /* We will now give hardware our shiny new allocated iob */
                bf->bf_mpdu = requeue_iob;
                bf->bf_buf_addr = virt_to_bus ( requeue_iob->data );

                /*
                 * change the default rx antenna if rx diversity chooses the
                 * other antenna 3 times in a row.
                 */
                if (sc->rx.defant != rs.rs_antenna) {
                        if (++sc->rx.rxotherant >= 3)
                                ath_setdefantenna(sc, rs.rs_antenna);
                } else {
                        sc->rx.rxotherant = 0;
                }

                DBGIO("ath9k: rx %d bytes, signal %d, bitrate %d, hw_value %d\n", rs.rs_datalen,
                                                rs.rs_rssi, sc->rates[rix].bitrate, rs.rs_rate);

                net80211_rx(dev, iob, rs.rs_rssi,
                                sc->rates[rix].bitrate);

requeue_drop_frag:
                list_del(&bf->list);
                list_add_tail(&bf->list, &sc->rx.rxbuf);
                ath_rx_buf_link(sc, bf);
                ath9k_hw_rxena(ah);
        } while (1);

        return 0;
}
struct ath_txq* ath_txq_setup ( struct ath_softc sc,
int  qtype,
int  subtype 
) [read]

Definition at line 106 of file ath9k_xmit.c.

References ah, ARRAY_SIZE, ath9k_hw_releasetxqueue(), ath9k_hw_setuptxqueue(), ATH9K_TXQ_USEDEFAULT, ATH_TXFIFO_DEPTH, ATH_TXQ_AC_BE, ATH_TXQ_SETUP, ath_txq::axq_acq, ath_txq::axq_ampdu_depth, ath_txq::axq_depth, ath_txq::axq_link, ath_txq::axq_q, ath_txq::axq_qnum, ath_txq::axq_tx_inprogress, DBG, INIT_LIST_HEAD, ath_txq::mac80211_qnum, memset(), NULL, ath_softc::sc_ah, subtype, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_physCompBuf, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_subtype, ath_softc::tx, ath_tx::txq, ath_txq::txq_fifo, ath_txq::txq_fifo_pending, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXEOLINT_ENABLE, ath_txq::txq_headidx, ath_txq::txq_tailidx, ath_tx::txqsetup, and WME_AC_BE.

Referenced by ath9k_init_queues().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath9k_tx_queue_info qi;
        static const int subtype_txq_to_hwq[] = {
                [WME_AC_BE] = ATH_TXQ_AC_BE,
        };
        int axq_qnum, i;

        memset(&qi, 0, sizeof(qi));
        qi.tqi_subtype = subtype_txq_to_hwq[subtype];
        qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
        qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
        qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
        qi.tqi_physCompBuf = 0;

        /*
         * Enable interrupts only for EOL and DESC conditions.
         * We mark tx descriptors to receive a DESC interrupt
         * when a tx queue gets deep; otherwise waiting for the
         * EOL to reap descriptors.  Note that this is done to
         * reduce interrupt load and this only defers reaping
         * descriptors, never transmitting frames.  Aside from
         * reducing interrupts this also permits more concurrency.
         * The only potential downside is if the tx queue backs
         * up in which case the top half of the kernel may backup
         * due to a lack of tx descriptors.
         *
         * The UAPSD queue is an exception, since we take a desc-
         * based intr on the EOSP frames.
         */
        qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
                        TXQ_FLAG_TXDESCINT_ENABLE;

        axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
        if (axq_qnum == -1) {
                /*
                 * NB: don't print a message, this happens
                 * normally on parts with too few tx queues
                 */
                return NULL;
        }
        if ((unsigned int)axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
                DBG("ath9k: qnum %d out of range, max %zd!\n",
                        axq_qnum, ARRAY_SIZE(sc->tx.txq));
                ath9k_hw_releasetxqueue(ah, axq_qnum);
                return NULL;
        }
        if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
                struct ath_txq *txq = &sc->tx.txq[axq_qnum];

                txq->axq_qnum = axq_qnum;
                txq->mac80211_qnum = -1;
                txq->axq_link = NULL;
                INIT_LIST_HEAD(&txq->axq_q);
                INIT_LIST_HEAD(&txq->axq_acq);
                txq->axq_depth = 0;
                txq->axq_ampdu_depth = 0;
                txq->axq_tx_inprogress = 0;
                sc->tx.txqsetup |= 1<<axq_qnum;

                txq->txq_headidx = txq->txq_tailidx = 0;
                for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
                        INIT_LIST_HEAD(&txq->txq_fifo[i]);
                INIT_LIST_HEAD(&txq->txq_fifo_pending);
        }
        return &sc->tx.txq[axq_qnum];
}
void ath_tx_cleanupq ( struct ath_softc sc,
struct ath_txq txq 
)
int ath_drain_all_txq ( struct ath_softc sc,
int  retry_tx 
)

Definition at line 216 of file ath9k_xmit.c.

References ah, ath9k_hw_abort_tx_dma(), ath9k_hw_numtxpending(), ATH9K_NUM_TX_QUEUES, ath_draintxq(), ATH_TXQ_SETUP, ath_txq::axq_qnum, DBG, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, ath_txq::stopped, ath_softc::tx, and ath_tx::txq.

Referenced by ath9k_stop(), ath_radio_disable(), ath_reset(), and ath_set_channel().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath_txq *txq;
        int i, npend = 0;

        if (sc->sc_flags & SC_OP_INVALID)
                return 1;

        ath9k_hw_abort_tx_dma(ah);

        /* Check if any queue remains active */
        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
                if (!ATH_TXQ_SETUP(sc, i))
                        continue;

                npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
        }

        if (npend)
                DBG("ath9k: Failed to stop TX DMA!\n");

        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
                if (!ATH_TXQ_SETUP(sc, i))
                        continue;

                /*
                 * The caller will resume queues with ieee80211_wake_queues.
                 * Mark the queue as not stopped to prevent ath_tx_complete
                 * from waking the queue too early.
                 */
                txq = &sc->tx.txq[i];
                txq->stopped = 0;
                ath_draintxq(sc, txq, retry_tx);
        }

        return !npend;
}
void ath_draintxq ( struct ath_softc sc,
struct ath_txq txq,
int  retry_tx 
)

Definition at line 181 of file ath9k_xmit.c.

References __unused, ath_tx_complete_buf(), ath_tx_return_buffer(), ath_txq::axq_depth, ath_txq::axq_link, ath_txq::axq_q, ath_txq::axq_tx_inprogress, ath_buf::bf_lastbf, ath_buf::bf_stale, INIT_LIST_HEAD, ath_buf::list, list_cut_position, list_del, list_empty, list_first_entry, memset(), and NULL.

Referenced by ath_drain_all_txq().

{
        struct ath_buf *bf, *lastbf __unused;
        struct list_head bf_head;
        struct ath_tx_status ts;

        memset(&ts, 0, sizeof(ts));
        INIT_LIST_HEAD(&bf_head);

        for (;;) {
                if (list_empty(&txq->axq_q)) {
                        txq->axq_link = NULL;
                        break;
                }
                bf = list_first_entry(&txq->axq_q, struct ath_buf,
                                      list);

                if (bf->bf_stale) {
                        list_del(&bf->list);

                        ath_tx_return_buffer(sc, bf);
                        continue;
                }

                lastbf = bf->bf_lastbf;

                list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);

                txq->axq_depth--;
                ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
        }

        txq->axq_tx_inprogress = 0;
}
void ath_txq_schedule ( struct ath_softc sc,
struct ath_txq txq 
)

Referenced by ath_reset(), and ath_tx_processq().

int ath_tx_init ( struct ath_softc sc,
int  nbufs 
)

Definition at line 788 of file ath9k_xmit.c.

References ath_descdma_setup(), ath_tx_cleanup(), ath_tx_complete_poll_work(), DBG, error, ath_softc::tx, ath_softc::tx_complete_work, ath_tx::txbuf, and ath_tx::txdma.

Referenced by ath9k_init_device().

{
        int error = 0;

        error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
                                  "tx", nbufs, 1, 1);
        if (error != 0) {
                DBG("ath9k: "
                        "Failed to allocate tx descriptors: %d\n", error);
                goto err;
        }

        sc->tx_complete_work = ath_tx_complete_poll_work;

err:
        if (error != 0)
                ath_tx_cleanup(sc);

        return error;
}
void ath_tx_cleanup ( struct ath_softc sc)
int ath_txq_update ( struct ath_softc sc,
int  qnum,
struct ath9k_tx_queue_info q 
)
int ath_tx_start ( struct net80211_device dev,
struct io_buffer iob,
struct ath_tx_control txctl 
)

Definition at line 569 of file ath9k_xmit.c.

References ATH_MAX_QDEPTH, ath_tx_setup_buffer(), ath_tx_start_dma(), ENOMEM, ath_txq::pending_frames, net80211_device::priv, ath_txq::stopped, ath_softc::tx, ath_tx_control::txq, and ath_tx::txq_map.

Referenced by ath9k_tx().

{
        struct ath_softc *sc = dev->priv;
        struct ath_txq *txq = txctl->txq;
        struct ath_buf *bf;
        int q;

        /*
         * At this point, the vif, hw_key and sta pointers in the tx control
         * info are no longer valid (overwritten by the ath_frame_info data.
         */

        bf = ath_tx_setup_buffer(dev, txctl->txq, iob);
        if (!bf)
                return -ENOMEM;

        q = 0;
        if (txq == sc->tx.txq_map[q] &&
            ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
                txq->stopped = 1;
        }

        ath_tx_start_dma(sc, bf, txctl);

        return 0;
}
void ath_tx_tasklet ( struct ath_softc sc)

Definition at line 771 of file ath9k_xmit.c.

References ath9k_hw_gettxintrtxqs(), ATH9K_NUM_TX_QUEUES, ath_tx_processq(), ATH_TXQ_SETUP, ath_softc::sc_ah, ath_softc::tx, and ath_tx::txq.

Referenced by ath9k_tasklet().

{
        int i;
        u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);

        ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);

        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
                if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
                        ath_tx_processq(sc, &sc->tx.txq[i]);
        }
}
void ath_hw_pll_work ( struct ath_softc sc)
void ath_ani_calibrate ( struct ath_softc sc)

Definition at line 200 of file ath9k_main.c.

References ah, ath_common::ani, ath9k_ops_config::ani_poll_interval, ath9k_hw_ani_monitor(), ath9k_hw_calibrate(), ath9k_hw_common(), ath9k_hw_reset_calvalid(), ATH9K_PM_AWAKE, ATH_LONG_CALINTERVAL, ATH_LONG_CALINTERVAL_INT, ATH_RESTART_CALINTERVAL, ATH_STA_SHORT_CALINTERVAL, ath_update_survey_stats(), ath_hw::caldata, ath_ani::caldone, ath_ani::checkani_timer, common, ath_hw::config, ath_hw::curchan, currticks(), DBG2, ath9k_ops_config::enable_ani, ath_ani::longcal_timer, min, ath9k_hw_cal_data::nfcal_interference, ath_hw::power_mode, ath_ani::resetcal_timer, ath_common::rx_chainmask, ath_softc::sc_ah, ath_ani::shortcal_timer, TICKS_PER_SEC, ath_ani::timer, and timestamp.

Referenced by ath_isr().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        int longcal = 0;
        int shortcal = 0;
        int aniflag = 0;
        unsigned int timestamp = (currticks() * 1000 ) / TICKS_PER_SEC;
        u32 cal_interval, short_cal_interval, long_cal_interval;

        if (ah->caldata && ah->caldata->nfcal_interference)
                long_cal_interval = ATH_LONG_CALINTERVAL_INT;
        else
                long_cal_interval = ATH_LONG_CALINTERVAL;

        short_cal_interval = ATH_STA_SHORT_CALINTERVAL;

        /* Only calibrate if awake */
        if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
                goto set_timer;

        /* Long calibration runs independently of short calibration. */
        if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
                longcal = 1;
                DBG2("ath9k: longcal @%d\n", timestamp);
                common->ani.longcal_timer = timestamp;
        }

        /* Short calibration applies only while caldone is false */
        if (!common->ani.caldone) {
                if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
                        shortcal = 1;
                        DBG2("ath9k: "
                                "shortcal @%d\n", timestamp);
                        common->ani.shortcal_timer = timestamp;
                        common->ani.resetcal_timer = timestamp;
                }
        } else {
                if ((timestamp - common->ani.resetcal_timer) >=
                    ATH_RESTART_CALINTERVAL) {
                        common->ani.caldone = ath9k_hw_reset_calvalid(ah);
                        if (common->ani.caldone)
                                common->ani.resetcal_timer = timestamp;
                }
        }

        /* Verify whether we must check ANI */
        if ((timestamp - common->ani.checkani_timer) >=
             ah->config.ani_poll_interval) {
                aniflag = 1;
                common->ani.checkani_timer = timestamp;
        }

        /* Skip all processing if there's nothing to do. */
        if (longcal || shortcal || aniflag) {
                /* Call ANI routine if necessary */
                if (aniflag) {
                        ath9k_hw_ani_monitor(ah, ah->curchan);
                        ath_update_survey_stats(sc);
                }

                /* Perform calibration if necessary */
                if (longcal || shortcal) {
                        common->ani.caldone =
                                ath9k_hw_calibrate(ah,
                                                   ah->curchan,
                                                   common->rx_chainmask,
                                                   longcal);
                }
        }

set_timer:
        /*
        * Set timer interval based on previous results.
        * The interval must be the shortest necessary to satisfy ANI,
        * short calibration and long calibration.
        */
        cal_interval = ATH_LONG_CALINTERVAL;
        if (sc->sc_ah->config.enable_ani)
                cal_interval = min(cal_interval,
                                   (u32)ah->config.ani_poll_interval);
        if (!common->ani.caldone)
                cal_interval = min(cal_interval, (u32)short_cal_interval);

        common->ani.timer = timestamp + cal_interval;
}
void ath9k_tasklet ( struct ath_softc sc)

Definition at line 339 of file ath9k_main.c.

References ah, ath9k_hw_enable_interrupts(), ATH9K_INT_BB_WATCHDOG, ATH9K_INT_FATAL, ATH9K_INT_RX, ATH9K_INT_RXEOL, ATH9K_INT_RXORN, ATH9K_INT_TX, ath_reset(), ath_rx_tasklet(), ath_tx_tasklet(), ath_softc::intrstatus, ath_softc::sc_ah, and status.

Referenced by ath9k_init_softc().

{
        struct ath_hw *ah = sc->sc_ah;

        u32 status = sc->intrstatus;
        u32 rxmask;

        if ((status & ATH9K_INT_FATAL) ||
            (status & ATH9K_INT_BB_WATCHDOG)) {
                ath_reset(sc, 1);
                return;
        }

        rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);

        if (status & rxmask) {
                ath_rx_tasklet(sc, 0, 0);
        }

        if (status & ATH9K_INT_TX) {
                ath_tx_tasklet(sc);
        }

        /* re-enable hardware interrupt */
        ath9k_hw_enable_interrupts(ah);
}
int ath_reset ( struct ath_softc sc,
int  retry_tx 
)

Definition at line 511 of file ath9k_main.c.

References ah, ath_common::ani, ath9k_cmn_update_txpow(), ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_reset(), ath9k_hw_set_interrupts(), ATH9K_NUM_TX_QUEUES, ath_drain_all_txq(), ath_flushrecv(), ath_start_ani(), ath_startrecv(), ath_stoprecv(), ath_txq_schedule(), ATH_TXQ_SETUP, ath_hw::caldata, common, ath_softc::config, ath_hw::curchan, ath_softc::curtxpow, DBG, ath_softc::hw_busy_count, ath_hw::imask, r, ath_softc::sc_ah, ath_ani::timer, ath_softc::tx, ath_config::txpowlimit, and ath_tx::txq.

Referenced by ath9k_tasklet(), ath_hw_check(), ath_hw_pll_rx_hang_check(), and ath_tx_complete_poll_work().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        int r;

        sc->hw_busy_count = 0;

        /* Stop ANI */
        common->ani.timer = 0;

        ath9k_hw_disable_interrupts(ah);
        ath_drain_all_txq(sc, retry_tx);

        ath_stoprecv(sc);
        ath_flushrecv(sc);

        r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, 0);
        if (r)
                DBG("ath9k: "
                        "Unable to reset hardware; reset status %d\n", r);

        if (ath_startrecv(sc) != 0)
                DBG("ath9k: Unable to start recv logic\n");

        /*
         * We may be doing a reset in response to a request
         * that changes the channel so update any state that
         * might change as a result.
         */
        ath9k_cmn_update_txpow(ah, sc->curtxpow,
                               sc->config.txpowlimit, &sc->curtxpow);

        ath9k_hw_set_interrupts(ah, ah->imask);

        if (retry_tx) {
                int i;
                for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
                        if (ATH_TXQ_SETUP(sc, i)) {
                                ath_txq_schedule(sc, &sc->tx.txq[i]);
                        }
                }
        }

        /* Start ANI */
        ath_start_ani(common);

        return r;
}
static void ath_read_cachesize ( struct ath_common common,
int *  csz 
) [inline, static]

Definition at line 495 of file ath9k.h.

References ath_common::bus_ops, and ath_bus_ops::read_cachesize.

Referenced by ath9k_init_softc().

{
        common->bus_ops->read_cachesize(common, csz);
}
void ath_isr ( struct net80211_device dev)

Definition at line 366 of file ath9k_main.c.

References ah, ath_common::ani, ATH9K_HW_CAP_AUTOSLEEP, ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_getisr(), ath9k_hw_intrpend(), ath9k_hw_setrxabort(), ath9k_hw_updatetxtriglevel(), ATH9K_INT_FATAL, ATH9K_INT_RXORN, ATH9K_INT_TIM_TIMER, ATH9K_INT_TXURN, ATH9K_PM_AWAKE, ath9k_setpower(), ath_ani_calibrate(), ath_hw::caps, common, currticks(), ath9k_hw_capabilities::hw_caps, ath_softc::hw_pll_work, ath_softc::hw_pll_work_timer, ath_hw::imask, ath_softc::intr_tq, ath_softc::intrstatus, net80211_device::priv, ath_softc::ps_flags, ath_softc::ps_idle, PS_WAIT_FOR_BEACON, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, SCHED_INTR, status, TICKS_PER_SEC, ath_ani::timer, timestamp, ath_softc::tx_complete_work, and ath_softc::tx_complete_work_timer.

Referenced by ath9k_poll().

{
#define SCHED_INTR (                            \
                ATH9K_INT_FATAL |               \
                ATH9K_INT_BB_WATCHDOG |         \
                ATH9K_INT_RXORN |               \
                ATH9K_INT_RXEOL |               \
                ATH9K_INT_RX |                  \
                ATH9K_INT_RXLP |                \
                ATH9K_INT_RXHP |                \
                ATH9K_INT_TX |                  \
                ATH9K_INT_BMISS |               \
                ATH9K_INT_CST |                 \
                ATH9K_INT_TSFOOR |              \
                ATH9K_INT_GENTIMER)

        struct ath_softc *sc = dev->priv;
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        enum ath9k_int status;
        unsigned long timestamp = (currticks() * 1000 ) / TICKS_PER_SEC;
        int sched = 0;

        /*
         * The hardware is not ready/present, don't
         * touch anything. Note this can happen early
         * on if the IRQ is shared.
         */
        if (sc->sc_flags & SC_OP_INVALID)
                return;


        /* Check calibration */
        if(timestamp >= (unsigned int)common->ani.timer && common->ani.timer)
                ath_ani_calibrate(sc);

        /* Check tx_complete_work */
        if(timestamp >= (unsigned int)sc->tx_complete_work_timer && sc->tx_complete_work_timer)
                sc->tx_complete_work(sc);

        /* Check hw_pll_work */
        if(timestamp >= (unsigned int)sc->hw_pll_work_timer && sc->hw_pll_work_timer)
                sc->hw_pll_work(sc);

        /* shared irq, not for us */

        if (!ath9k_hw_intrpend(ah))
                return;

        /*
         * Figure out the reason(s) for the interrupt.  Note
         * that the hal returns a pseudo-ISR that may include
         * bits we haven't explicitly enabled so we mask the
         * value to insure we only process bits we requested.
         */
        ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
        status &= ah->imask;    /* discard unasked-for bits */

        /*
         * If there are no status bits set, then this interrupt was not
         * for me (should have been caught above).
         */
        if (!status)
                return;

        /* Cache the status */
        sc->intrstatus = status;

        if (status & SCHED_INTR)
                sched = 1;

        /*
         * If a FATAL or RXORN interrupt is received, we have to reset the
         * chip immediately.
         */
        if ((status & ATH9K_INT_FATAL) || (status & ATH9K_INT_RXORN))
                goto chip_reset;

        if (status & ATH9K_INT_TXURN)
                ath9k_hw_updatetxtriglevel(ah, 1);

        if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                if (status & ATH9K_INT_TIM_TIMER) {
                        if (sc->ps_idle)
                                goto chip_reset;
                        /* Clear RxAbort bit so that we can
                         * receive frames */
                        ath9k_setpower(sc, ATH9K_PM_AWAKE);
                        ath9k_hw_setrxabort(sc->sc_ah, 0);
                        sc->ps_flags |= PS_WAIT_FOR_BEACON;
                }

chip_reset:

        if (sched) {
                /* turn off every interrupt */
                ath9k_hw_disable_interrupts(ah);
                sc->intr_tq(sc);
        }

        return;

#undef SCHED_INTR
}
void ath9k_init_crypto ( struct ath_softc sc)

Definition at line 275 of file ath9k_init.c.

References AR_KEYTABLE_SIZE, AR_PCU_MIC_NEW_LOC_ENA, ath9k_hw_common(), ATH_CRYPT_CAP_MIC_COMBINED, ath_hw_keyreset(), common, ath_common::crypt_caps, ath_common::keymax, ath_hw::misc_mode, and ath_softc::sc_ah.

Referenced by ath9k_init_softc().

{
        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
        unsigned int i = 0;

        /* Get the hardware key cache size. */
        common->keymax = AR_KEYTABLE_SIZE;

        /*
         * Reset the key cache since some parts do not
         * reset the contents on initial power up.
         */
        for (i = 0; i < common->keymax; i++)
                ath_hw_keyreset(common, (u16) i);

        /*
         * Check whether the separate key cache entries
         * are required to handle both tx+rx MIC keys.
         * With split mic keys the number of stations is limited
         * to 27 otherwise 59.
         */
        if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
                common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
}
int ath9k_init_device ( u16  devid,
struct ath_softc sc,
u16  subsysid,
const struct ath_bus_ops bus_ops 
)

Definition at line 486 of file ath9k_init.c.

References ath9k_deinit_softc(), ath9k_init_softc(), ath9k_init_txpower_limits(), ath9k_ops, ath9k_set_hw_capab(), ath_hw_pll_work(), ATH_RSSI_DUMMY_MARKER, ath_rx_cleanup(), ath_rx_init(), ATH_RXBUF, ath_tx_cleanup(), ath_tx_init(), ATH_TXBUF, ath_softc::dev, error, ath_softc::hw_pll_work, ath_softc::hwinfo, ath_softc::last_rssi, and net80211_register().

Referenced by ath_pci_probe().

{
        struct net80211_device *dev = sc->dev;
        /*struct ath_common *common;
        struct ath_hw *ah;*/
        int error = 0;
        /*struct ath_regulatory *reg;*/

        /* Bring up device */
        error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
        if (error != 0)
                goto error_init;

        /*ah = sc->sc_ah;
        common = ath9k_hw_common(ah);*/
        ath9k_set_hw_capab(sc, dev);
        /* TODO Cottsay: reg */
        /* Initialize regulatory */
        /*error = ath_regd_init(&common->regulatory, sc->dev->wiphy,
                              ath9k_reg_notifier);
        if (error)
                goto error_regd;

        reg = &common->regulatory;*/

        /* Setup TX DMA */
        error = ath_tx_init(sc, ATH_TXBUF);
        if (error != 0)
                goto error_tx;

        /* Setup RX DMA */
        error = ath_rx_init(sc, ATH_RXBUF);
        if (error != 0)
                goto error_rx;

        ath9k_init_txpower_limits(sc);

        /* Register with mac80211 */
        error = net80211_register(dev, &ath9k_ops, sc->hwinfo);
        if (error)
                goto error_register;

        /* TODO Cottsay: reg */
        /* Handle world regulatory */
        /*if (!ath_is_world_regd(reg)) {
                error = regulatory_hint(hw->wiphy, reg->alpha2);
                if (error)
                        goto error_world;
        }*/

        sc->hw_pll_work = ath_hw_pll_work;
        sc->last_rssi = ATH_RSSI_DUMMY_MARKER;

        /* TODO Cottsay: rfkill */
        /*ath_start_rfkill_poll(sc);*/

        return 0;

//error_world:
//      net80211_unregister(dev);
error_register:
        ath_rx_cleanup(sc);
error_rx:
        ath_tx_cleanup(sc);
error_tx:
        ath9k_deinit_softc(sc);
error_init:
        return error;
}
void ath9k_deinit_device ( struct ath_softc sc)
void ath9k_set_hw_capab ( struct ath_softc sc,
struct net80211_device dev 
)

Referenced by ath9k_init_device().

int ath_set_channel ( struct ath_softc sc,
struct net80211_device dev,
struct ath9k_channel hchan 
)

Definition at line 116 of file ath9k_main.c.

References __unused, ah, ath_common::ani, ath9k_cmn_update_txpow(), ath9k_hw_check_alive(), ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_reset(), ath9k_hw_set_interrupts(), ath_drain_all_txq(), ath_start_ani(), ath_startrecv(), ath_stoprecv(), ath_softc::caldata, net80211_channel::center_freq, channel, ath9k_channel::channel, net80211_device::channel, net80211_device::channels, common, ath_softc::config, ath_hw::curchan, currticks(), ath_softc::curtxpow, DBG, DBG2, EIO, ath_softc::hw_busy_count, ath_softc::hw_pll_work_timer, ath_hw::imask, NULL, r, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, SC_OP_OFFCHANNEL, TICKS_PER_SEC, ath_ani::timer, ath_softc::tx_complete_work, ath_softc::tx_complete_work_timer, and ath_config::txpowlimit.

Referenced by ath9k_config().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath_common *common = ath9k_hw_common(ah);
        int fastcc __unused = 1, stopped __unused;
        struct net80211_channel *channel = dev->channels + dev->channel;
        struct ath9k_hw_cal_data *caldata = NULL;
        int r;

        if (sc->sc_flags & SC_OP_INVALID)
                return -EIO;

        sc->hw_busy_count = 0;

        common->ani.timer = 0;
        sc->tx_complete_work_timer = 0;
        sc->hw_pll_work_timer = 0;

        /*
         * This is only performed if the channel settings have
         * actually changed.
         *
         * To switch channels clear any pending DMA operations;
         * wait long enough for the RX fifo to drain, reset the
         * hardware at the new frequency, and then re-enable
         * the relevant bits of the h/w.
         */
        ath9k_hw_disable_interrupts(ah);
        stopped = ath_drain_all_txq(sc, 0);

        if (!ath_stoprecv(sc))
                stopped = 0;

        if (!ath9k_hw_check_alive(ah))
                stopped = 0;

        /* XXX: do not flush receive queue here. We don't want
         * to flush data frames already in queue because of
         * changing channel. */

        if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
                caldata = &sc->caldata;

        DBG2("ath9k: "
                "(%d MHz) -> (%d MHz)\n",
                sc->sc_ah->curchan->channel,
                channel->center_freq);

        r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
        if (r) {
                DBG("ath9k: "
                        "Unable to reset channel (%d MHz), reset status %d\n",
                        channel->center_freq, r);
                goto ps_restore;
        }

        if (ath_startrecv(sc) != 0) {
                DBG("ath9k: Unable to restart recv logic\n");
                r = -EIO;
                goto ps_restore;
        }

        ath9k_cmn_update_txpow(ah, sc->curtxpow,
                               sc->config.txpowlimit, &sc->curtxpow);
        ath9k_hw_set_interrupts(ah, ah->imask);

        if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
                sc->tx_complete_work(sc);
                sc->hw_pll_work_timer = (currticks() * 1000 ) / TICKS_PER_SEC + 500;
                ath_start_ani(common);
        }

 ps_restore:
        return r;
}
void ath_radio_enable ( struct ath_softc sc,
struct net80211_device dev 
)
void ath_radio_disable ( struct ath_softc sc,
struct net80211_device dev 
)

Definition at line 471 of file ath9k_main.c.

References ah, ath9k_cmn_get_curchannel(), ath9k_hw_cfg_gpio_input(), ath9k_hw_configpcipowersave(), ath9k_hw_disable_interrupts(), ath9k_hw_phy_disable(), ath9k_hw_reset(), ath9k_hw_set_gpio(), ath_drain_all_txq(), ath_flushrecv(), ath_stoprecv(), ath_hw::caldata, net80211_channel::center_freq, channel, net80211_device::channel, net80211_device::channels, ath_hw::curchan, DBG, ath_softc::hw_pll_work_timer, ath_hw::led_pin, ath_softc::ps_idle, r, and ath_softc::sc_ah.

Referenced by ath9k_stop().

{
        struct ath_hw *ah = sc->sc_ah;
        struct net80211_channel *channel = dev->channels + dev->channel;
        int r;

        sc->hw_pll_work_timer = 0;

        /*
         * Keep the LED on when the radio is disabled
         * during idle unassociated state.
         */
        if (!sc->ps_idle) {
                ath9k_hw_set_gpio(ah, ah->led_pin, 1);
                ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
        }

        /* Disable interrupts */
        ath9k_hw_disable_interrupts(ah);

        ath_drain_all_txq(sc, 0);       /* clear pending tx frames */

        ath_stoprecv(sc);               /* turn off frame recv */
        ath_flushrecv(sc);              /* flush recv queue */

        if (!ah->curchan)
                ah->curchan = ath9k_cmn_get_curchannel(dev, ah);

        r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, 0);
        if (r) {
                DBG("ath9k: "
                        "Unable to reset channel (%d MHz), reset status %d\n",
                        channel->center_freq, r);
        }

        ath9k_hw_phy_disable(ah);

        ath9k_hw_configpcipowersave(ah, 1, 1);
}
int ath9k_setpower ( struct ath_softc sc,
enum ath9k_power_mode  mode 
)

Definition at line 26 of file ath9k_main.c.

References ath9k_hw_setpower(), ret, and ath_softc::sc_ah.

Referenced by ath_isr().

{
        int ret;

        ret = ath9k_hw_setpower(sc->sc_ah, mode);

        return ret;
}
int ath9k_uses_beacons ( int  type)
u8 ath_txchainmask_reduction ( struct ath_softc sc,
u8  chainmask,
u32  rate 
)

Definition at line 409 of file ath9k_xmit.c.

References ah, CHANNEL_5GHZ, ath9k_channel::channelFlags, ath_hw::curchan, ath_softc::sc_ah, ath_softc::sc_flags, and SC_OP_ENABLE_APM.

Referenced by ath_buf_set_rate().

{
        struct ath_hw *ah = sc->sc_ah;
        struct ath9k_channel *curchan = ah->curchan;
        if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
                        (curchan->channelFlags & CHANNEL_5GHZ) &&
                        (chainmask == 0x7) && (rate < 0x90))
                return 0x3;
        else
                return chainmask;
}
void ath_start_rfkill_poll ( struct ath_softc sc)
void ath9k_rfkill_poll_state ( struct net80211_device dev)

Variable Documentation

Definition at line 909 of file ath9k_main.c.

Referenced by ath9k_init_device().

Definition at line 29 of file ath9k_init.c.

Referenced by ath_pci_remove().