iPXE
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Go to the source code of this file.
Macros | |
#define | _ATH5K_RESET |
Functions | |
FILE_LICENCE (MIT) | |
static int | fls (int x) |
static int | ath5k_hw_write_ofdm_timings (struct ath5k_hw *ah, struct net80211_channel *channel) |
ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 More... | |
static void | ath5k_hw_write_rate_duration (struct ath5k_hw *ah, unsigned int mode __unused) |
ath5k_hw_write_rate_duration - fill rate code to duration table More... | |
static int | ath5k_hw_nic_reset (struct ath5k_hw *ah, u32 val) |
int | ath5k_hw_wake (struct ath5k_hw *ah) |
int | ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, int initial __unused) |
static int | ath5k_hw_chan_has_spur_noise (struct ath5k_hw *ah, struct net80211_channel *channel) |
static void | ath5k_hw_tweak_initval_settings (struct ath5k_hw *ah, struct net80211_channel *channel) |
static void | ath5k_hw_commit_eeprom_settings (struct ath5k_hw *ah, struct net80211_channel *channel, u8 *ant, u8 ee_mode) |
int | ath5k_hw_reset (struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel) |
#define _ATH5K_RESET |
Definition at line 26 of file ath5k_reset.c.
FILE_LICENCE | ( | MIT | ) |
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Definition at line 40 of file ath5k_reset.c.
References r.
Referenced by ath5k_hw_write_ofdm_timings().
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ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
@ah: the &struct ath5k_hw @channel: the currently set channel upon reset
Write the delta slope coefficient (used on pilot tracking ?) for OFDM operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
Since delta slope is floating point we split it on its exponent and mantissa and provide these values on hw.
For more infos i think this patent is related http://www.freepatentsonline.com/7184495.html
Definition at line 85 of file ath5k_reset.c.
References ah, AR5K_AR5212, AR5K_PHY_TIMING_3, AR5K_PHY_TIMING_3_DSC_EXP, AR5K_PHY_TIMING_3_DSC_MAN, AR5K_REG_WRITE_BITS, ath5k_hw_htoclock(), channel, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EFAULT, EINVAL, and fls().
Referenced by ath5k_hw_reset().
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inlinestatic |
ath5k_hw_write_rate_duration - fill rate code to duration table
@ah: the &struct ath5k_hw @mode: one of enum ath5k_driver_mode
Write the rate code to duration table upon hw reset. This is a helper for ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on the hardware, based on current mode, for each rate. The rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have different rate code so we write their value twice (one for long preample and one for short).
Note: Band doesn't matter here, if we set the values for OFDM it works on both a and g modes. So all we have to do is set values for all g rates that include all OFDM and CCK rates. If we operate in turbo or xr/half/ quarter rate mode, we need to use another set of bitrates (that's why we need the mode parameter) but we don't handle these proprietary modes yet.
Definition at line 156 of file ath5k_reset.c.
References ah, AR5K_RATE_DUR, AR5K_SET_SHORT_PREAMBLE, ath5k_bitrate_to_hw_rix(), ath5k_hw_reg_write(), ath5k_softc::dev, ath5k_softc::hwinfo, NET80211_BAND_2GHZ, net80211_duration(), net80211_hw_info::nr_rates, net80211_hw_info::rates, and reg.
Referenced by ath5k_hw_reset().
Definition at line 198 of file ath5k_reset.c.
References ah, AR5K_AR5210, AR5K_CFG, AR5K_INIT_CFG, AR5K_RESET_CTL, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RXDP, ath5k_hw_reg_read(), ath5k_hw_reg_write(), udelay(), and val.
Referenced by ath5k_hw_nic_wakeup().
int ath5k_hw_wake | ( | struct ath5k_hw * | ah | ) |
Definition at line 240 of file ath5k_reset.c.
References ah, AR5K_PCICFG, AR5K_PCICFG_SPWR_DN, AR5K_SLEEP_CTL, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV, ath5k_hw_reg_read(), ath5k_hw_reg_write(), data, EIO, and udelay().
Referenced by ath5k_hw_nic_wakeup().
int ath5k_hw_nic_wakeup | ( | struct ath5k_hw * | ah, |
int | flags, | ||
int initial | __unused | ||
) |
Definition at line 282 of file ath5k_reset.c.
References ah, AR5K_AR5210, AR5K_AR5211, AR5K_PHY_MODE, AR5K_PHY_MODE_FREQ_2GHZ, AR5K_PHY_MODE_FREQ_5GHZ, AR5K_PHY_MODE_MOD_CCK, AR5K_PHY_MODE_MOD_DYN, AR5K_PHY_MODE_MOD_OFDM, AR5K_PHY_MODE_RAD_RF5111, AR5K_PHY_MODE_RAD_RF5112, AR5K_PHY_PLL, AR5K_PHY_PLL_40MHZ, AR5K_PHY_PLL_40MHZ_5413, AR5K_PHY_PLL_44MHZ, AR5K_PHY_PLL_RF5111, AR5K_PHY_PLL_RF5112, AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCI, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RF5112, AR5K_RF5413, ath5k_hw_nic_reset(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_wake(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EINVAL, EIO, flags, mdelay(), PCI_CAP_ID_EXP, pci_find_capability(), and udelay().
Referenced by ath5k_hw_attach(), and ath5k_hw_reset().
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Definition at line 414 of file ath5k_reset.c.
References ah, AR5K_RF5112, AR5K_RF5413, AR5K_SREV_AR2417, and channel.
Referenced by ath5k_hw_commit_eeprom_settings().
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Definition at line 435 of file ath5k_reset.c.
References ah, AR5K_AR5212, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_ECO_ENABLE, AR5K_PHY_ADC_CTL, AR5K_PHY_ADC_CTL_INBUFGAIN_OFF, AR5K_PHY_ADC_CTL_INBUFGAIN_ON, AR5K_PHY_ADC_CTL_PWD_ADC_OFF, AR5K_PHY_ADC_CTL_PWD_DAC_OFF, AR5K_PHY_BLUETOOTH, AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_WORLD, AR5K_PHY_DAG_CCK_CTL, AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR, AR5K_PHY_DAG_CCK_CTL_RSSI_THR, AR5K_PHY_FAST_ADC, AR5K_PHY_FRAME_CTL, AR5K_PHY_SCAL, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL_32MHZ_2417, AR5K_PHY_SCAL_32MHZ_HB63, AR5K_QCUDCU_CLKGT, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5112, AR5K_RF5413, AR5K_SEQ_MASK, AR5K_SREV_AR2417, AR5K_SREV_AR5211, AR5K_SREV_PHY_5212A, AR5K_SREV_PHY_5212B, AR5K_SREV_RAD_5112A, AR5K_TXCFG, AR5K_TXCFG_DCU_DBL_BUF_DIS, AR5K_USEC_1, AR5K_USEC_32, AR5K_USEC_5211, AR5K_USEC_RX_LATENCY_5210, AR5K_USEC_TX_LATENCY_5211, ath5k_eeprom_is_hb63(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), channel, CHANNEL_5GHZ, and data.
Referenced by ath5k_hw_reset().
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Definition at line 537 of file ath5k_reset.c.
References ah, AR5K_EEPROM_VERSION_4_1, AR5K_EEPROM_VERSION_5_0, AR5K_EEPROM_VERSION_5_1, AR5K_INIT_CYCRSSI_THR1, AR5K_PHY_ANT_CTL, AR5K_PHY_ANT_CTL_SWTABLE_IDLE, AR5K_PHY_ANT_CTL_TXRX_EN, AR5K_PHY_ANT_SWITCH_TABLE_0, AR5K_PHY_ANT_SWITCH_TABLE_1, AR5K_PHY_DESIRED_SIZE, AR5K_PHY_DESIRED_SIZE_ADC, AR5K_PHY_DESIRED_SIZE_PGA, AR5K_PHY_GAIN, AR5K_PHY_GAIN_2GHZ, AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX, AR5K_PHY_GAIN_TXRX_ATTEN, AR5K_PHY_HEAVY_CLIP_ENABLE, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE, AR5K_PHY_IQ_CORR_Q_I_COFF_S, AR5K_PHY_NF, AR5K_PHY_NF_SVAL, AR5K_PHY_NF_THRESH62, AR5K_PHY_NFTHRES, AR5K_PHY_OFDM_SELFCORR, AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, AR5K_PHY_RF_CTL3, AR5K_PHY_RF_CTL3_TXE2XLNA_ON, AR5K_PHY_RF_CTL4, AR5K_PHY_SETTLING, AR5K_PHY_SETTLING_SWITCH, AR5K_PHY_TX_PWR_ADJ, AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA, AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_SREV_PHY_5212A, ath5k_hw_chan_has_spur_noise(), ath5k_hw_reg_write(), channel, CHANNEL_G, CHANNEL_TURBO, ath5k_eeprom_info::ee_adc_desired_size, ath5k_eeprom_info::ee_adc_desired_size_turbo, ath5k_eeprom_info::ee_atn_tx_rx, ath5k_eeprom_info::ee_atn_tx_rx_turbo, ath5k_eeprom_info::ee_cck_ofdm_gain_delta, ath5k_eeprom_info::ee_cck_ofdm_power_delta, ath5k_eeprom_info::ee_false_detect, ath5k_eeprom_info::ee_i_cal, ath5k_eeprom_info::ee_margin_tx_rx, ath5k_eeprom_info::ee_margin_tx_rx_turbo, ath5k_eeprom_info::ee_noise_floor_thr, ath5k_eeprom_info::ee_pga_desired_size, ath5k_eeprom_info::ee_pga_desired_size_turbo, ath5k_eeprom_info::ee_q_cal, ath5k_eeprom_info::ee_scaled_cck_delta, ath5k_eeprom_info::ee_switch_settling, ath5k_eeprom_info::ee_switch_settling_turbo, ath5k_eeprom_info::ee_thr_62, ath5k_eeprom_info::ee_tx_end2xlna_enable, ath5k_eeprom_info::ee_tx_end2xpa_disable, and ath5k_eeprom_info::ee_tx_frm2xpa_enable.
Referenced by ath5k_hw_reset().
int ath5k_hw_reset | ( | struct ath5k_hw * | ah, |
struct net80211_channel * | channel, | ||
int | change_channel | ||
) |
Definition at line 690 of file ath5k_reset.c.
References ah, AR5K_ANT_FIXED_A, AR5K_ANT_FIXED_B, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_BEACON, AR5K_BEACON_ENABLE, AR5K_BEACON_RESET_TSF, AR5K_DEFAULT_ANTENNA, AR5K_DMASIZE_128B, AR5K_EEPROM_HDR_RFKILL, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_GPIOCR, AR5K_GPIODO, AR5K_HIGH_ID, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_LOW_ID, AR5K_MIC_QOS_CTL, AR5K_MIC_QOS_SEL, AR5K_MODE_11A, AR5K_MODE_11A_TURBO, AR5K_MODE_11B, AR5K_MODE_11G, AR5K_MODE_11G_TURBO, AR5K_MODE_XR, AR5K_PCICFG, AR5K_PCICFG_LEDSTATE, AR5K_PHY, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ADC_TEST, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, AR5K_PHY_IQ_RUN, AR5K_PHY_RX_DELAY, AR5K_PHY_RX_DELAY_M, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY_TST1, AR5K_PHY_TST1_TXHOLD, AR5K_PISR, AR5K_QOS_NOACK, AR5K_QOS_NOACK_2BIT_VALUES, AR5K_QOS_NOACK_BIT_OFFSET, AR5K_QOS_NOACK_BYTE_OFFSET, AR5K_QUEUE_DCU_SEQNUM, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5111, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS_S, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_SREV_AR2413, AR5K_SREV_AR5211, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, AR5K_STA_ID1_DEFAULT_ANTENNA, AR5K_STA_ID1_DESC_ANTENNA, AR5K_STA_ID1_RTS_DEF_ANTENNA, AR5K_STA_ID1_SELFGEN_DEF_ANT, AR5K_TUNE_BMISS_THRES, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_RSSI_THRES, AR5K_TXCFG, AR5K_TXCFG_B_MODE, AR5K_TXCFG_SDMAMR, ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_gpio(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_tx_queue(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_imr(), ath5k_hw_set_opmode(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_write_initvals(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), channel, CHANNEL_A, CHANNEL_B, CHANNEL_CCK, CHANNEL_G, CHANNEL_MODES, CHANNEL_OFDM, CHANNEL_T, CHANNEL_TG, CHANNEL_XR, DBG, delay, EINVAL, mdelay(), NULL, and udelay().
Referenced by ath5k_reset().