iPXE
Macros | Functions | Variables
ath9k_init.c File Reference
#include <ipxe/malloc.h>
#include <ipxe/pci_io.h>
#include <ipxe/pci.h>
#include <ipxe/ethernet.h>
#include "ath9k.h"

Go to the source code of this file.

Macros

#define CHAN2G(_freq, _idx)
 
#define CHAN5G(_freq, _idx)
 
#define SHPCHECK(__hw_rate, __flags)   ((__flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
 
#define RATE(_bitrate, _hw_rate, _flags)
 
#define DS2PHYS(_dd, _ds)   ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))
 
#define ATH_DESC_4KB_BOUND_CHECK(_daddr)   ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)
 

Functions

 FILE_LICENCE (BSD2)
 
static void ath9k_deinit_softc (struct ath_softc *sc)
 
static void ath9k_iowrite32 (void *hw_priv, u32 val, u32 reg_offset)
 
static unsigned int ath9k_ioread32 (void *hw_priv, u32 reg_offset)
 
static unsigned int ath9k_reg_rmw (void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 
int ath_descdma_setup (struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head, const char *name, int nbuf, int ndesc, int is_tx)
 
void ath9k_init_crypto (struct ath_softc *sc)
 
static int ath9k_init_queues (struct ath_softc *sc)
 
static int ath9k_init_channels_rates (struct ath_softc *sc)
 
static void ath9k_init_misc (struct ath_softc *sc)
 
static int ath9k_init_softc (u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
 
static void ath9k_init_band_txpower (struct ath_softc *sc, int band)
 
static void ath9k_init_txpower_limits (struct ath_softc *sc)
 
void ath9k_set_hw_capab (struct ath_softc *sc, struct net80211_device *dev __unused)
 
int ath9k_init_device (u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
 
void ath9k_deinit_device (struct ath_softc *sc)
 
void ath_descdma_cleanup (struct ath_softc *sc __unused, struct ath_descdma *dd, struct list_head *head)
 

Variables

int is_ath9k_unloaded
 
static const struct net80211_channel ath9k_2ghz_chantable []
 
static const struct net80211_channel ath9k_5ghz_chantable []
 
static struct ath9k_legacy_rate ath9k_legacy_rates []
 

Macro Definition Documentation

◆ CHAN2G

#define CHAN2G (   _freq,
  _idx 
)
Value:
{ \
.band = NET80211_BAND_2GHZ, \
.center_freq = (_freq), \
.hw_value = (_idx), \
.maxpower = 20, \
}
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45

Definition at line 32 of file ath9k_init.c.

◆ CHAN5G

#define CHAN5G (   _freq,
  _idx 
)
Value:
{ \
.band = NET80211_BAND_5GHZ, \
.center_freq = (_freq), \
.hw_value = (_idx), \
.maxpower = 20, \
}
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47

Definition at line 39 of file ath9k_init.c.

◆ SHPCHECK

#define SHPCHECK (   __hw_rate,
  __flags 
)    ((__flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)

Definition at line 103 of file ath9k_init.c.

◆ RATE

#define RATE (   _bitrate,
  _hw_rate,
  _flags 
)
Value:
{ \
.bitrate = (_bitrate), \
.flags = (_flags), \
.hw_value = (_hw_rate), \
.hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
}
#define SHPCHECK(__hw_rate, __flags)
Definition: ath9k_init.c:103
uint8_t flags
Flags.
Definition: ena.h:18

Definition at line 106 of file ath9k_init.c.

◆ DS2PHYS

#define DS2PHYS (   _dd,
  _ds 
)    ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))

◆ ATH_DESC_4KB_BOUND_CHECK

#define ATH_DESC_4KB_BOUND_CHECK (   _daddr)    ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( BSD2  )

◆ ath9k_deinit_softc()

static void ath9k_deinit_softc ( struct ath_softc sc)
static

Definition at line 561 of file ath9k_init.c.

562 {
563  int i = 0;
564 
565  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
566  if (ATH_TXQ_SETUP(sc, i))
567  ath_tx_cleanupq(sc, &sc->tx.txq[i]);
568 
569  ath9k_hw_deinit(sc->sc_ah);
570 
571  free(sc->hwinfo);
572  sc->hwinfo = NULL;
573  free(sc->sc_ah);
574  sc->sc_ah = NULL;
575 }
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
Definition: ath9k_xmit.c:255
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
struct ath_hw * sc_ah
Definition: ath9k.h:454
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
void ath9k_hw_deinit(struct ath_hw *ah)
Definition: ath9k_hw.c:850
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
struct ath_tx tx
Definition: ath9k.h:476
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ath9k_hw_deinit(), ATH9K_NUM_TX_QUEUES, ath_tx_cleanupq(), ATH_TXQ_SETUP, free, ath_softc::hwinfo, NULL, ath_softc::sc_ah, ath_softc::tx, and ath_tx::txq.

Referenced by ath9k_deinit_device(), and ath9k_init_device().

◆ ath9k_iowrite32()

static void ath9k_iowrite32 ( void *  hw_priv,
u32  val,
u32  reg_offset 
)
static

Definition at line 136 of file ath9k_init.c.

137 {
138  struct ath_hw *ah = (struct ath_hw *) hw_priv;
139  struct ath_common *common = ath9k_hw_common(ah);
140  struct ath_softc *sc = (struct ath_softc *) common->priv;
141 
142  writel(val, sc->mem + reg_offset);
143 }
Definition: hw.h:656
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
void __asmcall int val
Definition: setjmp.h:28
void * mem
Definition: ath9k.h:455
uint8_t ah
Definition: registers.h:85

References ah, ath9k_hw_common(), common, ath_softc::mem, val, and writel().

Referenced by ath9k_init_softc().

◆ ath9k_ioread32()

static unsigned int ath9k_ioread32 ( void *  hw_priv,
u32  reg_offset 
)
static

Definition at line 145 of file ath9k_init.c.

146 {
147  struct ath_hw *ah = (struct ath_hw *) hw_priv;
148  struct ath_common *common = ath9k_hw_common(ah);
149  struct ath_softc *sc = (struct ath_softc *) common->priv;
150  u32 val;
151 
152  val = readl(sc->mem + reg_offset);
153  return val;
154 }
Definition: hw.h:656
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
void __asmcall int val
Definition: setjmp.h:28
void * mem
Definition: ath9k.h:455
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_common(), common, ath_softc::mem, readl(), and val.

Referenced by ath9k_init_softc().

◆ ath9k_reg_rmw()

static unsigned int ath9k_reg_rmw ( void *  hw_priv,
u32  reg_offset,
u32  set,
u32  clr 
)
static

Definition at line 156 of file ath9k_init.c.

157 {
158  struct ath_hw *ah = (struct ath_hw *) hw_priv;
159  struct ath_common *common = ath9k_hw_common(ah);
160  struct ath_softc *sc = (struct ath_softc *) common->priv;
161  u32 val;
162 
163  val = readl(sc->mem + reg_offset);
164  val &= ~clr;
165  val |= set;
166  writel(val, sc->mem + reg_offset);
167 
168  return val;
169 }
Definition: hw.h:656
uint32_t readl(volatile uint32_t *io_addr)
Read 32-bit dword from memory-mapped device.
void writel(uint32_t data, volatile uint32_t *io_addr)
Write 32-bit dword to memory-mapped device.
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
static fd_set * set
Definition: posix_io.h:48
void __asmcall int val
Definition: setjmp.h:28
void * mem
Definition: ath9k.h:455
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_common(), common, ath_softc::mem, readl(), set, val, and writel().

Referenced by ath9k_init_softc().

◆ ath_descdma_setup()

int ath_descdma_setup ( struct ath_softc sc,
struct ath_descdma dd,
struct list_head head,
const char *  name,
int  nbuf,
int  ndesc,
int  is_tx 
)

Definition at line 180 of file ath9k_init.c.

183 {
184 #define DS2PHYS(_dd, _ds) \
185  ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))
186 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)
187  u8 *ds;
188  struct ath_buf *bf;
189  int i, bsize, error, desc_len;
190 
191  DBG2("ath9k: %s DMA: %d buffers %d desc/buf\n",
192  name, nbuf, ndesc);
193 
195 
196  if (is_tx)
197  desc_len = sc->sc_ah->caps.tx_desc_len;
198  else
199  desc_len = sizeof(struct ath_desc);
200 
201  /* ath_desc must be a multiple of DWORDs */
202  if ((desc_len % 4) != 0) {
203  DBG("ath9k: ath_desc not DWORD aligned\n");
204  error = -ENOMEM;
205  goto fail;
206  }
207 
208  dd->dd_desc_len = desc_len * nbuf * ndesc;
209 
210  /*
211  * Need additional DMA memory because we can't use
212  * descriptors that cross the 4K page boundary.
213  * However, iPXE only utilizes 16 buffers, which
214  * will never make up more than half of one page,
215  * so we will only ever skip 1 descriptor, if that.
216  */
218  u32 ndesc_skipped = 1;
219  u32 dma_len;
220 
221  dma_len = ndesc_skipped * desc_len;
222  dd->dd_desc_len += dma_len;
223  }
224 
225  /* allocate descriptors */
226  dd->dd_desc = malloc_dma(dd->dd_desc_len, 16);
227  if (dd->dd_desc == NULL) {
228  error = -ENOMEM;
229  goto fail;
230  }
231  dd->dd_desc_paddr = virt_to_bus(dd->dd_desc);
232  ds = (u8 *) dd->dd_desc;
233  DBG2("ath9k: %s DMA map: %p (%d) -> %llx (%d)\n",
234  name, ds, (u32) dd->dd_desc_len,
235  ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
236 
237  /* allocate buffers */
238  bsize = sizeof(struct ath_buf) * nbuf;
239  bf = zalloc(bsize);
240  if (bf == NULL) {
241  error = -ENOMEM;
242  goto fail2;
243  }
244  dd->dd_bufptr = bf;
245 
246  for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
247  bf->bf_desc = ds;
248  bf->bf_daddr = DS2PHYS(dd, ds);
249 
250  if (!(sc->sc_ah->caps.hw_caps &
252  /*
253  * Skip descriptor addresses which can cause 4KB
254  * boundary crossing (addr + length) with a 32 dword
255  * descriptor fetch.
256  */
257  while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
258  ds += (desc_len * ndesc);
259  bf->bf_desc = ds;
260  bf->bf_daddr = DS2PHYS(dd, ds);
261  }
262  }
263  list_add_tail(&bf->list, head);
264  }
265  return 0;
266 fail2:
267  free_dma(dd->dd_desc, dd->dd_desc_len);
268 fail:
269  memset(dd, 0, sizeof(*dd));
270  return error;
271 #undef ATH_DESC_4KB_BOUND_CHECK
272 #undef DS2PHYS
273 }
const char * name
Definition: ath9k_hw.c:1984
void * bf_desc
Definition: ath9k.h:225
struct arbelprm_completion_with_error error
Definition: arbel.h:12
#define DS2PHYS(_dd, _ds)
uint8_t head
Head number.
Definition: int13.h:34
Definition: mac.h:240
#define ito64(x)
Definition: ath9k.h:37
#define ATH_DESC_4KB_BOUND_CHECK(_daddr)
#define ENOMEM
Not enough space.
Definition: errno.h:534
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define list_add_tail(new, head)
Add a new entry to the tail of a list.
Definition: list.h:93
#define u32
Definition: vga.h:21
Definition: ath9k.h:219
u32 dd_desc_paddr
Definition: ath9k.h:107
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
uint32_t ds
Definition: librm.h:254
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
struct ath9k_hw_capabilities caps
Definition: hw.h:663
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
u32 dd_desc_len
Definition: ath9k.h:108
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
struct ath_buf * dd_bufptr
Definition: ath9k.h:109
void * dd_desc
Definition: ath9k.h:106
#define DBG2(...)
Definition: compiler.h:515
void * memset(void *dest, int character, size_t len) __nonnull

References ATH9K_HW_CAP_4KB_SPLITTRANS, ATH_DESC_4KB_BOUND_CHECK, ath_buf::bf_desc, ath_hw::caps, DBG, DBG2, ath_descdma::dd_bufptr, ath_descdma::dd_desc, ath_descdma::dd_desc_len, ath_descdma::dd_desc_paddr, ds, DS2PHYS, ENOMEM, error, free_dma(), head, ath9k_hw_capabilities::hw_caps, INIT_LIST_HEAD, ito64, list_add_tail, malloc_dma(), memset(), name, NULL, ath_softc::sc_ah, ath9k_hw_capabilities::tx_desc_len, u32, virt_to_bus(), and zalloc().

Referenced by ath_rx_init(), and ath_tx_init().

◆ ath9k_init_crypto()

void ath9k_init_crypto ( struct ath_softc sc)

Definition at line 275 of file ath9k_init.c.

276 {
277  struct ath_common *common = ath9k_hw_common(sc->sc_ah);
278  unsigned int i = 0;
279 
280  /* Get the hardware key cache size. */
281  common->keymax = AR_KEYTABLE_SIZE;
282 
283  /*
284  * Reset the key cache since some parts do not
285  * reset the contents on initial power up.
286  */
287  for (i = 0; i < common->keymax; i++)
288  ath_hw_keyreset(common, (u16) i);
289 
290  /*
291  * Check whether the separate key cache entries
292  * are required to handle both tx+rx MIC keys.
293  * With split mic keys the number of stations is limited
294  * to 27 otherwise 59.
295  */
297  common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
298 }
uint16_t u16
Definition: stdint.h:21
int ath_hw_keyreset(struct ath_common *common, u16 entry)
Definition: ath_key.c:41
#define AR_PCU_MIC_NEW_LOC_ENA
Definition: reg.h:1642
#define AR_KEYTABLE_SIZE
Definition: hw.h:148
u32 misc_mode
Definition: hw.h:749
struct ath_hw * sc_ah
Definition: ath9k.h:454
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11

References AR_KEYTABLE_SIZE, AR_PCU_MIC_NEW_LOC_ENA, ath9k_hw_common(), ATH_CRYPT_CAP_MIC_COMBINED, ath_hw_keyreset(), common, ath_hw::misc_mode, and ath_softc::sc_ah.

Referenced by ath9k_init_softc().

◆ ath9k_init_queues()

static int ath9k_init_queues ( struct ath_softc sc)
static

Definition at line 300 of file ath9k_init.c.

301 {
302  int i = 0;
303 
304  for (i = 0; i < WME_NUM_AC; i++) {
305  sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
306  sc->tx.txq_map[i]->mac80211_qnum = i;
307  }
308  return 0;
309 }
int mac80211_qnum
Definition: ath9k.h:181
struct ath_tx tx
Definition: ath9k.h:476
#define WME_NUM_AC
Definition: common.h:35
struct ath_txq * txq_map[WME_NUM_AC]
Definition: ath9k.h:287
struct ath_txq * ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
Definition: ath9k_xmit.c:106

References ATH9K_TX_QUEUE_DATA, ath_txq_setup(), ath_txq::mac80211_qnum, ath_softc::tx, ath_tx::txq_map, and WME_NUM_AC.

Referenced by ath9k_init_softc().

◆ ath9k_init_channels_rates()

static int ath9k_init_channels_rates ( struct ath_softc sc)
static

Definition at line 311 of file ath9k_init.c.

312 {
313  unsigned int i;
314 
316 
317  if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
319 
321 
322  for (i = 0; i < ARRAY_SIZE(ath9k_legacy_rates); i++)
325  }
326 
327  if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
329 
331 
332  for (i = 4; i < ARRAY_SIZE(ath9k_legacy_rates); i++)
335  }
336  return 0;
337 }
struct net80211_channel channels[NET80211_MAX_CHANNELS]
List of RF channels supported by the card.
Definition: net80211.h:498
static const struct net80211_channel ath9k_2ghz_chantable[]
Definition: ath9k_init.c:50
static const struct net80211_channel ath9k_5ghz_chantable[]
Definition: ath9k_init.c:71
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
u16 rates[NET80211_NR_BANDS][NET80211_MAX_RATES]
List of transmission rates supported by the card, indexed by band.
Definition: net80211.h:508
void * memcpy(void *dest, const void *src, size_t len) __nonnull
struct ath_hw * sc_ah
Definition: ath9k.h:454
int nr_rates[NET80211_NR_BANDS]
Number of supported rates, indexed by band.
Definition: net80211.h:511
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
static struct ath9k_legacy_rate ath9k_legacy_rates[]
Definition: ath9k_init.c:113
struct ath9k_hw_capabilities caps
Definition: hw.h:663
int nr_channels
Number of supported channels.
Definition: net80211.h:501
struct ath9k_legacy_rate rates[NET80211_MAX_RATES]
Definition: ath9k.h:478

References ARRAY_SIZE, ath9k_2ghz_chantable, ath9k_5ghz_chantable, ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_5GHZ, ath9k_legacy_rates, ath9k_legacy_rate::bitrate, ath_hw::caps, net80211_hw_info::channels, ath9k_hw_capabilities::hw_caps, ath_softc::hwinfo, memcpy(), NET80211_BAND_2GHZ, NET80211_BAND_5GHZ, net80211_hw_info::nr_channels, net80211_hw_info::nr_rates, ath_softc::rates, net80211_hw_info::rates, and ath_softc::sc_ah.

Referenced by ath9k_init_softc().

◆ ath9k_init_misc()

static void ath9k_init_misc ( struct ath_softc sc)
static

Definition at line 339 of file ath9k_init.c.

340 {
341  struct ath_common *common = ath9k_hw_common(sc->sc_ah);
342 
343  common->ani.timer = 0;
344 
346 
347  common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
348  common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
349 
352 
353  memcpy(common->bssidmask, eth_broadcast, ETH_ALEN);
354 }
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Definition: ath9k_hw.c:1866
uint8_t eth_broadcast[ETH_ALEN]
Ethernet broadcast MAC address.
Definition: ethernet.c:47
#define ATH_TXPOWER_MAX
Definition: ath9k.h:359
void * memcpy(void *dest, const void *src, size_t len) __nonnull
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct ath_config config
Definition: ath9k.h:474
u8 defant
Definition: ath9k.h:297
struct ath_rx rx
Definition: ath9k.h:475
static void ath9k_hw_set_diversity(struct ath_hw *ah, int value)
Definition: hw-ops.h:241
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
#define ETH_ALEN
Definition: if_ether.h:8
struct ib_cm_common common
Definition: ib_mad.h:11
struct ath9k_hw_capabilities caps
Definition: hw.h:663
u16 txpowlimit
Definition: ath9k.h:65

References ath9k_hw_common(), ath9k_hw_getdefantenna(), ath9k_hw_set_diversity(), ATH_TXPOWER_MAX, ath_hw::caps, common, ath_softc::config, ath_rx::defant, ETH_ALEN, eth_broadcast, memcpy(), ath_softc::rx, ath9k_hw_capabilities::rx_chainmask, ath_softc::sc_ah, ath9k_hw_capabilities::tx_chainmask, and ath_config::txpowlimit.

Referenced by ath9k_init_softc().

◆ ath9k_init_softc()

static int ath9k_init_softc ( u16  devid,
struct ath_softc sc,
u16  subsysid,
const struct ath_bus_ops bus_ops 
)
static

Definition at line 356 of file ath9k_init.c.

358 {
359  struct ath_hw *ah = NULL;
360  struct ath_common *common;
361  int ret = 0, i;
362  int csz = 0;
363 
364  ah = zalloc(sizeof(struct ath_hw));
365  if (!ah)
366  return -ENOMEM;
367 
368  ah->dev = sc->dev;
369  ah->hw_version.devid = devid;
370  ah->hw_version.subsysid = subsysid;
371  ah->reg_ops.read = ath9k_ioread32;
372  ah->reg_ops.write = ath9k_iowrite32;
373  ah->reg_ops.rmw = ath9k_reg_rmw;
374  sc->sc_ah = ah;
375 
376  sc->hwinfo = zalloc(sizeof(*sc->hwinfo));
377  if (!sc->hwinfo) {
378  DBG("ath9k: cannot allocate 802.11 hardware info structure\n");
379  return -ENOMEM;
380  }
381 
382  ah->ah_flags |= AH_USE_EEPROM;
383  sc->sc_ah->led_pin = -1;
384 
386  common->ops = &ah->reg_ops;
387  common->bus_ops = bus_ops;
388  common->ah = ah;
389  common->dev = sc->dev;
390  common->priv = sc;
391 
392  sc->intr_tq = ath9k_tasklet;
393 
394  /*
395  * Cache line size is used to size and align various
396  * structures used to communicate with the hardware.
397  */
398  ath_read_cachesize(common, &csz);
399  common->cachelsz = csz << 2; /* convert to bytes */
400 
401  /* Initializes the hardware for all supported chipsets */
402  ret = ath9k_hw_init(ah);
403  if (ret)
404  goto err_hw;
405 
406  memcpy(sc->hwinfo->hwaddr, common->macaddr, ETH_ALEN);
407 
408  ret = ath9k_init_queues(sc);
409  if (ret)
410  goto err_queues;
411 
412  ret = ath9k_init_channels_rates(sc);
413  if (ret)
414  goto err_btcoex;
415 
416  ath9k_init_crypto(sc);
417  ath9k_init_misc(sc);
418 
419  return 0;
420 
421 err_btcoex:
422  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
423  if (ATH_TXQ_SETUP(sc, i))
424  ath_tx_cleanupq(sc, &sc->tx.txq[i]);
425 err_queues:
427 err_hw:
428  free(sc->hwinfo);
429  sc->hwinfo = NULL;
430 
431  free(ah);
432  sc->sc_ah = NULL;
433 
434  return ret;
435 }
Definition: hw.h:656
void ath9k_init_crypto(struct ath_softc *sc)
Definition: ath9k_init.c:275
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
Definition: ath9k_xmit.c:255
void ath9k_tasklet(struct ath_softc *sc)
Definition: ath9k_main.c:339
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
Definition: ath9k_init.c:156
static void ath9k_init_misc(struct ath_softc *sc)
Definition: ath9k_init.c:339
struct net80211_device * dev
Definition: ath9k.h:445
#define ENOMEM
Not enough space.
Definition: errno.h:534
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static void ath_read_cachesize(struct ath_common *common, int *csz)
Definition: ath9k.h:495
#define AH_USE_EEPROM
Definition: hw.h:653
u8 hwaddr[ETH_ALEN]
Default hardware MAC address.
Definition: net80211.h:447
struct ath_hw * sc_ah
Definition: ath9k.h:454
const struct ath_bus_ops * bus_ops
Definition: ath.h:224
static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
Definition: ath9k_init.c:136
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
void ath9k_hw_deinit(struct ath_hw *ah)
Definition: ath9k_hw.c:850
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ath_tx tx
Definition: ath9k.h:476
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
#define ETH_ALEN
Definition: if_ether.h:8
struct ib_cm_common common
Definition: ib_mad.h:11
static int ath9k_init_channels_rates(struct ath_softc *sc)
Definition: ath9k_init.c:311
int ath9k_hw_init(struct ath_hw *ah)
Definition: ath9k_hw.c:569
int led_pin
Definition: hw.h:795
void(* intr_tq)(struct ath_softc *sc)
Definition: ath9k.h:453
uint8_t ah
Definition: registers.h:85
static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
Definition: ath9k_init.c:145
static int ath9k_init_queues(struct ath_softc *sc)
Definition: ath9k_init.c:300
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, AH_USE_EEPROM, ath9k_hw_common(), ath9k_hw_deinit(), ath9k_hw_init(), ath9k_init_channels_rates(), ath9k_init_crypto(), ath9k_init_misc(), ath9k_init_queues(), ath9k_ioread32(), ath9k_iowrite32(), ATH9K_NUM_TX_QUEUES, ath9k_reg_rmw(), ath9k_tasklet(), ath_read_cachesize(), ath_tx_cleanupq(), ATH_TXQ_SETUP, ath_common::bus_ops, common, DBG, ath_softc::dev, ENOMEM, ETH_ALEN, free, net80211_hw_info::hwaddr, ath_softc::hwinfo, ath_softc::intr_tq, ath_hw::led_pin, memcpy(), NULL, ath_softc::sc_ah, ath_softc::tx, ath_tx::txq, and zalloc().

Referenced by ath9k_init_device().

◆ ath9k_init_band_txpower()

static void ath9k_init_band_txpower ( struct ath_softc sc,
int  band 
)
static

Definition at line 437 of file ath9k_init.c.

438 {
439  struct net80211_channel *chan;
440  struct ath_hw *ah = sc->sc_ah;
442  int i;
443 
444  for (i = 0; i < sc->hwinfo->nr_channels; i++) {
445  chan = &sc->hwinfo->channels[i];
446  if(chan->band != band)
447  continue;
448  ah->curchan = &ah->channels[chan->hw_value];
450  chan->maxpower = reg->max_power_level / 2;
451  }
452 }
Definition: hw.h:656
struct net80211_channel channels[NET80211_MAX_CHANNELS]
List of RF channels supported by the card.
Definition: net80211.h:498
u16 hw_value
Hardware channel value.
Definition: net80211.h:414
u8 maxpower
Maximum allowable transmit power, in dBm.
Definition: net80211.h:425
struct ath_hw * sc_ah
Definition: ath9k.h:454
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
static unsigned int unsigned int reg
Definition: intel.h:245
u8 band
The band with which this channel is associated.
Definition: net80211.h:388
An 802.11 RF channel.
Definition: net80211.h:385
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, int test)
Definition: ath9k_hw.c:1937
int nr_channels
Number of supported channels.
Definition: net80211.h:501
uint8_t ah
Definition: registers.h:85
#define MAX_RATE_POWER
Definition: hw.h:144

References ah, ath9k_hw_regulatory(), ath9k_hw_set_txpowerlimit(), net80211_channel::band, net80211_hw_info::channels, net80211_channel::hw_value, ath_softc::hwinfo, MAX_RATE_POWER, net80211_channel::maxpower, net80211_hw_info::nr_channels, reg, and ath_softc::sc_ah.

Referenced by ath9k_init_txpower_limits().

◆ ath9k_init_txpower_limits()

static void ath9k_init_txpower_limits ( struct ath_softc sc)
static

Definition at line 454 of file ath9k_init.c.

455 {
456  struct ath_hw *ah = sc->sc_ah;
457  struct ath9k_channel *curchan = ah->curchan;
458 
459  if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
461  if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
463 
464  ah->curchan = curchan;
465 }
Definition: hw.h:656
#define NET80211_BAND_2GHZ
The 2.4 GHz ISM band, unlicensed in most countries.
Definition: net80211.h:45
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define NET80211_BAND_5GHZ
The band from 4.9 GHz to 5.7 GHz, which tends to be more restricted.
Definition: net80211.h:47
uint8_t ah
Definition: registers.h:85
static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
Definition: ath9k_init.c:437

References ah, ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_5GHZ, ath9k_init_band_txpower(), NET80211_BAND_2GHZ, NET80211_BAND_5GHZ, and ath_softc::sc_ah.

Referenced by ath9k_init_device().

◆ ath9k_set_hw_capab()

void ath9k_set_hw_capab ( struct ath_softc sc,
struct net80211_device *dev  __unused 
)

Definition at line 467 of file ath9k_init.c.

468 {
469  sc->hwinfo->flags = NET80211_HW_RX_HAS_FCS;
470  sc->hwinfo->signal_type = NET80211_SIGNAL_DB;
471  sc->hwinfo->signal_max = 40; /* 35dB should give perfect 54Mbps */
472  sc->hwinfo->channel_change_time = 5000;
473 
474  if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
475  {
478  }
479  if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
480  {
482  sc->hwinfo->modes |= NET80211_MODE_A;
483  }
484 }
int modes
A bitwise OR of the 802.11x modes supported by this device.
Definition: net80211.h:450
unsigned signal_max
Maximum signal in arbitrary cases.
Definition: net80211.h:495
enum net80211_hw_info::@547 flags
A set of flags indicating peculiarities of this device.
#define NET80211_BAND_BIT_5GHZ
Bitmask for the 5GHz band.
Definition: net80211.h:54
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
#define NET80211_MODE_B
802.11b: 1-11 Mbps operation using DSSS/CCK signaling on the 2.4GHz band
Definition: net80211.h:66
enum net80211_hw_info::@548 signal_type
Signal strength information that can be provided by the device.
struct ath9k_hw_capabilities caps
Definition: hw.h:663
#define NET80211_BAND_BIT_2GHZ
Bitmask for the 2GHz band.
Definition: net80211.h:52
int bands
A bitwise OR of the bands on which this device can communicate.
Definition: net80211.h:453
unsigned channel_change_time
Estimate of the time required to change channels, in microseconds.
Definition: net80211.h:518
#define NET80211_MODE_G
802.11g: 54 Mbps operation using ERP/OFDM signaling on the 2.4GHz band
Definition: net80211.h:69
#define NET80211_MODE_A
802.11a: 54 Mbps operation using OFDM signaling on the 5GHz band
Definition: net80211.h:63

References ATH9K_HW_CAP_2GHZ, ATH9K_HW_CAP_5GHZ, net80211_hw_info::bands, ath_hw::caps, net80211_hw_info::channel_change_time, net80211_hw_info::flags, ath9k_hw_capabilities::hw_caps, ath_softc::hwinfo, net80211_hw_info::modes, NET80211_BAND_BIT_2GHZ, NET80211_BAND_BIT_5GHZ, NET80211_MODE_A, NET80211_MODE_B, NET80211_MODE_G, ath_softc::sc_ah, net80211_hw_info::signal_max, and net80211_hw_info::signal_type.

Referenced by ath9k_init_device().

◆ ath9k_init_device()

int ath9k_init_device ( u16  devid,
struct ath_softc sc,
u16  subsysid,
const struct ath_bus_ops bus_ops 
)

Definition at line 486 of file ath9k_init.c.

488 {
489  struct net80211_device *dev = sc->dev;
490  /*struct ath_common *common;
491  struct ath_hw *ah;*/
492  int error = 0;
493  /*struct ath_regulatory *reg;*/
494 
495  /* Bring up device */
496  error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
497  if (error != 0)
498  goto error_init;
499 
500  /*ah = sc->sc_ah;
501  common = ath9k_hw_common(ah);*/
502  ath9k_set_hw_capab(sc, dev);
503  /* TODO Cottsay: reg */
504  /* Initialize regulatory */
505  /*error = ath_regd_init(&common->regulatory, sc->dev->wiphy,
506  ath9k_reg_notifier);
507  if (error)
508  goto error_regd;
509 
510  reg = &common->regulatory;*/
511 
512  /* Setup TX DMA */
513  error = ath_tx_init(sc, ATH_TXBUF);
514  if (error != 0)
515  goto error_tx;
516 
517  /* Setup RX DMA */
518  error = ath_rx_init(sc, ATH_RXBUF);
519  if (error != 0)
520  goto error_rx;
521 
523 
524  /* Register with mac80211 */
525  error = net80211_register(dev, &ath9k_ops, sc->hwinfo);
526  if (error)
527  goto error_register;
528 
529  /* TODO Cottsay: reg */
530  /* Handle world regulatory */
531  /*if (!ath_is_world_regd(reg)) {
532  error = regulatory_hint(hw->wiphy, reg->alpha2);
533  if (error)
534  goto error_world;
535  }*/
536 
539 
540  /* TODO Cottsay: rfkill */
541  /*ath_start_rfkill_poll(sc);*/
542 
543  return 0;
544 
545 //error_world:
546 // net80211_unregister(dev);
547 error_register:
548  ath_rx_cleanup(sc);
549 error_rx:
550  ath_tx_cleanup(sc);
551 error_tx:
552  ath9k_deinit_softc(sc);
553 error_init:
554  return error;
555 }
#define ATH_TXBUF
Definition: base.h:53
#define ATH_RXBUF
Definition: base.h:52
struct arbelprm_completion_with_error error
Definition: arbel.h:12
void ath9k_set_hw_capab(struct ath_softc *sc, struct net80211_device *dev __unused)
Definition: ath9k_init.c:467
void ath_tx_cleanup(struct ath_softc *sc)
Definition: ath9k_xmit.c:809
static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
Definition: ath9k_init.c:356
struct net80211_device * dev
Definition: ath9k.h:445
struct net80211_device_operations ath9k_ops
Definition: ath9k_main.c:909
void(* hw_pll_work)(struct ath_softc *sc)
Definition: ath9k.h:486
int last_rssi
Definition: ath9k.h:482
#define ATH_RSSI_DUMMY_MARKER
Definition: common.h:37
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
void ath_rx_cleanup(struct ath_softc *sc)
Definition: ath9k_recv.c:142
int ath_tx_init(struct ath_softc *sc, int nbufs)
Definition: ath9k_xmit.c:788
void ath_hw_pll_work(struct ath_softc *sc)
Definition: ath9k_main.c:325
static void ath9k_deinit_softc(struct ath_softc *sc)
Definition: ath9k_init.c:561
int ath_rx_init(struct ath_softc *sc, int nbufs)
Definition: ath9k_recv.c:97
int net80211_register(struct net80211_device *dev, struct net80211_device_operations *ops, struct net80211_hw_info *hw)
Register 802.11 device with network stack.
Definition: net80211.c:791
static void ath9k_init_txpower_limits(struct ath_softc *sc)
Definition: ath9k_init.c:454

References ath9k_deinit_softc(), ath9k_init_softc(), ath9k_init_txpower_limits(), ath9k_ops, ath9k_set_hw_capab(), ath_hw_pll_work(), ATH_RSSI_DUMMY_MARKER, ath_rx_cleanup(), ath_rx_init(), ATH_RXBUF, ath_tx_cleanup(), ath_tx_init(), ATH_TXBUF, ath_softc::dev, error, ath_softc::hw_pll_work, ath_softc::hwinfo, ath_softc::last_rssi, and net80211_register().

Referenced by ath_pci_probe().

◆ ath9k_deinit_device()

void ath9k_deinit_device ( struct ath_softc sc)

Definition at line 577 of file ath9k_init.c.

578 {
579  struct net80211_device *dev = sc->dev;
580 
581  net80211_unregister(dev);
582  ath_rx_cleanup(sc);
583  ath_tx_cleanup(sc);
584  ath9k_deinit_softc(sc);
585 }
void net80211_unregister(struct net80211_device *dev)
Unregister 802.11 device from network stack.
Definition: net80211.c:824
void ath_tx_cleanup(struct ath_softc *sc)
Definition: ath9k_xmit.c:809
struct net80211_device * dev
Definition: ath9k.h:445
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
void ath_rx_cleanup(struct ath_softc *sc)
Definition: ath9k_recv.c:142
static void ath9k_deinit_softc(struct ath_softc *sc)
Definition: ath9k_init.c:561

References ath9k_deinit_softc(), ath_rx_cleanup(), ath_tx_cleanup(), ath_softc::dev, and net80211_unregister().

Referenced by ath_pci_remove().

◆ ath_descdma_cleanup()

void ath_descdma_cleanup ( struct ath_softc *sc  __unused,
struct ath_descdma dd,
struct list_head head 
)

Definition at line 587 of file ath9k_init.c.

590 {
591  free_dma(dd->dd_desc, dd->dd_desc_len);
592 
594  free(dd->dd_bufptr);
595  memset(dd, 0, sizeof(*dd));
596 }
uint8_t head
Head number.
Definition: int13.h:34
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
u32 dd_desc_len
Definition: ath9k.h:108
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
struct ath_buf * dd_bufptr
Definition: ath9k.h:109
void * dd_desc
Definition: ath9k.h:106
void * memset(void *dest, int character, size_t len) __nonnull

References ath_descdma::dd_bufptr, ath_descdma::dd_desc, ath_descdma::dd_desc_len, free, free_dma(), head, INIT_LIST_HEAD, and memset().

Variable Documentation

◆ is_ath9k_unloaded

int is_ath9k_unloaded

Definition at line 29 of file ath9k_init.c.

Referenced by ath_pci_remove().

◆ ath9k_2ghz_chantable

const struct net80211_channel ath9k_2ghz_chantable[]
static
Initial value:
= {
CHAN2G(2412, 0),
CHAN2G(2417, 1),
CHAN2G(2422, 2),
CHAN2G(2427, 3),
CHAN2G(2432, 4),
CHAN2G(2437, 5),
CHAN2G(2442, 6),
CHAN2G(2447, 7),
CHAN2G(2452, 8),
CHAN2G(2457, 9),
CHAN2G(2462, 10),
CHAN2G(2467, 11),
CHAN2G(2472, 12),
CHAN2G(2484, 13),
}
#define CHAN2G(_freq, _idx)
Definition: ath9k_init.c:32

Definition at line 50 of file ath9k_init.c.

Referenced by ath9k_init_channels_rates().

◆ ath9k_5ghz_chantable

const struct net80211_channel ath9k_5ghz_chantable[]
static
Initial value:
= {
CHAN5G(5180, 14),
CHAN5G(5200, 15),
CHAN5G(5220, 16),
CHAN5G(5240, 17),
CHAN5G(5260, 18),
CHAN5G(5280, 19),
CHAN5G(5300, 20),
CHAN5G(5320, 21),
CHAN5G(5500, 22),
CHAN5G(5520, 23),
CHAN5G(5540, 24),
CHAN5G(5560, 25),
CHAN5G(5580, 26),
CHAN5G(5600, 27),
CHAN5G(5620, 28),
CHAN5G(5640, 29),
CHAN5G(5660, 30),
CHAN5G(5680, 31),
CHAN5G(5700, 32),
CHAN5G(5745, 33),
CHAN5G(5765, 34),
CHAN5G(5785, 35),
CHAN5G(5805, 36),
CHAN5G(5825, 37),
}
#define CHAN5G(_freq, _idx)
Definition: ath9k_init.c:39

Definition at line 71 of file ath9k_init.c.

Referenced by ath9k_init_channels_rates().

◆ ath9k_legacy_rates

struct ath9k_legacy_rate ath9k_legacy_rates[]
static
Initial value:
= {
RATE(10, 0x1b, 0),
RATE(60, 0x0b, 0),
RATE(90, 0x0f, 0),
RATE(120, 0x0a, 0),
RATE(180, 0x0e, 0),
RATE(240, 0x09, 0),
RATE(360, 0x0d, 0),
RATE(480, 0x08, 0),
RATE(540, 0x0c, 0),
}
#define RATE(_bitrate, _hw_rate, _flags)
Definition: ath9k_init.c:106

Definition at line 113 of file ath9k_init.c.

Referenced by ath9k_init_channels_rates().