iPXE
Data Structures | Macros | Enumerations | Functions | Variables
ath9k.h File Reference
#include "common.h"

Go to the source code of this file.

Data Structures

struct  ath_config
 
struct  ath_descdma
 
struct  ath_txq
 
struct  ath_atx_ac
 
struct  ath_frame_info
 
struct  ath_buf_state
 
struct  ath_buf
 
struct  ath_atx_tid
 
struct  ath_node
 
struct  ath_tx_control
 
struct  ath_tx
 @txq_map: Index is mac80211 queue number. More...
 
struct  ath_rx_edma
 
struct  ath_rx
 
struct  ath9k_legacy_rate
 
struct  survey_info
 
struct  ath9k_vif_iter_data
 
struct  ath_softc
 

Macros

#define ito64(x)
 
#define INCR(_l, _sz)
 
#define DECR(_l, _sz)
 
#define A_MAX(a, b)   ((a) > (b) ? (a) : (b))
 
#define TSF_TO_TU(_h, _l)   ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 
#define ATH_TXQ_SETUP(sc, i)   ((sc)->tx.txqsetup & (1<<i))
 
#define ATH_TXBUF_RESET(_bf)
 
#define ATH_RXBUF_RESET(_bf)
 
#define bf_isampdu(bf)   (bf->bf_state.bf_type & BUF_AMPDU)
 
#define bf_isaggr(bf)   (bf->bf_state.bf_type & BUF_AGGR)
 
#define bf_isxretried(bf)   (bf->bf_state.bf_type & BUF_XRETRY)
 
#define ATH_TXSTATUS_RING_SIZE   64
 
#define ATH_RXBUF   16
 
#define ATH_TXBUF   16
 
#define ATH_TXBUF_RESERVE   5
 
#define ATH_MAX_QDEPTH   (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 
#define ATH_TXMAXTRY   13
 
#define TID_TO_WME_AC(_tid)
 
#define ATH_AGGR_DELIM_SZ   4
 
#define ATH_AGGR_MINPLEN   256 /* in bytes, minimum packet length */
 
#define ATH_AGGR_ENCRYPTDELIM   10
 
#define ATH_AGGR_MIN_QDEPTH   2
 
#define ATH_AMPDU_SUBFRAME_DEFAULT   32
 
#define FCS_LEN   4
 
#define IEEE80211_SEQ_SEQ_SHIFT   4
 
#define IEEE80211_SEQ_MAX   4096
 
#define IEEE80211_WEP_IVLEN   3
 
#define IEEE80211_WEP_KIDLEN   1
 
#define IEEE80211_WEP_CRCLEN   4
 
#define IEEE80211_MAX_MPDU_LEN
 
#define ATH_BA_ISSET(_bm, _n)
 
#define ATH_BA_INDEX(_st, _seq)   (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 
#define ATH_AGGR_GET_NDELIM(_len)
 
#define BAW_WITHIN(_start, _bawsz, _seqno)   ((((_seqno) - (_start)) & 4095) < (_bawsz))
 
#define ATH_AN_2_TID(_an, _tidno)   (&(_an)->tid[(_tidno)])
 
#define ATH_TX_COMPLETE_POLL_INT   1000
 
#define ATH_TXFIFO_DEPTH   8
 
#define AGGR_CLEANUP   BIT(1)
 
#define AGGR_ADDBA_COMPLETE   BIT(2)
 
#define AGGR_ADDBA_PROGRESS   BIT(3)
 
#define ATH_TX_ERROR   0x01
 
#define ATH_TX_XRETRY   0x02
 
#define ATH_TX_BAR   0x04
 
#define ATH_STA_SHORT_CALINTERVAL   1000 /* 1 second */
 
#define ATH_AP_SHORT_CALINTERVAL   100 /* 100 ms */
 
#define ATH_ANI_POLLINTERVAL_OLD   100 /* 100 ms */
 
#define ATH_ANI_POLLINTERVAL_NEW   1000 /* 1000 ms */
 
#define ATH_LONG_CALINTERVAL_INT   1000 /* 1000 ms */
 
#define ATH_LONG_CALINTERVAL   30000 /* 30 seconds */
 
#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 
#define DEFAULT_CACHELINE   32
 
#define ATH_REGCLASSIDS_MAX   10
 
#define ATH_CABQ_READY_TIME   80 /* % of beacon interval */
 
#define ATH_MAX_SW_RETRIES   10
 
#define ATH_CHAN_MAX   255
 
#define ATH_TXPOWER_MAX   100 /* .5 dBm units */
 
#define ATH_RATE_DUMMY_MARKER   0
 
#define SC_OP_INVALID   BIT(0)
 
#define SC_OP_BEACONS   BIT(1)
 
#define SC_OP_RXAGGR   BIT(2)
 
#define SC_OP_TXAGGR   BIT(3)
 
#define SC_OP_OFFCHANNEL   BIT(4)
 
#define SC_OP_PREAMBLE_SHORT   BIT(5)
 
#define SC_OP_PROTECT_ENABLE   BIT(6)
 
#define SC_OP_RXFLUSH   BIT(7)
 
#define SC_OP_LED_ASSOCIATED   BIT(8)
 
#define SC_OP_LED_ON   BIT(9)
 
#define SC_OP_TSF_RESET   BIT(11)
 
#define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 
#define SC_OP_BT_SCAN   BIT(13)
 
#define SC_OP_ANI_RUN   BIT(14)
 
#define SC_OP_ENABLE_APM   BIT(15)
 
#define SC_OP_PRIM_STA_VIF   BIT(16)
 
#define PS_WAIT_FOR_BEACON   BIT(0)
 
#define PS_WAIT_FOR_CAB   BIT(1)
 
#define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 
#define PS_WAIT_FOR_TX_ACK   BIT(3)
 
#define PS_BEACON_SYNC   BIT(4)
 
#define PS_TSFOOR_SYNC   BIT(5)
 

Enumerations

enum  buffer_type { BUF_AMPDU = BIT(0), BUF_AGGR = BIT(1), BUF_XRETRY = BIT(2) }
 enum buffer_type - Buffer type flags More...
 
enum  ATH_AGGR_STATUS { ATH_AGGR_DONE, ATH_AGGR_BAW_CLOSED, ATH_AGGR_LIMITED }
 
enum  ath9k_rate_control_flags {
  IEEE80211_TX_RC_USE_RTS_CTS = BIT(0), IEEE80211_TX_RC_USE_CTS_PROTECT = BIT(1), IEEE80211_TX_RC_USE_SHORT_PREAMBLE = BIT(2), IEEE80211_TX_RC_MCS = BIT(3),
  IEEE80211_TX_RC_GREEN_FIELD = BIT(4), IEEE80211_TX_RC_40_MHZ_WIDTH = BIT(5), IEEE80211_TX_RC_DUP_DATA = BIT(6), IEEE80211_TX_RC_SHORT_GI = BIT(7)
}
 
enum  survey_info_flags {
  SURVEY_INFO_NOISE_DBM = 1<<0, SURVEY_INFO_IN_USE = 1<<1, SURVEY_INFO_CHANNEL_TIME = 1<<2, SURVEY_INFO_CHANNEL_TIME_BUSY = 1<<3,
  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY = 1<<4, SURVEY_INFO_CHANNEL_TIME_RX = 1<<5, SURVEY_INFO_CHANNEL_TIME_TX = 1<<6
}
 

Functions

 FILE_LICENCE (BSD2)
 
int ath_descdma_setup (struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head, const char *name, int nbuf, int ndesc, int is_tx)
 
void ath_descdma_cleanup (struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head)
 
int ath_startrecv (struct ath_softc *sc)
 
int ath_stoprecv (struct ath_softc *sc)
 
void ath_flushrecv (struct ath_softc *sc)
 
u32 ath_calcrxfilter (struct ath_softc *sc)
 
int ath_rx_init (struct ath_softc *sc, int nbufs)
 
void ath_rx_cleanup (struct ath_softc *sc)
 
int ath_rx_tasklet (struct ath_softc *sc, int flush, int hp)
 
struct ath_txqath_txq_setup (struct ath_softc *sc, int qtype, int subtype)
 
void ath_tx_cleanupq (struct ath_softc *sc, struct ath_txq *txq)
 
int ath_drain_all_txq (struct ath_softc *sc, int retry_tx)
 
void ath_draintxq (struct ath_softc *sc, struct ath_txq *txq, int retry_tx)
 
void ath_txq_schedule (struct ath_softc *sc, struct ath_txq *txq)
 
int ath_tx_init (struct ath_softc *sc, int nbufs)
 
void ath_tx_cleanup (struct ath_softc *sc)
 
int ath_txq_update (struct ath_softc *sc, int qnum, struct ath9k_tx_queue_info *q)
 
int ath_tx_start (struct net80211_device *dev, struct io_buffer *iob, struct ath_tx_control *txctl)
 
void ath_tx_tasklet (struct ath_softc *sc)
 
void ath_hw_pll_work (struct ath_softc *sc)
 
void ath_ani_calibrate (struct ath_softc *sc)
 
void ath9k_tasklet (struct ath_softc *sc)
 
int ath_reset (struct ath_softc *sc, int retry_tx)
 
static void ath_read_cachesize (struct ath_common *common, int *csz)
 
void ath_isr (struct net80211_device *dev)
 
void ath9k_init_crypto (struct ath_softc *sc)
 
int ath9k_init_device (u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
 
void ath9k_deinit_device (struct ath_softc *sc)
 
void ath9k_set_hw_capab (struct ath_softc *sc, struct net80211_device *dev)
 
int ath_set_channel (struct ath_softc *sc, struct net80211_device *dev, struct ath9k_channel *hchan)
 
void ath_radio_enable (struct ath_softc *sc, struct net80211_device *dev)
 
void ath_radio_disable (struct ath_softc *sc, struct net80211_device *dev)
 
int ath9k_setpower (struct ath_softc *sc, enum ath9k_power_mode mode)
 
int ath9k_uses_beacons (int type)
 
u8 ath_txchainmask_reduction (struct ath_softc *sc, u8 chainmask, u32 rate)
 
void ath_start_rfkill_poll (struct ath_softc *sc)
 
void ath9k_rfkill_poll_state (struct net80211_device *dev)
 

Variables

struct ath_config __attribute__
 
struct net80211_device_operations ath9k_ops
 
int ath9k_modparam_nohwcrypt
 
int is_ath9k_unloaded
 

Macro Definition Documentation

◆ ito64

#define ito64 (   x)
Value:
(sizeof(x) == 1) ? \
(((unsigned long long int)(x)) & (0xff)) : \
(sizeof(x) == 2) ? \
(((unsigned long long int)(x)) & 0xffff) : \
((sizeof(x) == 4) ? \
(((unsigned long long int)(x)) & 0xffffffff) : \
(unsigned long long int)(x))

Definition at line 37 of file ath9k.h.

◆ INCR

#define INCR (   _l,
  _sz 
)
Value:
do { \
(_l)++; \
(_l) &= ((_sz) - 1); \
} while (0)

Definition at line 46 of file ath9k.h.

◆ DECR

#define DECR (   _l,
  _sz 
)
Value:
do { \
(_l)--; \
(_l) &= ((_sz) - 1); \
} while (0)

Definition at line 52 of file ath9k.h.

◆ A_MAX

#define A_MAX (   a,
 
)    ((a) > (b) ? (a) : (b))

Definition at line 57 of file ath9k.h.

◆ TSF_TO_TU

#define TSF_TO_TU (   _h,
  _l 
)    ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))

Definition at line 59 of file ath9k.h.

◆ ATH_TXQ_SETUP

#define ATH_TXQ_SETUP (   sc,
 
)    ((sc)->tx.txqsetup & (1<<i))

Definition at line 62 of file ath9k.h.

◆ ATH_TXBUF_RESET

#define ATH_TXBUF_RESET (   _bf)
Value:
do { \
(_bf)->bf_stale = 0; \
(_bf)->bf_lastbf = NULL; \
(_bf)->bf_next = NULL; \
memset(&((_bf)->bf_state), 0, \
sizeof(struct ath_buf_state)); \
} while (0)
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

Definition at line 73 of file ath9k.h.

◆ ATH_RXBUF_RESET

#define ATH_RXBUF_RESET (   _bf)
Value:
do { \
(_bf)->bf_stale = 0; \
} while (0)

Definition at line 81 of file ath9k.h.

◆ bf_isampdu

#define bf_isampdu (   bf)    (bf->bf_state.bf_type & BUF_AMPDU)

Definition at line 99 of file ath9k.h.

◆ bf_isaggr

#define bf_isaggr (   bf)    (bf->bf_state.bf_type & BUF_AGGR)

Definition at line 100 of file ath9k.h.

◆ bf_isxretried

#define bf_isxretried (   bf)    (bf->bf_state.bf_type & BUF_XRETRY)

Definition at line 101 of file ath9k.h.

◆ ATH_TXSTATUS_RING_SIZE

#define ATH_TXSTATUS_RING_SIZE   64

Definition at line 103 of file ath9k.h.

◆ ATH_RXBUF

#define ATH_RXBUF   16

Definition at line 122 of file ath9k.h.

◆ ATH_TXBUF

#define ATH_TXBUF   16

Definition at line 123 of file ath9k.h.

◆ ATH_TXBUF_RESERVE

#define ATH_TXBUF_RESERVE   5

Definition at line 124 of file ath9k.h.

◆ ATH_MAX_QDEPTH

#define ATH_MAX_QDEPTH   (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)

Definition at line 125 of file ath9k.h.

◆ ATH_TXMAXTRY

#define ATH_TXMAXTRY   13

Definition at line 126 of file ath9k.h.

◆ TID_TO_WME_AC

#define TID_TO_WME_AC (   _tid)
Value:
((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
WME_AC_VO)
#define WME_AC_BE
Definition: common.h:34

Definition at line 128 of file ath9k.h.

◆ ATH_AGGR_DELIM_SZ

#define ATH_AGGR_DELIM_SZ   4

Definition at line 134 of file ath9k.h.

◆ ATH_AGGR_MINPLEN

#define ATH_AGGR_MINPLEN   256 /* in bytes, minimum packet length */

Definition at line 135 of file ath9k.h.

◆ ATH_AGGR_ENCRYPTDELIM

#define ATH_AGGR_ENCRYPTDELIM   10

Definition at line 137 of file ath9k.h.

◆ ATH_AGGR_MIN_QDEPTH

#define ATH_AGGR_MIN_QDEPTH   2

Definition at line 139 of file ath9k.h.

◆ ATH_AMPDU_SUBFRAME_DEFAULT

#define ATH_AMPDU_SUBFRAME_DEFAULT   32

Definition at line 140 of file ath9k.h.

◆ FCS_LEN

#define FCS_LEN   4

Definition at line 142 of file ath9k.h.

◆ IEEE80211_SEQ_SEQ_SHIFT

#define IEEE80211_SEQ_SEQ_SHIFT   4

Definition at line 143 of file ath9k.h.

◆ IEEE80211_SEQ_MAX

#define IEEE80211_SEQ_MAX   4096

Definition at line 144 of file ath9k.h.

◆ IEEE80211_WEP_IVLEN

#define IEEE80211_WEP_IVLEN   3

Definition at line 145 of file ath9k.h.

◆ IEEE80211_WEP_KIDLEN

#define IEEE80211_WEP_KIDLEN   1

Definition at line 146 of file ath9k.h.

◆ IEEE80211_WEP_CRCLEN

#define IEEE80211_WEP_CRCLEN   4

Definition at line 147 of file ath9k.h.

◆ IEEE80211_MAX_MPDU_LEN

#define IEEE80211_MAX_MPDU_LEN
Value:
(3840 + FCS_LEN + \
IEEE80211_WEP_KIDLEN + \
IEEE80211_WEP_CRCLEN))
#define FCS_LEN
Definition: ath9k.h:142
#define IEEE80211_WEP_IVLEN
Definition: ath9k.h:145

Definition at line 148 of file ath9k.h.

◆ ATH_BA_ISSET

#define ATH_BA_ISSET (   _bm,
  _n 
)
Value:
(((_n) < (WME_BA_BMP_SIZE)) && \
((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
#define WME_BA_BMP_SIZE
Definition: common.h:30

Definition at line 155 of file ath9k.h.

◆ ATH_BA_INDEX

#define ATH_BA_INDEX (   _st,
  _seq 
)    (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))

Definition at line 159 of file ath9k.h.

◆ ATH_AGGR_GET_NDELIM

#define ATH_AGGR_GET_NDELIM (   _len)
Value:
(((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
#define ATH_AGGR_MINPLEN
Definition: ath9k.h:135
#define ATH_AGGR_DELIM_SZ
Definition: ath9k.h:134

Definition at line 162 of file ath9k.h.

◆ BAW_WITHIN

#define BAW_WITHIN (   _start,
  _bawsz,
  _seqno 
)    ((((_seqno) - (_start)) & 4095) < (_bawsz))

Definition at line 166 of file ath9k.h.

◆ ATH_AN_2_TID

#define ATH_AN_2_TID (   _an,
  _tidno 
)    (&(_an)->tid[(_tidno)])

Definition at line 169 of file ath9k.h.

◆ ATH_TX_COMPLETE_POLL_INT

#define ATH_TX_COMPLETE_POLL_INT   1000

Definition at line 171 of file ath9k.h.

◆ ATH_TXFIFO_DEPTH

#define ATH_TXFIFO_DEPTH   8

Definition at line 179 of file ath9k.h.

◆ AGGR_CLEANUP

#define AGGR_CLEANUP   BIT(1)

Definition at line 261 of file ath9k.h.

◆ AGGR_ADDBA_COMPLETE

#define AGGR_ADDBA_COMPLETE   BIT(2)

Definition at line 262 of file ath9k.h.

◆ AGGR_ADDBA_PROGRESS

#define AGGR_ADDBA_PROGRESS   BIT(3)

Definition at line 263 of file ath9k.h.

◆ ATH_TX_ERROR

#define ATH_TX_ERROR   0x01

Definition at line 272 of file ath9k.h.

◆ ATH_TX_XRETRY

#define ATH_TX_XRETRY   0x02

Definition at line 273 of file ath9k.h.

◆ ATH_TX_BAR

#define ATH_TX_BAR   0x04

Definition at line 274 of file ath9k.h.

◆ ATH_STA_SHORT_CALINTERVAL

#define ATH_STA_SHORT_CALINTERVAL   1000 /* 1 second */

Definition at line 334 of file ath9k.h.

◆ ATH_AP_SHORT_CALINTERVAL

#define ATH_AP_SHORT_CALINTERVAL   100 /* 100 ms */

Definition at line 335 of file ath9k.h.

◆ ATH_ANI_POLLINTERVAL_OLD

#define ATH_ANI_POLLINTERVAL_OLD   100 /* 100 ms */

Definition at line 336 of file ath9k.h.

◆ ATH_ANI_POLLINTERVAL_NEW

#define ATH_ANI_POLLINTERVAL_NEW   1000 /* 1000 ms */

Definition at line 337 of file ath9k.h.

◆ ATH_LONG_CALINTERVAL_INT

#define ATH_LONG_CALINTERVAL_INT   1000 /* 1000 ms */

Definition at line 338 of file ath9k.h.

◆ ATH_LONG_CALINTERVAL

#define ATH_LONG_CALINTERVAL   30000 /* 30 seconds */

Definition at line 339 of file ath9k.h.

◆ ATH_RESTART_CALINTERVAL

#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */

Definition at line 340 of file ath9k.h.

◆ DEFAULT_CACHELINE

#define DEFAULT_CACHELINE   32

Definition at line 353 of file ath9k.h.

◆ ATH_REGCLASSIDS_MAX

#define ATH_REGCLASSIDS_MAX   10

Definition at line 354 of file ath9k.h.

◆ ATH_CABQ_READY_TIME

#define ATH_CABQ_READY_TIME   80 /* % of beacon interval */

Definition at line 355 of file ath9k.h.

◆ ATH_MAX_SW_RETRIES

#define ATH_MAX_SW_RETRIES   10

Definition at line 356 of file ath9k.h.

◆ ATH_CHAN_MAX

#define ATH_CHAN_MAX   255

Definition at line 357 of file ath9k.h.

◆ ATH_TXPOWER_MAX

#define ATH_TXPOWER_MAX   100 /* .5 dBm units */

Definition at line 359 of file ath9k.h.

◆ ATH_RATE_DUMMY_MARKER

#define ATH_RATE_DUMMY_MARKER   0

Definition at line 360 of file ath9k.h.

◆ SC_OP_INVALID

#define SC_OP_INVALID   BIT(0)

Definition at line 362 of file ath9k.h.

◆ SC_OP_BEACONS

#define SC_OP_BEACONS   BIT(1)

Definition at line 363 of file ath9k.h.

◆ SC_OP_RXAGGR

#define SC_OP_RXAGGR   BIT(2)

Definition at line 364 of file ath9k.h.

◆ SC_OP_TXAGGR

#define SC_OP_TXAGGR   BIT(3)

Definition at line 365 of file ath9k.h.

◆ SC_OP_OFFCHANNEL

#define SC_OP_OFFCHANNEL   BIT(4)

Definition at line 366 of file ath9k.h.

◆ SC_OP_PREAMBLE_SHORT

#define SC_OP_PREAMBLE_SHORT   BIT(5)

Definition at line 367 of file ath9k.h.

◆ SC_OP_PROTECT_ENABLE

#define SC_OP_PROTECT_ENABLE   BIT(6)

Definition at line 368 of file ath9k.h.

◆ SC_OP_RXFLUSH

#define SC_OP_RXFLUSH   BIT(7)

Definition at line 369 of file ath9k.h.

◆ SC_OP_LED_ASSOCIATED

#define SC_OP_LED_ASSOCIATED   BIT(8)

Definition at line 370 of file ath9k.h.

◆ SC_OP_LED_ON

#define SC_OP_LED_ON   BIT(9)

Definition at line 371 of file ath9k.h.

◆ SC_OP_TSF_RESET

#define SC_OP_TSF_RESET   BIT(11)

Definition at line 372 of file ath9k.h.

◆ SC_OP_BT_PRIORITY_DETECTED

#define SC_OP_BT_PRIORITY_DETECTED   BIT(12)

Definition at line 373 of file ath9k.h.

◆ SC_OP_BT_SCAN

#define SC_OP_BT_SCAN   BIT(13)

Definition at line 374 of file ath9k.h.

◆ SC_OP_ANI_RUN

#define SC_OP_ANI_RUN   BIT(14)

Definition at line 375 of file ath9k.h.

◆ SC_OP_ENABLE_APM

#define SC_OP_ENABLE_APM   BIT(15)

Definition at line 376 of file ath9k.h.

◆ SC_OP_PRIM_STA_VIF

#define SC_OP_PRIM_STA_VIF   BIT(16)

Definition at line 377 of file ath9k.h.

◆ PS_WAIT_FOR_BEACON

#define PS_WAIT_FOR_BEACON   BIT(0)

Definition at line 380 of file ath9k.h.

◆ PS_WAIT_FOR_CAB

#define PS_WAIT_FOR_CAB   BIT(1)

Definition at line 381 of file ath9k.h.

◆ PS_WAIT_FOR_PSPOLL_DATA

#define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)

Definition at line 382 of file ath9k.h.

◆ PS_WAIT_FOR_TX_ACK

#define PS_WAIT_FOR_TX_ACK   BIT(3)

Definition at line 383 of file ath9k.h.

◆ PS_BEACON_SYNC

#define PS_BEACON_SYNC   BIT(4)

Definition at line 384 of file ath9k.h.

◆ PS_TSFOOR_SYNC

#define PS_TSFOOR_SYNC   BIT(5)

Definition at line 385 of file ath9k.h.

Enumeration Type Documentation

◆ buffer_type

enum buffer_type - Buffer type flags

@BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) @BUF_AGGR: Indicates whether the buffer can be aggregated (used in aggregation scheduling) @BUF_XRETRY: To denote excessive retries of the buffer

Enumerator
BUF_AMPDU 
BUF_AGGR 
BUF_XRETRY 

Definition at line 93 of file ath9k.h.

93  {
94  BUF_AMPDU = BIT(0),
95  BUF_AGGR = BIT(1),
96  BUF_XRETRY = BIT(2),
97 };
Definition: ath9k.h:95
#define BIT(nr)
Definition: ath.h:32

◆ ATH_AGGR_STATUS

Enumerator
ATH_AGGR_DONE 
ATH_AGGR_BAW_CLOSED 
ATH_AGGR_LIMITED 

Definition at line 173 of file ath9k.h.

◆ ath9k_rate_control_flags

Enumerator
IEEE80211_TX_RC_USE_RTS_CTS 
IEEE80211_TX_RC_USE_CTS_PROTECT 
IEEE80211_TX_RC_USE_SHORT_PREAMBLE 
IEEE80211_TX_RC_MCS 
IEEE80211_TX_RC_GREEN_FIELD 
IEEE80211_TX_RC_40_MHZ_WIDTH 
IEEE80211_TX_RC_DUP_DATA 
IEEE80211_TX_RC_SHORT_GI 

Definition at line 396 of file ath9k.h.

◆ survey_info_flags

Enumerator
SURVEY_INFO_NOISE_DBM 
SURVEY_INFO_IN_USE 
SURVEY_INFO_CHANNEL_TIME 
SURVEY_INFO_CHANNEL_TIME_BUSY 
SURVEY_INFO_CHANNEL_TIME_EXT_BUSY 
SURVEY_INFO_CHANNEL_TIME_RX 
SURVEY_INFO_CHANNEL_TIME_TX 

Definition at line 420 of file ath9k.h.

Function Documentation

◆ FILE_LICENCE()

FILE_LICENCE ( BSD2  )

◆ ath_descdma_setup()

int ath_descdma_setup ( struct ath_softc sc,
struct ath_descdma dd,
struct list_head head,
const char *  name,
int  nbuf,
int  ndesc,
int  is_tx 
)

Definition at line 180 of file ath9k_init.c.

183 {
184 #define DS2PHYS(_dd, _ds) \
185  ((_dd)->dd_desc_paddr + ((char *)(_ds) - (char *)(_dd)->dd_desc))
186 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF9F) ? 1 : 0)
187  u8 *ds;
188  struct ath_buf *bf;
189  int i, bsize, error, desc_len;
190 
191  DBG2("ath9k: %s DMA: %d buffers %d desc/buf\n",
192  name, nbuf, ndesc);
193 
195 
196  if (is_tx)
197  desc_len = sc->sc_ah->caps.tx_desc_len;
198  else
199  desc_len = sizeof(struct ath_desc);
200 
201  /* ath_desc must be a multiple of DWORDs */
202  if ((desc_len % 4) != 0) {
203  DBG("ath9k: ath_desc not DWORD aligned\n");
204  error = -ENOMEM;
205  goto fail;
206  }
207 
208  dd->dd_desc_len = desc_len * nbuf * ndesc;
209 
210  /*
211  * Need additional DMA memory because we can't use
212  * descriptors that cross the 4K page boundary.
213  * However, iPXE only utilizes 16 buffers, which
214  * will never make up more than half of one page,
215  * so we will only ever skip 1 descriptor, if that.
216  */
218  u32 ndesc_skipped = 1;
219  u32 dma_len;
220 
221  dma_len = ndesc_skipped * desc_len;
222  dd->dd_desc_len += dma_len;
223  }
224 
225  /* allocate descriptors */
226  dd->dd_desc = malloc_dma(dd->dd_desc_len, 16);
227  if (dd->dd_desc == NULL) {
228  error = -ENOMEM;
229  goto fail;
230  }
231  dd->dd_desc_paddr = virt_to_bus(dd->dd_desc);
232  ds = (u8 *) dd->dd_desc;
233  DBG2("ath9k: %s DMA map: %p (%d) -> %llx (%d)\n",
234  name, ds, (u32) dd->dd_desc_len,
235  ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
236 
237  /* allocate buffers */
238  bsize = sizeof(struct ath_buf) * nbuf;
239  bf = zalloc(bsize);
240  if (bf == NULL) {
241  error = -ENOMEM;
242  goto fail2;
243  }
244  dd->dd_bufptr = bf;
245 
246  for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
247  bf->bf_desc = ds;
248  bf->bf_daddr = DS2PHYS(dd, ds);
249 
250  if (!(sc->sc_ah->caps.hw_caps &
252  /*
253  * Skip descriptor addresses which can cause 4KB
254  * boundary crossing (addr + length) with a 32 dword
255  * descriptor fetch.
256  */
257  while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
258  ds += (desc_len * ndesc);
259  bf->bf_desc = ds;
260  bf->bf_daddr = DS2PHYS(dd, ds);
261  }
262  }
263  list_add_tail(&bf->list, head);
264  }
265  return 0;
266 fail2:
267  free_dma(dd->dd_desc, dd->dd_desc_len);
268 fail:
269  memset(dd, 0, sizeof(*dd));
270  return error;
271 #undef ATH_DESC_4KB_BOUND_CHECK
272 #undef DS2PHYS
273 }
const char * name
Definition: ath9k_hw.c:1984
void * bf_desc
Definition: ath9k.h:225
struct arbelprm_completion_with_error error
Definition: arbel.h:12
#define DS2PHYS(_dd, _ds)
uint8_t head
Head number.
Definition: int13.h:34
Definition: mac.h:240
#define ito64(x)
Definition: ath9k.h:37
#define ATH_DESC_4KB_BOUND_CHECK(_daddr)
#define ENOMEM
Not enough space.
Definition: errno.h:534
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define list_add_tail(new, head)
Add a new entry to the tail of a list.
Definition: list.h:93
#define u32
Definition: vga.h:21
Definition: ath9k.h:219
u32 dd_desc_paddr
Definition: ath9k.h:107
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
uint32_t ds
Definition: librm.h:254
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
struct ath9k_hw_capabilities caps
Definition: hw.h:663
static void *__malloc malloc_dma(size_t size, size_t phys_align)
Allocate memory for DMA.
Definition: malloc.h:66
u32 dd_desc_len
Definition: ath9k.h:108
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static void free_dma(void *ptr, size_t size)
Free memory allocated with malloc_dma()
Definition: malloc.h:81
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
uint8_t u8
Definition: stdint.h:19
uint32_t u32
Definition: stdint.h:23
struct ath_buf * dd_bufptr
Definition: ath9k.h:109
void * dd_desc
Definition: ath9k.h:106
#define DBG2(...)
Definition: compiler.h:515
void * memset(void *dest, int character, size_t len) __nonnull

References ATH9K_HW_CAP_4KB_SPLITTRANS, ATH_DESC_4KB_BOUND_CHECK, ath_buf::bf_desc, ath_hw::caps, DBG, DBG2, ath_descdma::dd_bufptr, ath_descdma::dd_desc, ath_descdma::dd_desc_len, ath_descdma::dd_desc_paddr, ds, DS2PHYS, ENOMEM, error, free_dma(), head, ath9k_hw_capabilities::hw_caps, INIT_LIST_HEAD, ito64, list_add_tail, malloc_dma(), memset(), name, NULL, ath_softc::sc_ah, ath9k_hw_capabilities::tx_desc_len, u32, virt_to_bus(), and zalloc().

Referenced by ath_rx_init(), and ath_tx_init().

◆ ath_descdma_cleanup()

void ath_descdma_cleanup ( struct ath_softc sc,
struct ath_descdma dd,
struct list_head head 
)

Referenced by ath_rx_cleanup(), and ath_tx_cleanup().

◆ ath_startrecv()

int ath_startrecv ( struct ath_softc sc)

Definition at line 194 of file ath9k_recv.c.

195 {
196  struct ath_hw *ah = sc->sc_ah;
197  struct ath_buf *bf, *tbf;
198 
199  if (list_empty(&sc->rx.rxbuf))
200  goto start_recv;
201 
202  sc->rx.rxlink = NULL;
203  list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
204  ath_rx_buf_link(sc, bf);
205  }
206 
207  /* We could have deleted elements so the list may be empty now */
208  if (list_empty(&sc->rx.rxbuf))
209  goto start_recv;
210 
211  bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
214 
215 start_recv:
216  ath_opmode_init(sc);
218 
219  return 0;
220 }
Definition: hw.h:656
static void ath_opmode_init(struct ath_softc *sc)
Definition: ath9k_recv.c:75
static void ath9k_hw_rxena(struct ath_hw *ah)
Definition: hw-ops.h:33
static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
Definition: ath9k_recv.c:33
#define list_empty(list)
Test whether a list is empty.
Definition: list.h:136
u32 bf_daddr
Definition: ath9k.h:226
#define list_first_entry(list, type, member)
Get the container of the first entry in a list.
Definition: list.h:333
#define SC_OP_OFFCHANNEL
Definition: ath9k.h:366
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct list_head rxbuf
Definition: ath9k.h:301
#define list_for_each_entry_safe(pos, tmp, head, member)
Iterate over entries in a list, safe against deletion of the current entry.
Definition: list.h:447
Definition: ath9k.h:219
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
Definition: ath9k_mac.c:519
struct ath_rx rx
Definition: ath9k.h:475
struct list_head list
Definition: ath9k.h:220
u32 * rxlink
Definition: ath9k.h:299
u32 sc_flags
Definition: ath9k.h:465
uint8_t ah
Definition: registers.h:85
void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning)
Definition: ath9k_mac.c:524
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, ath9k_hw_putrxbuf(), ath9k_hw_rxena(), ath9k_hw_startpcureceive(), ath_opmode_init(), ath_rx_buf_link(), ath_buf::bf_daddr, ath_buf::list, list_empty, list_first_entry, list_for_each_entry_safe, NULL, ath_softc::rx, ath_rx::rxbuf, ath_rx::rxlink, ath_softc::sc_ah, ath_softc::sc_flags, and SC_OP_OFFCHANNEL.

Referenced by ath9k_start(), ath_reset(), and ath_set_channel().

◆ ath_stoprecv()

int ath_stoprecv ( struct ath_softc sc)

Definition at line 222 of file ath9k_recv.c.

223 {
224  struct ath_hw *ah = sc->sc_ah;
225  int stopped, reset = 0;
226 
229  stopped = ath9k_hw_stopdmarecv(ah, &reset);
230 
231  sc->rx.rxlink = NULL;
232 
233  if (!(ah->ah_flags & AH_UNPLUGGED) &&
234  !stopped) {
235  DBG("ath9k: "
236  "Could not stop RX, we could be "
237  "confusing the DMA engine when we start RX up\n");
238  }
239  return stopped && !reset;
240 }
Definition: hw.h:656
#define AH_UNPLUGGED
Definition: hw.h:654
int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset)
Definition: ath9k_mac.c:536
void ath9k_hw_abortpcurecv(struct ath_hw *ah)
Definition: ath9k_mac.c:531
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct ath_rx rx
Definition: ath9k.h:475
u32 * rxlink
Definition: ath9k.h:299
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Definition: ath9k_hw.c:1893
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ah, AH_UNPLUGGED, ath9k_hw_abortpcurecv(), ath9k_hw_setrxfilter(), ath9k_hw_stopdmarecv(), DBG, NULL, ath_softc::rx, ath_rx::rxlink, and ath_softc::sc_ah.

Referenced by ath9k_stop(), ath_radio_disable(), ath_reset(), and ath_set_channel().

◆ ath_flushrecv()

void ath_flushrecv ( struct ath_softc sc)

Definition at line 242 of file ath9k_recv.c.

243 {
244  sc->sc_flags |= SC_OP_RXFLUSH;
245  ath_rx_tasklet(sc, 1, 0);
246  sc->sc_flags &= ~SC_OP_RXFLUSH;
247 }
#define SC_OP_RXFLUSH
Definition: ath9k.h:369
int ath_rx_tasklet(struct ath_softc *sc, int flush, int hp __unused)
Definition: ath9k_recv.c:430
u32 sc_flags
Definition: ath9k.h:465

References ath_rx_tasklet(), ath_softc::sc_flags, and SC_OP_RXFLUSH.

Referenced by ath_radio_disable(), and ath_reset().

◆ ath_calcrxfilter()

u32 ath_calcrxfilter ( struct ath_softc sc)

Definition at line 179 of file ath9k_recv.c.

180 {
181 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
182 
183  u32 rfilt;
184 
188 
189  return rfilt;
190 
191 #undef RX_FILTER_PRESERVE
192 }
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define RX_FILTER_PRESERVE
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Definition: ath9k_hw.c:1880
uint32_t u32
Definition: stdint.h:23

References ath9k_hw_getrxfilter(), ATH9K_RX_FILTER_BCAST, ATH9K_RX_FILTER_BEACON, ATH9K_RX_FILTER_MCAST, ATH9K_RX_FILTER_UCAST, RX_FILTER_PRESERVE, and ath_softc::sc_ah.

Referenced by ath_opmode_init().

◆ ath_rx_init()

int ath_rx_init ( struct ath_softc sc,
int  nbufs 
)

Definition at line 97 of file ath9k_recv.c.

98 {
99  struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100  struct io_buffer *iob;
101  struct ath_buf *bf;
102  int error = 0;
103 
104  sc->sc_flags &= ~SC_OP_RXFLUSH;
105 
106  common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
107  sc->sc_ah->caps.rx_status_len;
108 
109  DBG2("ath9k: cachelsz %d rxbufsize %d\n",
110  common->cachelsz, common->rx_bufsize);
111 
112  /* Initialize rx descriptors */
113 
114  error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
115  "rx", nbufs, 1, 0);
116  if (error != 0) {
117  DBG("ath9k: "
118  "failed to allocate rx descriptors: %d\n",
119  error);
120  goto err;
121  }
122 
123  list_for_each_entry(bf, &sc->rx.rxbuf, list) {
124  iob = alloc_iob_raw ( common->rx_bufsize, common->cachelsz, 0 );
125  if (iob == NULL) {
126  error = -ENOMEM;
127  goto err;
128  }
129 
130  bf->bf_mpdu = iob;
131  bf->bf_buf_addr = virt_to_bus ( iob->data );
132  }
133  sc->rx.rxlink = NULL;
134 
135 err:
136  if (error)
137  ath_rx_cleanup(sc);
138 
139  return error;
140 }
struct io_buffer * bf_mpdu
Definition: ath9k.h:224
#define SC_OP_RXFLUSH
Definition: ath9k.h:369
struct io_buffer * alloc_iob_raw(size_t len, size_t align, size_t offset)
Allocate I/O buffer with specified alignment and offset.
Definition: iobuf.c:48
struct arbelprm_completion_with_error error
Definition: arbel.h:12
struct ath_descdma rxdma
Definition: ath9k.h:302
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head, const char *name, int nbuf, int ndesc, int is_tx)
Definition: ath9k_init.c:180
#define ENOMEM
Not enough space.
Definition: errno.h:534
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
void ath_rx_cleanup(struct ath_softc *sc)
Definition: ath9k_recv.c:142
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define list_for_each_entry(pos, head, member)
Iterate over entries in a list.
Definition: list.h:420
struct list_head rxbuf
Definition: ath9k.h:301
u32 bf_buf_addr
Definition: ath9k.h:227
Definition: ath9k.h:219
struct ath_rx rx
Definition: ath9k.h:475
#define IEEE80211_MAX_MPDU_LEN
Definition: ath9k.h:148
struct list_head list
Definition: ath9k.h:220
u32 * rxlink
Definition: ath9k.h:299
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
u32 sc_flags
Definition: ath9k.h:465
struct ath9k_hw_capabilities caps
Definition: hw.h:663
void * data
Start of data.
Definition: iobuf.h:44
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define DBG2(...)
Definition: compiler.h:515
A persistent I/O buffer.
Definition: iobuf.h:32

References alloc_iob_raw(), ath9k_hw_common(), ath_descdma_setup(), ath_rx_cleanup(), ath_buf::bf_buf_addr, ath_buf::bf_mpdu, ath_hw::caps, common, io_buffer::data, DBG, DBG2, ENOMEM, error, IEEE80211_MAX_MPDU_LEN, ath_buf::list, list_for_each_entry, NULL, ath_softc::rx, ath9k_hw_capabilities::rx_status_len, ath_rx::rxbuf, ath_rx::rxdma, ath_rx::rxlink, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_RXFLUSH, and virt_to_bus().

Referenced by ath9k_init_device().

◆ ath_rx_cleanup()

void ath_rx_cleanup ( struct ath_softc sc)

Definition at line 142 of file ath9k_recv.c.

143 {
144  struct io_buffer *iob;
145  struct ath_buf *bf;
146 
147  list_for_each_entry(bf, &sc->rx.rxbuf, list) {
148  iob = bf->bf_mpdu;
149  if (iob) {
150  free_iob(iob);
151  bf->bf_buf_addr = 0;
152  bf->bf_mpdu = NULL;
153  }
154  }
155 
156  if (sc->rx.rxdma.dd_desc_len != 0)
157  ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
158 }
void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head)
struct io_buffer * bf_mpdu
Definition: ath9k.h:224
void free_iob(struct io_buffer *iobuf)
Free I/O buffer.
Definition: iobuf.c:145
struct ath_descdma rxdma
Definition: ath9k.h:302
#define list_for_each_entry(pos, head, member)
Iterate over entries in a list.
Definition: list.h:420
struct list_head rxbuf
Definition: ath9k.h:301
u32 bf_buf_addr
Definition: ath9k.h:227
Definition: ath9k.h:219
struct ath_rx rx
Definition: ath9k.h:475
struct list_head list
Definition: ath9k.h:220
u32 dd_desc_len
Definition: ath9k.h:108
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
A persistent I/O buffer.
Definition: iobuf.h:32

References ath_descdma_cleanup(), ath_buf::bf_buf_addr, ath_buf::bf_mpdu, ath_descdma::dd_desc_len, free_iob(), ath_buf::list, list_for_each_entry, NULL, ath_softc::rx, ath_rx::rxbuf, and ath_rx::rxdma.

Referenced by ath9k_deinit_device(), ath9k_init_device(), and ath_rx_init().

◆ ath_rx_tasklet()

int ath_rx_tasklet ( struct ath_softc sc,
int  flush,
int  hp 
)

Definition at line 430 of file ath9k_recv.c.

431 {
432  struct ath_buf *bf;
433  struct io_buffer *iob = NULL, *requeue_iob;
434  struct ath_hw *ah = sc->sc_ah;
435  struct ath_common *common = ath9k_hw_common(ah);
436  /*
437  * The hw can technically differ from common->hw when using ath9k
438  * virtual wiphy so to account for that we iterate over the active
439  * wiphys and find the appropriate wiphy and therefore hw.
440  */
441  struct net80211_device *dev = sc->dev;
442  int retval;
443  int decrypt_error = 0;
444  struct ath_rx_status rs;
445  int rix = 0;
446 
447  do {
448  /* If handling rx interrupt and flush is in progress => exit */
449  if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
450  break;
451 
452  memset(&rs, 0, sizeof(rs));
453  bf = ath_get_next_rx_buf(sc, &rs);
454 
455  if (!bf)
456  break;
457 
458  iob = bf->bf_mpdu;
459  if (!iob)
460  continue;
461 
462  /*
463  * If we're asked to flush receive queue, directly
464  * chain it back at the queue without processing it.
465  */
466  if (flush)
467  goto requeue_drop_frag;
468 
470  &rix, &decrypt_error);
471  if (retval)
472  goto requeue_drop_frag;
473 
474  /* Ensure we always have an iob to requeue once we are done
475  * processing the current buffer's iob */
476  requeue_iob = alloc_iob_raw ( common->rx_bufsize,
477  common->cachelsz, 0 );
478 
479  /* If there is no memory we ignore the current RX'd frame,
480  * tell hardware it can give us a new frame using the old
481  * iob and put it at the tail of the sc->rx.rxbuf list for
482  * processing. */
483  if (!requeue_iob)
484  goto requeue_drop_frag;
485 
486  iob_put(iob, rs.rs_datalen + ah->caps.rx_status_len);
487  if (ah->caps.rx_status_len)
488  iob_pull(iob, ah->caps.rx_status_len);
489 
490  /* We will now give hardware our shiny new allocated iob */
491  bf->bf_mpdu = requeue_iob;
492  bf->bf_buf_addr = virt_to_bus ( requeue_iob->data );
493 
494  /*
495  * change the default rx antenna if rx diversity chooses the
496  * other antenna 3 times in a row.
497  */
498  if (sc->rx.defant != rs.rs_antenna) {
499  if (++sc->rx.rxotherant >= 3)
500  ath_setdefantenna(sc, rs.rs_antenna);
501  } else {
502  sc->rx.rxotherant = 0;
503  }
504 
505  DBGIO("ath9k: rx %d bytes, signal %d, bitrate %d, hw_value %d\n", rs.rs_datalen,
506  rs.rs_rssi, sc->rates[rix].bitrate, rs.rs_rate);
507 
508  net80211_rx(dev, iob, rs.rs_rssi,
509  sc->rates[rix].bitrate);
510 
511 requeue_drop_frag:
512  list_del(&bf->list);
513  list_add_tail(&bf->list, &sc->rx.rxbuf);
514  ath_rx_buf_link(sc, bf);
516  } while (1);
517 
518  return 0;
519 }
#define iob_pull(iobuf, len)
Definition: iobuf.h:98
struct io_buffer * bf_mpdu
Definition: ath9k.h:224
Definition: hw.h:656
#define iob_put(iobuf, len)
Definition: iobuf.h:116
#define SC_OP_RXFLUSH
Definition: ath9k.h:369
struct io_buffer * alloc_iob_raw(size_t len, size_t align, size_t offset)
Allocate I/O buffer with specified alignment and offset.
Definition: iobuf.c:48
void net80211_rx(struct net80211_device *dev, struct io_buffer *iob, int signal, u16 rate)
Handle receipt of 802.11 frame.
Definition: net80211.c:2689
static void ath9k_hw_rxena(struct ath_hw *ah)
Definition: hw-ops.h:33
static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
Definition: ath9k_recv.c:33
struct net80211_device * dev
Definition: ath9k.h:445
#define list_del(list)
Delete an entry from a list.
Definition: list.h:119
u8 rxotherant
Definition: ath9k.h:298
static __always_inline unsigned long virt_to_bus(volatile const void *addr)
Convert virtual address to a bus address.
Definition: io.h:183
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define list_add_tail(new, head)
Add a new entry to the tail of a list.
Definition: list.h:93
struct list_head rxbuf
Definition: ath9k.h:301
u8 defant
Definition: ath9k.h:297
u32 bf_buf_addr
Definition: ath9k.h:227
#define DBGIO(...)
Definition: compiler.h:549
Definition: ath9k.h:219
struct ath_rx rx
Definition: ath9k.h:475
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
struct list_head list
Definition: ath9k.h:220
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
u32 sc_flags
Definition: ath9k.h:465
unsigned long retval
Definition: xen.h:45
static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
Definition: ath9k_recv.c:67
static int ath9k_rx_iob_preprocess(struct ath_common *common, struct net80211_device *dev, struct ath_rx_status *rx_stats, int *rix, int *decrypt_error)
Definition: ath9k_recv.c:407
uint8_t ah
Definition: registers.h:85
struct ath9k_legacy_rate rates[NET80211_MAX_RATES]
Definition: ath9k.h:478
static struct ath_buf * ath_get_next_rx_buf(struct ath_softc *sc, struct ath_rx_status *rs)
Definition: ath9k_recv.c:249
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
void * memset(void *dest, int character, size_t len) __nonnull
A persistent I/O buffer.
Definition: iobuf.h:32

References ah, alloc_iob_raw(), ath9k_hw_common(), ath9k_hw_rxena(), ath9k_rx_iob_preprocess(), ath_get_next_rx_buf(), ath_rx_buf_link(), ath_setdefantenna(), ath_buf::bf_buf_addr, ath_buf::bf_mpdu, ath9k_legacy_rate::bitrate, common, DBGIO, ath_rx::defant, ath_softc::dev, iob_pull, iob_put, ath_buf::list, list_add_tail, list_del, memset(), net80211_rx(), NULL, ath_softc::rates, retval, ath_rx_status::rs_antenna, ath_rx_status::rs_datalen, ath_rx_status::rs_rate, ath_rx_status::rs_rssi, ath_softc::rx, ath_rx::rxbuf, ath_rx::rxotherant, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_RXFLUSH, and virt_to_bus().

Referenced by ath9k_tasklet(), and ath_flushrecv().

◆ ath_txq_setup()

struct ath_txq* ath_txq_setup ( struct ath_softc sc,
int  qtype,
int  subtype 
)

Definition at line 106 of file ath9k_xmit.c.

107 {
108  struct ath_hw *ah = sc->sc_ah;
109  struct ath9k_tx_queue_info qi;
110  static const int subtype_txq_to_hwq[] = {
112  };
113  int axq_qnum, i;
114 
115  memset(&qi, 0, sizeof(qi));
116  qi.tqi_subtype = subtype_txq_to_hwq[subtype];
117  qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
118  qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
119  qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
120  qi.tqi_physCompBuf = 0;
121 
122  /*
123  * Enable interrupts only for EOL and DESC conditions.
124  * We mark tx descriptors to receive a DESC interrupt
125  * when a tx queue gets deep; otherwise waiting for the
126  * EOL to reap descriptors. Note that this is done to
127  * reduce interrupt load and this only defers reaping
128  * descriptors, never transmitting frames. Aside from
129  * reducing interrupts this also permits more concurrency.
130  * The only potential downside is if the tx queue backs
131  * up in which case the top half of the kernel may backup
132  * due to a lack of tx descriptors.
133  *
134  * The UAPSD queue is an exception, since we take a desc-
135  * based intr on the EOSP frames.
136  */
137  qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
139 
140  axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
141  if (axq_qnum == -1) {
142  /*
143  * NB: don't print a message, this happens
144  * normally on parts with too few tx queues
145  */
146  return NULL;
147  }
148  if ((unsigned int)axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
149  DBG("ath9k: qnum %d out of range, max %zd!\n",
150  axq_qnum, ARRAY_SIZE(sc->tx.txq));
151  ath9k_hw_releasetxqueue(ah, axq_qnum);
152  return NULL;
153  }
154  if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
155  struct ath_txq *txq = &sc->tx.txq[axq_qnum];
156 
157  txq->axq_qnum = axq_qnum;
158  txq->mac80211_qnum = -1;
159  txq->axq_link = NULL;
160  INIT_LIST_HEAD(&txq->axq_q);
161  INIT_LIST_HEAD(&txq->axq_acq);
162  txq->axq_depth = 0;
163  txq->axq_ampdu_depth = 0;
164  txq->axq_tx_inprogress = 0;
165  sc->tx.txqsetup |= 1<<axq_qnum;
166 
167  txq->txq_headidx = txq->txq_tailidx = 0;
168  for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
169  INIT_LIST_HEAD(&txq->txq_fifo[i]);
171  }
172  return &sc->tx.txq[axq_qnum];
173 }
Definition: hw.h:656
u8 txq_headidx
Definition: ath9k.h:192
u32 * axq_link
Definition: ath9k.h:183
int mac80211_qnum
Definition: ath9k.h:181
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
u8 txq_tailidx
Definition: ath9k.h:193
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
struct list_head axq_q
Definition: ath9k.h:184
#define WME_AC_BE
Definition: common.h:34
u32 axq_ampdu_depth
Definition: ath9k.h:186
Definition: ath9k.h:180
int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:259
u32 txqsetup
Definition: ath9k.h:283
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define ATH9K_TXQ_USEDEFAULT
Definition: mac.h:597
#define ATH_TXFIFO_DEPTH
Definition: ath9k.h:179
struct list_head txq_fifo[ATH_TXFIFO_DEPTH]
Definition: ath9k.h:190
uint8_t subtype
Slow protocols subtype.
Definition: eth_slow.h:12
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo)
Definition: ath9k_mac.c:216
u32 axq_qnum
Definition: ath9k.h:182
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
struct ath_tx tx
Definition: ath9k.h:476
struct list_head axq_acq
Definition: ath9k.h:189
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
u32 axq_depth
Definition: ath9k.h:185
uint8_t ah
Definition: registers.h:85
struct list_head txq_fifo_pending
Definition: ath9k.h:191
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
int axq_tx_inprogress
Definition: ath9k.h:188
void * memset(void *dest, int character, size_t len) __nonnull

References ah, ARRAY_SIZE, ath9k_hw_releasetxqueue(), ath9k_hw_setuptxqueue(), ATH9K_TXQ_USEDEFAULT, ATH_TXFIFO_DEPTH, ATH_TXQ_AC_BE, ATH_TXQ_SETUP, ath_txq::axq_acq, ath_txq::axq_ampdu_depth, ath_txq::axq_depth, ath_txq::axq_link, ath_txq::axq_q, ath_txq::axq_qnum, ath_txq::axq_tx_inprogress, DBG, INIT_LIST_HEAD, ath_txq::mac80211_qnum, memset(), NULL, ath_softc::sc_ah, subtype, ath9k_tx_queue_info::tqi_aifs, ath9k_tx_queue_info::tqi_cwmax, ath9k_tx_queue_info::tqi_cwmin, ath9k_tx_queue_info::tqi_physCompBuf, ath9k_tx_queue_info::tqi_qflags, ath9k_tx_queue_info::tqi_subtype, ath_softc::tx, ath_tx::txq, ath_txq::txq_fifo, ath_txq::txq_fifo_pending, TXQ_FLAG_TXDESCINT_ENABLE, TXQ_FLAG_TXEOLINT_ENABLE, ath_txq::txq_headidx, ath_txq::txq_tailidx, ath_tx::txqsetup, and WME_AC_BE.

Referenced by ath9k_init_queues().

◆ ath_tx_cleanupq()

void ath_tx_cleanupq ( struct ath_softc sc,
struct ath_txq txq 
)

Definition at line 255 of file ath9k_xmit.c.

256 {
258  sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
259 }
int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:259
u32 txqsetup
Definition: ath9k.h:283
struct ath_hw * sc_ah
Definition: ath9k.h:454
u32 axq_qnum
Definition: ath9k.h:182
struct ath_tx tx
Definition: ath9k.h:476

References ath9k_hw_releasetxqueue(), ath_txq::axq_qnum, ath_softc::sc_ah, ath_softc::tx, and ath_tx::txqsetup.

Referenced by ath9k_deinit_softc(), and ath9k_init_softc().

◆ ath_drain_all_txq()

int ath_drain_all_txq ( struct ath_softc sc,
int  retry_tx 
)

Definition at line 216 of file ath9k_xmit.c.

217 {
218  struct ath_hw *ah = sc->sc_ah;
219  struct ath_txq *txq;
220  int i, npend = 0;
221 
222  if (sc->sc_flags & SC_OP_INVALID)
223  return 1;
224 
226 
227  /* Check if any queue remains active */
228  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
229  if (!ATH_TXQ_SETUP(sc, i))
230  continue;
231 
232  npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
233  }
234 
235  if (npend)
236  DBG("ath9k: Failed to stop TX DMA!\n");
237 
238  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
239  if (!ATH_TXQ_SETUP(sc, i))
240  continue;
241 
242  /*
243  * The caller will resume queues with ieee80211_wake_queues.
244  * Mark the queue as not stopped to prevent ath_tx_complete
245  * from waking the queue too early.
246  */
247  txq = &sc->tx.txq[i];
248  txq->stopped = 0;
249  ath_draintxq(sc, txq, retry_tx);
250  }
251 
252  return !npend;
253 }
Definition: hw.h:656
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Definition: ath9k_mac.c:62
int stopped
Definition: ath9k.h:187
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
Definition: ath9k.h:180
struct ath_hw * sc_ah
Definition: ath9k.h:454
void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
Definition: ath9k_mac.c:129
u32 axq_qnum
Definition: ath9k.h:182
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
struct ath_tx tx
Definition: ath9k.h:476
void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, int retry_tx __unused)
Definition: ath9k_xmit.c:181
u32 sc_flags
Definition: ath9k.h:465
#define SC_OP_INVALID
Definition: ath9k.h:362
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ah, ath9k_hw_abort_tx_dma(), ath9k_hw_numtxpending(), ATH9K_NUM_TX_QUEUES, ath_draintxq(), ATH_TXQ_SETUP, ath_txq::axq_qnum, DBG, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, ath_txq::stopped, ath_softc::tx, and ath_tx::txq.

Referenced by ath9k_stop(), ath_radio_disable(), ath_reset(), and ath_set_channel().

◆ ath_draintxq()

void ath_draintxq ( struct ath_softc sc,
struct ath_txq txq,
int  retry_tx 
)

Definition at line 181 of file ath9k_xmit.c.

182 {
183  struct ath_buf *bf, *lastbf __unused;
184  struct list_head bf_head;
185  struct ath_tx_status ts;
186 
187  memset(&ts, 0, sizeof(ts));
188  INIT_LIST_HEAD(&bf_head);
189 
190  for (;;) {
191  if (list_empty(&txq->axq_q)) {
192  txq->axq_link = NULL;
193  break;
194  }
195  bf = list_first_entry(&txq->axq_q, struct ath_buf,
196  list);
197 
198  if (bf->bf_stale) {
199  list_del(&bf->list);
200 
201  ath_tx_return_buffer(sc, bf);
202  continue;
203  }
204 
205  lastbf = bf->bf_lastbf;
206 
207  list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
208 
209  txq->axq_depth--;
210  ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
211  }
212 
213  txq->axq_tx_inprogress = 0;
214 }
u32 * axq_link
Definition: ath9k.h:183
struct list_head axq_q
Definition: ath9k.h:184
A doubly-linked list entry (or list head)
Definition: list.h:18
#define list_empty(list)
Test whether a list is empty.
Definition: list.h:136
#define list_first_entry(list, type, member)
Get the container of the first entry in a list.
Definition: list.h:333
#define list_del(list)
Delete an entry from a list.
Definition: list.h:119
static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, struct ath_txq *txq, struct list_head *bf_q, struct ath_tx_status *ts, int txok, int sendbar)
Definition: ath9k_xmit.c:623
int bf_stale
Definition: ath9k.h:228
Definition: ath9k.h:219
struct ath_buf * bf_lastbf
Definition: ath9k.h:221
struct list_head list
Definition: ath9k.h:220
#define list_cut_position(new, list, entry)
Cut a list into two.
Definition: list.h:185
static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
Definition: ath9k_xmit.c:97
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
#define INIT_LIST_HEAD(list)
Initialise a list head.
Definition: list.h:45
u32 axq_depth
Definition: ath9k.h:185
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
int axq_tx_inprogress
Definition: ath9k.h:188
void * memset(void *dest, int character, size_t len) __nonnull

References __unused, ath_tx_complete_buf(), ath_tx_return_buffer(), ath_txq::axq_depth, ath_txq::axq_link, ath_txq::axq_q, ath_txq::axq_tx_inprogress, ath_buf::bf_lastbf, ath_buf::bf_stale, INIT_LIST_HEAD, ath_buf::list, list_cut_position, list_del, list_empty, list_first_entry, memset(), and NULL.

Referenced by ath_drain_all_txq().

◆ ath_txq_schedule()

void ath_txq_schedule ( struct ath_softc sc,
struct ath_txq txq 
)

Referenced by ath_reset().

◆ ath_tx_init()

int ath_tx_init ( struct ath_softc sc,
int  nbufs 
)

Definition at line 788 of file ath9k_xmit.c.

789 {
790  int error = 0;
791 
792  error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
793  "tx", nbufs, 1, 1);
794  if (error != 0) {
795  DBG("ath9k: "
796  "Failed to allocate tx descriptors: %d\n", error);
797  goto err;
798  }
799 
801 
802 err:
803  if (error != 0)
804  ath_tx_cleanup(sc);
805 
806  return error;
807 }
struct ath_descdma txdma
Definition: ath9k.h:286
struct arbelprm_completion_with_error error
Definition: arbel.h:12
int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head, const char *name, int nbuf, int ndesc, int is_tx)
Definition: ath9k_init.c:180
void(* tx_complete_work)(struct ath_softc *sc)
Definition: ath9k.h:484
static void ath_tx_complete_poll_work(struct ath_softc *sc)
Definition: ath9k_xmit.c:741
void ath_tx_cleanup(struct ath_softc *sc)
Definition: ath9k_xmit.c:809
struct ath_tx tx
Definition: ath9k.h:476
struct list_head txbuf
Definition: ath9k.h:284
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498

References ath_descdma_setup(), ath_tx_cleanup(), ath_tx_complete_poll_work(), DBG, error, ath_softc::tx, ath_softc::tx_complete_work, ath_tx::txbuf, and ath_tx::txdma.

Referenced by ath9k_init_device().

◆ ath_tx_cleanup()

void ath_tx_cleanup ( struct ath_softc sc)

Definition at line 809 of file ath9k_xmit.c.

810 {
811  if (sc->tx.txdma.dd_desc_len != 0)
812  ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
813 }
struct ath_descdma txdma
Definition: ath9k.h:286
void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, struct list_head *head)
struct ath_tx tx
Definition: ath9k.h:476
struct list_head txbuf
Definition: ath9k.h:284
u32 dd_desc_len
Definition: ath9k.h:108

References ath_descdma_cleanup(), ath_descdma::dd_desc_len, ath_softc::tx, ath_tx::txbuf, and ath_tx::txdma.

Referenced by ath9k_deinit_device(), ath9k_init_device(), and ath_tx_init().

◆ ath_txq_update()

int ath_txq_update ( struct ath_softc sc,
int  qnum,
struct ath9k_tx_queue_info q 
)

◆ ath_tx_start()

int ath_tx_start ( struct net80211_device dev,
struct io_buffer iob,
struct ath_tx_control txctl 
)

Definition at line 569 of file ath9k_xmit.c.

571 {
572  struct ath_softc *sc = dev->priv;
573  struct ath_txq *txq = txctl->txq;
574  struct ath_buf *bf;
575  int q;
576 
577  /*
578  * At this point, the vif, hw_key and sta pointers in the tx control
579  * info are no longer valid (overwritten by the ath_frame_info data.
580  */
581 
582  bf = ath_tx_setup_buffer(dev, txctl->txq, iob);
583  if (!bf)
584  return -ENOMEM;
585 
586  q = 0;
587  if (txq == sc->tx.txq_map[q] &&
588  ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
589  txq->stopped = 1;
590  }
591 
592  ath_tx_start_dma(sc, bf, txctl);
593 
594  return 0;
595 }
int pending_frames
Definition: ath9k.h:194
int stopped
Definition: ath9k.h:187
struct ath_txq * txq
Definition: ath9k.h:266
static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, struct ath_tx_control *txctl)
Definition: ath9k_xmit.c:549
struct net80211_device * dev
Definition: ath9k.h:445
#define ENOMEM
Not enough space.
Definition: errno.h:534
Definition: ath9k.h:180
void * priv
Driver private data.
Definition: net80211.h:798
Definition: ath9k.h:219
struct ath_tx tx
Definition: ath9k.h:476
#define ATH_MAX_QDEPTH
Definition: ath9k.h:125
struct ath_txq * txq_map[WME_NUM_AC]
Definition: ath9k.h:287
static struct ath_buf * ath_tx_setup_buffer(struct net80211_device *dev, struct ath_txq *txq, struct io_buffer *iob)
Definition: ath9k_xmit.c:498

References ATH_MAX_QDEPTH, ath_tx_setup_buffer(), ath_tx_start_dma(), ath_softc::dev, ENOMEM, ath_txq::pending_frames, net80211_device::priv, ath_txq::stopped, ath_softc::tx, ath_tx_control::txq, and ath_tx::txq_map.

Referenced by ath9k_tx().

◆ ath_tx_tasklet()

void ath_tx_tasklet ( struct ath_softc sc)

Definition at line 771 of file ath9k_xmit.c.

772 {
773  int i;
774  u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
775 
776  ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
777 
778  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
779  if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
780  ath_tx_processq(sc, &sc->tx.txq[i]);
781  }
782 }
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
struct ath_hw * sc_ah
Definition: ath9k.h:454
void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
Definition: ath9k_mac.c:156
static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
Definition: ath9k_xmit.c:656
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
struct ath_tx tx
Definition: ath9k.h:476
uint32_t u32
Definition: stdint.h:23

References ath9k_hw_gettxintrtxqs(), ATH9K_NUM_TX_QUEUES, ath_tx_processq(), ATH_TXQ_SETUP, ath_softc::sc_ah, ath_softc::tx, and ath_tx::txq.

Referenced by ath9k_tasklet().

◆ ath_hw_pll_work()

void ath_hw_pll_work ( struct ath_softc sc)

Definition at line 325 of file ath9k_main.c.

326 {
327  u32 pll_sqsum;
328 
329  if (AR_SREV_9485(sc->sc_ah)) {
330  pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
331 
332  ath_hw_pll_rx_hang_check(sc, pll_sqsum);
333 
334  sc->hw_pll_work_timer = (currticks() * 1000 ) / TICKS_PER_SEC + 200;
335  }
336 }
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
Definition: ath9k_hw.c:609
#define AR_SREV_9485(_ah)
Definition: reg.h:867
static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
Definition: ath9k_main.c:308
struct ath_hw * sc_ah
Definition: ath9k.h:454
unsigned long hw_pll_work_timer
Definition: ath9k.h:487
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
uint32_t u32
Definition: stdint.h:23

References ar9003_get_pll_sqsum_dvc(), AR_SREV_9485, ath_hw_pll_rx_hang_check(), currticks(), ath_softc::hw_pll_work_timer, ath_softc::sc_ah, and TICKS_PER_SEC.

Referenced by ath9k_init_device().

◆ ath_ani_calibrate()

void ath_ani_calibrate ( struct ath_softc sc)

Definition at line 200 of file ath9k_main.c.

201 {
202  struct ath_hw *ah = sc->sc_ah;
203  struct ath_common *common = ath9k_hw_common(ah);
204  int longcal = 0;
205  int shortcal = 0;
206  int aniflag = 0;
207  unsigned int timestamp = (currticks() * 1000 ) / TICKS_PER_SEC;
208  u32 cal_interval, short_cal_interval, long_cal_interval;
209 
210  if (ah->caldata && ah->caldata->nfcal_interference)
211  long_cal_interval = ATH_LONG_CALINTERVAL_INT;
212  else
213  long_cal_interval = ATH_LONG_CALINTERVAL;
214 
215  short_cal_interval = ATH_STA_SHORT_CALINTERVAL;
216 
217  /* Only calibrate if awake */
218  if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
219  goto set_timer;
220 
221  /* Long calibration runs independently of short calibration. */
222  if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
223  longcal = 1;
224  DBG2("ath9k: longcal @%d\n", timestamp);
225  common->ani.longcal_timer = timestamp;
226  }
227 
228  /* Short calibration applies only while caldone is false */
229  if (!common->ani.caldone) {
230  if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
231  shortcal = 1;
232  DBG2("ath9k: "
233  "shortcal @%d\n", timestamp);
234  common->ani.shortcal_timer = timestamp;
235  common->ani.resetcal_timer = timestamp;
236  }
237  } else {
238  if ((timestamp - common->ani.resetcal_timer) >=
240  common->ani.caldone = ath9k_hw_reset_calvalid(ah);
241  if (common->ani.caldone)
242  common->ani.resetcal_timer = timestamp;
243  }
244  }
245 
246  /* Verify whether we must check ANI */
247  if ((timestamp - common->ani.checkani_timer) >=
248  ah->config.ani_poll_interval) {
249  aniflag = 1;
250  common->ani.checkani_timer = timestamp;
251  }
252 
253  /* Skip all processing if there's nothing to do. */
254  if (longcal || shortcal || aniflag) {
255  /* Call ANI routine if necessary */
256  if (aniflag) {
257  ath9k_hw_ani_monitor(ah, ah->curchan);
259  }
260 
261  /* Perform calibration if necessary */
262  if (longcal || shortcal) {
263  common->ani.caldone =
265  ah->curchan,
266  common->rx_chainmask,
267  longcal);
268  }
269  }
270 
271 set_timer:
272  /*
273  * Set timer interval based on previous results.
274  * The interval must be the shortest necessary to satisfy ANI,
275  * short calibration and long calibration.
276  */
277  cal_interval = ATH_LONG_CALINTERVAL;
278  if (sc->sc_ah->config.enable_ani)
279  cal_interval = min(cal_interval,
280  (u32)ah->config.ani_poll_interval);
281  if (!common->ani.caldone)
282  cal_interval = min(cal_interval, (u32)short_cal_interval);
283 
284  common->ani.timer = timestamp + cal_interval;
285 }
Definition: hw.h:656
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
u32 enable_ani
Definition: hw.h:231
#define ATH_STA_SHORT_CALINTERVAL
Definition: ath9k.h:334
#define ATH_RESTART_CALINTERVAL
Definition: ath9k.h:340
#define min(x, y)
Definition: ath.h:34
enum ath9k_power_mode power_mode
Definition: hw.h:691
void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan __unused)
Definition: ath9k_ani.c:597
int ath9k_hw_reset_calvalid(struct ath_hw *ah)
Definition: ath9k_calib.c:173
__be64 timestamp
Definition: CIB_PRM.h:38
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define ATH_LONG_CALINTERVAL_INT
Definition: ath9k.h:338
struct ath9k_ops_config config
Definition: hw.h:662
static int ath_update_survey_stats(struct ath_softc *sc)
Definition: ath9k_main.c:71
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
static int ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, int longcal)
Definition: hw-ops.h:49
struct ib_cm_common common
Definition: ib_mad.h:11
#define ATH_LONG_CALINTERVAL
Definition: ath9k.h:339
uint8_t ah
Definition: registers.h:85
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
uint32_t u32
Definition: stdint.h:23
#define DBG2(...)
Definition: compiler.h:515

References ah, ath9k_hw_ani_monitor(), ath9k_hw_calibrate(), ath9k_hw_common(), ath9k_hw_reset_calvalid(), ATH9K_PM_AWAKE, ATH_LONG_CALINTERVAL, ATH_LONG_CALINTERVAL_INT, ATH_RESTART_CALINTERVAL, ATH_STA_SHORT_CALINTERVAL, ath_update_survey_stats(), common, ath_hw::config, currticks(), DBG2, ath9k_ops_config::enable_ani, min, ath_hw::power_mode, ath_softc::sc_ah, TICKS_PER_SEC, and timestamp.

Referenced by ath_isr().

◆ ath9k_tasklet()

void ath9k_tasklet ( struct ath_softc sc)

Definition at line 339 of file ath9k_main.c.

340 {
341  struct ath_hw *ah = sc->sc_ah;
342 
343  u32 status = sc->intrstatus;
344  u32 rxmask;
345 
346  if ((status & ATH9K_INT_FATAL) ||
348  ath_reset(sc, 1);
349  return;
350  }
351 
353 
354  if (status & rxmask) {
355  ath_rx_tasklet(sc, 0, 0);
356  }
357 
358  if (status & ATH9K_INT_TX) {
359  ath_tx_tasklet(sc);
360  }
361 
362  /* re-enable hardware interrupt */
364 }
Definition: hw.h:656
void ath9k_hw_enable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:616
int ath_rx_tasklet(struct ath_softc *sc, int flush, int hp)
Definition: ath9k_recv.c:430
void ath_tx_tasklet(struct ath_softc *sc)
Definition: ath9k_xmit.c:771
uint8_t status
Status.
Definition: ena.h:16
struct ath_hw * sc_ah
Definition: ath9k.h:454
int ath_reset(struct ath_softc *sc, int retry_tx)
Definition: ath9k_main.c:511
u32 intrstatus
Definition: ath9k.h:464
uint8_t ah
Definition: registers.h:85
uint32_t u32
Definition: stdint.h:23

References ah, ath9k_hw_enable_interrupts(), ATH9K_INT_BB_WATCHDOG, ATH9K_INT_FATAL, ATH9K_INT_RX, ATH9K_INT_RXEOL, ATH9K_INT_RXORN, ATH9K_INT_TX, ath_reset(), ath_rx_tasklet(), ath_tx_tasklet(), ath_softc::intrstatus, ath_softc::sc_ah, and status.

Referenced by ath9k_init_softc().

◆ ath_reset()

int ath_reset ( struct ath_softc sc,
int  retry_tx 
)

Definition at line 511 of file ath9k_main.c.

512 {
513  struct ath_hw *ah = sc->sc_ah;
514  struct ath_common *common = ath9k_hw_common(ah);
515  int r;
516 
517  sc->hw_busy_count = 0;
518 
519  /* Stop ANI */
520  common->ani.timer = 0;
521 
523  ath_drain_all_txq(sc, retry_tx);
524 
525  ath_stoprecv(sc);
526  ath_flushrecv(sc);
527 
528  r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, 0);
529  if (r)
530  DBG("ath9k: "
531  "Unable to reset hardware; reset status %d\n", r);
532 
533  if (ath_startrecv(sc) != 0)
534  DBG("ath9k: Unable to start recv logic\n");
535 
536  /*
537  * We may be doing a reset in response to a request
538  * that changes the channel so update any state that
539  * might change as a result.
540  */
542  sc->config.txpowlimit, &sc->curtxpow);
543 
544  ath9k_hw_set_interrupts(ah, ah->imask);
545 
546  if (retry_tx) {
547  int i;
548  for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
549  if (ATH_TXQ_SETUP(sc, i)) {
550  ath_txq_schedule(sc, &sc->tx.txq[i]);
551  }
552  }
553  }
554 
555  /* Start ANI */
557 
558  return r;
559 }
Definition: hw.h:656
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
Definition: ath9k_hw.c:1216
struct ath9k_channel * curchan
Definition: hw.h:665
#define ATH_TXQ_SETUP(sc, i)
Definition: ath9k.h:62
static void ath_start_ani(struct ath_common *common)
Definition: ath9k_main.c:35
struct ath_txq txq[ATH9K_NUM_TX_QUEUES]
Definition: ath9k.h:285
void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow, u16 new_txpow, u16 *txpower)
Definition: ath9k_common.c:61
int ath_drain_all_txq(struct ath_softc *sc, int retry_tx)
Definition: ath9k_xmit.c:216
void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct ath_config config
Definition: ath9k.h:474
void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
Definition: ath9k_mac.c:641
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
#define ATH9K_NUM_TX_QUEUES
Definition: mac.h:580
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
u16 curtxpow
Definition: ath9k.h:467
struct ath_tx tx
Definition: ath9k.h:476
unsigned int hw_busy_count
Definition: ath9k.h:462
struct ib_cm_common common
Definition: ib_mad.h:11
int ath_startrecv(struct ath_softc *sc)
Definition: ath9k_recv.c:194
void ath_flushrecv(struct ath_softc *sc)
Definition: ath9k_recv.c:242
u16 txpowlimit
Definition: ath9k.h:65
uint8_t ah
Definition: registers.h:85
int ath_stoprecv(struct ath_softc *sc)
Definition: ath9k_recv.c:222
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:54

References ah, ath9k_cmn_update_txpow(), ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_reset(), ath9k_hw_set_interrupts(), ATH9K_NUM_TX_QUEUES, ath_drain_all_txq(), ath_flushrecv(), ath_start_ani(), ath_startrecv(), ath_stoprecv(), ath_txq_schedule(), ATH_TXQ_SETUP, common, ath_softc::config, ath_hw::curchan, ath_softc::curtxpow, DBG, ath_softc::hw_busy_count, r, ath_softc::sc_ah, ath_softc::tx, ath_config::txpowlimit, and ath_tx::txq.

Referenced by ath9k_tasklet(), ath_hw_check(), ath_hw_pll_rx_hang_check(), and ath_tx_complete_poll_work().

◆ ath_read_cachesize()

static void ath_read_cachesize ( struct ath_common common,
int *  csz 
)
inlinestatic

Definition at line 495 of file ath9k.h.

496 {
497  common->bus_ops->read_cachesize(common, csz);
498 }
struct ib_cm_common common
Definition: ib_mad.h:11

References common.

Referenced by ath9k_init_softc().

◆ ath_isr()

void ath_isr ( struct net80211_device dev)

Definition at line 366 of file ath9k_main.c.

367 {
368 #define SCHED_INTR ( \
369  ATH9K_INT_FATAL | \
370  ATH9K_INT_BB_WATCHDOG | \
371  ATH9K_INT_RXORN | \
372  ATH9K_INT_RXEOL | \
373  ATH9K_INT_RX | \
374  ATH9K_INT_RXLP | \
375  ATH9K_INT_RXHP | \
376  ATH9K_INT_TX | \
377  ATH9K_INT_BMISS | \
378  ATH9K_INT_CST | \
379  ATH9K_INT_TSFOOR | \
380  ATH9K_INT_GENTIMER)
381 
382  struct ath_softc *sc = dev->priv;
383  struct ath_hw *ah = sc->sc_ah;
384  struct ath_common *common = ath9k_hw_common(ah);
385  enum ath9k_int status;
386  unsigned long timestamp = (currticks() * 1000 ) / TICKS_PER_SEC;
387  int sched = 0;
388 
389  /*
390  * The hardware is not ready/present, don't
391  * touch anything. Note this can happen early
392  * on if the IRQ is shared.
393  */
394  if (sc->sc_flags & SC_OP_INVALID)
395  return;
396 
397 
398  /* Check calibration */
399  if(timestamp >= (unsigned int)common->ani.timer && common->ani.timer)
400  ath_ani_calibrate(sc);
401 
402  /* Check tx_complete_work */
403  if(timestamp >= (unsigned int)sc->tx_complete_work_timer && sc->tx_complete_work_timer)
404  sc->tx_complete_work(sc);
405 
406  /* Check hw_pll_work */
407  if(timestamp >= (unsigned int)sc->hw_pll_work_timer && sc->hw_pll_work_timer)
408  sc->hw_pll_work(sc);
409 
410  /* shared irq, not for us */
411 
412  if (!ath9k_hw_intrpend(ah))
413  return;
414 
415  /*
416  * Figure out the reason(s) for the interrupt. Note
417  * that the hal returns a pseudo-ISR that may include
418  * bits we haven't explicitly enabled so we mask the
419  * value to insure we only process bits we requested.
420  */
421  ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
422  status &= ah->imask; /* discard unasked-for bits */
423 
424  /*
425  * If there are no status bits set, then this interrupt was not
426  * for me (should have been caught above).
427  */
428  if (!status)
429  return;
430 
431  /* Cache the status */
432  sc->intrstatus = status;
433 
434  if (status & SCHED_INTR)
435  sched = 1;
436 
437  /*
438  * If a FATAL or RXORN interrupt is received, we have to reset the
439  * chip immediately.
440  */
442  goto chip_reset;
443 
444  if (status & ATH9K_INT_TXURN)
446 
447  if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
448  if (status & ATH9K_INT_TIM_TIMER) {
449  if (sc->ps_idle)
450  goto chip_reset;
451  /* Clear RxAbort bit so that we can
452  * receive frames */
454  ath9k_hw_setrxabort(sc->sc_ah, 0);
456  }
457 
458 chip_reset:
459 
460  if (sched) {
461  /* turn off every interrupt */
463  sc->intr_tq(sc);
464  }
465 
466  return;
467 
468 #undef SCHED_INTR
469 }
static int ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
Definition: hw-ops.h:57
Definition: hw.h:656
int ath9k_hw_setrxabort(struct ath_hw *ah, int set)
Definition: ath9k_mac.c:490
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
unsigned long tx_complete_work_timer
Definition: ath9k.h:485
int ps_idle
Definition: ath9k.h:469
u16 ps_flags
Definition: ath9k.h:466
ath9k_int
Definition: hw.h:251
int ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
Definition: ath9k_main.c:26
uint8_t status
Status.
Definition: ena.h:16
struct net80211_device * dev
Definition: ath9k.h:445
void(* tx_complete_work)(struct ath_softc *sc)
Definition: ath9k.h:484
void ath_ani_calibrate(struct ath_softc *sc)
Definition: ath9k_main.c:200
__be64 timestamp
Definition: CIB_PRM.h:38
struct ath_hw * sc_ah
Definition: ath9k.h:454
#define SCHED_INTR
int ath9k_hw_intrpend(struct ath_hw *ah)
Definition: ath9k_mac.c:583
void(* hw_pll_work)(struct ath_softc *sc)
Definition: ath9k.h:486
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
void * priv
Driver private data.
Definition: net80211.h:798
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel)
ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
Definition: ath9k_mac.c:101
struct ib_cm_common common
Definition: ib_mad.h:11
u32 sc_flags
Definition: ath9k.h:465
#define SC_OP_INVALID
Definition: ath9k.h:362
unsigned long hw_pll_work_timer
Definition: ath9k.h:487
#define PS_WAIT_FOR_BEACON
Definition: ath9k.h:380
u32 intrstatus
Definition: ath9k.h:464
void(* intr_tq)(struct ath_softc *sc)
Definition: ath9k.h:453
uint8_t ah
Definition: registers.h:85
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42

References ah, ATH9K_HW_CAP_AUTOSLEEP, ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_getisr(), ath9k_hw_intrpend(), ath9k_hw_setrxabort(), ath9k_hw_updatetxtriglevel(), ATH9K_INT_FATAL, ATH9K_INT_RXORN, ATH9K_INT_TIM_TIMER, ATH9K_INT_TXURN, ATH9K_PM_AWAKE, ath9k_setpower(), ath_ani_calibrate(), common, currticks(), ath_softc::dev, ath_softc::hw_pll_work, ath_softc::hw_pll_work_timer, ath_softc::intr_tq, ath_softc::intrstatus, net80211_device::priv, ath_softc::ps_flags, ath_softc::ps_idle, PS_WAIT_FOR_BEACON, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, SCHED_INTR, status, TICKS_PER_SEC, timestamp, ath_softc::tx_complete_work, and ath_softc::tx_complete_work_timer.

Referenced by ath9k_poll().

◆ ath9k_init_crypto()

void ath9k_init_crypto ( struct ath_softc sc)

Definition at line 275 of file ath9k_init.c.

276 {
277  struct ath_common *common = ath9k_hw_common(sc->sc_ah);
278  unsigned int i = 0;
279 
280  /* Get the hardware key cache size. */
281  common->keymax = AR_KEYTABLE_SIZE;
282 
283  /*
284  * Reset the key cache since some parts do not
285  * reset the contents on initial power up.
286  */
287  for (i = 0; i < common->keymax; i++)
288  ath_hw_keyreset(common, (u16) i);
289 
290  /*
291  * Check whether the separate key cache entries
292  * are required to handle both tx+rx MIC keys.
293  * With split mic keys the number of stations is limited
294  * to 27 otherwise 59.
295  */
297  common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
298 }
uint16_t u16
Definition: stdint.h:21
int ath_hw_keyreset(struct ath_common *common, u16 entry)
Definition: ath_key.c:41
#define AR_PCU_MIC_NEW_LOC_ENA
Definition: reg.h:1642
#define AR_KEYTABLE_SIZE
Definition: hw.h:148
u32 misc_mode
Definition: hw.h:749
struct ath_hw * sc_ah
Definition: ath9k.h:454
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11

References AR_KEYTABLE_SIZE, AR_PCU_MIC_NEW_LOC_ENA, ath9k_hw_common(), ATH_CRYPT_CAP_MIC_COMBINED, ath_hw_keyreset(), common, ath_hw::misc_mode, and ath_softc::sc_ah.

Referenced by ath9k_init_softc().

◆ ath9k_init_device()

int ath9k_init_device ( u16  devid,
struct ath_softc sc,
u16  subsysid,
const struct ath_bus_ops bus_ops 
)

Definition at line 486 of file ath9k_init.c.

488 {
489  struct net80211_device *dev = sc->dev;
490  /*struct ath_common *common;
491  struct ath_hw *ah;*/
492  int error = 0;
493  /*struct ath_regulatory *reg;*/
494 
495  /* Bring up device */
496  error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
497  if (error != 0)
498  goto error_init;
499 
500  /*ah = sc->sc_ah;
501  common = ath9k_hw_common(ah);*/
502  ath9k_set_hw_capab(sc, dev);
503  /* TODO Cottsay: reg */
504  /* Initialize regulatory */
505  /*error = ath_regd_init(&common->regulatory, sc->dev->wiphy,
506  ath9k_reg_notifier);
507  if (error)
508  goto error_regd;
509 
510  reg = &common->regulatory;*/
511 
512  /* Setup TX DMA */
513  error = ath_tx_init(sc, ATH_TXBUF);
514  if (error != 0)
515  goto error_tx;
516 
517  /* Setup RX DMA */
518  error = ath_rx_init(sc, ATH_RXBUF);
519  if (error != 0)
520  goto error_rx;
521 
523 
524  /* Register with mac80211 */
525  error = net80211_register(dev, &ath9k_ops, sc->hwinfo);
526  if (error)
527  goto error_register;
528 
529  /* TODO Cottsay: reg */
530  /* Handle world regulatory */
531  /*if (!ath_is_world_regd(reg)) {
532  error = regulatory_hint(hw->wiphy, reg->alpha2);
533  if (error)
534  goto error_world;
535  }*/
536 
539 
540  /* TODO Cottsay: rfkill */
541  /*ath_start_rfkill_poll(sc);*/
542 
543  return 0;
544 
545 //error_world:
546 // net80211_unregister(dev);
547 error_register:
548  ath_rx_cleanup(sc);
549 error_rx:
550  ath_tx_cleanup(sc);
551 error_tx:
552  ath9k_deinit_softc(sc);
553 error_init:
554  return error;
555 }
#define ATH_TXBUF
Definition: base.h:53
#define ATH_RXBUF
Definition: base.h:52
struct arbelprm_completion_with_error error
Definition: arbel.h:12
void ath9k_set_hw_capab(struct ath_softc *sc, struct net80211_device *dev __unused)
Definition: ath9k_init.c:467
void ath_tx_cleanup(struct ath_softc *sc)
Definition: ath9k_xmit.c:809
static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, const struct ath_bus_ops *bus_ops)
Definition: ath9k_init.c:356
struct net80211_device * dev
Definition: ath9k.h:445
struct net80211_device_operations ath9k_ops
Definition: ath9k_main.c:909
void(* hw_pll_work)(struct ath_softc *sc)
Definition: ath9k.h:486
int last_rssi
Definition: ath9k.h:482
#define ATH_RSSI_DUMMY_MARKER
Definition: common.h:37
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
struct net80211_hw_info * hwinfo
Definition: ath9k.h:477
void ath_rx_cleanup(struct ath_softc *sc)
Definition: ath9k_recv.c:142
int ath_tx_init(struct ath_softc *sc, int nbufs)
Definition: ath9k_xmit.c:788
void ath_hw_pll_work(struct ath_softc *sc)
Definition: ath9k_main.c:325
static void ath9k_deinit_softc(struct ath_softc *sc)
Definition: ath9k_init.c:561
int ath_rx_init(struct ath_softc *sc, int nbufs)
Definition: ath9k_recv.c:97
int net80211_register(struct net80211_device *dev, struct net80211_device_operations *ops, struct net80211_hw_info *hw)
Register 802.11 device with network stack.
Definition: net80211.c:791
static void ath9k_init_txpower_limits(struct ath_softc *sc)
Definition: ath9k_init.c:454

References ath9k_deinit_softc(), ath9k_init_softc(), ath9k_init_txpower_limits(), ath9k_ops, ath9k_set_hw_capab(), ath_hw_pll_work(), ATH_RSSI_DUMMY_MARKER, ath_rx_cleanup(), ath_rx_init(), ATH_RXBUF, ath_tx_cleanup(), ath_tx_init(), ATH_TXBUF, ath_softc::dev, error, ath_softc::hw_pll_work, ath_softc::hwinfo, ath_softc::last_rssi, and net80211_register().

Referenced by ath_pci_probe().

◆ ath9k_deinit_device()

void ath9k_deinit_device ( struct ath_softc sc)

Definition at line 577 of file ath9k_init.c.

578 {
579  struct net80211_device *dev = sc->dev;
580 
581  net80211_unregister(dev);
582  ath_rx_cleanup(sc);
583  ath_tx_cleanup(sc);
584  ath9k_deinit_softc(sc);
585 }
void net80211_unregister(struct net80211_device *dev)
Unregister 802.11 device from network stack.
Definition: net80211.c:824
void ath_tx_cleanup(struct ath_softc *sc)
Definition: ath9k_xmit.c:809
struct net80211_device * dev
Definition: ath9k.h:445
Structure encapsulating the complete state of an 802.11 device.
Definition: net80211.h:786
void ath_rx_cleanup(struct ath_softc *sc)
Definition: ath9k_recv.c:142
static void ath9k_deinit_softc(struct ath_softc *sc)
Definition: ath9k_init.c:561

References ath9k_deinit_softc(), ath_rx_cleanup(), ath_tx_cleanup(), ath_softc::dev, and net80211_unregister().

Referenced by ath_pci_remove().

◆ ath9k_set_hw_capab()

void ath9k_set_hw_capab ( struct ath_softc sc,
struct net80211_device dev 
)

◆ ath_set_channel()

int ath_set_channel ( struct ath_softc sc,
struct net80211_device dev,
struct ath9k_channel hchan 
)

Definition at line 116 of file ath9k_main.c.

118 {
119  struct ath_hw *ah = sc->sc_ah;
120  struct ath_common *common = ath9k_hw_common(ah);
121  int fastcc __unused = 1, stopped __unused;
122  struct net80211_channel *channel = dev->channels + dev->channel;
123  struct ath9k_hw_cal_data *caldata = NULL;
124  int r;
125 
126  if (sc->sc_flags & SC_OP_INVALID)
127  return -EIO;
128 
129  sc->hw_busy_count = 0;
130 
131  common->ani.timer = 0;
132  sc->tx_complete_work_timer = 0;
133  sc->hw_pll_work_timer = 0;
134 
135  /*
136  * This is only performed if the channel settings have
137  * actually changed.
138  *
139  * To switch channels clear any pending DMA operations;
140  * wait long enough for the RX fifo to drain, reset the
141  * hardware at the new frequency, and then re-enable
142  * the relevant bits of the h/w.
143  */
145  stopped = ath_drain_all_txq(sc, 0);
146 
147  if (!ath_stoprecv(sc))
148  stopped = 0;
149 
150  if (!ath9k_hw_check_alive(ah))
151  stopped = 0;
152 
153  /* XXX: do not flush receive queue here. We don't want
154  * to flush data frames already in queue because of
155  * changing channel. */
156 
157  if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
158  caldata = &sc->caldata;
159 
160  DBG2("ath9k: "
161  "(%d MHz) -> (%d MHz)\n",
162  sc->sc_ah->curchan->channel,
163  channel->center_freq);
164 
165  r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
166  if (r) {
167  DBG("ath9k: "
168  "Unable to reset channel (%d MHz), reset status %d\n",
169  channel->center_freq, r);
170  goto ps_restore;
171  }
172 
173  if (ath_startrecv(sc) != 0) {
174  DBG("ath9k: Unable to restart recv logic\n");
175  r = -EIO;
176  goto ps_restore;
177  }
178 
180  sc->config.txpowlimit, &sc->curtxpow);
181  ath9k_hw_set_interrupts(ah, ah->imask);
182 
183  if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
184  sc->tx_complete_work(sc);
185  sc->hw_pll_work_timer = (currticks() * 1000 ) / TICKS_PER_SEC + 500;
187  }
188 
189  ps_restore:
190  return r;
191 }
u16 channel
Definition: hw.h:349
Definition: hw.h:656
#define TICKS_PER_SEC
Number of ticks per second.
Definition: timer.h:15
unsigned long tx_complete_work_timer
Definition: ath9k.h:485
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
Definition: ath9k_hw.c:1216
struct ath9k_channel * curchan
Definition: hw.h:665
u8 channel
The channel currently in use, as an index into the channels array.
Definition: net80211.h:812
static void ath_start_ani(struct ath_common *common)
Definition: ath9k_main.c:35
void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow, u16 new_txpow, u16 *txpower)
Definition: ath9k_common.c:61
int ath_drain_all_txq(struct ath_softc *sc, int retry_tx)
Definition: ath9k_xmit.c:216
#define SC_OP_OFFCHANNEL
Definition: ath9k.h:366
void(* tx_complete_work)(struct ath_softc *sc)
Definition: ath9k.h:484
struct ath_hw * sc_ah
Definition: ath9k.h:454
struct ath_config config
Definition: ath9k.h:474
void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints)
Definition: ath9k_mac.c:641
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
An 802.11 RF channel.
Definition: net80211.h:385
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
u16 curtxpow
Definition: ath9k.h:467
unsigned int hw_busy_count
Definition: ath9k.h:462
struct ib_cm_common common
Definition: ib_mad.h:11
u32 sc_flags
Definition: ath9k.h:465
#define SC_OP_INVALID
Definition: ath9k.h:362
unsigned long hw_pll_work_timer
Definition: ath9k.h:487
#define __unused
Declare a variable or data structure as unused.
Definition: compiler.h:573
int ath_startrecv(struct ath_softc *sc)
Definition: ath9k_recv.c:194
struct ath9k_hw_cal_data caldata
Definition: ath9k.h:481
#define EIO
Input/output error.
Definition: errno.h:433
struct net80211_channel channels[NET80211_MAX_CHANNELS]
A list of all possible channels we might use.
Definition: net80211.h:806
int ath9k_hw_check_alive(struct ath_hw *ah)
Definition: ath9k_hw.c:1189
u16 txpowlimit
Definition: ath9k.h:65
uint8_t ah
Definition: registers.h:85
int ath_stoprecv(struct ath_softc *sc)
Definition: ath9k_recv.c:222
unsigned long currticks(void)
Get current system time in ticks.
Definition: timer.c:42
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
#define DBG2(...)
Definition: compiler.h:515
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:54

References __unused, ah, ath9k_cmn_update_txpow(), ath9k_hw_check_alive(), ath9k_hw_common(), ath9k_hw_disable_interrupts(), ath9k_hw_reset(), ath9k_hw_set_interrupts(), ath_drain_all_txq(), ath_start_ani(), ath_startrecv(), ath_stoprecv(), ath_softc::caldata, channel, ath9k_channel::channel, net80211_device::channel, net80211_device::channels, common, ath_softc::config, ath_hw::curchan, currticks(), ath_softc::curtxpow, DBG, DBG2, EIO, ath_softc::hw_busy_count, ath_softc::hw_pll_work_timer, NULL, r, ath_softc::sc_ah, ath_softc::sc_flags, SC_OP_INVALID, SC_OP_OFFCHANNEL, TICKS_PER_SEC, ath_softc::tx_complete_work, ath_softc::tx_complete_work_timer, and ath_config::txpowlimit.

Referenced by ath9k_config().

◆ ath_radio_enable()

void ath_radio_enable ( struct ath_softc sc,
struct net80211_device dev 
)

◆ ath_radio_disable()

void ath_radio_disable ( struct ath_softc sc,
struct net80211_device dev 
)

Definition at line 471 of file ath9k_main.c.

472 {
473  struct ath_hw *ah = sc->sc_ah;
474  struct net80211_channel *channel = dev->channels + dev->channel;
475  int r;
476 
477  sc->hw_pll_work_timer = 0;
478 
479  /*
480  * Keep the LED on when the radio is disabled
481  * during idle unassociated state.
482  */
483  if (!sc->ps_idle) {
484  ath9k_hw_set_gpio(ah, ah->led_pin, 1);
485  ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
486  }
487 
488  /* Disable interrupts */
490 
491  ath_drain_all_txq(sc, 0); /* clear pending tx frames */
492 
493  ath_stoprecv(sc); /* turn off frame recv */
494  ath_flushrecv(sc); /* flush recv queue */
495 
496  if (!ah->curchan)
497  ah->curchan = ath9k_cmn_get_curchannel(dev, ah);
498 
499  r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, 0);
500  if (r) {
501  DBG("ath9k: "
502  "Unable to reset channel (%d MHz), reset status %d\n",
503  channel->center_freq, r);
504  }
505 
507 
509 }
Definition: hw.h:656
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, struct ath9k_hw_cal_data *caldata, int bChannelChange)
Definition: ath9k_hw.c:1216
int ps_idle
Definition: ath9k.h:469
u8 channel
The channel currently in use, as an index into the channels array.
Definition: net80211.h:812
static void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
Definition: hw-ops.h:26
int ath_drain_all_txq(struct ath_softc *sc, int retry_tx)
Definition: ath9k_xmit.c:216
struct ath_hw * sc_ah
Definition: ath9k.h:454
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Definition: ath9k_hw.c:1850
uint32_t channel
RNDIS channel.
Definition: netvsc.h:14
struct ath9k_channel * ath9k_cmn_get_curchannel(struct net80211_device *dev, struct ath_hw *ah)
Definition: ath9k_common.c:47
int ath9k_hw_phy_disable(struct ath_hw *ah)
Definition: ath9k_hw.c:1916
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
Definition: ath9k_mac.c:602
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Definition: ath9k_hw.c:1783
An 802.11 RF channel.
Definition: net80211.h:385
unsigned long hw_pll_work_timer
Definition: ath9k.h:487
struct net80211_channel channels[NET80211_MAX_CHANNELS]
A list of all possible channels we might use.
Definition: net80211.h:806
void ath_flushrecv(struct ath_softc *sc)
Definition: ath9k_recv.c:242
uint8_t ah
Definition: registers.h:85
int ath_stoprecv(struct ath_softc *sc)
Definition: ath9k_recv.c:222
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static const uint8_t r[3][4]
MD4 shift amounts.
Definition: md4.c:54

References ah, ath9k_cmn_get_curchannel(), ath9k_hw_cfg_gpio_input(), ath9k_hw_configpcipowersave(), ath9k_hw_disable_interrupts(), ath9k_hw_phy_disable(), ath9k_hw_reset(), ath9k_hw_set_gpio(), ath_drain_all_txq(), ath_flushrecv(), ath_stoprecv(), channel, net80211_device::channel, net80211_device::channels, DBG, ath_softc::hw_pll_work_timer, ath_softc::ps_idle, r, and ath_softc::sc_ah.

Referenced by ath9k_stop().

◆ ath9k_setpower()

int ath9k_setpower ( struct ath_softc sc,
enum ath9k_power_mode  mode 
)

Definition at line 26 of file ath9k_main.c.

27 {
28  int ret;
29 
30  ret = ath9k_hw_setpower(sc->sc_ah, mode);
31 
32  return ret;
33 }
struct ath_hw * sc_ah
Definition: ath9k.h:454
int ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Definition: ath9k_hw.c:1532

References ath9k_hw_setpower(), and ath_softc::sc_ah.

Referenced by ath_isr().

◆ ath9k_uses_beacons()

int ath9k_uses_beacons ( int  type)

◆ ath_txchainmask_reduction()

u8 ath_txchainmask_reduction ( struct ath_softc sc,
u8  chainmask,
u32  rate 
)

Definition at line 409 of file ath9k_xmit.c.

410 {
411  struct ath_hw *ah = sc->sc_ah;
412  struct ath9k_channel *curchan = ah->curchan;
413  if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
414  (curchan->channelFlags & CHANNEL_5GHZ) &&
415  (chainmask == 0x7) && (rate < 0x90))
416  return 0x3;
417  else
418  return chainmask;
419 }
Definition: hw.h:656
u32 channelFlags
Definition: hw.h:350
struct ath_hw * sc_ah
Definition: ath9k.h:454
u32 sc_flags
Definition: ath9k.h:465
#define CHANNEL_5GHZ
Definition: ath5k.h:633
uint8_t ah
Definition: registers.h:85
#define SC_OP_ENABLE_APM
Definition: ath9k.h:376

References ah, CHANNEL_5GHZ, ath9k_channel::channelFlags, ath_softc::sc_ah, ath_softc::sc_flags, and SC_OP_ENABLE_APM.

Referenced by ath_buf_set_rate().

◆ ath_start_rfkill_poll()

void ath_start_rfkill_poll ( struct ath_softc sc)

◆ ath9k_rfkill_poll_state()

void ath9k_rfkill_poll_state ( struct net80211_device dev)

Variable Documentation

◆ __attribute__

◆ ath9k_ops

struct net80211_device_operations ath9k_ops

Definition at line 909 of file ath9k_main.c.

Referenced by ath9k_init_device().

◆ ath9k_modparam_nohwcrypt

int ath9k_modparam_nohwcrypt

◆ is_ath9k_unloaded

int is_ath9k_unloaded

Definition at line 29 of file ath9k_init.c.

Referenced by ath_pci_remove().