iPXE
Macros | Typedefs | Functions | Variables
ath9k_ar9003_eeprom.c File Reference
#include <ipxe/io.h>
#include <ipxe/malloc.h>
#include "hw.h"
#include "ar9003_phy.h"
#include "ar9003_eeprom.h"

Go to the source code of this file.

Macros

#define COMP_HDR_LEN   4
 
#define COMP_CKSUM_LEN   2
 
#define AR_CH0_TOP   (0x00016288)
 
#define AR_CH0_TOP_XPABIASLVL   (0x300)
 
#define AR_CH0_TOP_XPABIASLVL_S   (8)
 
#define AR_CH0_THERM   (0x00016290)
 
#define AR_CH0_THERM_XPABIASLVL_MSB   0x3
 
#define AR_CH0_THERM_XPABIASLVL_MSB_S   0
 
#define AR_CH0_THERM_XPASHORT2GND   0x4
 
#define AR_CH0_THERM_XPASHORT2GND_S   2
 
#define AR_SWITCH_TABLE_COM_ALL   (0xffff)
 
#define AR_SWITCH_TABLE_COM_ALL_S   (0)
 
#define AR_SWITCH_TABLE_COM2_ALL   (0xffffff)
 
#define AR_SWITCH_TABLE_COM2_ALL_S   (0)
 
#define AR_SWITCH_TABLE_ALL   (0xfff)
 
#define AR_SWITCH_TABLE_ALL_S   (0)
 
#define LE16(x)   (uint16_t)(x)
 
#define LE32(x)   (uint32_t)(x)
 
#define EXT_ADDITIVE   (0x8000)
 
#define CTL_11A_EXT   (CTL_11A | EXT_ADDITIVE)
 
#define CTL_11G_EXT   (CTL_11G | EXT_ADDITIVE)
 
#define CTL_11B_EXT   (CTL_11B | EXT_ADDITIVE)
 
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN   6 /* 10*log10(2)*2 */
 
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
 
#define PWRINCR_3_TO_1_CHAIN   9 /* 10*log(3)*2 */
 
#define PWRINCR_3_TO_2_CHAIN   3 /* floor(10*log(3/2)*2) */
 
#define PWRINCR_2_TO_1_CHAIN   6 /* 10*log(2)*2 */
 
#define SUB_NUM_CTL_MODES_AT_5G_40   2 /* excluding HT40, EXT-OFDM */
 
#define SUB_NUM_CTL_MODES_AT_2G_40   3 /* excluding HT40, EXT-OFDM, EXT-CCK */
 
#define CTL(_tpower, _flag)   ((_tpower) | ((_flag) << 6))
 
#define EEPROM_DATA_LEN_9485   1088
 
#define N_LOOP   (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
 
#define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
 
#define MDEFAULT   15
 
#define MSTATE   100
 
#define POW_SM(_r, _s)   (((_r) & 0x3f) << (_s))
 

Typedefs

typedef int(* eeprom_read_op) (struct ath_hw *ah, int address, u8 *buffer, int count)
 

Functions

static int ar9003_hw_power_interpolate (int32_t x, int32_t *px, int32_t *py, uint16_t np)
 
static const struct ar9300_eepromar9003_eeprom_struct_find_by_id (int id)
 
static u16 ath9k_hw_fbin2freq (u8 fbin, int is2GHz)
 
static int ath9k_hw_ar9300_check_eeprom (struct ath_hw *ah __unused)
 
static int interpolate (int x, int xa, int xb, int ya, int yb)
 
static u32 ath9k_hw_ar9300_get_eeprom (struct ath_hw *ah, enum eeprom_param param)
 
static int ar9300_eeprom_read_byte (struct ath_common *common, int address, u8 *buffer)
 
static int ar9300_eeprom_read_word (struct ath_common *common, int address, u8 *buffer)
 
static int ar9300_read_eeprom (struct ath_hw *ah, int address, u8 *buffer, int count)
 
static int ar9300_otp_read_word (struct ath_hw *ah, int addr, u32 *data)
 
static int ar9300_read_otp (struct ath_hw *ah, int address, u8 *buffer, int count)
 
static void ar9300_comp_hdr_unpack (u8 *best, int *code, int *reference, int *length, int *major, int *minor)
 
static u16 ar9300_comp_cksum (u8 *data, int dsize)
 
static int ar9300_uncompress_block (struct ath_hw *ah __unused, u8 *mptr, int mdataSize, u8 *block, int size)
 
static int ar9300_compress_decision (struct ath_hw *ah, int it, int code, int reference, u8 *mptr, u8 *word, int length, int mdata_size)
 
static int ar9300_check_header (void *data)
 
static int ar9300_check_eeprom_header (struct ath_hw *ah, eeprom_read_op read, int base_addr)
 
static int ar9300_eeprom_restore_flash (struct ath_hw *ah, u8 *mptr, int mdata_size)
 
static int ar9300_eeprom_restore_internal (struct ath_hw *ah, u8 *mptr, int mdata_size)
 
static int ath9k_hw_ar9300_fill_eeprom (struct ath_hw *ah)
 
static int ath9k_hw_ar9300_get_eeprom_ver (struct ath_hw *ah)
 
static int ath9k_hw_ar9300_get_eeprom_rev (struct ath_hw *ah __unused)
 
static s32 ar9003_hw_xpa_bias_level_get (struct ath_hw *ah, int is2ghz)
 
static void ar9003_hw_xpa_bias_level_apply (struct ath_hw *ah, int is2ghz)
 
static u32 ar9003_hw_ant_ctrl_common_get (struct ath_hw *ah, int is2ghz)
 
static u32 ar9003_hw_ant_ctrl_common_2_get (struct ath_hw *ah, int is2ghz)
 
static u16 ar9003_hw_ant_ctrl_chain_get (struct ath_hw *ah, int chain, int is2ghz)
 
static void ar9003_hw_ant_ctrl_apply (struct ath_hw *ah, int is2ghz)
 
static void ar9003_hw_drive_strength_apply (struct ath_hw *ah)
 
static u16 ar9003_hw_atten_chain_get (struct ath_hw *ah, int chain, struct ath9k_channel *chan)
 
static u16 ar9003_hw_atten_chain_get_margin (struct ath_hw *ah, int chain, struct ath9k_channel *chan)
 
static void ar9003_hw_atten_apply (struct ath_hw *ah, struct ath9k_channel *chan)
 
static int is_pmu_set (struct ath_hw *ah, u32 pmu_reg, int pmu_set)
 
static void ar9003_hw_internal_regulator_apply (struct ath_hw *ah)
 
static void ar9003_hw_apply_tuning_caps (struct ath_hw *ah)
 
static void ath9k_hw_ar9300_set_board_values (struct ath_hw *ah, struct ath9k_channel *chan)
 
static void ath9k_hw_ar9300_set_addac (struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
 
static u8 ar9003_hw_eeprom_get_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
 
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
 
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
 
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr (struct ath_hw *ah, u16 rateIndex, u16 freq)
 
static int ar9003_hw_tx_power_regwrite (struct ath_hw *ah, u8 *pPwrArray)
 
static void ar9003_hw_set_target_power_eeprom (struct ath_hw *ah, u16 freq, u8 *targetPowerValT2)
 
static int ar9003_hw_cal_pier_get (struct ath_hw *ah, int mode, int ipier, int ichain, int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage)
 
static int ar9003_hw_power_control_override (struct ath_hw *ah, int frequency, int *correction, int *voltage __unused, int *temperature)
 
static int ar9003_hw_calibration_apply (struct ath_hw *ah, int frequency)
 
static u16 ar9003_hw_get_direct_edge_power (struct ar9300_eeprom *eep, int idx, int edge, int is2GHz)
 
static u16 ar9003_hw_get_indirect_edge_power (struct ar9300_eeprom *eep, int idx, unsigned int edge, u16 freq, int is2GHz)
 
static u16 ar9003_hw_get_max_edge_power (struct ar9300_eeprom *eep, u16 freq, int idx, int is2GHz)
 
static void ar9003_hw_set_power_per_rate_table (struct ath_hw *ah, struct ath9k_channel *chan, u8 *pPwrArray, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u16 powerLimit)
 
static u8 mcsidx_to_tgtpwridx (unsigned int mcs_idx, u8 base_pwridx)
 
static void ath9k_hw_ar9300_set_txpower (struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)
 
static u16 ath9k_hw_ar9300_get_spur_channel (struct ath_hw *ah __unused, u16 i __unused, int is2GHz __unused)
 
s32 ar9003_hw_get_tx_gain_idx (struct ath_hw *ah)
 
s32 ar9003_hw_get_rx_gain_idx (struct ath_hw *ah)
 
u8ar9003_get_spur_chan_ptr (struct ath_hw *ah, int is_2ghz)
 
unsigned int ar9003_get_paprd_scale_factor (struct ath_hw *ah, struct ath9k_channel *chan)
 

Variables

static const struct ar9300_eeprom ar9300_default
 
static const struct ar9300_eeprom ar9300_x113
 
static const struct ar9300_eeprom ar9300_h112
 
static const struct ar9300_eeprom ar9300_x112
 
static const struct ar9300_eeprom ar9300_h116
 
static const struct ar9300_eepromar9300_eep_templates []
 
const struct eeprom_ops eep_ar9300_ops
 

Macro Definition Documentation

◆ COMP_HDR_LEN

#define COMP_HDR_LEN   4

Definition at line 27 of file ath9k_ar9003_eeprom.c.

◆ COMP_CKSUM_LEN

#define COMP_CKSUM_LEN   2

Definition at line 28 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_TOP

#define AR_CH0_TOP   (0x00016288)

Definition at line 30 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_TOP_XPABIASLVL

#define AR_CH0_TOP_XPABIASLVL   (0x300)

Definition at line 31 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_TOP_XPABIASLVL_S

#define AR_CH0_TOP_XPABIASLVL_S   (8)

Definition at line 32 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_THERM

#define AR_CH0_THERM   (0x00016290)

Definition at line 34 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_THERM_XPABIASLVL_MSB

#define AR_CH0_THERM_XPABIASLVL_MSB   0x3

Definition at line 35 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_THERM_XPABIASLVL_MSB_S

#define AR_CH0_THERM_XPABIASLVL_MSB_S   0

Definition at line 36 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_THERM_XPASHORT2GND

#define AR_CH0_THERM_XPASHORT2GND   0x4

Definition at line 37 of file ath9k_ar9003_eeprom.c.

◆ AR_CH0_THERM_XPASHORT2GND_S

#define AR_CH0_THERM_XPASHORT2GND_S   2

Definition at line 38 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_COM_ALL

#define AR_SWITCH_TABLE_COM_ALL   (0xffff)

Definition at line 40 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_COM_ALL_S

#define AR_SWITCH_TABLE_COM_ALL_S   (0)

Definition at line 41 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_COM2_ALL

#define AR_SWITCH_TABLE_COM2_ALL   (0xffffff)

Definition at line 43 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_COM2_ALL_S

#define AR_SWITCH_TABLE_COM2_ALL_S   (0)

Definition at line 44 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_ALL

#define AR_SWITCH_TABLE_ALL   (0xfff)

Definition at line 46 of file ath9k_ar9003_eeprom.c.

◆ AR_SWITCH_TABLE_ALL_S

#define AR_SWITCH_TABLE_ALL_S   (0)

Definition at line 47 of file ath9k_ar9003_eeprom.c.

◆ LE16

#define LE16 (   x)    (uint16_t)(x)

Definition at line 49 of file ath9k_ar9003_eeprom.c.

◆ LE32

#define LE32 (   x)    (uint32_t)(x)

Definition at line 50 of file ath9k_ar9003_eeprom.c.

◆ EXT_ADDITIVE

#define EXT_ADDITIVE   (0x8000)

Definition at line 53 of file ath9k_ar9003_eeprom.c.

◆ CTL_11A_EXT

#define CTL_11A_EXT   (CTL_11A | EXT_ADDITIVE)

Definition at line 54 of file ath9k_ar9003_eeprom.c.

◆ CTL_11G_EXT

#define CTL_11G_EXT   (CTL_11G | EXT_ADDITIVE)

Definition at line 55 of file ath9k_ar9003_eeprom.c.

◆ CTL_11B_EXT

#define CTL_11B_EXT   (CTL_11B | EXT_ADDITIVE)

Definition at line 56 of file ath9k_ar9003_eeprom.c.

◆ REDUCE_SCALED_POWER_BY_TWO_CHAIN

#define REDUCE_SCALED_POWER_BY_TWO_CHAIN   6 /* 10*log10(2)*2 */

Definition at line 57 of file ath9k_ar9003_eeprom.c.

◆ REDUCE_SCALED_POWER_BY_THREE_CHAIN

#define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */

Definition at line 58 of file ath9k_ar9003_eeprom.c.

◆ PWRINCR_3_TO_1_CHAIN

#define PWRINCR_3_TO_1_CHAIN   9 /* 10*log(3)*2 */

Definition at line 59 of file ath9k_ar9003_eeprom.c.

◆ PWRINCR_3_TO_2_CHAIN

#define PWRINCR_3_TO_2_CHAIN   3 /* floor(10*log(3/2)*2) */

Definition at line 60 of file ath9k_ar9003_eeprom.c.

◆ PWRINCR_2_TO_1_CHAIN

#define PWRINCR_2_TO_1_CHAIN   6 /* 10*log(2)*2 */

Definition at line 61 of file ath9k_ar9003_eeprom.c.

◆ SUB_NUM_CTL_MODES_AT_5G_40

#define SUB_NUM_CTL_MODES_AT_5G_40   2 /* excluding HT40, EXT-OFDM */

Definition at line 63 of file ath9k_ar9003_eeprom.c.

◆ SUB_NUM_CTL_MODES_AT_2G_40

#define SUB_NUM_CTL_MODES_AT_2G_40   3 /* excluding HT40, EXT-OFDM, EXT-CCK */

Definition at line 64 of file ath9k_ar9003_eeprom.c.

◆ CTL

#define CTL (   _tpower,
  _flag 
)    ((_tpower) | ((_flag) << 6))

Definition at line 66 of file ath9k_ar9003_eeprom.c.

◆ EEPROM_DATA_LEN_9485

#define EEPROM_DATA_LEN_9485   1088

Definition at line 68 of file ath9k_ar9003_eeprom.c.

◆ N_LOOP

#define N_LOOP   (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))

◆ AR9300_EEP_BASE_DRIV_STRENGTH

#define AR9300_EEP_BASE_DRIV_STRENGTH   0x1

◆ MDEFAULT

#define MDEFAULT   15

◆ MSTATE

#define MSTATE   100

◆ POW_SM

#define POW_SM (   _r,
  _s 
)    (((_r) & 0x3f) << (_s))

Typedef Documentation

◆ eeprom_read_op

typedef int(* eeprom_read_op) (struct ath_hw *ah, int address, u8 *buffer, int count)

Definition at line 3265 of file ath9k_ar9003_eeprom.c.

Function Documentation

◆ ar9003_hw_power_interpolate()

static int ar9003_hw_power_interpolate ( int32_t  x,
int32_t px,
int32_t py,
uint16_t  np 
)
static

Definition at line 3821 of file ath9k_ar9003_eeprom.c.

3823 {
3824  int ip = 0;
3825  int lx = 0, ly = 0, lhave = 0;
3826  int hx = 0, hy = 0, hhave = 0;
3827  int dx = 0;
3828  int y = 0;
3829 
3830  lhave = 0;
3831  hhave = 0;
3832 
3833  /* identify best lower and higher x calibration measurement */
3834  for (ip = 0; ip < np; ip++) {
3835  dx = x - px[ip];
3836 
3837  /* this measurement is higher than our desired x */
3838  if (dx <= 0) {
3839  if (!hhave || dx > (x - hx)) {
3840  /* new best higher x measurement */
3841  hx = px[ip];
3842  hy = py[ip];
3843  hhave = 1;
3844  }
3845  }
3846  /* this measurement is lower than our desired x */
3847  if (dx >= 0) {
3848  if (!lhave || dx < (x - lx)) {
3849  /* new best lower x measurement */
3850  lx = px[ip];
3851  ly = py[ip];
3852  lhave = 1;
3853  }
3854  }
3855  }
3856 
3857  /* the low x is good */
3858  if (lhave) {
3859  /* so is the high x */
3860  if (hhave) {
3861  /* they're the same, so just pick one */
3862  if (hx == lx)
3863  y = ly;
3864  else /* interpolate */
3865  y = interpolate(x, lx, hx, ly, hy);
3866  } else /* only low is good, use it */
3867  y = ly;
3868  } else if (hhave) /* only high is good, use it */
3869  y = hy;
3870  else /* nothing is good,this should never happen unless np=0, ???? */
3871  y = -(1 << 30);
3872  return y;
3873 }
static int interpolate(int x, int xa, int xb, int ya, int yb)
uint16_t dx
Definition: registers.h:43
IP4_t ip
Destination IP address.
Definition: pxe_api.h:58

References dx, interpolate(), and ip.

Referenced by ar9003_hw_atten_chain_get(), ar9003_hw_atten_chain_get_margin(), ar9003_hw_eeprom_get_cck_tgt_pwr(), ar9003_hw_eeprom_get_ht20_tgt_pwr(), ar9003_hw_eeprom_get_ht40_tgt_pwr(), ar9003_hw_eeprom_get_tgt_pwr(), and ar9003_hw_power_control_override().

◆ ar9003_eeprom_struct_find_by_id()

static const struct ar9300_eeprom* ar9003_eeprom_struct_find_by_id ( int  id)
static

Definition at line 2971 of file ath9k_ar9003_eeprom.c.

2972 {
2973 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2974  unsigned int it;
2975 
2976  for (it = 0; it < N_LOOP; it++)
2977  if (ar9300_eep_templates[it]->templateVersion == id)
2978  return ar9300_eep_templates[it];
2979  return NULL;
2980 #undef N_LOOP
2981 }
#define N_LOOP
u8 templateVersion
Definition: ar9003_eeprom.h:25
static const struct ar9300_eeprom * ar9300_eep_templates[]
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362

References ar9300_eep_templates, N_LOOP, NULL, and templateVersion.

Referenced by ar9300_compress_decision().

◆ ath9k_hw_fbin2freq()

static u16 ath9k_hw_fbin2freq ( u8  fbin,
int  is2GHz 
)
static

Definition at line 2984 of file ath9k_ar9003_eeprom.c.

2985 {
2986  if (fbin == AR5416_BCHAN_UNUSED)
2987  return fbin;
2988 
2989  return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2990 }
uint16_t u16
Definition: stdint.h:21
#define AR5416_BCHAN_UNUSED
Definition: eeprom.h:157

References AR5416_BCHAN_UNUSED.

Referenced by ar9003_hw_get_indirect_edge_power(), and ar9003_hw_get_max_edge_power().

◆ ath9k_hw_ar9300_check_eeprom()

static int ath9k_hw_ar9300_check_eeprom ( struct ath_hw *ah  __unused)
static

Definition at line 2992 of file ath9k_ar9003_eeprom.c.

2993 {
2994  return 0;
2995 }

◆ interpolate()

static int interpolate ( int  x,
int  xa,
int  xb,
int  ya,
int  yb 
)
static

Definition at line 2997 of file ath9k_ar9003_eeprom.c.

2998 {
2999  int bf, factor, plus;
3000 
3001  bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
3002  factor = bf / 2;
3003  plus = bf % 2;
3004  return ya + factor + plus;
3005 }

Referenced by ar9003_hw_calibration_apply(), and ar9003_hw_power_interpolate().

◆ ath9k_hw_ar9300_get_eeprom()

static u32 ath9k_hw_ar9300_get_eeprom ( struct ath_hw ah,
enum eeprom_param  param 
)
static

Definition at line 3007 of file ath9k_ar9003_eeprom.c.

3009 {
3010  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3011  struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3012 
3013  switch (param) {
3014  case EEP_MAC_LSW:
3015  return eep->macAddr[0] << 8 | eep->macAddr[1];
3016  case EEP_MAC_MID:
3017  return eep->macAddr[2] << 8 | eep->macAddr[3];
3018  case EEP_MAC_MSW:
3019  return eep->macAddr[4] << 8 | eep->macAddr[5];
3020  case EEP_REG_0:
3021  return (uint16_t)(pBase->regDmn[0]);
3022  case EEP_REG_1:
3023  return (uint16_t)(pBase->regDmn[1]);
3024  case EEP_OP_CAP:
3025  return pBase->deviceCap;
3026  case EEP_OP_MODE:
3027  return pBase->opCapFlags.opFlags;
3028  case EEP_RF_SILENT:
3029  return pBase->rfSilent;
3030  case EEP_TX_MASK:
3031  return (pBase->txrxMask >> 4) & 0xf;
3032  case EEP_RX_MASK:
3033  return pBase->txrxMask & 0xf;
3034  case EEP_DRIVE_STRENGTH:
3035 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3038  /* Bit 4 is internal regulator flag */
3039  return (pBase->featureEnable & 0x10) >> 4;
3040  case EEP_SWREG:
3041  return (uint32_t)(pBase->swreg);
3042  case EEP_PAPRD:
3043  return !!(pBase->featureEnable & BIT(5));
3044  case EEP_CHAIN_MASK_REDUCE:
3045  return (pBase->miscConfiguration >> 0x3) & 0x1;
3046  case EEP_ANT_DIV_CTL1:
3047  return (uint32_t)(eep->base_ext1.ant_div_control);
3048  default:
3049  return 0;
3050  }
3051 }
unsigned short uint16_t
Definition: stdint.h:11
struct eepFlags opCapFlags
#define AR9300_EEP_BASE_DRIV_STRENGTH
struct hv_monitor_parameter param[4][32]
Parameters.
Definition: hyperv.h:24
struct ar9300_BaseExtension_1 base_ext1
unsigned int uint32_t
Definition: stdint.h:12
#define BIT(nr)
Definition: ath.h:32
struct ar9300_base_eep_hdr baseEepHeader
uint8_t ah
Definition: registers.h:85

References ah, ar9300_BaseExtension_1::ant_div_control, AR9300_EEP_BASE_DRIV_STRENGTH, ar9300_eeprom::base_ext1, ar9300_eeprom::baseEepHeader, BIT, ar9300_base_eep_hdr::deviceCap, EEP_ANT_DIV_CTL1, EEP_CHAIN_MASK_REDUCE, EEP_DRIVE_STRENGTH, EEP_INTERNAL_REGULATOR, EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW, EEP_OP_CAP, EEP_OP_MODE, EEP_PAPRD, EEP_REG_0, EEP_REG_1, EEP_RF_SILENT, EEP_RX_MASK, EEP_SWREG, EEP_TX_MASK, ar9300_base_eep_hdr::featureEnable, ar9300_eeprom::macAddr, ar9300_base_eep_hdr::miscConfiguration, ar9300_base_eep_hdr::opCapFlags, eepFlags::opFlags, param, ar9300_base_eep_hdr::regDmn, ar9300_base_eep_hdr::rfSilent, ar9300_base_eep_hdr::swreg, and ar9300_base_eep_hdr::txrxMask.

Referenced by ar9003_hw_ant_ctrl_apply(), ar9003_hw_drive_strength_apply(), and ar9003_hw_internal_regulator_apply().

◆ ar9300_eeprom_read_byte()

static int ar9300_eeprom_read_byte ( struct ath_common common,
int  address,
u8 buffer 
)
static

Definition at line 3053 of file ath9k_ar9003_eeprom.c.

3055 {
3056  u16 val;
3057 
3058  if (!ath9k_hw_nvram_read(common, address / 2, &val))
3059  return 0;
3060 
3061  *buffer = (val >> (8 * (address % 2))) & 0xff;
3062  return 1;
3063 }
uint16_t u16
Definition: stdint.h:21
uint64_t address
Base address.
Definition: ena.h:24
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
struct ib_cm_common common
Definition: ib_mad.h:11
void __asmcall int val
Definition: setjmp.h:28

References address, ath9k_hw_nvram_read(), buffer, common, and val.

Referenced by ar9300_read_eeprom().

◆ ar9300_eeprom_read_word()

static int ar9300_eeprom_read_word ( struct ath_common common,
int  address,
u8 buffer 
)
static

Definition at line 3065 of file ath9k_ar9003_eeprom.c.

3067 {
3068  u16 val;
3069 
3070  if (!ath9k_hw_nvram_read(common, address / 2, &val))
3071  return 0;
3072 
3073  buffer[0] = val >> 8;
3074  buffer[1] = val & 0xff;
3075 
3076  return 1;
3077 }
uint16_t u16
Definition: stdint.h:21
uint64_t address
Base address.
Definition: ena.h:24
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
struct ib_cm_common common
Definition: ib_mad.h:11
void __asmcall int val
Definition: setjmp.h:28

References address, ath9k_hw_nvram_read(), buffer, common, and val.

Referenced by ar9300_read_eeprom().

◆ ar9300_read_eeprom()

static int ar9300_read_eeprom ( struct ath_hw ah,
int  address,
u8 buffer,
int  count 
)
static

Definition at line 3079 of file ath9k_ar9003_eeprom.c.

3081 {
3082  struct ath_common *common = ath9k_hw_common(ah);
3083  int i;
3084 
3085  if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3086  DBG("ath9k: "
3087  "eeprom address not in range\n");
3088  return 0;
3089  }
3090 
3091  /*
3092  * Since we're reading the bytes in reverse order from a little-endian
3093  * word stream, an even address means we only use the lower half of
3094  * the 16-bit word at that address
3095  */
3096  if (address % 2 == 0) {
3098  goto error;
3099 
3100  count--;
3101  }
3102 
3103  for (i = 0; i < count / 2; i++) {
3105  goto error;
3106 
3107  address -= 2;
3108  buffer += 2;
3109  }
3110 
3111  if (count % 2)
3113  goto error;
3114 
3115  return 1;
3116 
3117 error:
3118  DBG("ath9k: "
3119  "unable to read eeprom region at offset %d\n", address);
3120  return 0;
3121 }
#define AR9300_EEPROM_SIZE
Definition: ar9003_eeprom.h:69
uint64_t address
Base address.
Definition: ena.h:24
struct arbelprm_completion_with_error error
Definition: arbel.h:12
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
static int ar9300_eeprom_read_byte(struct ath_common *common, int address, u8 *buffer)
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
uint16_t count
Number of entries.
Definition: ena.h:22
uint8_t ah
Definition: registers.h:85
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
static int ar9300_eeprom_read_word(struct ath_common *common, int address, u8 *buffer)

References address, ah, ar9300_eeprom_read_byte(), ar9300_eeprom_read_word(), AR9300_EEPROM_SIZE, ath9k_hw_common(), buffer, common, count, DBG, and error.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_otp_read_word()

static int ar9300_otp_read_word ( struct ath_hw ah,
int  addr,
u32 data 
)
static

Definition at line 3123 of file ath9k_ar9003_eeprom.c.

3124 {
3125  REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3126 
3128  AR9300_OTP_STATUS_VALID, 1000))
3129  return 0;
3130 
3132  return 1;
3133 }
#define AR9300_OTP_STATUS_VALID
Definition: ar9003_eeprom.h:78
#define AR9300_OTP_STATUS_TYPE
Definition: ar9003_eeprom.h:77
#define AR9300_OTP_STATUS
Definition: ar9003_eeprom.h:76
#define AR9300_OTP_READ_DATA
Definition: ar9003_eeprom.h:81
#define AR9300_OTP_BASE
Definition: ar9003_eeprom.h:75
u32 addr
Definition: sky2.h:8
#define REG_READ(_ah, _reg)
Definition: hw.h:80
int ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Definition: ath9k_hw.c:93
uint8_t ah
Definition: registers.h:85
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12

References addr, ah, AR9300_OTP_BASE, AR9300_OTP_READ_DATA, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, AR9300_OTP_STATUS_VALID, ath9k_hw_wait(), data, and REG_READ.

Referenced by ar9300_read_otp().

◆ ar9300_read_otp()

static int ar9300_read_otp ( struct ath_hw ah,
int  address,
u8 buffer,
int  count 
)
static

Definition at line 3135 of file ath9k_ar9003_eeprom.c.

3137 {
3138  u32 data;
3139  int i;
3140 
3141  for (i = 0; i < count; i++) {
3142  int offset = 8 * ((address - i) % 4);
3143  if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3144  return 0;
3145 
3146  buffer[i] = (data >> offset) & 0xff;
3147  }
3148 
3149  return 1;
3150 }
uint64_t address
Base address.
Definition: ena.h:24
uint32_t buffer
Buffer index (or NETVSC_RNDIS_NO_BUFFER)
Definition: netvsc.h:16
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
static int ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
uint16_t count
Number of entries.
Definition: ena.h:22
uint8_t ah
Definition: registers.h:85
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint32_t u32
Definition: stdint.h:23

References address, ah, ar9300_otp_read_word(), buffer, count, data, and offset.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_comp_hdr_unpack()

static void ar9300_comp_hdr_unpack ( u8 best,
int *  code,
int *  reference,
int *  length,
int *  major,
int *  minor 
)
static

Definition at line 3153 of file ath9k_ar9003_eeprom.c.

3155 {
3156  unsigned long value[4];
3157 
3158  value[0] = best[0];
3159  value[1] = best[1];
3160  value[2] = best[2];
3161  value[3] = best[3];
3162  *code = ((value[0] >> 5) & 0x0007);
3163  *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3164  *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3165  *major = (value[2] & 0x000f);
3166  *minor = (value[3] & 0x00ff);
3167 }
uint16_t length
Length.
Definition: intel.h:14
uint32_t major
Major version.
Definition: netvsc.h:14
uint32_t minor
Minor version.
Definition: netvsc.h:16
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
uint8_t code
Response code.
Definition: scsi.h:16

References code, length, major, minor, and value.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_comp_cksum()

static u16 ar9300_comp_cksum ( u8 data,
int  dsize 
)
static

Definition at line 3169 of file ath9k_ar9003_eeprom.c.

3170 {
3171  int it, checksum = 0;
3172 
3173  for (it = 0; it < dsize; it++) {
3174  checksum += data[it];
3175  checksum &= 0xffff;
3176  }
3177 
3178  return checksum;
3179 }
uint8_t checksum
Checksum.
Definition: pnpbios.c:37
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12

References checksum, and data.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_uncompress_block()

static int ar9300_uncompress_block ( struct ath_hw *ah  __unused,
u8 mptr,
int  mdataSize,
u8 block,
int  size 
)
static

Definition at line 3181 of file ath9k_ar9003_eeprom.c.

3186 {
3187  int it;
3188  int spot;
3189  int offset;
3190  int length;
3191 
3192  spot = 0;
3193 
3194  for (it = 0; it < size; it += (length+2)) {
3195  offset = block[it];
3196  offset &= 0xff;
3197  spot += offset;
3198  length = block[it+1];
3199  length &= 0xff;
3200 
3201  if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3202  DBG2("ath9k: "
3203  "Restore at %d: spot=%d offset=%d length=%d\n",
3204  it, spot, offset, length);
3205  memcpy(&mptr[spot], &block[it+2], length);
3206  spot += length;
3207  } else if (length > 0) {
3208  DBG("ath9k: "
3209  "Bad restore at %d: spot=%d offset=%d length=%d\n",
3210  it, spot, offset, length);
3211  return 0;
3212  }
3213  }
3214  return 1;
3215 }
uint16_t length
Length.
Definition: intel.h:14
uint16_t block
Definition: tftp.h:12
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static userptr_t size_t offset
Offset of the first segment within the content.
Definition: deflate.h:259
uint8_t size
Entry size (in 32-bit words)
Definition: ena.h:16
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define DBG2(...)
Definition: compiler.h:515

References block, DBG, DBG2, length, memcpy(), offset, and size.

Referenced by ar9300_compress_decision().

◆ ar9300_compress_decision()

static int ar9300_compress_decision ( struct ath_hw ah,
int  it,
int  code,
int  reference,
u8 mptr,
u8 word,
int  length,
int  mdata_size 
)
static

Definition at line 3217 of file ath9k_ar9003_eeprom.c.

3223 {
3224  const struct ar9300_eeprom *eep = NULL;
3225 
3226  switch (code) {
3227  case _CompressNone:
3228  if (length != mdata_size) {
3229  DBG("ath9k: "
3230  "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3231  mdata_size, length);
3232  return -1;
3233  }
3234  memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3235  DBG2("ath9k: "
3236  "restored eeprom %d: uncompressed, length %d\n",
3237  it, length);
3238  break;
3239  case _CompressBlock:
3240  if (reference == 0) {
3241  } else {
3242  eep = ar9003_eeprom_struct_find_by_id(reference);
3243  if (eep == NULL) {
3244  DBG("ath9k: "
3245  "can't find reference eeprom struct %d\n",
3246  reference);
3247  return -1;
3248  }
3249  memcpy(mptr, eep, mdata_size);
3250  }
3251  DBG2("ath9k: "
3252  "restore eeprom %d: block, reference %d, length %d\n",
3253  it, reference, length);
3254  ar9300_uncompress_block(ah, mptr, mdata_size,
3255  (u8 *) (word + COMP_HDR_LEN), length);
3256  break;
3257  default:
3258  DBG("ath9k: "
3259  "unknown compression code %d\n", code);
3260  return -1;
3261  }
3262  return 0;
3263 }
uint16_t length
Length.
Definition: intel.h:14
static const struct ar9300_eeprom * ar9003_eeprom_struct_find_by_id(int id)
void * memcpy(void *dest, const void *src, size_t len) __nonnull
uint8_t code
Response code.
Definition: scsi.h:16
unsigned short word
Definition: smc9000.h:39
uint8_t ah
Definition: registers.h:85
#define COMP_HDR_LEN
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
#define NULL
NULL pointer (VOID *)
Definition: Base.h:362
uint8_t u8
Definition: stdint.h:19
static int ar9300_uncompress_block(struct ath_hw *ah __unused, u8 *mptr, int mdataSize, u8 *block, int size)
#define DBG2(...)
Definition: compiler.h:515

References _CompressBlock, _CompressNone, ah, ar9003_eeprom_struct_find_by_id(), ar9300_uncompress_block(), code, COMP_HDR_LEN, DBG, DBG2, length, memcpy(), and NULL.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_check_header()

static int ar9300_check_header ( void *  data)
static

Definition at line 3268 of file ath9k_ar9003_eeprom.c.

3269 {
3270  u32 *word = data;
3271  return !(*word == 0 || *word == (unsigned int)~0);
3272 }
unsigned short word
Definition: smc9000.h:39
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12
uint32_t u32
Definition: stdint.h:23

References data.

Referenced by ar9300_check_eeprom_header(), and ar9300_eeprom_restore_internal().

◆ ar9300_check_eeprom_header()

static int ar9300_check_eeprom_header ( struct ath_hw ah,
eeprom_read_op  read,
int  base_addr 
)
static

Definition at line 3274 of file ath9k_ar9003_eeprom.c.

3276 {
3277  u8 header[4];
3278 
3279  if (!read(ah, base_addr, header, 4))
3280  return 0;
3281 
3282  return ar9300_check_header(header);
3283 }
device device nvs read
Definition: threewire.h:60
static int ar9300_check_header(void *data)
uint64_t base_addr
Definition: multiboot.h:13
struct ena_aq_header header
Header.
Definition: ena.h:12
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19

References ah, ar9300_check_header(), base_addr, header, and read.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_eeprom_restore_flash()

static int ar9300_eeprom_restore_flash ( struct ath_hw ah,
u8 mptr,
int  mdata_size 
)
static

Definition at line 3285 of file ath9k_ar9003_eeprom.c.

3287 {
3288  struct ath_common *common = ath9k_hw_common(ah);
3289  u16 *data = (u16 *) mptr;
3290  int i;
3291 
3292  for (i = 0; i < mdata_size / 2; i++, data++)
3294 
3295  return 0;
3296 }
uint16_t u16
Definition: stdint.h:21
int ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
Definition: ath9k_eeprom.c:129
static struct ath_common * ath9k_hw_common(struct ath_hw *ah)
Definition: hw.h:869
struct ib_cm_common common
Definition: ib_mad.h:11
uint8_t ah
Definition: registers.h:85
struct arbelprm_port_state_change_st data
Message.
Definition: arbel.h:12

References ah, ath9k_hw_common(), ath9k_hw_nvram_read(), common, and data.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_eeprom_restore_internal()

static int ar9300_eeprom_restore_internal ( struct ath_hw ah,
u8 mptr,
int  mdata_size 
)
static

Definition at line 3304 of file ath9k_ar9003_eeprom.c.

3306 {
3307 #define MDEFAULT 15
3308 #define MSTATE 100
3309  int cptr;
3310  u8 *word;
3311  int code;
3312  int reference, length, major, minor;
3313  int osize;
3314  int it;
3315  u16 checksum, mchecksum;
3317 
3318  if (ath9k_hw_use_flash(ah))
3319  return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3320 
3321  word = zalloc(2048);
3322  if (!word)
3323  return -1;
3324 
3325  memcpy(mptr, &ar9300_default, mdata_size);
3326 
3328  if (AR_SREV_9485(ah))
3329  cptr = AR9300_BASE_ADDR_4K;
3330  else
3331  cptr = AR9300_BASE_ADDR;
3332  DBG2("ath9k: "
3333  "Trying EEPROM access at Address 0x%04x\n", cptr);
3334  if (ar9300_check_eeprom_header(ah, read, cptr))
3335  goto found;
3336 
3337  cptr = AR9300_BASE_ADDR_512;
3338  DBG2("ath9k: "
3339  "Trying EEPROM access at Address 0x%04x\n", cptr);
3340  if (ar9300_check_eeprom_header(ah, read, cptr))
3341  goto found;
3342 
3344  cptr = AR9300_BASE_ADDR;
3345  DBG2("ath9k: "
3346  "Trying OTP access at Address 0x%04x\n", cptr);
3347  if (ar9300_check_eeprom_header(ah, read, cptr))
3348  goto found;
3349 
3350  cptr = AR9300_BASE_ADDR_512;
3351  DBG2("ath9k: "
3352  "Trying OTP access at Address 0x%04x\n", cptr);
3353  if (ar9300_check_eeprom_header(ah, read, cptr))
3354  goto found;
3355 
3356  goto fail;
3357 
3358 found:
3359  DBG2("ath9k: Found valid EEPROM data\n");
3360 
3361  for (it = 0; it < MSTATE; it++) {
3362  if (!read(ah, cptr, word, COMP_HDR_LEN))
3363  goto fail;
3364 
3365  if (!ar9300_check_header(word))
3366  break;
3367 
3368  ar9300_comp_hdr_unpack(word, &code, &reference,
3369  &length, &major, &minor);
3370  DBG2("ath9k: "
3371  "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3372  cptr, code, reference, length, major, minor);
3373  if ((!AR_SREV_9485(ah) && length >= 1024) ||
3375  DBG2("ath9k: "
3376  "Skipping bad header\n");
3377  cptr -= COMP_HDR_LEN;
3378  continue;
3379  }
3380 
3381  osize = length;
3382  read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3384  mchecksum = word[COMP_HDR_LEN + osize] |
3385  (word[COMP_HDR_LEN + osize + 1] << 8);
3386  DBG2("ath9k: "
3387  "checksum %x %x\n", checksum, mchecksum);
3388  if (checksum == mchecksum) {
3389  ar9300_compress_decision(ah, it, code, reference, mptr,
3390  word, length, mdata_size);
3391  } else {
3392  DBG2("ath9k: "
3393  "skipping block with bad checksum\n");
3394  }
3395  cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3396  }
3397 
3398  free(word);
3399  return cptr;
3400 
3401 fail:
3402  free(word);
3403  return -1;
3404 }
uint16_t u16
Definition: stdint.h:21
uint16_t length
Length.
Definition: intel.h:14
#define AR9300_BASE_ADDR
Definition: ar9003_eeprom.h:72
uint8_t checksum
Checksum.
Definition: pnpbios.c:37
static const struct ar9300_eeprom ar9300_default
#define AR_SREV_9485(_ah)
Definition: reg.h:867
static int ar9300_compress_decision(struct ath_hw *ah, int it, int code, int reference, u8 *mptr, u8 *word, int length, int mdata_size)
uint32_t major
Major version.
Definition: netvsc.h:14
uint32_t minor
Minor version.
Definition: netvsc.h:16
void * memcpy(void *dest, const void *src, size_t len) __nonnull
#define AR9300_BASE_ADDR_4K
Definition: ar9003_eeprom.h:71
static int ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, int base_addr)
#define EEPROM_DATA_LEN_9485
#define ath9k_hw_use_flash(_ah)
Definition: eeprom.h:103
static void(* free)(struct refcnt *refcnt))
Definition: refcnt.h:54
device device nvs read
Definition: threewire.h:60
void * zalloc(size_t size)
Allocate cleared memory.
Definition: malloc.c:624
static int ar9300_check_header(void *data)
static int ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, int count)
static int ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, int count)
static u16 ar9300_comp_cksum(u8 *data, int dsize)
#define COMP_CKSUM_LEN
#define AR9300_BASE_ADDR_512
Definition: ar9003_eeprom.h:73
uint8_t code
Response code.
Definition: scsi.h:16
int(* eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer, int count)
unsigned short word
Definition: smc9000.h:39
uint8_t ah
Definition: registers.h:85
#define COMP_HDR_LEN
static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, int mdata_size)
static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference, int *length, int *major, int *minor)
#define MSTATE
uint8_t u8
Definition: stdint.h:19
#define DBG2(...)
Definition: compiler.h:515

References ah, AR9300_BASE_ADDR, AR9300_BASE_ADDR_4K, AR9300_BASE_ADDR_512, ar9300_check_eeprom_header(), ar9300_check_header(), ar9300_comp_cksum(), ar9300_comp_hdr_unpack(), ar9300_compress_decision(), ar9300_default, ar9300_eeprom_restore_flash(), ar9300_read_eeprom(), ar9300_read_otp(), AR_SREV_9485, ath9k_hw_use_flash, checksum, code, COMP_CKSUM_LEN, COMP_HDR_LEN, DBG2, EEPROM_DATA_LEN_9485, free, length, major, memcpy(), minor, MSTATE, read, and zalloc().

Referenced by ath9k_hw_ar9300_fill_eeprom().

◆ ath9k_hw_ar9300_fill_eeprom()

static int ath9k_hw_ar9300_fill_eeprom ( struct ath_hw ah)
static

Definition at line 3411 of file ath9k_ar9003_eeprom.c.

3412 {
3413  u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3414 
3416  sizeof(struct ar9300_eeprom)) < 0)
3417  return 0;
3418 
3419  return 1;
3420 }
static int ar9300_eeprom_restore_internal(struct ath_hw *ah, u8 *mptr, int mdata_size)
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19
if(natsemi->flags &NATSEMI_64BIT) return 1

References ah, ar9300_eeprom_restore_internal(), and if().

◆ ath9k_hw_ar9300_get_eeprom_ver()

static int ath9k_hw_ar9300_get_eeprom_ver ( struct ath_hw ah)
static

Definition at line 3423 of file ath9k_ar9003_eeprom.c.

3424 {
3425  return ah->eeprom.ar9300_eep.eepromVersion;
3426 }
uint8_t ah
Definition: registers.h:85

References ah.

◆ ath9k_hw_ar9300_get_eeprom_rev()

static int ath9k_hw_ar9300_get_eeprom_rev ( struct ath_hw *ah  __unused)
static

Definition at line 3429 of file ath9k_ar9003_eeprom.c.

3430 {
3431  return 0;
3432 }

◆ ar9003_hw_xpa_bias_level_get()

static s32 ar9003_hw_xpa_bias_level_get ( struct ath_hw ah,
int  is2ghz 
)
static

Definition at line 3434 of file ath9k_ar9003_eeprom.c.

3435 {
3436  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3437 
3438  if (is2ghz)
3439  return eep->modalHeader2G.xpaBiasLvl;
3440  else
3441  return eep->modalHeader5G.xpaBiasLvl;
3442 }
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
uint8_t ah
Definition: registers.h:85

References ah, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and ar9300_modal_eep_header::xpaBiasLvl.

Referenced by ar9003_hw_xpa_bias_level_apply().

◆ ar9003_hw_xpa_bias_level_apply()

static void ar9003_hw_xpa_bias_level_apply ( struct ath_hw ah,
int  is2ghz 
)
static

Definition at line 3444 of file ath9k_ar9003_eeprom.c.

3445 {
3446  int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3447 
3448  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3450  else {
3454  bias >> 2);
3457  }
3458 }
#define AR_CH0_THERM_XPASHORT2GND
#define AR_CH0_TOP_XPABIASLVL
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_CH0_TOP2
Definition: ar9003_phy.h:626
#define AR_SREV_9340(_ah)
Definition: reg.h:878
#define AR_CH0_TOP
static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, int is2ghz)
#define AR_CH0_THERM_XPABIASLVL_MSB
#define AR_CH0_TOP2_XPABIASLVL
Definition: ar9003_phy.h:627
uint8_t ah
Definition: registers.h:85
#define AR_CH0_THERM

References ah, ar9003_hw_xpa_bias_level_get(), AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, AR_CH0_THERM_XPASHORT2GND, AR_CH0_TOP, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, AR_CH0_TOP_XPABIASLVL, AR_SREV_9340, AR_SREV_9485, and REG_RMW_FIELD.

Referenced by ath9k_hw_ar9300_set_board_values().

◆ ar9003_hw_ant_ctrl_common_get()

static u32 ar9003_hw_ant_ctrl_common_get ( struct ath_hw ah,
int  is2ghz 
)
static

Definition at line 3460 of file ath9k_ar9003_eeprom.c.

3461 {
3462  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3463  uint32_t val;
3464 
3465  if (is2ghz)
3467  else
3469  return (uint32_t)(val);
3470 }
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
unsigned int uint32_t
Definition: stdint.h:12
void __asmcall int val
Definition: setjmp.h:28
uint8_t ah
Definition: registers.h:85

References ah, ar9300_modal_eep_header::antCtrlCommon, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and val.

Referenced by ar9003_hw_ant_ctrl_apply().

◆ ar9003_hw_ant_ctrl_common_2_get()

static u32 ar9003_hw_ant_ctrl_common_2_get ( struct ath_hw ah,
int  is2ghz 
)
static

Definition at line 3472 of file ath9k_ar9003_eeprom.c.

3473 {
3474  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3475  uint32_t val;
3476 
3477  if (is2ghz)
3479  else
3481  return (uint32_t)(val);
3482 }
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
unsigned int uint32_t
Definition: stdint.h:12
void __asmcall int val
Definition: setjmp.h:28
uint8_t ah
Definition: registers.h:85

References ah, ar9300_modal_eep_header::antCtrlCommon2, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and val.

Referenced by ar9003_hw_ant_ctrl_apply().

◆ ar9003_hw_ant_ctrl_chain_get()

static u16 ar9003_hw_ant_ctrl_chain_get ( struct ath_hw ah,
int  chain,
int  is2ghz 
)
static

Definition at line 3484 of file ath9k_ar9003_eeprom.c.

3487 {
3488  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3489  uint16_t val = 0;
3490 
3491  if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3492  if (is2ghz)
3493  val = eep->modalHeader2G.antCtrlChain[chain];
3494  else
3495  val = eep->modalHeader5G.antCtrlChain[chain];
3496  }
3497 
3498  return (uint16_t)(val);
3499 }
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
unsigned short uint16_t
Definition: stdint.h:11
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
void __asmcall int val
Definition: setjmp.h:28
uint8_t ah
Definition: registers.h:85
uint16_t antCtrlChain[AR9300_MAX_CHAINS]

References ah, ar9300_modal_eep_header::antCtrlChain, AR9300_MAX_CHAINS, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and val.

Referenced by ar9003_hw_ant_ctrl_apply().

◆ ar9003_hw_ant_ctrl_apply()

static void ar9003_hw_ant_ctrl_apply ( struct ath_hw ah,
int  is2ghz 
)
static

Definition at line 3501 of file ath9k_ar9003_eeprom.c.

3502 {
3503  int chain;
3504  u32 regval;
3505  u32 ant_div_ctl1;
3506  static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3510  };
3511 
3513 
3515 
3518 
3519  for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3520  if ((ah->rxchainmask & BIT(chain)) ||
3521  (ah->txchainmask & BIT(chain))) {
3523  is2ghz);
3524  REG_RMW_FIELD(ah, switch_chain_reg[chain],
3526  }
3527  }
3528 
3529  if (AR_SREV_9485(ah)) {
3531  /*
3532  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3533  * are the fields present
3534  */
3535  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3536  regval &= (~AR_ANT_DIV_CTRL_ALL);
3537  regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3538  /* enable_lnadiv */
3539  regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3540  regval |= ((value >> 6) & 0x1) <<
3542  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3543 
3544  /*enable fast_div */
3545  regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3546  regval &= (~AR_FAST_DIV_ENABLE);
3547  regval |= ((value >> 7) & 0x1) <<
3549  REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3550  ant_div_ctl1 =
3551  ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3552  /* check whether antenna diversity is enabled */
3553  if ((ant_div_ctl1 >> 0x6) == 0x3) {
3554  regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3555  /*
3556  * clear bits 25-30 main_lnaconf, alt_lnaconf,
3557  * main_tb, alt_tb
3558  */
3559  regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3563  /* by default use LNA1 for the main antenna */
3564  regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3566  regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3568  REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3569  }
3570 
3571 
3572  }
3573 
3574 }
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF
Definition: ar9003_phy.h:280
#define AR_SWITCH_TABLE_COM2_ALL
#define AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S
Definition: ar9003_phy.h:281
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define AR_SWITCH_TABLE_ALL
#define AR_PHY_SWITCH_CHAIN_1
Definition: ar9003_phy.h:840
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_PHY_SWITCH_COM
Definition: ar9002_phy.h:252
#define AR_PHY_SWITCH_COM_2
Definition: ar9003_phy.h:446
#define AR_PHY_9485_ANT_DIV_LNA2
Definition: ar9003_phy.h:288
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define AR_PHY_9485_ANT_DIV_LNA1
Definition: ar9003_phy.h:289
#define AR_PHY_9485_ANT_DIV_ALT_GAINTB
Definition: ar9003_phy.h:282
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
#define AR_FAST_DIV_ENABLE
Definition: ar9003_phy.h:304
#define AR_PHY_CCK_DETECT
Definition: ar9002_phy.h:413
#define REG_READ(_ah, _reg)
Definition: hw.h:80
static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, int is2ghz)
#define AR_ANT_DIV_CTRL_ALL
Definition: ar9003_phy.h:268
static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, int is2ghz)
#define BIT(nr)
Definition: ath.h:32
#define AR_PHY_9485_ANT_DIV_LNADIV
Definition: ar9003_phy.h:276
#define AR_PHY_SWITCH_CHAIN_2
Definition: ar9003_phy.h:893
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
#define AR_PHY_SWITCH_CHAIN_0
Definition: ar9002_phy.h:251
#define AR_PHY_MC_GAIN_CTRL
Definition: ar9003_phy.h:267
#define AR_PHY_9485_ANT_DIV_LNADIV_S
Definition: ar9003_phy.h:277
#define AR_ANT_DIV_CTRL_ALL_S
Definition: ar9003_phy.h:269
#define AR_SWITCH_TABLE_COM_ALL
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF
Definition: ar9003_phy.h:278
#define AR_PHY_9485_ANT_DIV_ALT_LNACONF_S
Definition: ar9003_phy.h:279
#define AR_FAST_DIV_ENABLE_S
Definition: ar9003_phy.h:305
uint32_t u32
Definition: stdint.h:23
static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, int is2ghz)
#define AR_PHY_9485_ANT_DIV_MAIN_GAINTB
Definition: ar9003_phy.h:284

References ah, ar9003_hw_ant_ctrl_chain_get(), ar9003_hw_ant_ctrl_common_2_get(), ar9003_hw_ant_ctrl_common_get(), AR9300_MAX_CHAINS, AR_ANT_DIV_CTRL_ALL, AR_ANT_DIV_CTRL_ALL_S, AR_FAST_DIV_ENABLE, AR_FAST_DIV_ENABLE_S, AR_PHY_9485_ANT_DIV_ALT_GAINTB, AR_PHY_9485_ANT_DIV_ALT_LNACONF, AR_PHY_9485_ANT_DIV_ALT_LNACONF_S, AR_PHY_9485_ANT_DIV_LNA1, AR_PHY_9485_ANT_DIV_LNA2, AR_PHY_9485_ANT_DIV_LNADIV, AR_PHY_9485_ANT_DIV_LNADIV_S, AR_PHY_9485_ANT_DIV_MAIN_GAINTB, AR_PHY_9485_ANT_DIV_MAIN_LNACONF, AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S, AR_PHY_CCK_DETECT, AR_PHY_MC_GAIN_CTRL, AR_PHY_SWITCH_CHAIN_0, AR_PHY_SWITCH_CHAIN_1, AR_PHY_SWITCH_CHAIN_2, AR_PHY_SWITCH_COM, AR_PHY_SWITCH_COM_2, AR_SREV_9485, AR_SWITCH_TABLE_ALL, AR_SWITCH_TABLE_COM2_ALL, AR_SWITCH_TABLE_COM_ALL, ath9k_hw_ar9300_get_eeprom(), BIT, EEP_ANT_DIV_CTL1, REG_READ, REG_RMW_FIELD, REG_WRITE, and value.

Referenced by ath9k_hw_ar9300_set_board_values().

◆ ar9003_hw_drive_strength_apply()

static void ar9003_hw_drive_strength_apply ( struct ath_hw ah)
static

Definition at line 3576 of file ath9k_ar9003_eeprom.c.

3577 {
3578  int drive_strength;
3579  unsigned long reg;
3580 
3582 
3583  if (!drive_strength)
3584  return;
3585 
3587  reg &= ~0x00ffffc0;
3588  reg |= 0x5 << 21;
3589  reg |= 0x5 << 18;
3590  reg |= 0x5 << 15;
3591  reg |= 0x5 << 12;
3592  reg |= 0x5 << 9;
3593  reg |= 0x5 << 6;
3595 
3597  reg &= ~0xffffffe0;
3598  reg |= 0x5 << 29;
3599  reg |= 0x5 << 26;
3600  reg |= 0x5 << 23;
3601  reg |= 0x5 << 20;
3602  reg |= 0x5 << 17;
3603  reg |= 0x5 << 14;
3604  reg |= 0x5 << 11;
3605  reg |= 0x5 << 8;
3606  reg |= 0x5 << 5;
3608 
3610  reg &= ~0xff800000;
3611  reg |= 0x5 << 29;
3612  reg |= 0x5 << 26;
3613  reg |= 0x5 << 23;
3615 }
#define AR_PHY_65NM_CH0_BIAS2
Definition: ar9003_phy.h:607
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
static unsigned int unsigned int reg
Definition: intel.h:245
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define AR_PHY_65NM_CH0_BIAS1
Definition: ar9003_phy.h:606
uint8_t ah
Definition: registers.h:85
#define AR_PHY_65NM_CH0_BIAS4
Definition: ar9003_phy.h:608

References ah, AR_PHY_65NM_CH0_BIAS1, AR_PHY_65NM_CH0_BIAS2, AR_PHY_65NM_CH0_BIAS4, ath9k_hw_ar9300_get_eeprom(), EEP_DRIVE_STRENGTH, reg, REG_READ, and REG_WRITE.

Referenced by ath9k_hw_ar9300_set_board_values().

◆ ar9003_hw_atten_chain_get()

static u16 ar9003_hw_atten_chain_get ( struct ath_hw ah,
int  chain,
struct ath9k_channel chan 
)
static

Definition at line 3617 of file ath9k_ar9003_eeprom.c.

3619 {
3620  int f[3], t[3];
3621  u16 value;
3622  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3623 
3624  if (chain >= 0 && chain < 3) {
3625  if (IS_CHAN_2GHZ(chan))
3626  return eep->modalHeader2G.xatten1DB[chain];
3627  else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3628  t[0] = eep->base_ext2.xatten1DBLow[chain];
3629  f[0] = 5180;
3630  t[1] = eep->modalHeader5G.xatten1DB[chain];
3631  f[1] = 5500;
3632  t[2] = eep->base_ext2.xatten1DBHigh[chain];
3633  f[2] = 5785;
3635  f, t, 3);
3636  return value;
3637  } else
3638  return eep->modalHeader5G.xatten1DB[chain];
3639  }
3640 
3641  return 0;
3642 }
uint16_t u16
Definition: stdint.h:21
u16 channel
Definition: hw.h:349
int32_t s32
Definition: stdint.h:22
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
u8 xatten1DBLow[AR9300_MAX_CHAINS]
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
u8 xatten1DBHigh[AR9300_MAX_CHAINS]
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
struct ar9300_BaseExtension_2 base_ext2
u8 xatten1DB[AR9300_MAX_CHAINS]
uint8_t ah
Definition: registers.h:85

References ah, ar9003_hw_power_interpolate(), ar9300_eeprom::base_ext2, ath9k_channel::channel, IS_CHAN_2GHZ, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, value, ar9300_modal_eep_header::xatten1DB, ar9300_BaseExtension_2::xatten1DBHigh, and ar9300_BaseExtension_2::xatten1DBLow.

Referenced by ar9003_hw_atten_apply().

◆ ar9003_hw_atten_chain_get_margin()

static u16 ar9003_hw_atten_chain_get_margin ( struct ath_hw ah,
int  chain,
struct ath9k_channel chan 
)
static

Definition at line 3645 of file ath9k_ar9003_eeprom.c.

3647 {
3648  int f[3], t[3];
3649  u16 value;
3650  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3651 
3652  if (chain >= 0 && chain < 3) {
3653  if (IS_CHAN_2GHZ(chan))
3654  return eep->modalHeader2G.xatten1Margin[chain];
3655  else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3656  t[0] = eep->base_ext2.xatten1MarginLow[chain];
3657  f[0] = 5180;
3658  t[1] = eep->modalHeader5G.xatten1Margin[chain];
3659  f[1] = 5500;
3660  t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3661  f[2] = 5785;
3663  f, t, 3);
3664  return value;
3665  } else
3666  return eep->modalHeader5G.xatten1Margin[chain];
3667  }
3668 
3669  return 0;
3670 }
uint16_t u16
Definition: stdint.h:21
u16 channel
Definition: hw.h:349
int32_t s32
Definition: stdint.h:22
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
u8 xatten1MarginLow[AR9300_MAX_CHAINS]
u8 xatten1MarginHigh[AR9300_MAX_CHAINS]
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
struct ar9300_BaseExtension_2 base_ext2
u8 xatten1Margin[AR9300_MAX_CHAINS]
uint8_t ah
Definition: registers.h:85

References ah, ar9003_hw_power_interpolate(), ar9300_eeprom::base_ext2, ath9k_channel::channel, IS_CHAN_2GHZ, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, value, ar9300_modal_eep_header::xatten1Margin, ar9300_BaseExtension_2::xatten1MarginHigh, and ar9300_BaseExtension_2::xatten1MarginLow.

Referenced by ar9003_hw_atten_apply().

◆ ar9003_hw_atten_apply()

static void ar9003_hw_atten_apply ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 3672 of file ath9k_ar9003_eeprom.c.

3673 {
3674  int i;
3675  u16 value;
3676  unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3679  };
3680 
3681  /* Test value. if 0 then attenuation is unused. Don't load anything. */
3682  for (i = 0; i < 3; i++) {
3683  if (ah->txchainmask & BIT(i)) {
3684  value = ar9003_hw_atten_chain_get(ah, i, chan);
3685  REG_RMW_FIELD(ah, ext_atten_reg[i],
3687 
3689  REG_RMW_FIELD(ah, ext_atten_reg[i],
3691  value);
3692  }
3693  }
3694 }
uint16_t u16
Definition: stdint.h:21
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_PHY_EXT_ATTEN_CTL_2
Definition: ar9003_phy.h:877
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN
Definition: ar9003_phy.h:346
static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
#define AR_PHY_EXT_ATTEN_CTL_0
Definition: ar9003_phy.h:259
pseudo_bit_t value[0x00020]
Definition: arbel.h:13
#define AR_PHY_EXT_ATTEN_CTL_1
Definition: ar9003_phy.h:822
static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, struct ath9k_channel *chan)
#define BIT(nr)
Definition: ath.h:32
uint8_t ah
Definition: registers.h:85
#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB
Definition: ar9003_phy.h:350

References ah, ar9003_hw_atten_chain_get(), ar9003_hw_atten_chain_get_margin(), AR_PHY_EXT_ATTEN_CTL_0, AR_PHY_EXT_ATTEN_CTL_1, AR_PHY_EXT_ATTEN_CTL_2, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, BIT, REG_RMW_FIELD, and value.

Referenced by ath9k_hw_ar9300_set_board_values().

◆ is_pmu_set()

static int is_pmu_set ( struct ath_hw ah,
u32  pmu_reg,
int  pmu_set 
)
static

Definition at line 3696 of file ath9k_ar9003_eeprom.c.

3697 {
3698  int timeout = 100;
3699 
3700  while ((unsigned int)pmu_set != REG_READ(ah, pmu_reg)) {
3701  if (timeout-- == 0)
3702  return 0;
3703  REG_WRITE(ah, pmu_reg, pmu_set);
3704  udelay(10);
3705  }
3706 
3707  return 1;
3708 }
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85
void timeout(int)

References ah, REG_READ, REG_WRITE, timeout(), and udelay().

Referenced by ar9003_hw_internal_regulator_apply().

◆ ar9003_hw_internal_regulator_apply()

static void ar9003_hw_internal_regulator_apply ( struct ath_hw ah)
static

Definition at line 3710 of file ath9k_ar9003_eeprom.c.

3711 {
3712  int internal_regulator =
3714 
3715  if (internal_regulator) {
3716  if (AR_SREV_9485(ah)) {
3717  int reg_pmu_set;
3718 
3719  reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3720  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3721  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3722  return;
3723 
3724  reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
3725  (2 << 14) | (6 << 17) | (1 << 20) |
3726  (3 << 24) | (1 << 28);
3727 
3728  REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3729  if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3730  return;
3731 
3732  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3733  | (4 << 26);
3734  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3735  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3736  return;
3737 
3738  reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3739  | (1 << 21);
3740  REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3741  if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3742  return;
3743  } else {
3744  /* Internal regulator is ON. Write swreg register. */
3750  /* Set REG_CONTROL1.SWREG_PROGRAM */
3752  REG_READ(ah,
3755  }
3756  } else {
3757  if (AR_SREV_9485(ah)) {
3759  while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3760  AR_PHY_PMU2_PGM))
3761  udelay(10);
3762 
3764  while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3765  AR_PHY_PMU1_PWD))
3766  udelay(10);
3768  while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3769  AR_PHY_PMU2_PGM))
3770  udelay(10);
3771  } else
3773  (REG_READ(ah,
3774  AR_RTC_SLEEP_CLK) |
3776  }
3777 
3778 }
#define AR_PHY_PMU2
Definition: ar9003_phy.h:640
#define AR_RTC_REG_CONTROL1
Definition: reg.h:1173
#define AR_SREV_9485(_ah)
Definition: reg.h:867
#define AR_RTC_REG_CONTROL0
Definition: reg.h:1170
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM
Definition: reg.h:1174
#define AR_PHY_PMU1_PWD
Definition: ar9003_phy.h:637
#define AR_RTC_SLEEP_CLK
Definition: reg.h:1212
void udelay(unsigned long usecs)
Delay for a fixed number of microseconds.
Definition: timer.c:60
#define AR_RTC_FORCE_SWREG_PRD
Definition: reg.h:1215
static int is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
#define AR_PHY_PMU1
Definition: ar9003_phy.h:636
#define REG_READ(_ah, _reg)
Definition: hw.h:80
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
#define REG_READ_FIELD(_a, _r, _f)
Definition: hw.h:105
uint8_t ah
Definition: registers.h:85
#define AR_PHY_PMU2_PGM
Definition: ar9003_phy.h:641
uint32_t swreg
Definition: ar9003_eeprom.h:54

References ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, AR_PHY_PMU2, AR_PHY_PMU2_PGM, AR_RTC_FORCE_SWREG_PRD, AR_RTC_REG_CONTROL0, AR_RTC_REG_CONTROL1, AR_RTC_REG_CONTROL1_SWREG_PROGRAM, AR_RTC_SLEEP_CLK, AR_SREV_9485, ath9k_hw_ar9300_get_eeprom(), EEP_INTERNAL_REGULATOR, EEP_SWREG, is_pmu_set(), REG_READ, REG_READ_FIELD, REG_RMW_FIELD, REG_WRITE, swreg, and udelay().

Referenced by ath9k_hw_ar9300_set_board_values().

◆ ar9003_hw_apply_tuning_caps()

static void ar9003_hw_apply_tuning_caps ( struct ath_hw ah)
static

Definition at line 3780 of file ath9k_ar9003_eeprom.c.

3781 {
3782  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3783  u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3784 
3785  if (eep->baseEepHeader.featureEnable & 0x40) {
3786  tuning_caps_param &= 0x7f;
3788  tuning_caps_param);
3790  tuning_caps_param);
3791  }
3792 }
#define AR_CH0_XTAL
Definition: ar9003_phy.h:630
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
#define AR_CH0_XTAL_CAPOUTDAC
Definition: ar9003_phy.h:633
struct ar9300_base_eep_hdr baseEepHeader
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19
#define AR_CH0_XTAL_CAPINDAC
Definition: ar9003_phy.h:631

References ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, AR_CH0_XTAL_CAPOUTDAC, ar9300_eeprom::baseEepHeader, ar9300_base_eep_hdr::featureEnable, ar9300_base_eep_hdr::params_for_tuning_caps, and REG_RMW_FIELD.

Referenced by ath9k_hw_ar9300_set_board_values().

◆ ath9k_hw_ar9300_set_board_values()

static void ath9k_hw_ar9300_set_board_values ( struct ath_hw ah,
struct ath9k_channel chan 
)
static

Definition at line 3794 of file ath9k_ar9003_eeprom.c.

3796 {
3800  ar9003_hw_atten_apply(ah, chan);
3801  if (!AR_SREV_9340(ah))
3803  if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3805 }
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
#define AR_SREV_9485(_ah)
Definition: reg.h:867
static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, int is2ghz)
#define AR_SREV_9340(_ah)
Definition: reg.h:878
static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, int is2ghz)
static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
uint8_t ah
Definition: registers.h:85

References ah, ar9003_hw_ant_ctrl_apply(), ar9003_hw_apply_tuning_caps(), ar9003_hw_atten_apply(), ar9003_hw_drive_strength_apply(), ar9003_hw_internal_regulator_apply(), ar9003_hw_xpa_bias_level_apply(), AR_SREV_9340, AR_SREV_9485, and IS_CHAN_2GHZ.

◆ ath9k_hw_ar9300_set_addac()

static void ath9k_hw_ar9300_set_addac ( struct ath_hw *ah  __unused,
struct ath9k_channel *chan  __unused 
)
static

Definition at line 3807 of file ath9k_ar9003_eeprom.c.

3809 {
3810 }

◆ ar9003_hw_eeprom_get_tgt_pwr()

static u8 ar9003_hw_eeprom_get_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
)
static

Definition at line 3875 of file ath9k_ar9003_eeprom.c.

3877 {
3878  u16 numPiers, i;
3879  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3881  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3882  struct cal_tgt_pow_legacy *pEepromTargetPwr;
3883  u8 *pFreqBin;
3884 
3885  if (is2GHz) {
3886  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3887  pEepromTargetPwr = eep->calTargetPower2G;
3888  pFreqBin = eep->calTarget_freqbin_2G;
3889  } else {
3890  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3891  pEepromTargetPwr = eep->calTargetPower5G;
3892  pFreqBin = eep->calTarget_freqbin_5G;
3893  }
3894 
3895  /*
3896  * create array of channels and targetpower from
3897  * targetpower piers stored on eeprom
3898  */
3899  for (i = 0; i < numPiers; i++) {
3900  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3901  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3902  }
3903 
3904  /* interpolate to get target power for given frequency */
3905  return (u8) ar9003_hw_power_interpolate((s32) freq,
3906  freqArray,
3907  targetPowerArray, numPiers);
3908 }
uint16_t u16
Definition: stdint.h:21
u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]
int32_t s32
Definition: stdint.h:22
#define AR9300_NUM_5G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:34
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
#define AR9300_NUM_2G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:37
struct cal_tgt_pow_legacy calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]
u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]
struct cal_tgt_pow_legacy calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19

References ah, ar9003_hw_power_interpolate(), AR9300_NUM_2G_20_TARGET_POWERS, AR9300_NUM_5G_20_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2G, ar9300_eeprom::calTarget_freqbin_5G, ar9300_eeprom::calTargetPower2G, ar9300_eeprom::calTargetPower5G, FBIN2FREQ, and cal_tgt_pow_legacy::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

◆ ar9003_hw_eeprom_get_ht20_tgt_pwr()

static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
)
static

Definition at line 3910 of file ath9k_ar9003_eeprom.c.

3913 {
3914  u16 numPiers, i;
3915  s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3917  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3918  struct cal_tgt_pow_ht *pEepromTargetPwr;
3919  u8 *pFreqBin;
3920 
3921  if (is2GHz) {
3922  numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3923  pEepromTargetPwr = eep->calTargetPower2GHT20;
3924  pFreqBin = eep->calTarget_freqbin_2GHT20;
3925  } else {
3926  numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3927  pEepromTargetPwr = eep->calTargetPower5GHT20;
3928  pFreqBin = eep->calTarget_freqbin_5GHT20;
3929  }
3930 
3931  /*
3932  * create array of channels and targetpower
3933  * from targetpower piers stored on eeprom
3934  */
3935  for (i = 0; i < numPiers; i++) {
3936  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3937  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3938  }
3939 
3940  /* interpolate to get target power for given frequency */
3941  return (u8) ar9003_hw_power_interpolate((s32) freq,
3942  freqArray,
3943  targetPowerArray, numPiers);
3944 }
uint16_t u16
Definition: stdint.h:21
u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
int32_t s32
Definition: stdint.h:22
#define AR9300_NUM_5G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:34
struct cal_tgt_pow_ht calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]
struct cal_tgt_pow_ht calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
#define AR9300_NUM_2G_20_TARGET_POWERS
Definition: ar9003_eeprom.h:37
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19

References ah, ar9003_hw_power_interpolate(), AR9300_NUM_2G_20_TARGET_POWERS, AR9300_NUM_5G_20_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2GHT20, ar9300_eeprom::calTarget_freqbin_5GHT20, ar9300_eeprom::calTargetPower2GHT20, ar9300_eeprom::calTargetPower5GHT20, FBIN2FREQ, and cal_tgt_pow_ht::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

◆ ar9003_hw_eeprom_get_ht40_tgt_pwr()

static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq,
int  is2GHz 
)
static

Definition at line 3946 of file ath9k_ar9003_eeprom.c.

3949 {
3950  u16 numPiers, i;
3951  s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3953  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3954  struct cal_tgt_pow_ht *pEepromTargetPwr;
3955  u8 *pFreqBin;
3956 
3957  if (is2GHz) {
3958  numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3959  pEepromTargetPwr = eep->calTargetPower2GHT40;
3960  pFreqBin = eep->calTarget_freqbin_2GHT40;
3961  } else {
3962  numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3963  pEepromTargetPwr = eep->calTargetPower5GHT40;
3964  pFreqBin = eep->calTarget_freqbin_5GHT40;
3965  }
3966 
3967  /*
3968  * create array of channels and targetpower from
3969  * targetpower piers stored on eeprom
3970  */
3971  for (i = 0; i < numPiers; i++) {
3972  freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3973  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3974  }
3975 
3976  /* interpolate to get target power for given frequency */
3977  return (u8) ar9003_hw_power_interpolate((s32) freq,
3978  freqArray,
3979  targetPowerArray, numPiers);
3980 }
uint16_t u16
Definition: stdint.h:21
u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
int32_t s32
Definition: stdint.h:22
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
struct cal_tgt_pow_ht calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]
uint8_t ah
Definition: registers.h:85
#define AR9300_NUM_5G_40_TARGET_POWERS
Definition: ar9003_eeprom.h:35
#define AR9300_NUM_2G_40_TARGET_POWERS
Definition: ar9003_eeprom.h:38
struct cal_tgt_pow_ht calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]
uint8_t u8
Definition: stdint.h:19

References ah, ar9003_hw_power_interpolate(), AR9300_NUM_2G_40_TARGET_POWERS, AR9300_NUM_5G_40_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_2GHT40, ar9300_eeprom::calTarget_freqbin_5GHT40, ar9300_eeprom::calTargetPower2GHT40, ar9300_eeprom::calTargetPower5GHT40, FBIN2FREQ, and cal_tgt_pow_ht::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

◆ ar9003_hw_eeprom_get_cck_tgt_pwr()

static u8 ar9003_hw_eeprom_get_cck_tgt_pwr ( struct ath_hw ah,
u16  rateIndex,
u16  freq 
)
static

Definition at line 3982 of file ath9k_ar9003_eeprom.c.

3984 {
3985  u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3986  s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3988  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3989  struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3990  u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3991 
3992  /*
3993  * create array of channels and targetpower from
3994  * targetpower piers stored on eeprom
3995  */
3996  for (i = 0; i < numPiers; i++) {
3997  freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3998  targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3999  }
4000 
4001  /* interpolate to get target power for given frequency */
4002  return (u8) ar9003_hw_power_interpolate((s32) freq,
4003  freqArray,
4004  targetPowerArray, numPiers);
4005 }
uint16_t u16
Definition: stdint.h:21
int32_t s32
Definition: stdint.h:22
#define AR9300_NUM_2G_CCK_TARGET_POWERS
Definition: ar9003_eeprom.h:36
struct cal_tgt_pow_legacy calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19

References ah, ar9003_hw_power_interpolate(), AR9300_NUM_2G_CCK_TARGET_POWERS, ar9300_eeprom::calTarget_freqbin_Cck, ar9300_eeprom::calTargetPowerCck, FBIN2FREQ, and cal_tgt_pow_legacy::tPow2x.

Referenced by ar9003_hw_set_target_power_eeprom().

◆ ar9003_hw_tx_power_regwrite()

static int ar9003_hw_tx_power_regwrite ( struct ath_hw ah,
u8 pPwrArray 
)
static

Definition at line 4008 of file ath9k_ar9003_eeprom.c.

4009 {
4010 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4011  /* make sure forced gain is not set */
4013 
4014  /* Write the OFDM power per rate set */
4015 
4016  /* 6 (LSB), 9, 12, 18 (MSB) */
4018  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4019  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4020  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4021  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4022 
4023  /* 24 (LSB), 36, 48, 54 (MSB) */
4025  POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4026  POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4027  POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4028  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4029 
4030  /* Write the CCK power per rate set */
4031 
4032  /* 1L (LSB), reserved, 2L, 2S (MSB) */
4034  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4035  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4036  /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4037  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4038 
4039  /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4041  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4042  POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4043  POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4044  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4045  );
4046 
4047  /* Write the power for duplicated frames - HT40 */
4048 
4049  /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4050  REG_WRITE(ah, 0xa3e0,
4051  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4052  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4053  POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4054  POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4055  );
4056 
4057  /* Write the HT20 power per rate set */
4058 
4059  /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4061  POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4062  POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4063  POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4064  POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4065  );
4066 
4067  /* 6 (LSB), 7, 12, 13 (MSB) */
4069  POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4070  POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4071  POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4072  POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4073  );
4074 
4075  /* 14 (LSB), 15, 20, 21 */
4077  POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4078  POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4079  POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4080  POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4081  );
4082 
4083  /* Mixed HT20 and HT40 rates */
4084 
4085  /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4087  POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4088  POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4089  POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4090  POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4091  );
4092 
4093  /*
4094  * Write the HT40 power per rate set
4095  * correct PAR difference between HT40 and HT20/LEGACY
4096  * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4097  */
4099  POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4100  POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4101  POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4102  POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4103  );
4104 
4105  /* 6 (LSB), 7, 12, 13 (MSB) */
4107  POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4108  POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4109  POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4110  POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4111  );
4112 
4113  /* 14 (LSB), 15, 20, 21 */
4115  POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4116  POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4117  POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4118  POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4119  );
4120 
4121  return 0;
4122 #undef POW_SM
4123 }
#define AR_PHY_POWER_TX_RATE(_d)
Definition: ar9003_phy.h:511
#define AR_PHY_TX_FORCED_GAIN
Definition: ar9003_phy.h:548
#define POW_SM(_r, _s)
#define REG_WRITE(_ah, _reg, _val)
Definition: hw.h:77
uint8_t ah
Definition: registers.h:85

References ah, ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_12, ALL_TARGET_HT20_13, ALL_TARGET_HT20_14, ALL_TARGET_HT20_15, ALL_TARGET_HT20_1_3_9_11_17_19, ALL_TARGET_HT20_20, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT20_4, ALL_TARGET_HT20_5, ALL_TARGET_HT20_6, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_12, ALL_TARGET_HT40_13, ALL_TARGET_HT40_14, ALL_TARGET_HT40_15, ALL_TARGET_HT40_1_3_9_11_17_19, ALL_TARGET_HT40_20, ALL_TARGET_HT40_21, ALL_TARGET_HT40_22, ALL_TARGET_HT40_23, ALL_TARGET_HT40_4, ALL_TARGET_HT40_5, ALL_TARGET_HT40_6, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_11L, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_36, ALL_TARGET_LEGACY_48, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_5S, ALL_TARGET_LEGACY_6_24, AR_PHY_POWER_TX_RATE, AR_PHY_TX_FORCED_GAIN, POW_SM, and REG_WRITE.

Referenced by ath9k_hw_ar9300_set_txpower().

◆ ar9003_hw_set_target_power_eeprom()

static void ar9003_hw_set_target_power_eeprom ( struct ath_hw ah,
u16  freq,
u8 targetPowerValT2 
)
static

Definition at line 4125 of file ath9k_ar9003_eeprom.c.

4127 {
4128  /* XXX: hard code for now, need to get from eeprom struct */
4129  u8 ht40PowerIncForPdadc = 0;
4130  int is2GHz = 0;
4131  unsigned int i = 0;
4132 
4133  if (freq < 4000)
4134  is2GHz = 1;
4135 
4136  targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4138  is2GHz);
4139  targetPowerValT2[ALL_TARGET_LEGACY_36] =
4141  is2GHz);
4142  targetPowerValT2[ALL_TARGET_LEGACY_48] =
4144  is2GHz);
4145  targetPowerValT2[ALL_TARGET_LEGACY_54] =
4147  is2GHz);
4148  targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4150  freq);
4151  targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4153  targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4155  targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4157  targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4159  is2GHz);
4160  targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4162  freq, is2GHz);
4163  targetPowerValT2[ALL_TARGET_HT20_4] =
4165  is2GHz);
4166  targetPowerValT2[ALL_TARGET_HT20_5] =
4168  is2GHz);
4169  targetPowerValT2[ALL_TARGET_HT20_6] =
4171  is2GHz);
4172  targetPowerValT2[ALL_TARGET_HT20_7] =
4174  is2GHz);
4175  targetPowerValT2[ALL_TARGET_HT20_12] =
4177  is2GHz);
4178  targetPowerValT2[ALL_TARGET_HT20_13] =
4180  is2GHz);
4181  targetPowerValT2[ALL_TARGET_HT20_14] =
4183  is2GHz);
4184  targetPowerValT2[ALL_TARGET_HT20_15] =
4186  is2GHz);
4187  targetPowerValT2[ALL_TARGET_HT20_20] =
4189  is2GHz);
4190  targetPowerValT2[ALL_TARGET_HT20_21] =
4192  is2GHz);
4193  targetPowerValT2[ALL_TARGET_HT20_22] =
4195  is2GHz);
4196  targetPowerValT2[ALL_TARGET_HT20_23] =
4198  is2GHz);
4199  targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4201  is2GHz) + ht40PowerIncForPdadc;
4202  targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4204  freq,
4205  is2GHz) + ht40PowerIncForPdadc;
4206  targetPowerValT2[ALL_TARGET_HT40_4] =
4208  is2GHz) + ht40PowerIncForPdadc;
4209  targetPowerValT2[ALL_TARGET_HT40_5] =
4211  is2GHz) + ht40PowerIncForPdadc;
4212  targetPowerValT2[ALL_TARGET_HT40_6] =
4214  is2GHz) + ht40PowerIncForPdadc;
4215  targetPowerValT2[ALL_TARGET_HT40_7] =
4217  is2GHz) + ht40PowerIncForPdadc;
4218  targetPowerValT2[ALL_TARGET_HT40_12] =
4220  is2GHz) + ht40PowerIncForPdadc;
4221  targetPowerValT2[ALL_TARGET_HT40_13] =
4223  is2GHz) + ht40PowerIncForPdadc;
4224  targetPowerValT2[ALL_TARGET_HT40_14] =
4226  is2GHz) + ht40PowerIncForPdadc;
4227  targetPowerValT2[ALL_TARGET_HT40_15] =
4229  is2GHz) + ht40PowerIncForPdadc;
4230  targetPowerValT2[ALL_TARGET_HT40_20] =
4232  is2GHz) + ht40PowerIncForPdadc;
4233  targetPowerValT2[ALL_TARGET_HT40_21] =
4235  is2GHz) + ht40PowerIncForPdadc;
4236  targetPowerValT2[ALL_TARGET_HT40_22] =
4238  is2GHz) + ht40PowerIncForPdadc;
4239  targetPowerValT2[ALL_TARGET_HT40_23] =
4241  is2GHz) + ht40PowerIncForPdadc;
4242 
4243  for (i = 0; i < ar9300RateSize; i++) {
4244  DBG2("ath9k: "
4245  "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4246  }
4247 }
static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq)
static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, u16 rateIndex, u16 freq, int is2GHz)
uint8_t ah
Definition: registers.h:85
uint8_t u8
Definition: stdint.h:19
#define DBG2(...)
Definition: compiler.h:515

References ah, ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_12, ALL_TARGET_HT20_13, ALL_TARGET_HT20_14, ALL_TARGET_HT20_15, ALL_TARGET_HT20_1_3_9_11_17_19, ALL_TARGET_HT20_20, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT20_4, ALL_TARGET_HT20_5, ALL_TARGET_HT20_6, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_12, ALL_TARGET_HT40_13, ALL_TARGET_HT40_14, ALL_TARGET_HT40_15, ALL_TARGET_HT40_1_3_9_11_17_19, ALL_TARGET_HT40_20, ALL_TARGET_HT40_21, ALL_TARGET_HT40_22, ALL_TARGET_HT40_23, ALL_TARGET_HT40_4, ALL_TARGET_HT40_5, ALL_TARGET_HT40_6, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_11L, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_36, ALL_TARGET_LEGACY_48, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_5S, ALL_TARGET_LEGACY_6_24, ar9003_hw_eeprom_get_cck_tgt_pwr(), ar9003_hw_eeprom_get_ht20_tgt_pwr(), ar9003_hw_eeprom_get_ht40_tgt_pwr(), ar9003_hw_eeprom_get_tgt_pwr(), ar9300RateSize, DBG2, HT_TARGET_RATE_0_8_16, HT_TARGET_RATE_12, HT_TARGET_RATE_13, HT_TARGET_RATE_14, HT_TARGET_RATE_15, HT_TARGET_RATE_1_3_9_11_17_19, HT_TARGET_RATE_20, HT_TARGET_RATE_21, HT_TARGET_RATE_22, HT_TARGET_RATE_23, HT_TARGET_RATE_4, HT_TARGET_RATE_5, HT_TARGET_RATE_6, HT_TARGET_RATE_7, LEGACY_TARGET_RATE_11L, LEGACY_TARGET_RATE_11S, LEGACY_TARGET_RATE_1L_5L, LEGACY_TARGET_RATE_36, LEGACY_TARGET_RATE_48, LEGACY_TARGET_RATE_54, LEGACY_TARGET_RATE_5S, and LEGACY_TARGET_RATE_6_24.

Referenced by ath9k_hw_ar9300_set_txpower().

◆ ar9003_hw_cal_pier_get()

static int ar9003_hw_cal_pier_get ( struct ath_hw ah,
int  mode,
int  ipier,
int  ichain,
int *  pfrequency,
int *  pcorrection,
int *  ptemperature,
int *  pvoltage 
)
static

Definition at line 4249 of file ath9k_ar9003_eeprom.c.

4256 {
4257  u8 *pCalPier;
4258  struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4259  int is2GHz;
4260  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4261 
4262  if (ichain >= AR9300_MAX_CHAINS) {
4263  DBG("ath9k: "
4264  "Invalid chain index, must be less than %d\n",
4266  return -1;
4267  }
4268 
4269  if (mode) { /* 5GHz */
4270  if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4271  DBG("ath9k: "
4272  "Invalid 5GHz cal pier index, must be less than %d\n",
4274  return -1;
4275  }
4276  pCalPier = &(eep->calFreqPier5G[ipier]);
4277  pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4278  is2GHz = 0;
4279  } else {
4280  if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4281  DBG("ath9k: "
4282  "Invalid 2GHz cal pier index, must be less than %d\n",
4284  return -1;
4285  }
4286 
4287  pCalPier = &(eep->calFreqPier2G[ipier]);
4288  pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4289  is2GHz = 1;
4290  }
4291 
4292  *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4293  *pcorrection = pCalPierStruct->refPower;
4294  *ptemperature = pCalPierStruct->tempMeas;
4295  *pvoltage = pCalPierStruct->voltMeas;
4296 
4297  return 0;
4298 }
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
#define AR9300_NUM_5G_CAL_PIERS
Definition: ar9003_eeprom.h:32
u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]
#define FBIN2FREQ(x, y)
Definition: ar9003_eeprom.h:48
#define AR9300_NUM_2G_CAL_PIERS
Definition: ar9003_eeprom.h:33
struct ar9300_cal_data_per_freq_op_loop calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]
u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]
uint8_t ah
Definition: registers.h:85
struct ar9300_cal_data_per_freq_op_loop calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]
#define DBG(...)
Print a debugging message.
Definition: compiler.h:498
uint8_t u8
Definition: stdint.h:19

References ah, AR9300_MAX_CHAINS, AR9300_NUM_2G_CAL_PIERS, AR9300_NUM_5G_CAL_PIERS, ar9300_eeprom::calFreqPier2G, ar9300_eeprom::calFreqPier5G, ar9300_eeprom::calPierData2G, ar9300_eeprom::calPierData5G, DBG, FBIN2FREQ, ar9300_cal_data_per_freq_op_loop::refPower, ar9300_cal_data_per_freq_op_loop::tempMeas, and ar9300_cal_data_per_freq_op_loop::voltMeas.

Referenced by ar9003_hw_calibration_apply().

◆ ar9003_hw_power_control_override()

static int ar9003_hw_power_control_override ( struct ath_hw ah,
int  frequency,
int *  correction,
int *voltage  __unused,
int *  temperature 
)
static

Definition at line 4300 of file ath9k_ar9003_eeprom.c.

4304 {
4305  int tempSlope = 0;
4306  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4307  int f[3], t[3];
4308 
4310  (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4312  if (ah->caps.tx_chainmask & BIT(1))
4314  (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4316  if (ah->caps.tx_chainmask & BIT(2))
4318  (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4320 
4321  /* enable open loop power control on chip */
4325  if (ah->caps.tx_chainmask & BIT(1))
4329  if (ah->caps.tx_chainmask & BIT(2))
4333 
4334  /*
4335  * enable temperature compensation
4336  * Need to use register names
4337  */
4338  if (frequency < 4000)
4340  else if (eep->base_ext2.tempSlopeLow != 0) {
4341  t[0] = eep->base_ext2.tempSlopeLow;
4342  f[0] = 5180;
4343  t[1] = eep->modalHeader5G.tempSlope;
4344  f[1] = 5500;
4345  t[2] = eep->base_ext2.tempSlopeHigh;
4346  f[2] = 5785;
4348  f, t, 3);
4349  } else
4351 
4354  temperature[0]);
4355 
4356  return 0;
4357 }
#define AR_PHY_TPC_6_B1
Definition: ar9003_phy.h:847
int32_t s32
Definition: stdint.h:22
#define AR_PHY_TPC_OLPC_GAIN_DELTA
Definition: ar9003_phy.h:414
int8_t tempSlope
Definition: ar9003_eeprom.h:34
#define REG_RMW(_ah, _reg, _set, _clr)
Definition: hw.h:86
#define AR_PHY_TPC_11_B0
Definition: ar9003_phy.h:526
#define AR_PHY_TPC_6_ERROR_EST_MODE
Definition: ar9003_phy.h:417
#define AR_PHY_TPC_11_B1
Definition: ar9003_phy.h:848
#define REG_RMW_FIELD(_a, _r, _f, _v)
Definition: hw.h:103
static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, uint16_t np)
#define AR_PHY_TPC_19
Definition: ar9003_phy.h:542
#define AR_PHY_TPC_19_ALPHA_THERM
Definition: ar9003_phy.h:545
#define AR_PHY_TPC_11_B2
Definition: ar9003_phy.h:901
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
#define AR_PHY_TPC_6_B2
Definition: ar9003_phy.h:900
struct ar9300_BaseExtension_2 base_ext2
#define AR_PHY_TPC_OLPC_GAIN_DELTA_S
Definition: ar9003_phy.h:415
#define AR_PHY_TPC_18_THERM_CAL_VALUE
Definition: ar9003_phy.h:537
#define BIT(nr)
Definition: ath.h:32
uint8_t ah
Definition: registers.h:85
#define AR_PHY_TPC_18
Definition: ar9003_phy.h:536
#define AR_PHY_TPC_6_ERROR_EST_MODE_S
Definition: ar9003_phy.h:418
#define AR_PHY_TPC_6_B0
Definition: ar9003_phy.h:524

References ah, ar9003_hw_power_interpolate(), AR_PHY_TPC_11_B0, AR_PHY_TPC_11_B1, AR_PHY_TPC_11_B2, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, AR_PHY_TPC_6_B0, AR_PHY_TPC_6_B1, AR_PHY_TPC_6_B2, AR_PHY_TPC_6_ERROR_EST_MODE, AR_PHY_TPC_6_ERROR_EST_MODE_S, AR_PHY_TPC_OLPC_GAIN_DELTA, AR_PHY_TPC_OLPC_GAIN_DELTA_S, ar9300_eeprom::base_ext2, BIT, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, REG_RMW, REG_RMW_FIELD, tempSlope, ar9300_modal_eep_header::tempSlope, ar9300_BaseExtension_2::tempSlopeHigh, and ar9300_BaseExtension_2::tempSlopeLow.

Referenced by ar9003_hw_calibration_apply().

◆ ar9003_hw_calibration_apply()

static int ar9003_hw_calibration_apply ( struct ath_hw ah,
int  frequency 
)
static

Definition at line 4360 of file ath9k_ar9003_eeprom.c.

4361 {
4362  int ichain, ipier, npier;
4363  int mode;
4364  int lfrequency[AR9300_MAX_CHAINS],
4365  lcorrection[AR9300_MAX_CHAINS],
4366  ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4367  int hfrequency[AR9300_MAX_CHAINS],
4368  hcorrection[AR9300_MAX_CHAINS],
4369  htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4370  int fdiff;
4371  int correction[AR9300_MAX_CHAINS],
4372  voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4373  int pfrequency, pcorrection, ptemperature, pvoltage;
4374 
4375  mode = (frequency >= 4000);
4376  if (mode)
4377  npier = AR9300_NUM_5G_CAL_PIERS;
4378  else
4379  npier = AR9300_NUM_2G_CAL_PIERS;
4380 
4381  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4382  lfrequency[ichain] = 0;
4383  hfrequency[ichain] = 100000;
4384  }
4385  /* identify best lower and higher frequency calibration measurement */
4386  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4387  for (ipier = 0; ipier < npier; ipier++) {
4388  if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4389  &pfrequency, &pcorrection,
4390  &ptemperature, &pvoltage)) {
4391  fdiff = frequency - pfrequency;
4392 
4393  /*
4394  * this measurement is higher than
4395  * our desired frequency
4396  */
4397  if (fdiff <= 0) {
4398  if (hfrequency[ichain] <= 0 ||
4399  hfrequency[ichain] >= 100000 ||
4400  fdiff >
4401  (frequency - hfrequency[ichain])) {
4402  /*
4403  * new best higher
4404  * frequency measurement
4405  */
4406  hfrequency[ichain] = pfrequency;
4407  hcorrection[ichain] =
4408  pcorrection;
4409  htemperature[ichain] =
4410  ptemperature;
4411  hvoltage[ichain] = pvoltage;
4412  }
4413  }
4414  if (fdiff >= 0) {
4415  if (lfrequency[ichain] <= 0
4416  || fdiff <
4417  (frequency - lfrequency[ichain])) {
4418  /*
4419  * new best lower
4420  * frequency measurement
4421  */
4422  lfrequency[ichain] = pfrequency;
4423  lcorrection[ichain] =
4424  pcorrection;
4425  ltemperature[ichain] =
4426  ptemperature;
4427  lvoltage[ichain] = pvoltage;
4428  }
4429  }
4430  }
4431  }
4432  }
4433 
4434  /* interpolate */
4435  for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4436  DBG2("ath9k: "
4437  "ch=%d f=%d low=%d %d h=%d %d\n",
4438  ichain, frequency, lfrequency[ichain],
4439  lcorrection[ichain], hfrequency[ichain],
4440  hcorrection[ichain]);
4441  /* they're the same, so just pick one */
4442  if (hfrequency[ichain] == lfrequency[ichain]) {
4443  correction[ichain] = lcorrection[ichain];
4444  voltage[ichain] = lvoltage[ichain];
4445  temperature[ichain] = ltemperature[ichain];
4446  }
4447  /* the low frequency is good */
4448  else if (frequency - lfrequency[ichain] < 1000) {
4449  /* so is the high frequency, interpolate */
4450  if (hfrequency[ichain] - frequency < 1000) {
4451 
4452  correction[ichain] = interpolate(frequency,
4453  lfrequency[ichain],
4454  hfrequency[ichain],
4455  lcorrection[ichain],
4456  hcorrection[ichain]);
4457 
4458  temperature[ichain] = interpolate(frequency,
4459  lfrequency[ichain],
4460  hfrequency[ichain],
4461  ltemperature[ichain],
4462  htemperature[ichain]);
4463 
4464  voltage[ichain] = interpolate(frequency,
4465  lfrequency[ichain],
4466  hfrequency[ichain],
4467  lvoltage[ichain],
4468  hvoltage[ichain]);
4469  }
4470  /* only low is good, use it */
4471  else {
4472  correction[ichain] = lcorrection[ichain];
4473  temperature[ichain] = ltemperature[ichain];
4474  voltage[ichain] = lvoltage[ichain];
4475  }
4476  }
4477  /* only high is good, use it */
4478  else if (hfrequency[ichain] - frequency < 1000) {
4479  correction[ichain] = hcorrection[ichain];
4480  temperature[ichain] = htemperature[ichain];
4481  voltage[ichain] = hvoltage[ichain];
4482  } else { /* nothing is good, presume 0???? */
4483  correction[ichain] = 0;
4484  temperature[ichain] = 0;
4485  voltage[ichain] = 0;
4486  }
4487  }
4488 
4489  ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4490  temperature);
4491 
4492  DBG2("ath9k: "
4493  "for frequency=%d, calibration correction = %d %d %d\n",
4494  frequency, correction[0], correction[1], correction[2]);
4495 
4496  return 0;
4497 }
#define AR9300_MAX_CHAINS
Definition: ar9003_eeprom.h:49
#define AR9300_NUM_5G_CAL_PIERS
Definition: ar9003_eeprom.h:32
static int interpolate(int x, int xa, int xb, int ya, int yb)
static int ar9003_hw_cal_pier_get(struct ath_hw *ah, int mode, int ipier, int ichain, int *pfrequency, int *pcorrection, int *ptemperature, int *pvoltage)
static int ar9003_hw_power_control_override(struct ath_hw *ah, int frequency, int *correction, int *voltage __unused, int *temperature)
#define AR9300_NUM_2G_CAL_PIERS
Definition: ar9003_eeprom.h:33
uint8_t ah
Definition: registers.h:85
#define DBG2(...)
Definition: compiler.h:515

References ah, ar9003_hw_cal_pier_get(), ar9003_hw_power_control_override(), AR9300_MAX_CHAINS, AR9300_NUM_2G_CAL_PIERS, AR9300_NUM_5G_CAL_PIERS, DBG2, and interpolate().

Referenced by ath9k_hw_ar9300_set_txpower().

◆ ar9003_hw_get_direct_edge_power()

static u16 ar9003_hw_get_direct_edge_power ( struct ar9300_eeprom eep,
int  idx,
int  edge,
int  is2GHz 
)
static

Definition at line 4499 of file ath9k_ar9003_eeprom.c.

4503 {
4504  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4505  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4506 
4507  if (is2GHz)
4508  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4509  else
4510  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4511 }
u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]
Definition: ar9003_eeprom.h:24
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]
#define CTL_EDGE_TPOWER(_ctl)
Definition: eeprom.h:213

References CTL_EDGE_TPOWER, ctlEdges, ar9300_eeprom::ctlPowerData_2G, and ar9300_eeprom::ctlPowerData_5G.

Referenced by ar9003_hw_get_max_edge_power().

◆ ar9003_hw_get_indirect_edge_power()

static u16 ar9003_hw_get_indirect_edge_power ( struct ar9300_eeprom eep,
int  idx,
unsigned int  edge,
u16  freq,
int  is2GHz 
)
static

Definition at line 4513 of file ath9k_ar9003_eeprom.c.

4518 {
4519  struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4520  struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4521 
4522  u8 *ctl_freqbin = is2GHz ?
4523  &eep->ctl_freqbin_2G[idx][0] :
4524  &eep->ctl_freqbin_5G[idx][0];
4525 
4526  if (is2GHz) {
4527  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4528  CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4529  return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4530  } else {
4531  if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4532  CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4533  return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4534  }
4535 
4536  return MAX_RATE_POWER;
4537 }
#define CTL_EDGE_FLAGS(_ctl)
Definition: eeprom.h:214
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]
u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]
Definition: ar9003_eeprom.h:24
struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]
struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
#define CTL_EDGE_TPOWER(_ctl)
Definition: eeprom.h:213
uint8_t u8
Definition: stdint.h:19
#define MAX_RATE_POWER
Definition: hw.h:144
u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]

References ath9k_hw_fbin2freq(), CTL_EDGE_FLAGS, CTL_EDGE_TPOWER, ar9300_eeprom::ctl_freqbin_2G, ar9300_eeprom::ctl_freqbin_5G, ctlEdges, ar9300_eeprom::ctlPowerData_2G, ar9300_eeprom::ctlPowerData_5G, and MAX_RATE_POWER.

Referenced by ar9003_hw_get_max_edge_power().

◆ ar9003_hw_get_max_edge_power()

static u16 ar9003_hw_get_max_edge_power ( struct ar9300_eeprom eep,
u16  freq,
int  idx,
int  is2GHz 
)
static

Definition at line 4542 of file ath9k_ar9003_eeprom.c.

4544 {
4545  u16 twiceMaxEdgePower = MAX_RATE_POWER;
4546  u8 *ctl_freqbin = is2GHz ?
4547  &eep->ctl_freqbin_2G[idx][0] :
4548  &eep->ctl_freqbin_5G[idx][0];
4549  u16 num_edges = is2GHz ?
4551  unsigned int edge;
4552 
4553  /* Get the edge power */
4554  for (edge = 0;
4555  (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4556  edge++) {
4557  /*
4558  * If there's an exact channel match or an inband flag set
4559  * on the lower channel use the given rdEdgePower
4560  */
4561  if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4562  twiceMaxEdgePower =
4564  edge, is2GHz);
4565  break;
4566  } else if ((edge > 0) &&
4567  (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4568  is2GHz))) {
4569  twiceMaxEdgePower =
4571  edge, freq,
4572  is2GHz);
4573  /*
4574  * Leave loop - no more affecting edges possible in
4575  * this monotonic increasing list
4576  */
4577  break;
4578  }
4579  }
4580  return twiceMaxEdgePower;
4581 }
uint16_t u16
Definition: stdint.h:21
#define AR9300_NUM_BAND_EDGES_5G
Definition: ar9003_eeprom.h:42
u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]
static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, int idx, unsigned int edge, u16 freq, int is2GHz)
#define AR5416_BCHAN_UNUSED
Definition: eeprom.h:157
#define AR9300_NUM_BAND_EDGES_2G
Definition: ar9003_eeprom.h:43
static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, int idx, int edge, int is2GHz)
static u16 ath9k_hw_fbin2freq(u8 fbin, int is2GHz)
uint8_t u8
Definition: stdint.h:19
#define MAX_RATE_POWER
Definition: hw.h:144
u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]

References AR5416_BCHAN_UNUSED, ar9003_hw_get_direct_edge_power(), ar9003_hw_get_indirect_edge_power(), AR9300_NUM_BAND_EDGES_2G, AR9300_NUM_BAND_EDGES_5G, ath9k_hw_fbin2freq(), ar9300_eeprom::ctl_freqbin_2G, ar9300_eeprom::ctl_freqbin_5G, and MAX_RATE_POWER.

Referenced by ar9003_hw_set_power_per_rate_table().

◆ ar9003_hw_set_power_per_rate_table()

static void ar9003_hw_set_power_per_rate_table ( struct ath_hw ah,
struct ath9k_channel chan,
u8 pPwrArray,
u16  cfgCtl,
u8  twiceAntennaReduction,
u8  twiceMaxRegulatoryPower,
u16  powerLimit 
)
static

Definition at line 4583 of file ath9k_ar9003_eeprom.c.

4589 {
4590  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4591  struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4592  u16 twiceMaxEdgePower = MAX_RATE_POWER;
4593  static const u16 tpScaleReductionTable[5] = {
4594  0, 3, 6, 9, MAX_RATE_POWER
4595  };
4596  int i;
4597  int16_t twiceLargestAntenna;
4598  u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4599  static const u16 ctlModesFor11a[] = {
4601  };
4602  static const u16 ctlModesFor11g[] = {
4605  };
4606  u16 numCtlModes;
4607  const u16 *pCtlMode;
4608  u16 ctlMode, freq;
4609  struct chan_centers centers;
4610  u8 *ctlIndex;
4611  u8 ctlNum;
4612  u16 twiceMinEdgePower;
4613  int is2ghz = IS_CHAN_2GHZ(chan);
4614 
4615  ath9k_hw_get_channel_centers(ah, chan, &centers);
4616 
4617  /* Compute TxPower reduction due to Antenna Gain */
4618  if (is2ghz)
4619  twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4620  else
4621  twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4622 
4623  twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4624  twiceLargestAntenna, 0);
4625 
4626  /*
4627  * scaledPower is the minimum of the user input power level
4628  * and the regulatory allowed power level
4629  */
4630  maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4631 
4632  if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4633  maxRegAllowedPower -=
4634  (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4635  }
4636 
4637  scaledPower = min(powerLimit, maxRegAllowedPower);
4638 
4639  /*
4640  * Reduce scaled Power by number of chains active to get
4641  * to per chain tx power level
4642  */
4643  switch (ar5416_get_ntxchains(ah->txchainmask)) {
4644  case 1:
4645  break;
4646  case 2:
4647  if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4648  scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4649  else
4650  scaledPower = 0;
4651  break;
4652  case 3:
4653  if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4654  scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4655  else
4656  scaledPower = 0;
4657  break;
4658  }
4659 
4660  scaledPower = max((u16)0, scaledPower);
4661 
4662  /*
4663  * Get target powers from EEPROM - our baseline for TX Power
4664  */
4665  if (is2ghz) {
4666  /* Setup for CTL modes */
4667  /* CTL_11B, CTL_11G, CTL_2GHT20 */
4668  numCtlModes =
4669  ARRAY_SIZE(ctlModesFor11g) -
4671  pCtlMode = ctlModesFor11g;
4672  if (IS_CHAN_HT40(chan))
4673  /* All 2G CTL's */
4674  numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4675  } else {
4676  /* Setup for CTL modes */
4677  /* CTL_11A, CTL_5GHT20 */
4678  numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4680  pCtlMode = ctlModesFor11a;
4681  if (IS_CHAN_HT40(chan))
4682  /* All 5G CTL's */
4683  numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4684  }
4685 
4686  /*
4687  * For MIMO, need to apply regulatory caps individually across
4688  * dynamically running modes: CCK, OFDM, HT20, HT40
4689  *
4690  * The outer loop walks through each possible applicable runtime mode.
4691  * The inner loop walks through each ctlIndex entry in EEPROM.
4692  * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4693  */
4694  for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4695  int isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4696  (pCtlMode[ctlMode] == CTL_2GHT40);
4697  if (isHt40CtlMode)
4698  freq = centers.synth_center;
4699  else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4700  freq = centers.ext_center;
4701  else
4702  freq = centers.ctl_center;
4703 
4704  DBG2("ath9k: "
4705  "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4706  ctlMode, numCtlModes, isHt40CtlMode,
4707  (pCtlMode[ctlMode] & EXT_ADDITIVE));
4708 
4709  /* walk through each CTL index stored in EEPROM */
4710  if (is2ghz) {
4711  ctlIndex = pEepData->ctlIndex_2G;
4712  ctlNum = AR9300_NUM_CTLS_2G;
4713  } else {
4714  ctlIndex = pEepData->ctlIndex_5G;
4715  ctlNum = AR9300_NUM_CTLS_5G;
4716  }
4717 
4718  for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4719  DBG2("ath9k: "
4720  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4721  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4722  chan->channel);
4723 
4724  /*
4725  * compare test group from regulatory
4726  * channel list with test mode from pCtlMode
4727  * list
4728  */
4729  if ((((cfgCtl & ~CTL_MODE_M) |
4730  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4731  ctlIndex[i]) ||
4732  (((cfgCtl & ~CTL_MODE_M) |
4733  (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4734  ((ctlIndex[i] & CTL_MODE_M) |
4735  SD_NO_CTL))) {
4736  twiceMinEdgePower =
4738  freq, i,
4739  is2ghz);
4740 
4741  if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4742  /*
4743  * Find the minimum of all CTL
4744  * edge powers that apply to
4745  * this channel
4746  */
4747  twiceMaxEdgePower =
4748  min(twiceMaxEdgePower,
4749  twiceMinEdgePower);
4750  else {
4751  /* specific */
4752  twiceMaxEdgePower =
4753  twiceMinEdgePower;
4754  break;
4755  }
4756  }
4757  }
4758 
4759  minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4760 
4761  DBG2("ath9k: "
4762  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4763  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4764  scaledPower, minCtlPower);
4765 
4766  /* Apply ctl mode to correct target power set */
4767  switch (pCtlMode[ctlMode]) {
4768  case CTL_11B:
4769  for (i = ALL_TARGET_LEGACY_1L_5L;
4770  i <= ALL_TARGET_LEGACY_11S; i++)
4771  pPwrArray[i] =
4772  (u8)min((u16)pPwrArray[i],
4773  minCtlPower);
4774  break;
4775  case CTL_11A:
4776  case CTL_11G:
4777  for (i = ALL_TARGET_LEGACY_6_24;
4778  i <= ALL_TARGET_LEGACY_54; i++)
4779  pPwrArray[i] =
4780  (u8)min((u16)pPwrArray[i],
4781  minCtlPower);
4782  break;
4783  case CTL_5GHT20:
4784  case CTL_2GHT20:
4785  for (i = ALL_TARGET_HT20_0_8_16;
4786  i <= ALL_TARGET_HT20_21; i++)
4787  pPwrArray[i] =
4788  (u8)min((u16)pPwrArray[i],
4789  minCtlPower);
4790  pPwrArray[ALL_TARGET_HT20_22] =
4791  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4792  minCtlPower);
4793  pPwrArray[ALL_TARGET_HT20_23] =
4794  (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4795  minCtlPower);
4796  break;
4797  case CTL_5GHT40:
4798  case CTL_2GHT40:
4799  for (i = ALL_TARGET_HT40_0_8_16;
4800  i <= ALL_TARGET_HT40_23; i++)
4801  pPwrArray[i] =
4802  (u8)min((u16)pPwrArray[i],
4803  minCtlPower);
4804  break;
4805  default:
4806  break;
4807  }
4808  } /* end ctl mode checking */
4809 }
uint16_t u16
Definition: stdint.h:21
u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]
u16 channel
Definition: hw.h:349
#define REDUCE_SCALED_POWER_BY_THREE_CHAIN
#define max(x, y)
Definition: ath.h:39
#define ar5416_get_ntxchains(_txchainmask)
Definition: eeprom.h:706
#define CTL_2GHT40
Definition: eeprom.h:75
#define EXT_ADDITIVE
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define SUB_NUM_CTL_MODES_AT_5G_40
#define min(x, y)
Definition: ath.h:34
u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]
static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, u16 freq, int idx, int is2GHz)
#define AR9300_NUM_CTLS_5G
Definition: ar9003_eeprom.h:40
#define REDUCE_SCALED_POWER_BY_TWO_CHAIN
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
#define u8
Definition: igbvf_osdep.h:38
#define CTL_11G_EXT
#define ARRAY_SIZE(x)
Definition: efx_common.h:43
#define CTL_11A
Definition: eeprom.h:70
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
#define CTL_11G
Definition: eeprom.h:72
#define SUB_NUM_CTL_MODES_AT_2G_40
#define SD_NO_CTL
Definition: eeprom.h:67
#define CTL_11A_EXT
#define CTL_2GHT20
Definition: eeprom.h:73
#define CTL_11B
Definition: eeprom.h:71
#define CTL_MODE_M
Definition: eeprom.h:69
#define CTL_11B_EXT
void ath9k_hw_get_channel_centers(struct ath_hw *ah __unused, struct ath9k_channel *chan, struct chan_centers *centers)
Definition: ath9k_hw.c:189
#define AR9300_NUM_CTLS_2G
Definition: ar9003_eeprom.h:41
uint8_t ah
Definition: registers.h:85
signed short int16_t
Definition: stdint.h:16
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
#define CTL_5GHT40
Definition: eeprom.h:76
#define CTL_5GHT20
Definition: eeprom.h:74
uint8_t u8
Definition: stdint.h:19
#define MAX_RATE_POWER
Definition: hw.h:144
#define DBG2(...)
Definition: compiler.h:515
u32 tp_scale
Definition: ath.h:140

References ah, ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_21, ALL_TARGET_HT20_22, ALL_TARGET_HT20_23, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_23, ALL_TARGET_LEGACY_11S, ALL_TARGET_LEGACY_1L_5L, ALL_TARGET_LEGACY_54, ALL_TARGET_LEGACY_6_24, ar9300_modal_eep_header::antennaGain, ar5416_get_ntxchains, ar9003_hw_get_max_edge_power(), AR9300_NUM_CTLS_2G, AR9300_NUM_CTLS_5G, ARRAY_SIZE, ath9k_hw_get_channel_centers(), ath9k_hw_regulatory(), ATH9K_TP_SCALE_MAX, ath9k_channel::channel, CTL_11A, CTL_11A_EXT, CTL_11B, CTL_11B_EXT, CTL_11G, CTL_11G_EXT, CTL_2GHT20, CTL_2GHT40, CTL_5GHT20, CTL_5GHT40, chan_centers::ctl_center, CTL_MODE_M, ar9300_eeprom::ctlIndex_2G, ar9300_eeprom::ctlIndex_5G, DBG2, EXT_ADDITIVE, chan_centers::ext_center, IS_CHAN_2GHZ, IS_CHAN_HT40, max, MAX_RATE_POWER, min, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, REDUCE_SCALED_POWER_BY_THREE_CHAIN, REDUCE_SCALED_POWER_BY_TWO_CHAIN, SD_NO_CTL, SUB_NUM_CTL_MODES_AT_2G_40, SUB_NUM_CTL_MODES_AT_5G_40, chan_centers::synth_center, ath_regulatory::tp_scale, and u8.

Referenced by ath9k_hw_ar9300_set_txpower().

◆ mcsidx_to_tgtpwridx()

static u8 mcsidx_to_tgtpwridx ( unsigned int  mcs_idx,
u8  base_pwridx 
)
inlinestatic

Definition at line 4811 of file ath9k_ar9003_eeprom.c.

4812 {
4813  u8 mod_idx = mcs_idx % 8;
4814 
4815  if (mod_idx <= 3)
4816  return mod_idx ? (base_pwridx + 1) : base_pwridx;
4817  else
4818  return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4819 }
uint8_t u8
Definition: stdint.h:19

Referenced by ath9k_hw_ar9300_set_txpower().

◆ ath9k_hw_ar9300_set_txpower()

static void ath9k_hw_ar9300_set_txpower ( struct ath_hw ah,
struct ath9k_channel chan,
u16  cfgCtl,
u8  twiceAntennaReduction,
u8  twiceMaxRegulatoryPower,
u8  powerLimit,
int  test 
)
static

Definition at line 4821 of file ath9k_ar9003_eeprom.c.

4826 {
4827  struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4828  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4829  struct ar9300_modal_eep_header *modal_hdr;
4830  u8 targetPowerValT2[ar9300RateSize];
4831  u8 target_power_val_t2_eep[ar9300RateSize];
4832  unsigned int i = 0, paprd_scale_factor = 0;
4833  u8 pwr_idx, min_pwridx = 0;
4834 
4835  ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4836 
4837  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4838  if (IS_CHAN_2GHZ(chan))
4839  modal_hdr = &eep->modalHeader2G;
4840  else
4841  modal_hdr = &eep->modalHeader5G;
4842 
4843  ah->paprd_ratemask =
4844  (uint32_t)(modal_hdr->papdRateMaskHt20) &
4846 
4847  ah->paprd_ratemask_ht40 =
4848  (uint32_t)(modal_hdr->papdRateMaskHt40) &
4850 
4851  paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4852  min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4854 
4855  if (!ah->paprd_table_write_done) {
4856  memcpy(target_power_val_t2_eep, targetPowerValT2,
4857  sizeof(targetPowerValT2));
4858  for (i = 0; i < 24; i++) {
4859  pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4860  if (ah->paprd_ratemask & (1 << i)) {
4861  if (targetPowerValT2[pwr_idx] &&
4862  targetPowerValT2[pwr_idx] ==
4863  target_power_val_t2_eep[pwr_idx])
4864  targetPowerValT2[pwr_idx] -=
4865  paprd_scale_factor;
4866  }
4867  }
4868  }
4869  memcpy(target_power_val_t2_eep, targetPowerValT2,
4870  sizeof(targetPowerValT2));
4871  }
4872 
4874  targetPowerValT2, cfgCtl,
4875  twiceAntennaReduction,
4876  twiceMaxRegulatoryPower,
4877  powerLimit);
4878 
4879  if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4880  for (i = 0; i < ar9300RateSize; i++) {
4881  if ((ah->paprd_ratemask & (1 << i)) &&
4882  ((unsigned int)abs(targetPowerValT2[i] -
4883  target_power_val_t2_eep[i]) >
4884  paprd_scale_factor)) {
4885  ah->paprd_ratemask &= ~(1 << i);
4886  DBG2("ath9k: "
4887  "paprd disabled for mcs %d\n", i);
4888  }
4889  }
4890  }
4891 
4892  regulatory->max_power_level = 0;
4893  for (i = 0; i < ar9300RateSize; i++) {
4894  if (targetPowerValT2[i] > regulatory->max_power_level)
4895  regulatory->max_power_level = targetPowerValT2[i];
4896  }
4897 
4898  if (test)
4899  return;
4900 
4901  for (i = 0; i < ar9300RateSize; i++) {
4902  DBG2("ath9k: "
4903  "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4904  }
4905 
4906  /*
4907  * This is the TX power we send back to driver core,
4908  * and it can use to pass to userspace to display our
4909  * currently configured TX power setting.
4910  *
4911  * Since power is rate dependent, use one of the indices
4912  * from the AR9300_Rates enum to select an entry from
4913  * targetPowerValT2[] to report. Currently returns the
4914  * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4915  * as CCK power is less interesting (?).
4916  */
4917  i = ALL_TARGET_LEGACY_6_24; /* legacy */
4918  if (IS_CHAN_HT40(chan))
4919  i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4920  else if (IS_CHAN_HT20(chan))
4921  i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4922 
4923  ah->txpower_limit = targetPowerValT2[i];
4924  regulatory->max_power_level = targetPowerValT2[i];
4925 
4926  /* Write target power array to registers */
4927  ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4929 
4930  if (IS_CHAN_2GHZ(chan)) {
4931  if (IS_CHAN_HT40(chan))
4933  else
4935  } else {
4936  if (IS_CHAN_HT40(chan))
4937  i = ALL_TARGET_HT40_7;
4938  else
4939  i = ALL_TARGET_HT20_7;
4940  }
4941  ah->paprd_target_power = targetPowerValT2[i];
4942 }
static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, u8 *targetPowerValT2)
u16 channel
Definition: hw.h:349
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, struct ath9k_channel *chan)
static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 *pPwrArray)
#define abs(x)
Definition: ath.h:44
void * memcpy(void *dest, const void *src, size_t len) __nonnull
static struct ath_regulatory * ath9k_hw_regulatory(struct ath_hw *ah)
Definition: hw.h:874
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
unsigned int uint32_t
Definition: stdint.h:12
uint8_t ah
Definition: registers.h:85
static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, u8 *pPwrArray, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u16 powerLimit)
static u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
#define AR9300_PAPRD_RATE_MASK
Definition: ar9003_eeprom.h:53
#define IS_CHAN_HT20(_c)
Definition: hw.h:370
#define IS_CHAN_HT40(_c)
Definition: hw.h:372
uint8_t u8
Definition: stdint.h:19
static int test
Definition: epic100.c:73
u16 max_power_level
Definition: ath.h:139
#define DBG2(...)
Definition: compiler.h:515

References abs, ah, ALL_TARGET_HT20_0_8_16, ALL_TARGET_HT20_7, ALL_TARGET_HT40_0_8_16, ALL_TARGET_HT40_7, ALL_TARGET_LEGACY_6_24, ar9003_get_paprd_scale_factor(), ar9003_hw_calibration_apply(), ar9003_hw_set_power_per_rate_table(), ar9003_hw_set_target_power_eeprom(), ar9003_hw_tx_power_regwrite(), AR9300_PAPRD_RATE_MASK, ar9300RateSize, ath9k_hw_regulatory(), ath9k_channel::channel, DBG2, EEP_PAPRD, IS_CHAN_2GHZ, IS_CHAN_HT20, IS_CHAN_HT40, ath_regulatory::max_power_level, mcsidx_to_tgtpwridx(), memcpy(), ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, ar9300_modal_eep_header::papdRateMaskHt20, ar9300_modal_eep_header::papdRateMaskHt40, and test.

◆ ath9k_hw_ar9300_get_spur_channel()

static u16 ath9k_hw_ar9300_get_spur_channel ( struct ath_hw *ah  __unused,
u16 __unused,
int is2GHz  __unused 
)
static

Definition at line 4944 of file ath9k_ar9003_eeprom.c.

4946 {
4947  return AR_NO_SPUR;
4948 }
#define AR_NO_SPUR
Definition: hw.h:240

References AR_NO_SPUR.

◆ ar9003_hw_get_tx_gain_idx()

s32 ar9003_hw_get_tx_gain_idx ( struct ath_hw ah)

Definition at line 4950 of file ath9k_ar9003_eeprom.c.

4951 {
4952  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4953 
4954  return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4955 }
struct ar9300_base_eep_hdr baseEepHeader
uint8_t ah
Definition: registers.h:85

References ah, ar9300_eeprom::baseEepHeader, and ar9300_base_eep_hdr::txrxgain.

Referenced by ar9003_tx_gain_table_apply().

◆ ar9003_hw_get_rx_gain_idx()

s32 ar9003_hw_get_rx_gain_idx ( struct ath_hw ah)

Definition at line 4957 of file ath9k_ar9003_eeprom.c.

4958 {
4959  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4960 
4961  return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4962 }
struct ar9300_base_eep_hdr baseEepHeader
uint8_t ah
Definition: registers.h:85

References ah, ar9300_eeprom::baseEepHeader, and ar9300_base_eep_hdr::txrxgain.

Referenced by ar9003_rx_gain_table_apply().

◆ ar9003_get_spur_chan_ptr()

u8* ar9003_get_spur_chan_ptr ( struct ath_hw ah,
int  is_2ghz 
)

Definition at line 4964 of file ath9k_ar9003_eeprom.c.

4965 {
4966  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4967 
4968  if (is_2ghz)
4969  return eep->modalHeader2G.spurChans;
4970  else
4971  return eep->modalHeader5G.spurChans;
4972 }
u8 spurChans[AR_EEPROM_MODAL_SPURS]
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
uint8_t ah
Definition: registers.h:85

References ah, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, and ar9300_modal_eep_header::spurChans.

Referenced by ar9003_hw_spur_mitigate_mrc_cck().

◆ ar9003_get_paprd_scale_factor()

unsigned int ar9003_get_paprd_scale_factor ( struct ath_hw ah,
struct ath9k_channel chan 
)

Definition at line 4974 of file ath9k_ar9003_eeprom.c.

4976 {
4977  struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4978 
4979  if (IS_CHAN_2GHZ(chan))
4980  return MS((uint32_t)(eep->modalHeader2G.papdRateMaskHt20),
4982  else {
4983  if (chan->channel >= 5700)
4984  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt20),
4986  else if (chan->channel >= 5400)
4987  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4989  else
4990  return MS((uint32_t)(eep->modalHeader5G.papdRateMaskHt40),
4992  }
4993 }
u16 channel
Definition: hw.h:349
#define IS_CHAN_2GHZ(_c)
Definition: hw.h:361
#define MS(_v, _f)
Definition: hw.h:102
#define AR9300_PAPRD_SCALE_1
Definition: ar9003_eeprom.h:54
struct ar9300_modal_eep_header modalHeader2G
struct ar9300_modal_eep_header modalHeader5G
#define AR9300_PAPRD_SCALE_2
Definition: ar9003_eeprom.h:56
unsigned int uint32_t
Definition: stdint.h:12
uint8_t ah
Definition: registers.h:85

References ah, AR9300_PAPRD_SCALE_1, AR9300_PAPRD_SCALE_2, ath9k_channel::channel, IS_CHAN_2GHZ, ar9300_eeprom::modalHeader2G, ar9300_eeprom::modalHeader5G, MS, ar9300_modal_eep_header::papdRateMaskHt20, and ar9300_modal_eep_header::papdRateMaskHt40.

Referenced by ath9k_hw_ar9300_set_txpower().

Variable Documentation

◆ ar9300_default

const struct ar9300_eeprom ar9300_default
static

Definition at line 74 of file ath9k_ar9003_eeprom.c.

Referenced by ar9300_eeprom_restore_internal().

◆ ar9300_x113

const struct ar9300_eeprom ar9300_x113
static

Definition at line 652 of file ath9k_ar9003_eeprom.c.

◆ ar9300_h112

const struct ar9300_eeprom ar9300_h112
static

Definition at line 1230 of file ath9k_ar9003_eeprom.c.

◆ ar9300_x112

const struct ar9300_eeprom ar9300_x112
static

Definition at line 1808 of file ath9k_ar9003_eeprom.c.

◆ ar9300_h116

const struct ar9300_eeprom ar9300_h116
static

Definition at line 2385 of file ath9k_ar9003_eeprom.c.

◆ ar9300_eep_templates

const struct ar9300_eeprom* ar9300_eep_templates[]
static
Initial value:
= {
}
static const struct ar9300_eeprom ar9300_default
static const struct ar9300_eeprom ar9300_h116
static const struct ar9300_eeprom ar9300_h112
static const struct ar9300_eeprom ar9300_x113
static const struct ar9300_eeprom ar9300_x112

Definition at line 2963 of file ath9k_ar9003_eeprom.c.

Referenced by ar9003_eeprom_struct_find_by_id().

◆ eep_ar9300_ops

const struct eeprom_ops eep_ar9300_ops
Initial value:
= {
.get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
.get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
.set_board_values = ath9k_hw_ar9300_set_board_values,
}
static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah __unused, u16 i __unused, int is2GHz __unused)
static int ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah __unused, struct ath9k_channel *chan __unused)
static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah __unused)
static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param)
static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan)
static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah __unused)
static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit, int test)

Definition at line 4995 of file ath9k_ar9003_eeprom.c.

Referenced by ath9k_hw_eeprom_init().